ZSPM4012B [IDT]
High Efficiency 2A Synchronous Buck Converter;型号: | ZSPM4012B |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | High Efficiency 2A Synchronous Buck Converter |
文件: | 总21页 (文件大小:658K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ZSPM4012B
High Efficiency 2A Synchronous
Buck Converter
Datasheet
Brief Description
Benefits
The ZSPM4012B is
a
DC/DC synchronous
•
•
Increased battery life
switching regulator with fully integrated power
switches, internal compensation, and full fault
protection. The 1MHz switching frequency enables
using small filter components, resulting in reduced
board space and reduced bill-of-materials costs.
Minimal external component count
(3 capacitors, 1 inductor)
•
Inherent fault protection and reporting
Available Support
•
•
The ZSPM4012B utilizes current mode feedback in
normal regulation pulse-width modulation (PWM)
mode. When the regulator is disabled (EN pin is
low), the ZSPM4012B draws less than 10µA quies-
cent current.
Evaluation Kit
Documentation
Physical Characteristics
•
•
Junction operating temperature -40°C to 125°C
Packaged in a 16pin QFN (3x3mm)
The ZSPM4012B integrates a wide range of
protection circuitry, including input supply under-
voltage lockout, output voltage soft start, current
limit, VOUT over-voltage, and thermal shutdown.
The ZSPM4012B includes supervisory reporting
through the PG (Power Good) open drain output to
interface other components in the system.
Related IDT Products
•
•
ZSPM4011B/ZSPM4013B: 1A/3A synchronous
buck converters, available with adjustable out-
put from 0.9 to 5.5V or fixed output voltages at
1.5V, 1.8V, 2.5V, 3.3V, 5.0V
(16-lead 3x3mm QFN)
Features
ZSPM1000: >5A single-phase, single-rail, true
digital PWM controller (24-pin 4x4mm QFN)
•
Output voltage options (depends on order code):
.
.
Fixed output voltages: 1.5V, 1.8V, 2.5V,
3.3V, or 5V with +/- 2% output tolerance
ZSPM4012B Application Circuits
Adjustable output voltage range: 0.9V to
5.5V with +/- 1.5% reference
Adjustable Output
BST
CBST
•
•
•
•
•
Wide input voltage range: 4.5V to 24V
1MHz +/- 10% fixed switching frequency
2A continuous output current
VCC
CBYPASS
VCC
VSW
FB
VOUT
COUT
LOUT
RTOP
RBOT
High efficiency – up to 95%
VOUT
Current mode PWM control with pulse-
frequency modulation (PFM) mode for
improved light load efficiency
10 kΩ
(optional)
EN
EN
PG
PG
•
Voltage supervisor for VOUT reported at the PG
pin
Fixed Output
•
•
Input supply under voltage lockout
BST
VCC
VCC
CBST
Soft start for controlled startup with no
overshoot
CBYPASS
VOUT
VSW
FB
LOUT
•
Full protection for over-current, over-
temperature, and VOUT over-voltage
COUT
VOUT
•
•
Less than 10µA in Disabled Mode
Low external component count
10kΩ
(optional)
EN
EN
PG
PG
© 2016 Integrated Device Technology, Inc.
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January 27, 2016
ZSPM4012B
High Efficiency 2A Synchronous
Buck Converter
Datasheet
ZSPM4012B Block Diagram
PG
EN
VCC
VCC
4.2V
VCC
Under-Voltage
Protection
MONITOR
&
VCC
CONTROL
Over-Voltage
Protection
FB
Bootstrap
Voltage
Oscillator
Thermal
Protection
BST
Ramp
Generator
Over Current
Protection
VCC
S
Vref
&
Typical Applications
Gate
Drive
Soft Start
VSW
Gate Drive
Control
•
Wireless access points, cable
modems
High-Side Switch
Comparator
Vref
Gate
Drive
Error Amp
•
•
•
Set-top boxes
PGND
FB
Low-Side Switch
DVD, LCD, LED supplies
Compensation
Network
Portable products, including
GPS, smart phones, tablet
PCs
PFM Mode
Comparator
GND
•
Printers
Ordering Information
Ordering Code
Description
Package
ZSPM4012BA1W00
ZSPM4012BA1W15
ZSPM4012BA1W18
ZSPM4012BA1W25
ZSPM4012BA1W33
ZSPM4012BA1W50
ZSPM4012BKIT
2A Synchronous Buck Converter: adjustable output, 0.9V to 5.5V, 16-pin 3x3mm QFN 7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
Kit
2A Synchronous Buck Converter: fixed output, 1.5V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 1.8V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 2.5V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 3.3V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 5.0V,16-pin 3x3mm QFN
ZSPM4012B Evaluation Kit for 2A Synchronous Buck Converter
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance
specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property
rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the
property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated
Device Technology, Inc. All rights reserved.
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
Contents
1
ZSPM4012B Characteristics ...............................................................................................................................5
1.1. Absolute Maximum Ratings..........................................................................................................................5
1.2. Thermal Characteristics................................................................................................................................5
1.3. Recommended Operating Conditions ..........................................................................................................6
1.4. Electrical Characteristics ..............................................................................................................................6
1.5. Regulator Characteristics .............................................................................................................................7
Typical Performance Characteristics – ZSPM401x Family.................................................................................9
Description of Circuit .........................................................................................................................................12
3.1. Block Diagram ............................................................................................................................................12
3.2. Internal Protection Details ..........................................................................................................................13
3.2.1. Internal Current Limit ...........................................................................................................................13
3.2.2. Thermal Shutdown...............................................................................................................................13
3.2.3. Voltage Reference Soft-Start...............................................................................................................13
3.2.4. VCC Under-Voltage Lockout................................................................................................................13
3.2.5. Output Over-Voltage Protection...........................................................................................................14
3.2.6. Output Under-Voltage Monitoring ........................................................................................................14
Application Circuits............................................................................................................................................15
4.1. Selection of External Components .............................................................................................................15
4.2. Typical Application Circuits.........................................................................................................................15
Pin Configuration and Package.........................................................................................................................16
5.1. Marking Diagram & Pin-out ........................................................................................................................17
5.2. Pin Description for 16 LEAD 3x3mm QFN .................................................................................................18
5.3. Detailed Pin Description .............................................................................................................................19
5.3.1. Unregulated Input, VCC (Pins # 2, 3) ..................................................................................................19
5.3.2. Bootstrap Control, BST (Pin #10) ........................................................................................................19
5.3.3. Sense Feedback, FB (Pin #5)..............................................................................................................19
5.3.4. Switching Output, VSW (Pins #12, 13) ................................................................................................19
5.3.5. Ground, GND (Pin #4) .........................................................................................................................19
5.3.6. Power Ground, PGND (Pins #14, 15)..................................................................................................19
5.3.7. Enable, EN (Pin #9) .............................................................................................................................19
5.3.8. PG Output, PG (Pin #8) .......................................................................................................................19
Ordering Information .........................................................................................................................................20
Related Documents...........................................................................................................................................20
Glossary ............................................................................................................................................................20
Document Revision History...............................................................................................................................21
2
3
4
5
6
7
8
9
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ZSPM4012B Datasheet
List of Figures
Figure 2.1 Startup Response ..................................................................................................................................9
Figure 2.2 100mA to 1A Load Step (VCC= 12V, VOUT =1.8V) .............................................................................9
Figure 2.3 100mA to 2A Load (VCC=12V, VOUT = 1.8V)......................................................................................9
Figure 2.4 100mA to 1A Load Step (VCC=12V, VOUT = 3.3V) .............................................................................9
Figure 2.5 100mA to 2A Load Step (VCC=12V, VOUT = 3.3V) .............................................................................9
Figure 2.6 Line Transient Response (VCC=10V to 15V, VOUT = 3.3V)...............................................................9
Figure 2.7 Load Regulation...................................................................................................................................10
Figure 2.8 Line Regulation (IOUT=1A)....................................................................................................................10
Figure 2.9 Efficiency vs. Output Current ( VOUT = 1.8V) .....................................................................................10
Figure 2.10 Efficiency vs. Output Current (VOUT = 3.3V) ......................................................................................10
Figure 2.11 Efficiency vs. Output Current ( VOUT = 5V) ........................................................................................10
Figure 2.12 Efficiency vs. Input Voltage (VOUT = 3.3V).........................................................................................10
Figure 2.13 Standby Current vs. Input Voltage.......................................................................................................11
Figure 2.14 Standby Current vs. Temperature .......................................................................................................11
Figure 2.15 Output Voltage vs. Temperature..........................................................................................................11
Figure 2.16 Oscillator Frequency vs. Temperature (Iout=300mA) .........................................................................11
Figure 2.17 Quiescent Current vs. Temperature (No load) ...................................................................................11
Figure 2.18 Input Current vs. Temperature (No load, No switching).....................................................................11
Figure 3.1 ZSPM4012B Block Diagram................................................................................................................12
Figure 3.2 Monitor and Control Logic Functionality ..............................................................................................13
Figure 4.1 Typical Application for Adjustable Output Voltage...............................................................................15
Figure 4.2 Typical Application for Fixed Output Voltage.......................................................................................15
Figure 5.1 ZSPM4012B Package Drawing ...........................................................................................................16
Figure 5.2 16 Lead 3x3mm QFN (top view)..........................................................................................................17
List of Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 5.1
Absolute Maximum Ratings...................................................................................................................5
Thermal Characteristics.........................................................................................................................5
Recommended Operating Conditions ...................................................................................................6
Electrical Characteristics .......................................................................................................................6
Regulator Characteristics ......................................................................................................................7
Pin Description, 16 lead, 3x3mm QFN ................................................................................................18
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
1
ZSPM4012B Characteristics
Important: Stresses beyond those listed under “Absolute Maximum Ratings” (section 1.1) may cause permanent
damage to the device. These are stress ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under “Recommended Operating Conditions” (section 1.3) is not implied.
Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
1.1. Absolute Maximum Ratings
Over operating free–air temperature range unless otherwise noted.
Table 1.1
Absolute Maximum Ratings
Parameter
Value1)
-0.3 to 26.4
-0.3 to (VCC+6)
-1 to 26.4
-0.3 to 6
+/-2k
UNIT
V
Voltage on VCC pin
Voltage on BST pin
V
Voltage on VSW pin
V
Voltage on EN, PG, FB pins
V
Electrostatic Discharge – Human Body Model 2)
Electrostatic Discharge – Charge Device Model 2)
Lead Temperature (soldering, 10 seconds)
V
+/-500
V
260
°C
1) All voltage values are with respect to network ground terminal.
2) ESD testing is performed according to the respective JESD22 JEDEC standard.
1.2.
Thermal Characteristics
Thermal Characteristics
Parameter
Table 1.2
Symbol
θJA
Value
Unit
°C/W
°C/W
°C
Thermal Resistance Junction to Air 1)
Thermal Resistance Junction to Case 1)
Storage Temperature Range
34.5
2.5
θJc
TSTG
TJ MAX
TJ
-65 to 150
150
Maximum Junction Temperature
°C
Operating Junction Temperature Range
1) Assumes 1 in2 area of 2 oz. copper and 25°C ambient temperature.
-40 to 125
°C
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
1.3. Recommended Operating Conditions
Table 1.3
Recommended Operating Conditions
Parameter
Symbol
VCC
Min
4.5
17.6
3.76
33
Typ
Max
24
Unit
V
Input Operating Voltage
12
Bootstrap Capacitor
CBST
22
4.7
26.4
5.64
nF
Output Filter Inductor Typical Value 1)
Output Filter Capacitor Typical Value 2)
Output Filter Capacitor ESR
LOUT
µH
µF
mΩ
µF
COUT
44 (2 x 22)
35
COUT-ESR
CBYPASS
2
100
Input Supply Bypass Capacitor Typical Value 3)
8
10
1) For best performance, an inductor with a saturation current rating higher than the maximum VOUT load requirement plus the inductor
current ripple.
2) For best performance, a low ESR ceramic capacitor should be used.
3) For best performance, a low ESR ceramic capacitor should be used. If CBYPASS is not a low ESR ceramic capacitor, a 0.1µF ceramic
capacitor should be added in parallel to CBYPASS
.
1.4. Electrical Characteristics
Electrical Characteristics, TJ = -40°C to 125°C, VCC = 12V (unless otherwise noted)
Table 1.4 Electrical Characteristics
Parameter
Symbol
Condition
Min
Typ
Max
Unit
VCC Supply Voltage
Input Supply Voltage
VCC
4.5
24
V
Quiescent Current:
Normal Mode
ICC-NORM
5.2
2.3
5
mA
VCC = 12V, ILOAD = 0A, EN ≥ 2.2
Quiescent Current:
Normal Mode, Non-switching
ICC-
NOSWITCH
mA
µA
VCC=12V, ILOAD=0A, EN ≥ 2.2
Non-switching
Quiescent Current:
Disabled Mode
ICC-DISABLE
VCC = 12V, EN = 0V
10
VCC Under Voltage Lockout
Input Supply Under Voltage
Threshold
VCC-UV
VCC Increasing
4.1
4.3
4.5
V
Input Supply Under Voltage
Threshold Hysteresis
VCC-
UV_HYST
300
325
350
mV
Oscillator
Oscillator Frequency
fOSC
0.9
1
1.1
MHz
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ZSPM4012B Datasheet
Parameter
Symbol
Condition
Min
Typ
Max
Unit
PG Open Drain Output
PG Release Timer
TPG
10
ms
µA
V
High-Level Output Leakage
Low-Level Output Voltage
EN Input Voltage Thresholds
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
IOH-PG
VOL-PG
VPG = 5V
0.5
IPG = -0.3mA
0.01
0.8
VIH-EN
VIL-EN
2.2
V
V
VHYST-EN
IIN-EN
480
3.5
mV
µA
µA
Input Leakage
VEN=5V
VEN=0V
-1.5
Thermal Shutdown
Thermal Shutdown Junction
Temperature
TSD
Note: Guaranteed by design
150
170
10
°C
°C
TSD Hysteresis
TSDHYST
1.5. Regulator Characteristics
Electrical Characteristics, TJ = -40°C to 125°C, VCC = 12V (unless otherwise noted)
Table 1.5 Regulator Characteristics
See important table notes at the end of the table.
Parameter Symbol
Switch Mode Regulator: LOUT=4.7µH and COUT=2 x 22µF
Condition
Min
Typ
Max
Unit
Output Voltage Tolerance in
Pulse-Width Modulation
(PWM) Mode
VOUT-PWM
ILOAD =1A
VOUT
2%
–
VOUT
VOUT
2%
+
V
Output Voltage Tolerance in
Pulse-Frequency Modulation
(PFM) Mode
VOUT-PFM
ILOAD = 0A
VOUT
1%
–
VOUT
1%
+
VOUT
3.5%
+
V
V
Steady State.
Differential Voltage Between
VOUT and VCC
VIN-OUT
1.2
(Example, VOUT maximum is
3.3V with VCC min of 4.5V)
High Side Switch On
Resistance 1)
IVSW = -1A
IVSW = 1A
180
120
mΩ
mΩ
RDSON
Low Side Switch On
Resistance 1)
Output Current
IOUT
IOCD
2
A
A
Over Current Detect
HS switch current
2.4
2.8
3.4
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ZSPM4012B Datasheet
Parameter
Symbol
Condition
Min
Typ
0.9
4
Max
Unit
V
Feedback Reference
(Adjustable Mode)
FBTH
0.886
0.914
Soft Start Ramp Time
tSS
ms
FBTH-TOL
For the adjustable version,
the ratio of VCC/VOUT cannot
exceed 16.
PFM Mode FB Comparator
Tolerance
-1.5
1.5
%
V
PFM Mode FB Comparator
Threshold
FBTH-PFM
VOUT-UV
VOUT
1%
+
VOUT Under Voltage
Threshold
88%
VOUT
90%
VOUT
92%
VOUT
VOUT Under Voltage
Hysteresis
VOUT-
UV_HYST
1.5%
VOUT
VOUT-OV
103%
VOUT
VOUT Over Voltage Threshold
VOUT Over Voltage
Hysteresis
VOUT-
OV_HYST
1% VOUT
97%
Max Duty Cycle 2)
DUTYMAX
95%
99%
1) RDSON is characterized at 1A and tested at lower current in production.
2) Regulator VSW pin is forced off for 240ns every 8 cycles to ensure the BST cap is replenished.
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
2
Typical Performance Characteristics – ZSPM401x Family
Graphs apply to ZSPM401x ICs. See section 1 for ZSPM4012B characteristics. Unless otherwise noted, TJ = -40°C to 125°C, VCC = 12V.
Figure 2.1 Startup Response
Figure 2.2 100mA to 1A Load Step (VCC= 12V, VOUT =1.8V)
Figure 2.3 100mA to 2A Load (VCC=12V, VOUT = 1.8V)
Figure 2.4 100mA to 1A Load Step (VCC=12V, VOUT = 3.3V)
Figure 2.5 100mA to 2A Load Step
(VCC=12V, VOUT = 3.3V)
Figure 2.6 Line Transient Response
(VCC=10V to 15V, VOUT = 3.3V)
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ZSPM4012B Datasheet
Figure 2.7 Load Regulation
Figure 2.8 Line Regulation (IOUT=1A)
Figure 2.9 Efficiency vs. Output Current ( VOUT = 1.8V)
Figure 2.10 Efficiency vs. Output Current (VOUT = 3.3V)
Figure 2.11 Efficiency vs. Output Current ( VOUT = 5V)
Figure 2.12 Efficiency vs. Input Voltage (VOUT = 3.3V)
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
Figure 2.13 Standby Current vs. Input Voltage
Figure 2.14 Standby Current vs. Temperature
Figure 2.15 Output Voltage vs. Temperature
Figure 2.16 Oscillator Frequency vs. Temperature
(Iout=300mA)
Figure 2.17 Quiescent Current vs. Temperature (No load)
Figure 2.18 Input Current vs. Temperature
(No load, No switching)
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
3
Description of Circuit
The ZSPM4012B current-mode synchronous step-down power supply product can be used in the commercial,
industrial, and automotive market segments. It includes flexibility for a wide range of output voltages and is
optimized for high efficiency power conversion with low RDSON integrated synchronous switches. A 1MHz internal
switching frequency facilitates low-cost LC filter combinations. The fixed-output versions also enable a minimum
external component count to provide a complete regulation solution with only 4 external components: an input
bypass capacitor, an inductor, an output capacitor, and the bootstrap capacitor. The regulator automatically
transitions between pulse frequency modulation (PFM) and pulse width modulation (PWM) mode to maximize
efficiency for the load demand.
See section 5.3.3 for details for adjusting VOUT for the adjustable output version of the ZSPM4012B.
3.1. Block Diagram
Figure 3.1 provides a block diagram of the ZSPM4012B, and Figure 3.2 illustrates its monitor and control logic
functions, which are explained in section 3.2.
Figure 3.1
ZSPM4012B Block Diagram
PG
EN
VCC
VCC
4.2V
VCC
Under-Voltage
Protection
MONITOR
&
VCC
CONTROL
Over-Voltage
Protection
FB
Bootstrap
Voltage
Oscillator
Thermal
Protection
BST
Ramp
Generator
Over Current
Protection
VCC
S
Vref
&
Gate
Drive
Soft Start
VSW
Gate Drive
Control
High-Side Switch
Comparator
Vref
Gate
Drive
Error Amp
PGND
FB
Low-Side Switch
Compensation
Network
PFM Mode
Comparator
GND
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ZSPM4012B Datasheet
Figure 3.2
Monitor and Control Logic Functionality
PG
Filter
VOUT-UV
Filter
EN
ENABLE
REGULATOR
Internal
Filter
POR
Filter
VCC-UV
Filter
VOUT-OV
TRI-STATE
VSW OUTPUT
Filter
TSD
OCD_Filter
IOCD
3.2. Internal Protection Details
3.2.1.
Internal Current Limit
The current through the high-side FET is sensed on a cycle-by-cycle basis, and if the current limit is reached, the
over-current detection (OCD) circuit will abbreviate the cycle. The device also senses the FB pin to identify hard
short conditions and will direct the VSW output to skip 4 cycles if the current limit occurs when FB is low. This
allows current built up in the inductor during the minimum on-time to decay sufficiently. The current limit is always
active when the regulator is enabled. Soft start ensures that current limit does not prevent regulator startup.
An additional feature of the over-current protection circuitry is that under extended over-current conditions, the
device will automatically disable. A simple toggle of the EN enable pin will return the device to normal operation.
3.2.2.
Thermal Shutdown
If the temperature of the die exceeds 170°C (typical), the thermal shutdown (TSD) circuit will set the VSW outputs
to the tri-state level to protect the device from damage. The PG and all other protection circuitry will stay active to
inform the system of the failure mode. If the ZSPM4012B cools to 160°C (typical), it will attempt to start up again,
following the normal soft start sequence. If the device reaches 170°C, the shutdown/restart sequence will repeat.
3.2.3.
Voltage Reference Soft-Start
The voltage reference in this device is ramped at a rate of 4ms to prevent the output from overshoot during
startup. This ramp restarts whenever there is a rising edge sensed on the EN pin. This occurs in both the fixed
and adjustable versions. During the soft start ramp, current limit is still active and still protects the device if the
output is shorted.
3.2.4.
VCC Under-Voltage Lockout
The ZSPM4012B is held in the off state until VCC reaches 4.3V (typical). See section 1.4 for the input hysteresis.
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
3.2.5.
Output Over-Voltage Protection
If the output of the regulator exceeds 103% of the regulation voltage, the output over-voltage (OUT-OV) protection
circuit will set the VSW outputs to the tri-state level to protect the ZSPM4012B from damage. (See Figure 3.2.)
This check occurs at the start of each switching cycle. If it occurs during the middle of a cycle, the switching for
that cycle will complete and the VSW outputs will tri-state at the start of the next cycle.
3.2.6.
Output Under-Voltage Monitoring
The switched mode output voltage is also monitored by the output under-voltage circuit (OUT-UV) as shown in
Figure 3.2. The PG line remains low until the output voltage reaches the VOUT-UV threshold (see Table 1.5). Once
the internal comparator detects that the output voltage is above the desired threshold, an internal delay timer is
activated and the PG line is de-asserted (to high) once this delay timer expires. In the event that the output
voltage decreases below VOUT-UV, the PG line will be asserted low and remain low until the output rises above
VOUT-UV and the delay timer times out. There is a hysteresis for the VOUT-UV threshold (see Table 1.5).
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ZSPM4012B Datasheet
4
Application Circuits
4.1. Selection of External Components
The internal compensation is optimized for a 44µF output capacitor (COUT) and a 4.7µH inductor (LOUT). The
minimum allowable value for the output capacitor is 33µF. To keep the output ripple low, a low ESR (less than
35mΩ) ceramic is recommended. The inductor range is 4.7µH +/-20%. For optimal over-current protection, the
inductor should be able to handle up to the regulator current limit without saturation.
Connect the VCC pin to the bypass capacitor CBYPASS to improve performance (see section 5.3.1 and Table 1.3).
Connect the BST pin to the bootstrap capacitor CBST as described in section 5.3.2. See Table 1.3 for the
recommended value.
For the adjustable version of the ZSPM4012B, an external voltage resistor divider is required (RTOP and RBOT).
See section 5.3.3 for details.
4.2. Typical Application Circuits
Figure 4.1
Typical Application for Adjustable Output Voltage
Adjustable Output
BST
CBST
VCC
CBYPASS
VCC
VSW
FB
VOUT
COUT
LOUT
RTOP
RBOT
VOUT
10 kΩ
(optional)
EN
EN
PG
PG
Figure 4.2
Typical Application for Fixed Output Voltage
Fixed Output
BST
VCC
VCC
CBST
CBYPASS
VOUT
VSW
LOUT
COUT
FB
VOUT
10kΩ
(optional)
EN
EN
PG
PG
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
5
Pin Configuration and Package
Figure 5.1
ZSPM4012B Package Drawing
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ZSPM4012B Datasheet
5.1. Marking Diagram & Pin-out
Figure 5.2
16 Lead 3x3mm QFN (top view)
4012B: Part Name
MY: Date Code
B: Revision
M = Month
XXXXX: Lot number (last five digits)
O: Pin 1 mark
VL: Voltage level
•
•
•
•
•
•
•
•
•
•
•
•
1
2
3
4
5
6
7
8
9
A
B
C
January
February
March
April
May
•
•
•
•
•
•
15 1.5V
18 1.8V
25 2.5V
33 3.3V
50 5.0V
00 0.9V – 5.5V variable
June
July
August
September
October
November
December
Y = Year
•
•
•
•
A
B
C
etc.
2011
2012
2013
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ZSPM4012B Datasheet
5.2. Pin Description for 16 LEAD 3x3mm QFN
Table 5.1
Pin Description, 16 lead, 3x3mm QFN
Name
Pin #
Function
Description
Connected to a 4.7µH (typical) inductor. Also connect to additional
VSW pins 12, 13, and 16.
VSW
1
Switching Voltage Node
VCC
VCC
2
3
Input Voltage
Input Voltage
Input voltage. Also connect to additional VCC pins 3 and 11.
Input voltage. Also connect to additional VCC pins 2 and 11.
Primary ground for the majority of the device except the low-side
power FET.
GND
FB
4
5
GND
Regulator FB voltage. Connects to VOUT for fixed-mode and the
output resistor divider for adjustable mode.
Feedback Input
NC
NC
PG
6
7
8
No Connect
No Connect
PG Output
Not connected.
Not connected.
Open-drain output.
Above 2.2V the device is enabled. Ground this pin to disable the
ZSPM4012B. Includes internal pull-up.
EN
9
Enable Input
Bootstrap capacitor for the high-side FET gate driver. Connect a
22nF ceramic capacitor from BST pin to VSW pin.
BST
10
Bootstrap Capacitor
VCC
VSW
VSW
11
12
13
Input Voltage
Input voltage. Also connect to additional VCC pins 2 and 3.
Connect to additional VSW pins 1, 13, and 16.
Connect to additional VSW pins 1, 12, and 16.
Switching Voltage Node
Switching Voltage Node
GND supply for internal low-side FET/integrated diode. Also
connect to additional PGND pin 15.
PGND
14
Power GND
GND supply for internal low-side FET/integrated diode. Also
connect to additional PGND pin 14.
PGND
VSW
15
16
Power GND
Switching Voltage Node
Connect to additional VSW pins 1, 12, and 13.
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
5.3. Detailed Pin Description
5.3.1.
Unregulated Input, VCC (Pins # 2, 3)
This terminal is the unregulated input voltage source for the ZSPM4012B. It is recommended that a 10µF bypass
capacitor be placed close to the device for best performance. Since this is the main supply for the ZSPM4012B,
good layout practices must be followed for this connection.
5.3.2.
Bootstrap Control, BST (Pin #10)
This terminal will provide the bootstrap voltage required for the high-side internal NMOS switch of the buck
regulator. An external ceramic capacitor placed between the BST input terminal, and the VSW pin will provide the
necessary voltage for the high-side switch. In normal operation, the capacitor is re-charged on every low side
synchronous switching action. If the switch mode approaches 100% duty cycle for the high side FET, the device
will automatically reduce the duty cycle switch to a minimum off time on every 8th cycle to allow this capacitor to
re-charge.
5.3.3.
Sense Feedback, FB (Pin #5)
This is the input terminal for the output voltage feedback. For the fixed-mode versions, this should be connected
directly to VOUT. The connection on the PCB should be kept as short as possible and should be made as close as
possible to the capacitor. The trace should not be shared with any other connection. For adjustable-mode
versions of the ZSPM4012B, this should be connected to the external resistor divider. To choose the resistors,
use the following equation:
VOUT = 0.9 (1 + RTOP/RBOT)
The input to the FB pin is high impedance, and input current should be less than 100nA. As a result, good layout
practices are required for the feedback resistors and feedback traces. When using the adjustable version, the
feedback trace should be kept as short and narrow as possible to reduce stray capacitance and the injection of
noise.
5.3.4.
Switching Output, VSW (Pins #12, 13)
This is the switching node of the regulator. It should be connected directly to the 4.7µH inductor with a wide, short
trace and to one end of the bootstrap capacitor. It switches between VCC and PGND at the switching frequency.
5.3.5.
Ground, GND (Pin #4)
This ground is used for the majority of the device including the analog reference, control loop, and other circuits.
5.3.6. Power Ground, PGND (Pins #14, 15)
This is a separate ground connection used for the low-side synchronous switch to isolate switching noise from the
rest of the device.
5.3.7.
Enable, EN (Pin #9)
This is the input terminal to activate the regulator. The input threshold is TTL/CMOS compatible. It also has an
internal pull-up to ensure a stable state if the pin is disconnected.
5.3.8.
PG Output, PG (Pin #8)
This is an open drain, active low output. See section 3.2.6 for a description of the function of this pin.
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
6
Ordering Information
Ordering Code
ZSPM4012BA1W00
Description
Package
2A Synchronous Buck Converter: adjustable output, 0.9V to 5.5V, 16-pin 3x3mm QFN
7” reel with 1000 ICs
ZSPM4012BA1W15
ZSPM4012BA1W18
ZSPM4012BA1W25
ZSPM4012BA1W33
ZSPM4012BA1W50
ZSPM4012BKIT
2A Synchronous Buck Converter: fixed output, 1.5V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 1.8V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 2.5V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 3.3V,16-pin 3x3mm QFN
2A Synchronous Buck Converter: fixed output, 5.0V,16-pin 3x3mm QFN
ZSPM4012B Evaluation Kit for 2A Synchronous Buck Converter
7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
7” reel with 1000 ICs
Kit
7
Related Documents
Document
ZSPM4012B Feature Sheet
ZSPM4012B Evaluation Kit Description
Visit IDT’s website www.IDT.com or contact your nearest sales office for the latest version of these documents.
8
Glossary
Term
Description
PWM
PFM
POR
ESR
Pulse width modulation (fixed frequency).
Pulse frequency modulation (fixed pulse width).
Power-on reset
Equivalent series resistance.
© 2016 Integrated Device Technology, Inc.
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ZSPM4012B Datasheet
9
Document Revision History
Revision
1.00
Date
April 2, 2013
June 21, 2013
Description
First release of ZSPM4012B, based on ZSPM4012, silicon revision A.
1.10
Update to allow for 5.5V output voltage, new transient response graph, addition of
thermal parameter for “Thermal Resistance Junction to Case (θJc)” specification, and
revision of “Thermal Resistance Junction to Ambient (θJA)” specification.
1.20
February 18, 2014 Revision of specifications for “Input Supply Under Voltage Threshold Hysteresis” in
Table 1.4.
January 27, 2016
Changed to IDT branding.
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specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The
information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an
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