ZSPM9010ZA1R_技术文档

ZSPM9010

Ultra-Compact, High-Performance

DrMOS Device

Datasheet

Brief Description

Features

The ZSPM9010 DrMOS is a fully optimized, ultra-

compact, integrated MOSFET plus driver power

stage solution for high-current, high-frequency, syn-

chronous buck DC-DC applications. The ZSPM9010

incorporates a driver IC, two power MOSFETs, and

a bootstrap Schottky diode in a thermally enhanced,

ultra-compact PQFN40 package (6mmx6mm).

•

Based on the Intel® 4.0 DrMOS standard

High-current handling: up to 50A

High-performance copper-clip package

Tri-state 3.3V PWM input driver

Skip Mode (low-side gate turn-off) input (SMOD#)

Warning flag for over-temperature conditions

Driver output disable function (DISB# pin)

With an integrated approach, the ZSPM9010’s com-

plete switching power stage is optimized for driver

and MOSFET dynamic performance, system induc-

tance, and power MOSFET R_DS(ON). It uses innova-

tive high-performance MOSFET technology, which

dramatically reduces switch ringing, eliminating the

snubber circuit in most buck converter applications.

Internal pull-up and pull-down for SMOD# and

DISB# inputs, respectively

•

Integrated Schottky diode technology in the

low-side MOSFET

•

Integrated bootstrap Schottky diode

Adaptive gate drive timing for shoot-through

protection

An innovative driver IC with reduced dead times and

propagation delays further enhances performance. A

thermal warning function (THWN) warns of potential

over-temperature situations. The ZSPM9010 also

incorporates features such as Skip Mode (SMOD)

for improved light-load efficiency with a tri-state 3.3V

pulse-width modulation (PWM) input for compatibility

with a wide range of PWM controllers.

•

Under-voltage lockout (UVLO)

Optimized for switching frequencies up to 1MHz

Available Support

•

ZSPM8010-KIT: Open-Loop Evaluation Board for

ZSPM9010

The ZSPM9010 DrMOS is compatible with IDT’s

ZSPM1000, a leading-edge configurable digital

power-management system controller for non-

isolated point-of-load (POL) supplies.

Physical Characteristics

•

Operation temperature: -40°C to +125°C

V_IN: 3V to 15V (typical 12V)

I_OUT: 40A (average), 50A (maximum)

Low-profile SMD package: 6mmx6mm PQFN40

IDT green packaging and RoHS compliant

Benefits

•

Fully optimized system efficiency: >93% peak

Clean switching waveforms with minimal ringing

72% space-saving compared to conventional

discrete solutions

Typical Application

•

Optimized for use with IDT’s ZSPM1000 true

digital PWM controller

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January 25, 2016

ZSPM9010

Ultra-Compact, High-Performance

DrMOS Device

Datasheet

ZSPM9010 Block Diagram

VDRV

BOOT

VIN

D_Boot

UVLO

10µA

VCIN

(Q1)

HS Power

MOSFET

GH

Logic

Level Shift

DISB#

GH

30k

Typical Applications

VCIN

PHASE

•

Telecom switches

Servers and storage

Desktop computers

Workstations

R_{UP_PWM}

Dead Time

Control

Input

Tri-State

Logic

PWM

VSWH

R_{DN_PWM}

VDRV

(Q2)

LS Power

MOSFET

GL

30k

GL

Logic

High-performance

gaming motherboards

THWN#

VCIN

GL

Temp

Sense

•

Base stations

Network routers

Industrial applications

10µA

CGND

SMOD#

PGND

Ordering Information

Product Sales Code Description

Package

Reel

ZSPM9010ZA1R

ZSPM8010-KIT

ZSPM9010 Lead-Free PQFN40 — Temperature range: -40°C to +125°C

Open-Loop Evaluation Board for ZSPM9010

Kit

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance

specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The

information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an

implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property

rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be

reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device

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January 25, 2016

ZSPM9010 Datasheet

Contents

1

IC Characteristics ............................................................................................................................................. 5

1.1. Absolute Maximum Ratings....................................................................................................................... 5

1.2. Recommended Operating Conditions ....................................................................................................... 6

1.3. Electrical Parameters ................................................................................................................................ 6

1.4. Typical Performance Characteristics......................................................................................................... 9

Functional Description.................................................................................................................................... 14

2.1. VDRV and Disable (DISB#)..................................................................................................................... 15

2.2. Thermal Warning Flag (THWN#)............................................................................................................. 16

2.3. Tri-State PWM Input................................................................................................................................ 16

2.4. Adaptive Gate Drive Circuit ..................................................................................................................... 18

2.5. Skip Mode (SMOD#) ............................................................................................................................... 18

2.6. PWM........................................................................................................................................................ 20

Application Design.......................................................................................................................................... 21

3.1. Supply Capacitor Selection ..................................................................................................................... 21

3.2. Bootstrap Circuit ...................................................................................................................................... 21

3.3. VCIN Filter ............................................................................................................................................... 21

3.4. Power Loss and Efficiency Testing Procedures...................................................................................... 22

Pin Configuration and Package...................................................................................................................... 24

4.1. Available Packages ................................................................................................................................. 24

4.2. Pin Description......................................................................................................................................... 25

4.3. Package Dimensions............................................................................................................................... 26

Circuit Board Layout Considerations.............................................................................................................. 27

Ordering Information ...................................................................................................................................... 28

Related Documents........................................................................................................................................ 29

Document Revision History............................................................................................................................ 29

2

3

4

5

6

7

8

List of Figures

Figure 1.1 Safe Operating Area........................................................................................................................... 9

Figure 1.2 Module Power Loss vs. Output Current.............................................................................................. 9

Figure 1.3 Power Loss vs. Switching Frequency................................................................................................. 9

Figure 1.4 Power Loss vs. Input Voltage ............................................................................................................. 9

Figure 1.5 Power Loss vs. Driver Supply Voltage ............................................................................................. 10

Figure 1.6 Power Loss vs. Output Voltage ........................................................................................................ 10

Figure 1.7 Power Loss vs. Output Inductance................................................................................................... 10

Figure 1.8 Driver Supply Current vs. Frequency ............................................................................................... 10

Figure 1.9 Driver Supply Current vs. Driver Supply Voltage............................................................................. 11

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January 25, 2016

ZSPM9010 Datasheet

Figure 1.10 Driver Supply Current vs. Output Current......................................................................................... 11

Figure 1.11 PWM Thresholds vs. Driver Supply Voltage..................................................................................... 11

Figure 1.12 PWM Thresholds vs. Temperature................................................................................................... 11

Figure 1.13 SMOD# Thresholds vs. Driver Supply Voltage................................................................................ 12

Figure 1.14 SMOD# Thresholds vs. Temperature............................................................................................... 12

Figure 1.15 SMOD# Pull-Up Current vs. Temperature........................................................................................ 12

Figure 1.16 Disable Thresholds vs. Driver Supply Voltage ................................................................................. 12

Figure 1.17 Disable Thresholds vs. Temperature................................................................................................ 13

Figure 1.18 Disable Pull-Down Current vs. Temperature.................................................................................... 13

Figure 2.1 Typical Application Circuit with PWM Control................................................................................... 14

Figure 2.2 ZSPM9010 Block Diagram ............................................................................................................... 15

Figure 2.3 Thermal Warning Flag (THWN) Operation....................................................................................... 16

Figure 2.4 PWM and Tri-State Timing Diagram................................................................................................. 17

Figure 2.5 SMOD# Timing Diagram................................................................................................................... 19

Figure 2.6 PWM Timing ..................................................................................................................................... 20

Figure 3.1 Power Loss Measurement Block Diagram ....................................................................................... 21

Figure 3.2 V_CINFilter Block Diagram.................................................................................................................. 22

Figure 4.1 Pin-out PQFN40 Package ................................................................................................................ 24

Figure 4.2 PQFN40 Physical Dimensions and Recommended Footprint..........................................................26

Figure 5.1 PCB Layout Example........................................................................................................................ 28

List of Tables

Table 2.1

Table 2.2

UVLO and Disable Logic .................................................................................................................. 15

SMOD# Logic.................................................................................................................................... 19

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January 25, 2016

ZSPM9010 Datasheet

1

IC Characteristics

1.1. Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. The device might not function or be operable above the

recommended operating conditions. Stresses exceeding the absolute maximum ratings might also damage the

device. In addition, extended exposure to stresses above the recommended operating conditions might affect

device reliability. IDT does not recommend designing to the “Absolute Maximum Ratings.”

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Maximum Voltage to CGND –

VCIN, VDRV, DISB#, PWM, SMOD#,

GL, THWN# pins

-0.3

6.0

V

Maximum Voltage to PGND or CGND –

VIN pin

-0.3

-8.0

25.0

6.0

V

Maximum Voltage to VSWH or PHASE –

BOOT, GH pins

Maximum Voltage to CGND –

BOOT, PHASE, GH pins

25.0

Maximum Voltage to CGND or PGND –

VSWH pin

DC only

< 20ns

Maximum Voltage to PGND – VSWH pin

Maximum Voltage to VDRV – BOOT pin

Maximum Sink Current – THWN# pin

25.0

22.0

7.0

V

-0.1

mA

I_THWN#

f_SW=300kHz, V_IN=12V,

V_OUT=1.0V

50

45

3.5

A

Maximum Average Output Current ¹⁾

I_OUT(AV)

f_SW=1MHz, V_IN=12V,

V_OUT=1.0V

A

°C/W

°C

Junction-to-PCB Thermal Resistance

Ambient Temperature Range

Maximum Junction Temperature

Storage Temperature Range

θ_JPCB

T_AMB

T_jMAX

T_STOR

-40

+125

+150

°C

-55

°C

Human Body Model, JESD22-

A114

2000

V

Electrostatic Discharge Protection

ESD

Charged Device Model,

JESD22-C101

1000

V

1)

I_OUT(AV)is rated using a DrMOS Evaluation Board, T_AMB= 25°C, natural convection cooling. This rating is limited by the peak

DrMOS temperature, T_jMAX= 150°C, and varies depending on operating conditions, PCB layout, and PCB board to ambient

thermal resistance.

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January 25, 2016

ZSPM9010 Datasheet

1.2. Recommended Operating Conditions

The “Recommended Operating Conditions” table defines the conditions for actual device operation. Recom-

mended operating conditions are specified to ensure optimal performance to the datasheet specifications. IDT

does not recommend exceeding them or designing to the “Absolute Maximum Ratings.”

PARAMETER

SYMBOL

V_CIN

CONDITIONS

MIN

4.5

3.0

TYP

5.0

MAX

5.5

UNITS

Control Circuit Supply Voltage

Gate Drive Circuit Supply Voltage

Output Stage Supply Voltage

V

V_DRV

5.0

5.5

V_IN

12.0

15.0

1.3. Electrical Parameters

Typical values are V_IN= 12V, V_DRV= 12V, and T_AMB= +25°C unless otherwise noted.

PARAMETER

Basic Operation

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Quiescent Current

I_Q

I_Q=I_{VCIN+ VDRV}

I

, PWM=LOW or

2

mA

HIGH or float

Under-Voltage Lock-Out

UVLO Threshold

UVLO

VCIN rising

2.9

3.1

0.4

3.3

V

UVLO Hysteresis

PWM Input

UVLO_{_Hyst}

Pull-Up Impedance

Pull-Down Impedance

R_{UP_PWM}

(VCIN = VDRV = 5V ±10%)

26

kΩ

V

R_{DN_PWM}(VCIN = VDRV = 5V ±10%)

12

(VCIN = VDRV = 5V ±10%)

V_{IH_PWM}

1.88

2.00

1.84

1.94

0.70

0.75

0.62

0.66

2.25

2.20

0.95

0.85

160

1.60

2.61

2.50

2.56

2.46

1.19

1.15

1.13

1.09

200

PWM High-Level Voltage

(VCIN = VDRV = 5V ±5%)

V

(VCIN = VDRV = 5V ±10%)

V_{TRI_HI}

V

Tri-state Upper Threshold

Tri-state Lower Threshold

(VCIN = VDRV = 5V ±5%)

V

V_{TRI_LO}

(VCIN = VDRV = 5V ±10%)

(VCIN = VDRV = 5V ±5%)

(VCIN = VDRV = 5V ±10%)

(VCIN = VDRV = 5V ±5%)

V

PWM Low-Level Voltage

V_{IL_PWM}

V

Tri-state Shutoff Time

Tri-state Open Voltage

t_{D_HOLD-OFF}

ns

V

V_{HiZ_PWM}(VCIN = VDRV = 5V ±10%)

(VCIN = VDRV = 5V ±5%)

1.40

1.45

1.90

1.80

V

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January 25, 2016

ZSPM9010 Datasheet

PARAMETER

DISB# Input

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

High-Level Input Voltage

Low-Level Input Voltage

Pull-Down Current

V_{IH_DISB#}

V_{IL_DISB#}

I_PLD

2

V

0.8

10

25

µA

ns

Propagation Delay DISB#, GL

Transition from HIGH to LOW

t_{PD_DISBL}

PWM=GND,

LSE=1

Propagation Delay DISB#, GL

Transition from LOW to HIGH

t_{PD_DISBH}

PWM=GND,

LSE=1

25

ns

SMOD# Input

High-Level Input Voltage

Low-Level Input Voltage

Pull-Up Current

V_{IH_SMOD#}

V_{IL_SMOD#}

I_PLU

2

V

0.8

10

µA

ns

Propagation Delay SMOD#, GL

Transition from HIGH to LOW

t_{PD_SLGLL}

PWM=GND,

DISB#=1

Propagation Delay SMOD#, GL

Transition from LOW to HIGH

t_{PD_SHGLH}PWM=GND,

DISB#=1

10

ns

Thermal Warning Flag

Activation Temperature

Reset Temperature

T_ACT

T_RST

150

135

30

°C

Ω

Pull-Down Resistance

250ns Timeout Circuit

R_THWN

I_PLD=5mA

Timeout Delay Between GH

Transition from HIGH to LOW

and GL Transition from LOW to

HIGH

t_{D_TIMEOUT}SW=0V

250

ns

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January 25, 2016

ZSPM9010 Datasheet

PARAMETER

High-Side Driver

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output Impedance, Sourcing

Output Impedance, Sinking

Rise Time for GH=10% to 90%

Fall Time for GH=90% to 10%

R_{SOURCE_GH}Source Current=100mA

R_{SINK_GH}Sink Current=100mA

t_{R_GH}

1

0.8

6

Ω

ns

t_{F_GH}

5

LS to HS Deadband Time: GL

going LOW to GH going HIGH,

1V GL to 10 % GH

t_{D_DEADON}

10

PWM LOW Propagation Delay:

PWM going LOW to GH going

LOW, V_{IL_PWM}to 90% GH

t_{PD_PLGHL}

16

30

ns

PWM HIGH Propagation Delay

with SMOD# Held LOW:

t_{PD_PHGHH}SMOD# = LOW

PWM going HIGH to GH going

HIGH, V_{IH_PWM}to 10% GH

Propagation Delay Exiting

Tri-state: PWM (from Tri-state)

going HIGH to GH going HIGH,

V_{IH_PWM}to 10% GH

t_{PD_TSGHH}

30

ns

Low-Side Driver

Output Impedance, Sourcing

Output Impedance, Sinking

Rise Time for GL = 10% to 90%

Fall Time for GL = 90% to 10%

R_{SOURCE_GL}Source Current=100mA

1

Ω

R_{SINK_GL}

t_{R_GL}

Sink Current=100mA

0.5

20

13

12

ns

t_{F_GL}

HS to LS Deadband Time:

SW going LOW to GL going

HIGH, 2.2V SW to 10% GL

t_{D_DEADOFF}

PWM-HIGH Propagation Delay:

PWM going HIGH to GL going

LOW, V_{IH_PWM}to 90% GL

t_{PD_PHGLL}

9

25

ns

Propagation Delay Exiting

Tri-state: PWM (from Tri-state)

going LOW to GL going HIGH,

V_{IL_PWM}to 10% GL

t_{PD_TSGLH}

20

Boot Diode

Forward-Voltage Drop

Breakdown Voltage

V_F

V_R

I_F=10mA

I_R=1mA

0.35

V

22

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January 25, 2016

ZSPM9010 Datasheet

1.4. Typical Performance Characteristics

Test conditions: V_IN=12V, V_OUT=1.0V, V_CIN=5V, V_DRV=5V, L_OUT=320nH, T_AMB=25°C, and natural convection cool-

ing, unless otherwise specified.

Figure 1.1

Safe Operating Area

Figure 1.2

Module Power Loss vs. Output Current

Figure 1.4

Power Loss vs. Input Voltage

Figure 1.3

Power Loss vs. Switching Frequency

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January 25, 2016

ZSPM9010 Datasheet

Figure 1.5

Power Loss vs. Driver Supply Voltage

Figure 1.6

Power Loss vs. Output Voltage

1.10

I_OUT= 30A, f_SW= 300kHz

1.05

1.00

0.95

0.90

4.50

4.75

5.00

5.25

5.50

Driver Supply Voltage, V_DRVand V_CIN(V)

Figure 1.7

1.06

Power Loss vs. Output Inductance

Figure 1.8

Driver Supply Current vs. Frequency

50

45

40

35

30

25

20

15

10

I_OUT= 30A, f_SW= 300kHz

I_OUT= 0A

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

5

200

300

400

500

600

700

800

900

1000

225

275

325

375

425

Output Inductance, L_OUT(nH)

Module Switching Frequency, f_SW(kHz)

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January 25, 2016

ZSPM9010 Datasheet

Figure 1.10 Driver Supply Current vs. Output

Current

Figure 1.9

Driver Supply Current vs. Driver

Supply Voltage

.

17

I_OUT= 0A, f_SW= 300kHz

16

15

14

13

12

4.50

4.75

5.00

5.25

5.50

Driver Supply Voltage, V_DRVand V_CIN(V)

Figure 1.11 PWM Thresholds vs. Driver Supply

Voltage

Figure 1.12 PWM Thresholds vs. Temperature

3.0

V_CIN= 5V

3.0

T_A= 25°C

2.5

2.0

1.5

1.0

0.5

0.0

V_{IH_PWM}

V_{TRI_HI}

2.5

V_{IH_PWM}

2.0

V_{TRI_HI}

V_{HiZ_PWM}

1.5

1.0

0.5

0.0

V_{TRI_LO}

V_{IL_PWM}

-50

-25

0

25

50

75

100

125

150

Driver IC Junction Temperature, T_J(^oC)

4.50

4.75

5.00

5.25

5.50

Driver Supply Voltage, V_CIN(V)

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January 25, 2016

ZSPM9010 Datasheet

Figure 1.13 SMOD# Thresholds vs. Driver

Figure 1.14 SMOD# Thresholds vs. Temperature

Supply Voltage

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

2.2

V_CIN= 5V

T_A= 25°C

2.0

1.8

1.6

1.4

1.2

V_{IH_SMOD}

V_{IL_SMOD}

4.50

4.75

5.00

5.25

5.50

-50

-25

0

25

50

75

100

125

150

Driver IC Junction Temperature (^oC)

Driver Supply Voltage, V_CIN(V)

Figure 1.16 Disable Thresholds vs. Driver

Supply Voltage

Figure 1.15 SMOD# Pull-Up Current vs.

Temperature

2.00

V_CIN= 5V

-9.0

V_CIN= 5V

1.90

-9.5

-10.0

-10.5

-11.0

-11.5

-12.0

1.80

V_{IH_DISB}

1.70

1.60

V_{IL_DISB}

1.50

1.40

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Driver IC Junction Temperature, T_J(°C)

Driver IC Junction Temperature, T_J(^oC)

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January 25, 2016

ZSPM9010 Datasheet

Figure 1.17 Disable Thresholds vs. Temperature

Figure 1.18 Disable Pull-Down Current vs.

Temperature

2.1

T_A= 25^oC

2.0

V_{IH_DISB}

1.9

1.8

1.7

V_{IL_DISB}

1.6

1.5

1.4

1.3

4.50

4.75

5.00

5.25

5.50

Driver Supply Voltage, V_CIN(V)

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January 25, 2016

ZSPM9010 Datasheet

2

Functional Description

The ZSPM9010 is a driver-plus-FET module optimized for the synchronous buck converter topology. A single

PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. It is capable of

driving speeds up to 1MHz.

Figure 2.1

Typical Application Circuit with PWM Control

Open Drain Output

THWN#

VIN

V_IN=3V to 15V

C_VIN

TEMP

SENSE

V_5V= 4.5V to 5.5V

D_Boot

VDRV

VCIN

CGND

BOOT

C_VDRV

R_BOOT

(Q1)

HDRV

HS Power

MOSFET

C_BOOT

L_OUT

V_OUT

PHASE

VSWH

PWM

SMOD#

DISB#

C_OUT

ZSPM9010

PWM

CONTROL

VC_IN

Enabled

OFF

(Q2)

LS Power

MOSFET

LDRV

Disabled

ON

CGND

PGND

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January 25, 2016

ZSPM9010 Datasheet

Figure 2.2

ZSPM9010 Block Diagram

VDRV

BOOT

VIN

D_Boot

UVLO

VCIN

(Q1)

HS Power

MOSFET

GH

Logic

Level Shift

DISB#

GH

10µA

30k

VCIN

PHASE

R_{UP_PWM}

Dead Time

Control

Input

Tri-State

Logic

PWM

VSWH

R_{DN_PWM}

VDRV

(Q2)

LS Power

MOSFET

GL

30k

GL

Logic

THWN#

VCIN

GL

Temp

Sense

10µA

CGND

SMOD#

PGND

2.1. VDRV and Disable (DISB#)

The VCIN pin is monitored by an under-voltage lockout (UVLO) circuit. When V_CINrises above ~3.1V, the driver is

enabled. When V_CINfalls below ~2.7V, the driver is disabled (GH, GL= 0; see Figure 2.2 and section 4.2). The

driver can also be disabled by pulling the DISB# pin LOW (DISB# < V_{IL_DISB}), which holds both GL and GH LOW

regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# >

V

_{IH_DISB}).

Table 2.1

Note: DISB# internal pull-down current source is 10µA (typical).

UVLO and Disable Logic

UVLO

DISB#

Driver State

0

1

X

0

Disabled (GH=0, GL=0)

Enabled (see Table 2.2 )

Disabled (GH=0, GL=0)

1

Open

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January 25, 2016

ZSPM9010 Datasheet

2.2. Thermal Warning Flag (THWN#)

The ZSPM9010 provides a thermal warning flag (THWN#) to indicate over-temperature conditions. The thermal

warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached.

The THWN# output returns to the high-impedance state once the temperature falls to the reset temperature

(135°C). For use, the THWN# output requires a pull-up resistor, which can be connected to VCIN. Note that

THWN# does NOT disable the DrMOS module.

Figure 2.3

Thermal Warning Flag (THWN) Operation

Reset

Activation

Temperature Temperature

High

Normal

Operation

Thermal

Warning

Low

135°C

150°C

T_{J_driverIC}

2.3. Tri-State PWM Input

The ZSPM9010 incorporates a tri-state 3.3V PWM input gate drive design. The tri-state gate drive has both logic

HIGH level and LOW level, along with a tri-state shutdown voltage window. When the PWM input signal enters and

remains within the tri-state voltage window for a defined hold-off time (t_{D_HOLD-OFF}), both GL and GH are pulled

LOW. This feature enables the gate drive to shut down both high and low side MOSFETs using only one control

signal. For example, this can be used for phase shedding in multi-phase voltage regulators.

When exiting a valid tri-state condition, the ZSPM9010 follows the PWM input command. If the PWM input goes

from tri-state to LOW, the low-side MOSFET is turned on. If the PWM input goes from tri-state to HIGH, the high-

side MOSFET is turned on, as illustrated in Figure 2.4. The ZSPM9010’s design allows for short propagation

delays when exiting the tri-state window (see section 1.3).

16

January 25, 2016

ZSPM9010 Datasheet

Figure 2.4

PWM and Tri-State Timing Diagram

V

IH_PWM

V IH_PWM

V

IH_PWM

V

IH_PWM

TRI_HI

V

TRI_HI

t_HOLD-OFF

V_{IL_PWM}

V

TRI_LO

V

IL_PW

IL_PWM

F_GHS

t_{R_GH}

t

GH

_

t_F

PWM

90%

10%

GH

to

SWH

V

VIN

DCM

CCM

DCM

V

OUT

2.2V

VSWH

GL

t

R_GL

t

F_GL

90%

1.0V

90%

10%

1

0%

t

PD_PHGLL

t

PD_PLGHL

t

PD_TSGHH

Exit

t

HOLD-OFF

t

PD_TSGHH

t

HOLD-OFF

t

PD_TSGLH

t

D_DEADON

t

D_DEADOFF

Enter

Exit

Enter

Tri-state Tri-state

3-state 3- state

Exit

Enter

Exit

Enter

3-state

3- state

Tri-state

Notes:

t_{PD_xxx}

t_{D_xxx}

= Propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal; example: t_{PD_PHGLL}= PWM going HIGH to LS V_GS(GL) going LOW

= Delay from IC generated signal to IC generated signal; example: t_{D_DEADON}= LS V_GSLOW to HS V_GSHIGH

PWM

Exiting Tri-state

t_{PD_PHGLL}= PWM rise to LS V_GSfall, V_{IH_PWM}to 90% LS V_GS

t_{PD_TSGHH}

t_{PD_TSGLH}

= PWM tri-state to HIGH to HS V_GSrise, V_{IH_PWM}to 10% HS V_GS

= PWM tri-state to LOW to LS V_GSrise, V_{IL_PWM}to 10% LS V_GS

t_{PD_PLGHL}= PWM fall to HS V_GSfall, V_{IL_PWM}to 90% HS V_GS

t_{PD_PHGHH}= PWM rise to HS V_GSrise, V_{IH_PWM}to 10% HS V_GS(assumes SMOD held Low)

SMOD (See Figure 2.5)

Dead Times

t_{PD_SLGLL}= SMOD fall to LS V_GSfall, 90% to 90% LS V_GS

t_{PD_SHGLH}= SMOD rise to LS V_GSrise, 10% to 10% LS V_GS

t_{D_DEADON}= LS V_GSfall to HS V_GSrise, LS-comp trip value to 10% HS V_GS

t_{D_DEADOFF}= VSWH fall to LS V_GSrise, SW-comp trip value to 10% LS V_GS

17

January 25, 2016

ZSPM9010 Datasheet

2.4. Adaptive Gate Drive Circuit

The low-side driver (GL) is designed to drive a ground-referenced low R_DS(ON)N-channel MOSFET. The bias for

GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out

of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW.

The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver

is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap

capacitor (C_BOOT). During startup, the VSWH pin is held at PGND, allowing C_BOOT(see section 3.2) to charge to

V_DRVthrough the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of Q1, the high-

side MOSFET. During this transition, the charge is removed from C_BOOTand delivered to the gate of Q1. As Q1

turns on, V_SWHrises to V_IN, forcing the BOOT pin to V_IN+ V_BOOT, which provides sufficient V_GSenhancement for

Q1.

To complete the switching cycle, Q1 is turned off by pulling GH to V_SWH. C_BOOTis then recharged to V_DRVwhen

V_SWHfalls to PGND. The GH output is in-phase with the PWM input. The high-side gate is held LOW when the

driver is disabled or the PWM signal is held within the tri-state window for longer than the tri-state hold-off time,

t_{D_HOLD-OFF}

.

The driver IC design ensures minimum MOSFET dead time while eliminating potential shoot-through (cross-

conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to prevent

simultaneous conduction. Figure 2.4 provides the relevant timing waveforms. To prevent overlap during the LOW-

to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the

PWM signal goes HIGH, Q2 begins to turn off after a propagation delay (t_{PD_PHGLL}). Once the GL pin is discharged

below ~1V, Q1 begins to turn on after adaptive delay t_{D_DEADON}

.

To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the

voltage at the VSWH pin. When the PWM signal goes LOW, Q1 begins to turn off after a propagation delay

(t_{PD_PLGHL}). Once the VSWH pin falls below approx. 2.2V, Q2 begins to turn on after adaptive delay t_{D_DEADOFF}

.

V_GS(Q1)is also monitored. When V_GS(Q1)is discharged below approx. 1.2V, a secondary adaptive delay is initiated

that results in Q2 being driven on after t_{D_TIMEOUT}, regardless of VSWH state. This function is implemented to

ensure C_BOOTis recharged each switching cycle in the event that the VSWH voltage does not fall below the 2.2V

adaptive threshold. Secondary delay t_{D_TIMEOUT}is longer than t_{D_DEADOFF}

.

2.5. Skip Mode (SMOD#)

The SMOD function allows higher converter efficiency under light-load conditions. During SMOD, the low-side

FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor

current attempts reverse current flow – also known as Diode Emulation Mode.

When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode

allows gating on the low-side FET. When the SMOD# pin is pulled LOW, the low-side FET is gated off. See the

timing diagram in Figure 2.5. If the SMOD# pin is connected to the PWM controller, the controller can actively

enable or disable SMOD when the controller detects light-load operation.

18

January 25, 2016

ZSPM9010 Datasheet

Table 2.2

SMOD# Logic

Note: The SMOD feature is intended to have a low propagation delay between the SMOD signal and the low-side FET V_GSresponse time to

control diode emulation on a cycle-by-cycle basis.

DISB#

PWM

SMOD#

GH

0

GL

0

1

X

0

1

Tri-State

0

1

0

1

0

1

0

1

0

Figure 2.5

SMOD# Timing Diagram

See Figure 2.4 for the definitions of the timing parameters.

SMOD#

V_{IH_SMOD}

V_{IL_SMOD}

V_{IH_PWM}

V_{IL_PWM}

PWM

90%

GH

to

SW

10%

DCM

V_OUT

CCM

2.2V

SW

GL

90%

2.2V

10%

t_{PD_PLGHL}

t_{PD_PHGLL}

t_{PD_PHGHH}

t_{PD_SHGLH}

t_{PD_SLGLL}

t_{D_DEADOFF}

t_{D_DEADON}

Delay from SMOD# going

LOW to LS V_GSLOW

Delay from SMOD# going

HIGH to LS V_GSHIGH

HS turn-on with SMOD# LOW

19

January 25, 2016

ZSPM9010 Datasheet

2.6. PWM

Figure 2.6

PWM Timing

V _{IH_PWM}

V_{IL_PWM}

PWM

GL

90%

1.0V

10%

90%

GH

to

SW

1.2V

10%

t_{D_TIMEOUT}

250ns Timeout)

(

2.2V

SW

t_{PD_PLGHL}

t_{PD_PHGLL}

t_{D_DEADOFF}

t_{D_DEADON}

20

January 25, 2016

ZSPM9010 Datasheet

3

Application Design

3.1. Supply Capacitor Selection

For the supply inputs (VDRV and VCIN), a local ceramic bypass capacitor is required to reduce noise and is used

to supply the peak transient currents during gate drive switching action. Recommendation: use at least a 1µF

capacitor with an X7R or X5R dielectric. Keep this capacitor close to the VCIN and VDRV pins and connect it to

the CGND ground plane with vias.

3.2. Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C_BOOT), as shown in Figure 3.1. A bootstrap capacitance of

100nF X7R or X5R capacitor is typically adequate. A series bootstrap resistor may be needed for specific

applications to improve switching noise immunity. The boot resistor may be required when operating near the

maximum rated V_INand is effective at controlling the high-side MOSFET turn-on slew rate and V_SWHovershoot.

Typical R_BOOTvalues from 0.5Ω to 2.0Ω are effective in reducing V_SWHovershoot.

3.3. VCIN Filter

The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFETs. In most cases,

VDRV can be connected directly to VCIN, which supplies power to the logic circuitry of the gate driver. For additional

noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommendation: use a 10Ω resistor (R_VCIN

)

between VDRV and VCIN and a 1µF capacitor (C_VCIN) from VCIN to CGND (see Figure 3.2).

Figure 3.1

Power Loss Measurement Block Diagram

Open Drain Output

VIN

A

I_IN

THWN#

V_IN

C_VIN

I_5V

V_5V

VDRV

VCIN

A

BOOT

C_VDRV

R_BOOT

C_BOOT

ZSPM9010

I_OUT

V_OUT

L_OUT

PWM

SMOD#

DISB#

PWM Input

A

PHASE

VSWH

OFF

ON

C_OUT

DISB

V_SW

v

PGND

CGND

21

January 25, 2016

ZSPM9010 Datasheet

Figure 3.2

V_CINFilter Block Diagram

Note: Blue lines indicate the optional recommended filter.

Open Drain Output

VIN

A

I_IN

THWN#

V_IN

C_VIN

I_5V

V_5V

VDRV

A

BOOT

R_VCIN

C_VDRV

R_BOOT

VCIN

C_VCIN

C_BOOT

ZSPM9010

I_OUT

V_OUT

L_OUT

PWM

SMOD#

DISB#

PWM Input

A

PHASE

VSWH

OFF

ON

C_OUT

DISB

V_SW

v

PGND

CGND

3.4. Power Loss and Efficiency Testing Procedures

The circuit in Figure 3.1 has been used to measure power losses. The efficiency has been calculated based on

the equations below.

Power loss calculations:

P

=

(

V_IN∗I_IN

)

+

(

V_5V∗I_5V

)

(1)

(2)

IN

P_SW

=

(

V_SW∗I_OUT

)

P_OUT

=

(

V_OUT∗I_OUT

)

(3)

(4)

(5)

P_{LOSS_MODULE}

=

(

P −P_SW

)

IN

P_{LOSS_BOARD}

=

(

P −P_OUT

)

IN

22

January 25, 2016

ZSPM9010 Datasheet

Efficiency calculations:





P_SW





EFF_MODULE= 100∗

%

(6)

(7)





P

IN







P_OUT





EFF_BOARD= 100∗





P

IN



23

January 25, 2016

ZSPM9010 Datasheet

4

Pin Configuration and Package

4.1. Available Packages

The ZSPM9010 is available in a 40-lead clip-bond PQFN package. The pin-out is shown in Figure 4.1. See

Figure 4.2 for the mechanical drawing of the package.

Figure 4.1

Pin-out PQFN40 Package

1

2

3

4

5

6

7

8

9

10

9

8

7

6

5

4

3

2

1

PWM

VIN

PWM

DISB#

THWN

CGND

GL

VIN

DISB#

THWN

CGND

GL

CGND

41

VIN

42

VIN

42

CGND

41

VIN

VSWH

PGND

VSWH

PGND

VSWH

43

VSWH

43

21 22 23 24 25 26 27 28 29 30

30 29 28 27 26 25 24 23 22 21

Top View

Bottom View

24

January 25, 2016

ZSPM9010 Datasheet

4.2. Pin Description

Name

Description

When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,

1

SMOD# the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add

a noise filter capacitor.

2

3

VCIN

IC bias supply. A 1µF (minimum) ceramic capacitor is recommended from this pin to CGND.

Power for gate driver. A 1µF (minimum) X5R/X7R ceramic capacitor from this pin to CGND is

recommended. Place it as close as possible to this pin.

VDRV

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a

bootstrap capacitor from this pin to PHASE.

4

BOOT

5, 37, 41

CGND

GH

IC ground. Ground return for driver IC.

6

7

Gate high. For manufacturing test only. This pin must float: it must not be connected.

PHASE Switch node pin for bootstrap capacitor routing; electrically shorted to VSWH pin.

No connection. The pin is not electrically connected internally but can be connected to VIN for

convenience.

8

NC

9 - 14, 42

VIN

Input power voltage (output stage supply voltage).

Switch node. Provides return for high-side bootstrapped driver and acts as a sense point for

the adaptive shoot-through protection.

15, 29 - 35, 43

VSWH

16 – 28

36

PGND

GL

Power ground (output stage ground). Source pin of the low-side MOSFET.

Gate low. For manufacturing test only. This pin must float. It must not be connected.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the

output is pulled LOW. THWN# does not disable the module.

38

THWN#

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are

held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter

capacitor.

39

40

DISB#

PWM

PWM signal input. This pin accepts a tri-state 3.3V PWM signal from the controller.

25

January 25, 2016

ZSPM9010 Datasheet

4.3. Package Dimensions

Figure 4.2

PQFN40 Physical Dimensions and Recommended Footprint

B

PIN#1

0.10 C

INDICATOR

6.00

2X

5.80

4.50

A

30

21

31

20

11

6.00

2.50

1.60

0.40

0.65

0.25

0.10 C

40

2X

1

0.50 TYP

10

TOP VIEW

0.60

0.35

SEE

DETAIL 'A'

0.15

2.10

LAND PATTERN

RECOMMENDATION

FRONT VIEW

4.40±0.10

(2.20)

0.10

0.05

C A B

C

0.30

0.40

(40X)

0.20

31

21

30

20

0.50

2.40±0.10

(0.70)

0.20

PIN #1 INDICATOR

0.50

1.50±0.10

40

(40X)

0.30

11

10

1

0.40

2.00±0.10

0.50

(0.20)

2.00±0.10

(0.20)

NOTES: UNLESS OTHERWISE SPECIFIED

BOTTOM VIEW

A) DOES NOT FULLY CONFORM TO JEDEC

REGISTRATION MO-220, DATED

MAY/2005.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH. MOLD FLASH OR

BURRS DOES NOT EXCEED 0.10MM.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M-1994.

1.10

0.90

0.10 C

0.08 C

0.30

0.20

0.05

0.00

E) DRAWING FILE NAME: PQFN40AREV2

C

SEATING

PLANE

DETAIL 'A'

SCALE: 2:1

26

January 25, 2016

ZSPM9010 Datasheet

5

Circuit Board Layout Considerations

Figure 5.1 provides an example of a proper layout for the ZSPM9010 and critical components. All of the high-

current paths, such as the V_IN, V_SWH, V_OUT, and GND copper traces, should be short and wide for low inductance

and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced

heat radiation and system performance.

The following guidelines are recommendations for the printed circuit board (PCB) designer:

1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-

current power loop inductance and the input current ripple induced by the power MOSFET switching

operation.

2. The V_SWHcopper trace serves two purposes. In addition to being the high-frequency current path from the

DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS

package. The trace should be short and wide enough to present a low-impedance path for the high-

frequency, high-current flow between the DrMOS and inductor to minimize losses and temperature rise. Note

that the VSWH node is a high-voltage and high-frequency switching node with a high noise potential. Care

should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for

the lower FET, the designer must balance using the largest area possible to improve DrMOS cooling with

maintaining acceptable noise emission.

3. Locate the output inductor close to the ZSPM9010 to minimize the power loss due to the VSWH copper trace.

Care should also be taken so the inductor dissipation does not heat the DrMOS.

4. The power MOSFETs used in the output stage are effective for minimizing ringing due to fast switching. In

most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and

PGND pins. The resistor and capacitor must be the proper size for the power dissipation.

5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the respective pins to ensure

clean and stable power. Routing width and length should be considered as well.

6. Include a trace from PHASE to VSWH to improve the noise margin. Keep the trace as short as possible.

7. The layout should include a placeholder to insert a small-value series boot resistor (R_BOOT) between the boot

capacitor (C_BOOT) and DrMOS BOOT pin. The BOOT-to-VSWH loop size, including R_BOOTand C_BOOT, should

be as small as possible. The boot resistor may be required when operating near the maximum rated V_IN. The

boot resistor is effective for controlling the high-side MOSFET turn-on slew rate and VSWH overshoot. R_BOOT

can improve the noise operating margin in synchronous buck designs that might have noise issues due to

ground bounce or high positive and negative VSWH ringing. However, inserting a boot resistance lowers the

DrMOS efficiency. Efficiency versus noise trade-offs must be considered. R_BOOTvalues from 0.5Ω to 2.0Ω are

typically effective in reducing VSWH overshoot.

8. The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If

possible, these pins should be connected directly to the VIN and board GND planes. Important: the use of

thermal relief traces in series with these pins is discouraged since this adds inductance to the power path.

Added inductance in series with the VIN or PGND pin degrades system noise immunity by increasing positive

and negative VSWH ringing.

9. Connect the CGND pad and PGND pins to the GND plane copper with multiple vias for stable grounding.

Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead

to faulty operation of the gate driver and MOSFETs.

27

January 25, 2016

ZSPM9010 Datasheet

10. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add a

capacitor from BOOT to ground; this may lead to excess current flow through the BOOT diode.

11. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. Do NOT

float these pins if avoidable. These pins should not have any noise filter capacitors.

12. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current

flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-

frequency components, such as R_BOOT, C_BOOT, the RC snubber, and the bypass capacitors should be located

as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible,

they should be connected from the backside through a network of low-inductance vias.

Figure 5.1

PCB Layout Example

Top View

Bottom View

6

Ordering Information

Product Sales Code Description

Package

Reel

ZSPM9010ZA1R

ZSPM8010-KIT

ZSPM9010 Lead-Free PQFN40 — Temperature range: -40°C to +125°C

Open-Loop Evaluation Board for ZSPM9010

Kit

28

January 25, 2016

ZSPM9010 Datasheet

7


型号：	ZSPM9010ZA1R
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Ultra-Compact, High-Performance DrMOS Device 服务器主板节能技术
文件：	总29页 (文件大小：851K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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