概述
数据手册IN74HC125AD 概述
Quad 3-State Noninverting Buffers 四路三态同相缓冲器
IN74HC125AD 数据手册
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PDF下载TECHNICAL DATA
IN74HC125A
Quad 3-State Noninverting Buffers
The IN74HC125A is identical in pinout to the LS/ALS125. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
The IN74HC125A noninverting buffers are designed to be used with 3-
state memory address drivers, clock drivers, and other bus-oriented systems.
The devices have four separate output enables that are active-low.
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HC125AN Plastic
High Noise Immunity Characteristic of CMOS Devices
IN74HC125AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
OE
Output
A
H
L
Y
H
L
Z
PIN 14 =VCC
PIN 7 = GND
L
L
H
X
X = don’t care
Z = high impedance
Rev. 00
IN74HC125A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±35
DC Supply Current, VCC and GND Pins
±75
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
VCC
VIN, VOUT
TA
V
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
Rev. 00
IN74HC125A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85 ≤125
°C
°C
-55°C
Minimum High-
Level Input Voltage
VOUT= VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High-
Level Output Voltage
VIN=VIH
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA
VOL
Maximum Low-
Level Output Voltage
VIN=VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIL
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
IOZ
Maximum Three-
State Leakage
Current
Output in High-Impedance
State
VIN=VIL or VIH
VIN=VCC or GND
6.0
±0.5
±5.0
±10
ICC
Maximum Quiescent VIN=VCC or GND
6.0
4.0
40
160
µA
Supply Current
(per Package)
I
OUT=0µA
Rev. 00
IN74HC125A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
Unit
ns
25 °C
to
≤85°C ≤125°C
-55°C
tPLH, tPHL Maximum Propagation Delay, Input A to
Output Y (Figures 1 and 3)
2.0
4.5
6.0
90
18
15
115
23
135
27
20
23
tPLZ, tPHZ Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
ns
tPZL, tPZH Maximum Propagation Delay, Output Enable toY
(Figures 2 and 4)
2.0
4.5
6.0
90
18
15
115
23
20
135
27
23
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Buffer)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
45
pF
PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Rev. 00
IN74HC125A
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
Rev. 00
IN74HC125A
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
8
7
14
1
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
-T-
SEATING
PLANE
N
0
°
10
°
M
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
Symbol
MIN
8.55
3.8
MAX
8.75
4
A
B
C
D
F
H
B
P
1.35
0.33
0.4
1.75
0.51
1.27
1
7
G
R x 45
C
1.27
5.27
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0°
8°
0.25 (0.010) M
T
M
C
0.1
0.25
0.25
6.2
K
M
P
NOTES:
0.19
5.8
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
Rev. 00
IN74HC125AD 相关器件
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| IN74HC125AN | INTEGRAL | Quad 3-State Noninverting Buffers High-Performance Silicon-Gate CMOS | 获取价格 |
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| IN74HC125AN | IKSEMICON | Quad 3-State Noninverting Buffers | 获取价格 |
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| IN74HC132AN | INTEGRAL | QUAD 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS High-Performance Silicon-Gate CMOS | 获取价格 |
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| IN74HC132AN | IKSEMICON | Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High-Performance Silicon-Gate CMOS | 获取价格 |
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