1EDI20I12SV [INFINEON]
1200 V single high-side gate driver IC with galvanic isolation, slew-rate control, DESAT, soft over-current shutdown and two-level turn-off;
| 型号： | 1EDI20I12SV |
| 厂家： | 
Infineon |
| 描述： | 1200 V single high-side gate driver IC with galvanic isolation, slew-rate control, DESAT, soft over-current shutdown and two-level turn-off |
| 文件： | 总34页 (文件大小：1331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™
High voltage gate driver IC
1EDS-SRC family
Real-time adjustable gate current control IC
1EDS20I12SV
1EDU20I12SV
1EDI20I12SV
EiceDRIVER™
Final datasheet
<Revision 2.3>, 31.1.2020
Industrial Power Control
Edition 31.1.2020
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2020 Infineon Technologies AG
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
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The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
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completeness of the product information given in this document with respect to such application.
Please note that this product is not qualified according to the AEC Q100 or AEC Q101 documents of the
Automotive Electronics Council.
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
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personal injury.
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 2.3>, 31.1.2020
5.2 Added clause regarding VDE 0884-10 quarterly monitoring..
all
Changed isolation characteristics regarding VDE 0884-10 expiration date. Product and
testing remain unchanged.
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™,
CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™,
PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™,
SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by
AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2010-10-26
Final datasheet
3
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Table of Contents
1
Block diagram.....................................................................................................................................7
2
2.1
2.2
Pin configuration, description, and functionality ...........................................................................8
Terminal configuration..........................................................................................................................8
Terminal functionality ...........................................................................................................................9
3
3.1
3.2
3.2.1
3.2.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
Functional description.....................................................................................................................13
Introduction.........................................................................................................................................13
IC Supply............................................................................................................................................13
Input side............................................................................................................................................14
Output side.........................................................................................................................................14
Non-inverting and inverting input terminals INP and INN ..................................................................14
Driver output terminal ON ..................................................................................................................14
SPEED setting....................................................................................................................................15
Preboost setting .................................................................................................................................16
Gate turn-off terminal OFF.................................................................................................................16
Terminal EN .......................................................................................................................................17
Protection and diagnosis features......................................................................................................17
Undervoltage lockout (UVLO) ............................................................................................................17
Ready and status output terminals.....................................................................................................17
Fault indication (terminal /FLT) ..........................................................................................................18
Watchdog ...........................................................................................................................................18
I/O signature check ............................................................................................................................18
Two-level turn-off (TLTO)...................................................................................................................19
Desaturation shut down protection.....................................................................................................19
IGBT overcurrent detection................................................................................................................19
Overcurrent protection ON/OFF.........................................................................................................20
Soft turn-off.........................................................................................................................................20
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Electrical parameters.......................................................................................................................21
Absolute maximum ratings.................................................................................................................21
Operating range .................................................................................................................................22
Electrical characteristics.....................................................................................................................23
Voltage supply....................................................................................................................................23
Logic input and output........................................................................................................................24
Gate driver..........................................................................................................................................24
Desaturation protection ......................................................................................................................26
Overcurrent protection disable...........................................................................................................26
Current sense.....................................................................................................................................26
Two-level turn-off................................................................................................................................27
5
5.1
5.2
Insulation characteristics................................................................................................................28
Tested according to VDE 0884-10 (Standard expired on Dec. 31, 2019, 1EDS20I12SV only) ........28
Recognized under UL 1577 (File E311313, 1EDS20I12SV and 1EDU20I12SV only).....................28
6
Timing diagrams...............................................................................................................................29
7
Package.............................................................................................................................................32
7.1
PG-DSO-36-64...................................................................................................................................32
Final datasheet
4
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Block diagram for the 1EDS-SRC family .............................................................................................7
Terminal configuration of the 1EDS-SRC family (Top View) ...............................................................8
Typical application..............................................................................................................................13
Timing diagram for turn-on.................................................................................................................15
External circuit for setting of preboost current (left: unipolar supply; right: bipolar supply) ...............16
I/O signature check ............................................................................................................................18
Timing of turn-on and turn-off propagation delay without two-level turn-off mode ............................29
Timing of EN turn-on and shut down propagation delay....................................................................29
Timing of short pulse suppression terminal INP and SIGI (TP < TFILIN)..............................................29
Figure 10 Timing of short pulse suppression terminal INN (TP < TFILIN).............................................................29
Figure 11 Timing of short pulse suppression terminal EN (TP < TFILIN) ..............................................................30
Figure 12 Timing for fault reset at terminal EN...................................................................................................30
Figure 13 Timing of CS events incl. terminals SOFF, /FLT and EN...................................................................30
Figure 14 Timing for DESAT events incl. terminals SOFF, /FLT and EN (timing is same for related INN input
signal).................................................................................................................................................31
Figure 15 Timing for two-level turn-off incl. terminals CZ and OFF (top: TTLSET < TTLLIM, bottom: TTLSET > TTLLIM)31
Figure 16 Package drawing................................................................................................................................32
Figure 17 PCB reference layout (left: top layer, right: bottom layer)..................................................................33
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Terminal Description ............................................................................................................................8
Switching speed levels on input and output side ...............................................................................16
Driver IC status for EN, INP, and INN................................................................................................17
Driver IC status UVLO at VCC1, VCC2 and PADP (EN = high)........................................................18
Abs. maximum ratings........................................................................................................................21
Operating parameters ........................................................................................................................22
Voltage supply....................................................................................................................................23
Logic input and output........................................................................................................................24
Gate driver..........................................................................................................................................24
Desaturation protection......................................................................................................................26
Overcurrent protection disable...........................................................................................................26
Current sense.....................................................................................................................................26
Two-level turn-off................................................................................................................................27
Insulation characteristics....................................................................................................................28
Tested for reinforced isolation limits according to VDE 0884-10 (Standard expired on Dec. 31,
2019, 1EDS20I12SV only) .................................................................................................................28
Recognized under UL 1577 ...............................................................................................................28
Table 16
Final datasheet
5
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
EiceDRIVER™
1EDS20I12SV
Real-time adjustable gate current control IC
1EDU20I12SV
1EDI20I12SV
Main features
Single-channel isolated IGBT Driver
Supports IGBT up to 1200 V
IGBT off-state: 2 A pull down to rail
Overcurrent protection for sense IGBTs and conventional IGBTs
Desaturation detection
Soft turn-off shut down: 1 A pull down to rail
Two-level turn-off
Operation at high ambient temperature up to 105°C
Compatible PWM inputs for 3.3 V, 5 V, and 15 V logic voltages
PG-DSO36
Product highlights
Optimized short circuit control for 3-level inverters
Online adjustable current source slew rate control during IGBT turn-on
UL certification according UL1577 (VISO = 5 kV, 1EDS20I12SV and 1EDU20I12SV only)
Isolation tested according VDE 0884-10 (standard expired Dec. 31, 2019, VIORM=1420V, 1EDS20I12SV only)
Potential applications
AC and brushless DC motor drives
High-voltage DC/DC converters
UPS systems
Welding
Servo drives
Description
The 1EDS20I12SV is a single-channel IGBT driver in a PG-DSO-36-64 package with a galvanically isolated
barrier according UL1577 and testing according to VDE0884-10. The driver IC controls three external p-channel
MOSFET or even more as a controlled current source during turn-on. The IC is therefore able to control
precisely the turn-on process in order to avoid excessive dvCE/dt or diC/dt transients. The IC has a peak sinking
capability of 2 A for turning off the IGBT. An external PNP transistor can be used to support IGBT with currents
ratings higher than 75 A.
The 1EDU20I12SV offers the same set of function including a galvanically isolated barrier according to UL1577.
The 1EDI20I12SV offers the same set of functions including the unique slew rate control with the exception that
its isolation barrier offers functional isolation.
All three devices together are the 1EDS-SRC family.
The logic input pins of the 1EDS-SRC family are 3.3 V, 5 V, and 15 V CMOS-compatible. The data transfer
across the galvanic isolation barrier is accomplished with the integrated coreless transformer technology. The
1EDS-SRC family provides several protection features such as IGBT desaturation shut down protection for
IGBT, overcurrent protection for sense IGBT, soft turn-off shut down, and two-level turn-off.
Final datasheet
6
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
1
Block diagram
VCC1
VCC2
UVLO /
Bias
UVLO /
Bias
/FLT
CS
DESAT / CS
Detection
circuits
DESAT
RDY2
RDY1
Safety
Logic
OCOFF
PRB
MAIN
LOGIC
/
MAIN
LOGIC
/
PADP
INN
CT
Trans-
ceiver
CT
Trans-
ceiver
PADP
RSENSE
ON
ON
CT Isolated
Transmission
path
Control loop
VCC2
INP
EN
Input
stage
(bidirectional)
GATE
PADN
TLTO
TLTO
CZ
VZ
PADN
Control loop
PADN
CZ
VZ
OFF
SPEED
PADN
VEE2
VCC1
VCC1
SIGI
SOFF
Signature
Logic
SIGO
VEE2
GND2
GND1
Input Side
Output Side
Figure 1
Block diagram for the 1EDS-SRC family
Final datasheet
7
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
2
Pin configuration, description, and functionality
2.1
Terminal configuration
VEE2
DESAT
OFF
1
2
3
4
5
6
7
8
9
36 GND1
35 PADN
34 VCC1
OCOFF
CS
33
PADP
32 INN
31 INP
30 EN
GATE
SOFF
GND2
VEE2
29
SPEED
1EDS-SRC family
28 GND1
27 /FLT
26 RDY1
25 RDY2
24 NC
RSENSE 10
VCC2 11
ON 12
NC 13
PRB 14
CZ 15
23 SIGI
22 SIGO
21 TST1
VZ 16
TST2 17
VEE2 18
20
19
NC
GND1
Figure 2
Table 1
Terminal configuration of the 1EDS-SRC family (Top View)
Terminal Description
Terminal
number
Terminal
name
Description
VEE2
DESAT
OFF
Negative power supply, output side
Desaturation shut down protection
Gate turn-off
1
2
3
OCOFF
CS
Overcurrent protection on/off
Sense IGBT overcurrent
Gate voltage sense
4
5
GATE
SOFF
GND2
VEE2
RSENSE
VCC2
6
Gate soft turn-off
7
Signal ground, output side
Negative power supply, output side
Sense resistor input
8
9
10
11
Positive power supply, output side
Final datasheet
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Table 1
Terminal Description
Terminal
number
Terminal
name
Description
ON
Gate control for external p-channel MOSFET
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
Not connected, connection to GND2 recommended
Preboost current adjustment
PRB
CZ
Two-level turn-off time set
VZ
Two-level turn-off voltage set
TST2
VEE2
GND1
NC
Reserved terminal, to be connected to VEE2
Negative power supply, output side
Ground, input side
Not connected, connection to GND1 recommended
Reserved terminal, to be connected to GND1
Signature test output
TST1
SIGO
SIGI
NC
Signature test input
Not connected, connection to GND1 recommended
Ready signal, monitoring the output side
Ready signal, monitoring the input side
Fault output
RDY2
RDY1
/FLT
GND1
SPEED
EN
Ground, input side
Setting of IGBT gate current level (analog)
Enable, shutdown, and fault reset input
Non-inverting driver input
INP
INN
Inverting driver input
PADP
VCC1
PADN
GND1
Input side logic reference voltage
Positive power supply, input side
Input side logic reference ground
Ground, input side
2.2
Terminal functionality
GND1
Logic ground terminal of the input side.
PADN
Input side logic reference ground. Direct connection to GND1 is required.
VCC1
5 V power supply for the input side.
The reference terminal for VCC1 is GND1.
PADP
3.3 V, 5 V or 15 V input side logic reference voltage.
The reference terminal for PADP is PADN.
Final datasheet
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
INN inverting driver input
INN control signal for the driver output while INP is set to high. The IGBT is turned on, if INN is set to low, and is
turned off, if INN is set to high, respectively. A minimum pulse width is required to prevent from glitches while
controlling the IGBT. An internal pull-up resistor ensures that the IGBT is kept in off-state, if terminal INN is left
unconnected.
The reference terminal for INN is PADN.
INP non-inverting driver input
INP control signal for the driver output while INN is set to low. The IGBT is turned on, if INP is set to high, and is
turned off, if INP is set to low, respectively. A minimum pulse width is required to suppress glitches while
controlling the IGBT. An internal pull-down resistor ensures that the IGBT is kept in off-state, if terminal INP is
left unconnected.
The reference terminal for INP is PADN.
EN input
Terminal EN needs to be set high for INP and INN to control the IGBT switching.
The EN input terminal serves two purposes:
Feature 1: Enable / shutdown of the output side. The IGBT is turned off by a soft turn-off, if terminal EN is set to
low. A minimum pulse width is defined to help suppress glitches on terminal EN.
The IGBT is switched on without preboost on the rising edge of terminal EN, if terminal INP is set high and
terminal INN is set low before activating EN.
Feature 2: Resets the desaturation or overcurrent condition signaled on terminal /FLT, if terminal EN is set to
low for more than 870 ns. A reset of signal /FLT is asserted at the rising edge of terminal EN.
The reference terminal for EN is PADN.
SPEED
IGBT on-state gate current setting sent from input side. This is an analog input terminal. The reference voltage
of the internal ADC is PADP.The reference terminal for SPEED is PADN.
/FLT fault output
Open-drain output terminal to signal desaturation of conventional IGBTs or overcurrent of sense IGBTs.
Terminal /FLT is set low, if desaturation or overcurrent occurs. The /FLT terminal has to be connected via a pull-
up resistor to PADP.
The reference terminal for /FLT is GND1.
RDY1 ready status
Open-drain output to signal the proper operation of the input side. RDY1 is set to high if the input side terminals
VCC1 and PADP are above their respective undervoltage thresholds. The RDY1 terminal should be connected
a via pull-up resistor to PADP.
The reference ground terminal for RDY1 is GND1.
RDY2 ready status
Open-drain output to signal the proper operation of the output side. RDY2 is set to high, if the output side supply
is above the UVLO2 level and the internal chip data transmission is operating properly. The RDY2 terminal
should be connected via a pull-up resistor to PADP.
The reference ground terminal for RDY2 is GND1.
SIGI
I/O signature check input terminal.
The reference terminal for SIGI is GND1.
Final datasheet
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
SIGO
I/O signature check output terminal
The reference terminal for SIGO is GND1.
TST1
Terminal TST1 is a reserved terminal and has to be connected to GND1.
TST2
TST2 is a reserved terminal and has to be connected to VEE2.
VEE2
Negative power supply terminal for the output side: All VEE2 terminals must be connected to GND2, if no
separate negative supply voltage is used.
DESAT
Monitoring of the IGBT saturation voltage VCE(sat) to detect desaturation caused by a short: The IGBT is shut
down by activating soft turn-off, if the voltage at this pin is above a given threshold. Two additional filters provide
a large robustness against noise and coupling effects. One of these filters is adjustable in terms of the filter time.
The reference terminal for DESAT is GND2.
OFF
Gate turn-off terminal in normal operation mode
The reference terminal for OFF is VEE2.
OCOFF
Input terminal to inhibit the automatic turn-off of the IGBT in case of a desaturation or current sense failure. The
fault status continues to be signaled on terminal /FLT. This feature is deactivated by an internal pull-down
resistor to GND2, if the terminal is left open.
The reference terminal for OCOFF is GND2
CS
Current sense comparator input terminal for sense IGBTs or standard IGBTs with external emitter shunts.
The reference terminal for CS is GND2. This feature is deactivated, if terminal CS is connected to GND2.
GATE
Input terminal for sensing the gate voltage at resistor ROFF, for example according to Figure 3.
The reference terminal for GATE is GND2.
PRB
The preboost current is adjusted by means of a voltage divider between GND2 and VEE2 for a bipolar supply.
The voltage divider is connected to VCC2 and VEE2 for unipolar supply.
The reference terminal for PRB is VEE2.
SOFF
Output terminal for IGBT soft turn-off in case of short circuit or overcurrent events
The reference terminal for SOFF is VEE2.
GND2
Reference ground terminal of the output side.
Final datasheet
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
RSENSE
Current sense feedback input of the turn-on gate current control loop.
The reference terminal for RSENSE is VCC2.
VCC2
Positive power supply terminal of the output side.
ON
Terminal for the connection to the gate terminal of an external p-channel MOSFET, such as OptiMOS™
BSD314SPE. This transistor is used to control the IGBT turn-on gate current.
The reference terminal for ON is VCC2.
CZ
This terminal sets the two-level turn-off timing via an external capacitor against VEE2. A short between
terminals CZ and VEE2 deactivates the two-level turn-off.
The reference terminal for CZ is VEE2.
VZ
Voltage adjustment terminal for the two-level turn-off feature: This terminal can be connected to VEE2 via a
resistor of 27 k (VTLTO = 9.3 V), shorted against VEE2 (VTLTO = 11.4 V), or left floating (VTLTO = 10.3 V).
The reference terminal for VZ is VEE2.
Final datasheet
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
3
Functional description
3.1
Introduction
The 1EDS-SRC family is an advanced IGBT gate driver family with various control and protection features to
allow the design of highly reliable systems. The integrated circuit consists of two galvanically isolated sides,
called input side and output side. The input side is typically interfaced with a CMOS-compatible DSP or a micro-
controller. The galvanically isolated output side is connected to the high voltage domain. The adjustable gate
current source allows the tuning of the IGBT turn-on slew rate to control the EMI of power electronic systems.
The turn-off process is accomplished with an internal MOSFET stage capable of driving 2 A. An internal
MOSFET switch capable of driving 1 A could be connected to an external gate resistor with higher resistance to
prevent from an overvoltage at the IGBT in case of a short circuit or an overcurrent shut down.
The driver also includes IGBT desaturation protection for conventional IGBTs and overcurrent protection for
sense IGBTs with the fault status signal at the input side. Two ready status output terminals indicate whether
the driver is properly supplied and operates normally. A two-level turn-off feature with adjustable delay protects
against excessive overvoltage at turn-off in case of an overcurrent or a short. The same delay is applied at turn-
on to prevent pulse width distortions.
5V
5V
VCC2
VCC1
VCC2
RDESAT
DDESAT
/FLT
DESAT
CDESAT
RS
RD
CD
CS
RDY2
RDY1
OCOFF
RSENSE
ON
C1
T1
T2
PADP
INP
GATE
INN
CZ
VZ
RSOFF
EN
ROFF
PADN
SPEED
RF
OFF
CF
SOFF
SIGI
PRB
SIGO
VCC2
RPRB2
RPRB1
VEE2
GND1
C3
C2
GND2
GND
Figure 3
Typical application
3.2
IC Supply
There are three supply voltage domains available having individual undervoltage lockout levels. The IC is in a
safe state during undervoltage lockout of any domain under all circumstances, meaning that the gate drive
outputs are never activated before each part of the IC is ready to operate.
Final datasheet
13
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
3.2.1
Input side
The driver is supplied with 5 V between terminals VCC1 to GND1. This supply voltage manages the basic
functions of the input side. The input side contains a second voltage domain for the logic input signals INP, INN,
and EN. This special voltage domain is supplied by the terminals PADP and PADN and can range from 3.3V
over 5V to 15V. It is mandatory to connect directly the terminals PADN and GND1. It is important to note, that
the voltage domains VCC1 and PADP have independent undervoltage lockout levels and both domains must be
supplied appropriately for operation.
VCC1 can be shorted to GND1 in order to deactivate the driver. No turn-on signals will be transmitted from the
input to the output side even if terminal VCC1 is left floating. Therefore, the IGBT won’t be turned on.
3.2.2
Output side
The EiceDRIVER™ 1EDS-SRC family is designed to support both bipolar and unipolar power supply
configurations. The driver IC is typically supplied with a positive voltage of 15 V on terminal VCC2 and a
negative voltage of -8 V on terminal VEE2, if configured for bipolar supply. The driver IC is typically supplied
with a positive voltage of 15 V on terminal VCC2 for a unipolar supply configuration. VEE2 and GND2 have to
be connected together as short as possible for unipolar supply.
3.3
Non-inverting and inverting input terminals INP and INN
There are two input modes to control the IGBT. In non-inverting mode, terminal INP controls the driver output
while terminal INN is set to low. In inverting mode, terminal INN controls the driver output while terminal INP is
set to high. A low signal at terminal INN will activate the output ON. A minimum input pulse width is defined to
suppress potential glitches.
3.4
Driver output terminal ON
The output side contains an integrated feedback control for the IGBT gate current. The gate current control is
completed by the external current sense resistor and a p-channel MOSFET. Several resistors and MOSFETs
can be placed in parallel in order to limit the individual power dissipation. The recommended P-channel
transistor is BSD314SPE (OptiMOS™-P 3, 30 V, 140 mΩ).
The entire turn-on procedure of an IGBT is separated into three phases according to Figure 4: the preboost, the
turn-on, and the VCC2 clamping phase.
The preboost phase controls a high current to drive the gate of the IGBT. The gate voltage is increased from its
starting point to a voltage lower than the gate-emitter threshold voltage of the IGBT, i.e. VGATE < VGE(th), within a
period of typ. 135 ns. It is important that the IGBT is not turned on during the preboost phase. The value of the
preboost current IPRB is proportional to the voltage VPRB at terminal PRB. The preboost current IPRB is defined as:
2 ∙ 푉푃푅퐵
(1)
퐼푃푅퐵 = |
|
3 ∙ ꢀ푆
The change from the preboost phase into the turn-on phase needs less than typically 25 ns. This time must be
considered for the setting of the preboost current amplitude in order not to overcharge the gate during the
preboost phase.
The gate current during the turn-on phase can be selected out of 11 levels for the proper adjustment of the turn-
on transition. The fine granularity between levels 1 and 10 allows accurate slope control. It behaves similar as a
traditional driver at level 11. The driver controls the voltage drop across the sense resistor RS. The
corresponding gate current Igg is
푉푅ꢁ퐸푁ꢁ퐸
퐼푔푔
=
(2)
ꢀꢁ퐸푁ꢁ퐸
The selection of the gate current for the turn-on phase is accomplished with terminal SPEED on the input side.
Terminal SPEED is an input terminal with voltage levels between 0 V and 3.3 V. The lowest voltage at terminal
SPEED corresponds with the highest gate current level, e.g. by connecting SPEED to GND1.
Final datasheet
14
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
VCC2
RSENSE
ON
vRS(t)
RS
external
turn-on
igg(t)
GATE
Rg int
vON(t)
vGE(t)
GND2
1EDS-SRC
Phases:
vRS
igg
preboost
turn-on current source
VCC2 clamping
Preboost
level
preboost value =
f(VEE2, RPRB1, RPRB2
)
Typ.
135 ns
t
Typ.
25 ns
vON
VCC2
v
VMiller
VON,ON
vGE
VGE(th)
0
t
VEE2
t3
t1 t2
t0
Figure 4
Timing diagram for turn-on
Finally, the IGBT gate voltage saturates at VCC2 in the VCC2 clamping phase. The driver clamps the gate
voltage of the external P-channel transistor 6 V below VCC2 according to Figure 4. This provides a low-resistive
connection between the gate of the IGBT and terminal VCC2
It is good board layout engineering to keep tightest proximity of the control loop consisting of driver IC, sense
resistor, p-channel MOSFET, and the VCC2 / VEE2 blocking capacitors to avoid oscillations.
3.5
SPEED setting
The 11 levels of gate current can be selected by applying an analog voltage VSPEED at terminal SPEED
according to the table below.
Final datasheet
15
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Table 2
Switching speed levels on input and output side
Voltage at terminal SPEED
Typ. reference VRSENSE
VVCC2-0.197
VVCC2-0.287
VVCC2-0.376
VVCC2-0.466
VVCC2-0.556
VVCC2-0.645
VVCC2-0.735
VVCC2-0.825
VVCC2-0.912
VVCC2-1.003
VVCC2-1.543
% of turn-on gate current amplitude
20%
29%
38%
46%
56%
64%
73%
82%
91%
100%
154%
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
3.3 V
2.91 V
2.63 V
2.35 V
2.08 V
1.80 V
1.52 V
1.25 V
0.97 V
0.69 V
0
3.6
Preboost setting
The preboost control is always active, both in bipolar or unipolar power supply configuration. The only exception
is, if the IGBT is turned on via EN according to section 3.8
The preboost current may be set by a simple voltage divider for bipolar gate supply as well as for unipolar
supply. In case of bipolar power supply, connect the voltage divider between GND2, PRB, and VEE2. In case of
a unipolar power supply, use VCC2, PRB, and VEE2 according to Figure 5.
VCC2
RPRB1
VCC2
GND2
PRB
RPRB1
RPRB2
PRB
GND2
VEE2
RPRB2
VEE2
1EDS-SRC
1EDS-SRC
Figure 5
External circuit for setting of preboost current (left: unipolar supply; right: bipolar supply)
The selected preboost current amplitude should charge the IGBT gate from the negative voltage VEE2 to a
value between 0 V and VGE(th) of the IGBT within 135 ns. The corresponding IGBT gate charge curves should be
consulted for the various collector-emitter voltages VCE for best accuracy.
3.7
Gate turn-off terminal OFF
The driver IC is able to sink a minimum gate current of 2 A peak. The closed loop controlled sink MOSFET
establishes the two-level turn-off function according to section 3.9.6 by controlling the second level during the
turn-off process for an adjustable time period TTLSET. An external turn-off boost transistor is recommended for
larger sink current capability.
Final datasheet
16
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
3.8
Terminal EN
Terminal EN is used to enable the input side for normal operation. A soft turn-off is initiated, when the signal at
terminal EN is logic low regardless of the status of signals at terminals INP and INN. The status of EN is
dominant over all communications over the insulation barrier. If therefore a shutdown is initiated via terminal EN
during normal operation and an overcurrent is detected simultaneously, the IGBT is turned off via soft turn-off.
However, /FLT is not activated as the chip is already being reset. /FLT will be activated after IC enable, if the
overcurrent still exists on the next IGBT turn-on command.
Signals on terminal EN have also priority over INN and INP. The signals at terminal EN have to pass a noise
filter. The EN signal is suppressed, if the pulse duration is shorter than the filter time and the driver reacts as
described in Table 3.
Table 3
EN
Driver IC status for EN, INP, and INN
INP
INN
high
low
Result
high
high
low
regular turn-off / soft off*
regular turn-off / soft off*
turn-on
high
high
low
high
high
high
high
high
turn-on
low
low
turn-on without preboost
Soft off
high
low
low
* soft turn-off only in case of simultaneous CS / DESAT event
A second function of the EN terminal is to reset the driver IC after an overcurrent event, which was triggered by
the DESAT or CS function. The IC is reset by holding EN low. The fault indication at terminal /FLT follows on the
next rising edge of signal EN
3.9
Protection and diagnosis features
Undervoltage lockout (UVLO)
3.9.1
The device is equipped with a system of defined undervoltage lockout (UVLO) levels on both the input and
output side to ensure proper operation of the IGBT.
Any triggering of UVLO will turn-off the IGBT by means of the soft turn-off function. All signals at INP and INN
are ignored until the voltage at terminals VCC1 recovers above VUVLOH1 at terminals VCC1 and VUVLOH3 at
terminal PADP.
The IGBT is switched off via terminal OFF in case of an UVLO event at pin VCC2. Signals from the input side
are ignored until VCC2 recovers to the power-up level of VUVLOH2. The IC will perform an immediate turn-on after
recovery of VCC2 according to Table 4.
3.9.2
Ready and status output terminals
The ready signal RDY1 for the input side covers the following conditions:
UVLO status of the input side supply voltage domains at terminals VCC1 and PADP
Establishment of correct signal transmission from input side to output side across the insulation barrier
The ready signal RDY2 for the output side indicates after a short delay:
UVLO status of the output side supply voltage VCC2
Establishment of bidirectional signal transmission across the insulation barrier
Both signals are monitoring signals only and need not to be reset actively.
Final datasheet
17
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Table 4
VCC1
UVLO
UVLO
UVLO
good
Driver IC status UVLO at VCC1, VCC2 and PADP (EN = high)
VCC2
good
PADP
good
RDY1
low
RDY2
X
Result
SOFF and 5µs watchdog
acc. INP / INN (turn-on with preboost)
OFF
good
good
high
low
high
high
low
good
UVLO
good
high
high
low
activate OFF and SOFF simultaneously
acc. INP / INN (turn-on with preboost)
OFF
UVLO
UVLO
UVLO
X
good
good
high
high
high
high
UVLO
X
good
low
SOFF and 5µs watchdog
acc. INP / INN (turn-on with preboost)
UVLO
UVLO
good
good
high
3.9.3
Fault indication (terminal /FLT)
Terminal /FLT is the indicator for a triggered DESAT or CS event. It is pulled low by an internal FET. The /FLT
function is reset by means of a low signal at terminal EN.
3.9.4
Watchdog
The bidirectional signal transmission across the insulation barrier is monitored by watchdogs on the input and
output side. These are the most important ones:
The IGBT is switched off via terminal SOFF and additionally switched off via terminal OFF, if the
transmission fails for a given duration.
A watchdog activates the terminal OFF after typically 5 µs in any case of a soft turn-off event.
3.9.5
I/O signature check
The I/O signature check is a feature that allows the confirmation of switching commands sent by the
microcontroller to the driver IC. The SIGO output terminal is an exclusive-or (XOR) combination of the terminals
INN, INP, and EN according to Figure 6. The desaturation status on terminal DESAT and the correct voltage at
terminal PADP are also monitored.
EN
VPADP
VPADP
UVLO (<2,7V)
0:FAIL
VPADN
DESAT/CS*
1:FAIL
0:NO FAIL
INN
INP
A
N
D
1:NO FAIL
VPADN
AND
AND
X
O
R
X
O
R
SIGI
GND1
SIGO
Figure 6
I/O signature check
Final datasheet
18
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
To save PCB space, the SIGI and SIGO terminals of a series of drivers can be interconnected via a daisy chain.
In this case, terminal SIGI of the first driver in the daisy chain should be connected to VCC1 or GND1. Terminal
SIGI of the next driver should be connected to terminal SIGO of the previous driver. Terminal SIGO of the last
driver in the daisy chain should be connected to the microcontroller.
The I/O signature check does not monitor the status of the IGBT.
Monitored status
INN / INP and EN
DESAT
PADP undervoltage
The reference terminals are VCC1 and GND1.
3.9.6
Two-level turn-off (TLTO)
The TLTO function is activated, if a capacitor is applied between terminal CZ and terminal VEE2. It affects any
turn-on and turn-off process, which is either initiated by the input signals INP, INN or EN or by any protection
function on the output side. Connecting terminal CZ with terminal VEE2 will deactivate the two-level turn-off
function.
The two-level turn-off introduces a second (lower) gate voltage level during the turn-off process according to
Figure 15This additional level ensures lower collector-emitter voltage overshoots during turn-off. The second
gate voltage level reduces the collector current of the IGBT when reaching this level. The obtained diC/dt is
therefore slower and generates less induced overvoltage. The required timing, which can be adjusted by the
capacitance value at terminal CZ, depends on stray inductance and overcurrent at the beginning of the two-level
turn-off period.
Three voltage levels are available:
The voltage level is set to 11.4 V, if terminal VZ is connected to VEE2,
the voltage level is set to 10.3 V, if terminal VZ is floating,
the voltage level is set to 9.3 V, if terminal VZ is connected to VEE2 via a 27 kΩ resistor
The second voltage level is set in a way that turn-off losses are the same as during normal turn-off for nominal
current values. The turn-on signal is delayed by the duration of the two-level turn-off in order to achieve identical
pulse lengths.
The duration of the plateau is set by the capacitor connected between terminals CZ and VEE2.
The IC starts charging the capacitance on CZ for obtaining the two-level set time TTLSET, when a turn-on signal is
given. The IC starts the turn-on sequence and resets the capacitor at terminal CZ as soon as the voltage at
terminal CZ exceeds 2.5 V.
The IC activates additionally a soft turn-off sequence, if a turn-off is initiated due to a desaturation condition on
terminal DESAT.
3.9.7
Desaturation shut down protection
Desaturation protection ensures the protection of the IGBT in case of a short. When the desaturation voltage on
terminal DESAT rises and reaches 9 V, the output is driven low by soft turn-off and the /FLT output terminal is
activated. The blanking time is determined by the combination of the highly precise internal current source and
an external capacitor. Desaturation protection is only set active at TDESATleb = 400ns after the preboost phase.
3.9.8
IGBT overcurrent detection
The IGBT overcurrent detection is a protection feature that senses the emitter current on current-sense IGBTs
or standard IGBTs via using an emitter shunt resistor. The voltage is measured by a comparator that triggers at
0.35 V. The current sense signal at terminal CS is ignored while the IGBT is off. An external blanking circuit is
necessary to prevent false tripping during turn-on. With non-sensing IGBT types, a low resistance shunt is used
to sense the emitter current. When a short is detected, the IGBT is switched off by a soft turn-off. Both the
desaturation and the current sense features can be used at the same time. This function is therefore not limited
to current sensing. It can be used for any shut down condition as well. The fault status is signaled on terminal
Final datasheet
19
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
/FLT. The fault status has to be reset via terminal EN. IGBT overcurrent detection is only active 400ns after the
preboost phase.
3.9.9
Overcurrent protection ON/OFF
The IGBT is switched off via a soft turn-off in case of a CS or DESAT event, if terminal OCOFF is connected to
GND2 or left unconnected. If terminal OCOFF is connected to VCC2, the IGBT is not switched off in such
cases. However, the signaling of CS or DESAT events to output /FLT is done in any case. The IGBT can be
turned off externally instead, e.g. via control input EN.
3.9.10
Soft turn-off
The IGBT can be turned off smoothly via an external higher-ohmic gate resistor attached to terminal SOFF. The
soft turn-off speed can be adjusted by selecting the appropriate resistor value. The soft turn-off reduces the
voltage overshoot considerably and may be used in combination with the two-level turn-off function of the IC.
The regular turn-off function at terminal OFF supports the soft turn-off as soon as the voltage between terminals
GATE and VEE2 drops below 3 V. An additional safety feature is installed by means of a watchdog timer, which
starts at the same time the soft turn-off is triggered. The watchdog turns off the IGBT in any case via terminal
OFF after 5 µs. If the soft-off function is not used, both the terminals SOFF and OFF can be combined to
increase the turn-off current capability of the IC.
Trigger conditions for a soft turn-off:
Desaturation condition at terminal DESAT
Overcurrent condition at terminal CS
Driver Enable OFF (EN equals GND1)
UVLO1 of the input side supply VCC1
UVLO of the input side logic reference PADP
Internal signal transmission error
Final datasheet
20
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
4
Electrical parameters
4.1
Absolute maximum ratings
Note: Absolute maximum ratings are defined as ratings, which may lead to destruction of the integrated circuit
when being exceeded. Unless otherwise noted all parameters refer to GND1 and to TA = 25°C.
Table 5
Abs. maximum ratings
Parameter
Symbol Min.
Max.
Unit
VOFFSET
Offset voltage VGND1 – VVEE2
1EDI20I12SV and 1EDU20I12SV only
-1200
1200
V
VVCC1
VPADP
VPADN
VVCC2
VVEE2
Positive power supply input side
PADP voltage
-0.3
-0.3
-0.3
-0.3
-12
–
6.5
16.05
0.3
PADN voltage
Positive power supply output side 1
Negative power supply output side 1
Maximum power supply voltage output side (VVCC2 - VVEE2
20.3
0.3
Vmax2
)
28
VTERMINAL
VPADP
VVCC1
Voltage at terminals INN, INP, EN, RDY1, RDY2, /FLT
Voltage at terminals SIGI, SIGO, SPEED
-0.3
-0.3
Voltage at terminal DESAT1
Voltage at terminals OCOFF 1, GATE 2, OFF 2, SOFF 2
Voltage at terminal GATE 3
Voltage at terminals CS 1, VZ 2, CZ 2, PRB 2
Voltage at terminal RSENSE, ON4
-5
VVCC2
VVCC2
5.5
5.5
VVCC2
-0.3
-0.3
-0.3
-7
IOD
Open drain output current (/FLT, RDY2, RDY1)
Output current at terminals SIGO
10
6
mA
–
ISIGO
ION,DC
IOFF
ISOFF
TJ
-6
–
DC output current at terminal ON (VVCC2 - VVEE2 = 20 V)
10
2.4
1.05
Peak output current at terminal OFF (tp = 2 µs, f = 20 kHz)
Peak output current at terminal SOFF (tp = 2 µs, f = 20 kHz)
A
–
–
Junction temperature
1EDS20I12SV
1EDI20I12SV
-40
-40
125
150
°C
TS
Storage temperature
Total power dissipation5
-55
–
125
980
102
6.69
PD,tot
Rth(j-a)
th(j-top)
mW
K/W
Thermal resistance (Both chips active), TA = 25 °C
value
–
–
1 with respect to terminal GND2
2 with respect to terminal VEE2
3 with respect to terminal OFF
4 with respect to terminal VCC2
5 Power dissipation is derated linearly with 9.8 mW/°C above an ambient temperature of TA = 25°C. See Figure 17 for
reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation
of components in close proximity.
Final datasheet
21
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Table 5
Abs. maximum ratings
Parameter
Symbol Min.
Max.
750
1000
50
Unit
ESD Capability
HBM 1
CDM 2
V
VESD
–
|dVISO/dt|
Common mode transient immunity
kV/µs
–
4.2
Operating range
Note: The IC operates as described in the functional description within the operating range. Unless otherwise
noted all parameters refer to terminal GND1 and TA = 25°C.
Table 6
Operating parameters
Parameter
Symbol Min.
Typ. Max.
Unit
VVCC1
Positive power supply input side
4.85
5
5.5
V
Input side logic reference voltage ranges VPADP - VPADN
VPAD
3
7
3.3
15
–
5.5
15.75
VIN,RSENSE
Control voltage by terminal SPEED at terminal RSENSE
Voltage at terminal SPEED 3
VVCC2
1.7
-
VVCC2-
0.2V
VSPEED
VVCC2
VVEE2
Vmax2
ISIGO
TA
0
3.3
20
0
–
4
Positive power supply output side
0
15
-8
–
4
Negative power supply output side
-12
–
Power supply voltage output side (VVCC2 - VVEE2
Output current at terminal SIGO
Ambient temperature
)
25
3
-3
-40
mA
°C
–
105
–
1 According to EIA/JESD22-A114-B
2 According to EIA/JESD22-C101
3 With respect to voltage VPADN
4 With respect to voltage VGND2
Final datasheet
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EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
4.3
Electrical characteristics
Note: The electrical characteristics given below include the spread of values for the junction temperature range
of -40°C ≤ TJ ≤ 125°C. All values refer to the supply condition of VVCC1 = VPADP = 5 V, VPADN = VGND1 = 0 V,
VVCC2 = 15 V, VVEE2 = -8 V and the given test conditions. Typical values represent the median values at
TA = 25°C under the above mentioned supply conditions. Unless otherwise noted all voltages are given
with respect to their respective reference terminal (GND1 for terminals 19 to 36, GND2 for terminals 1 to
18).
4.3.1
Voltage supply
Table 7
Voltage supply
Parameter
Symbol
Values
Unit Test condition
Min.
–
Typ.
4.63
4.47
–
Max.
4.85
–
VUVLOH1
UVLO threshold for VCC1
power up
power down
V
VUVLOL1
3.5
0.08
–
UVLO hysteresis VCC1 (VUVLOH1 - VUVLOL1) VUVLO1,hys
–
VUVLOH2
UVLO threshold VCC2
power up
power down
11.9
11.0
–
12.6
–
VUVLOL2
10.4
0.3
–
UVLO hysteresis VCC2 (VUVLOH2 - VUVLOL2) VUV,hys2
–
VUVLOH3
VUVLOL3
IQ1
UVLO threshold for PADP
power up
power down
–
2.95
–
1.6
–
–
VINP = VPADP, VINN
=
Quiescent current input side VCC1
9.6
13
mA
VPADN
VRDY1 = VRDY2 = VFLT
= VPADP
VINP = VPADP = 15 V
VFLT = VRDY1 = VRDY2
= 5 V, VINN = VPADN
Quiescent current input side VCC1
Quiescent current output side VCC2
–
–
9.6
7.3
13
IQ2
VINP = VPADP, VINN =
9.5
VPADN
VRDY1 = VRDY2 = VFLT
= VPADP
Quiescent current output side in UVLO
mode
IQ2,UVLO
IQ3
–
–
4.5
4.7
6
VVCC2 = 10.4 V
VINP = VPADP, VINN
=
Quiescent current output side VEE2
–
VPADN
VRDY1 = VRDY2 = VFLT
= VPADP
VINP = VPADP, VINN
=
IQ4
Quiescent current PADP
–
1
–
VPADN
VRDY1 = VRDY2 = 5 V
VFLT = 5 V
Final datasheet
23
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
4.3.2
Logic input and output
Table 8
Logic input and output
Parameter
Symbol
Values
Unit Test condition
Min.
Typ.
Max.
1.5
Low level input voltage terminals INP, INN, VIL
EN
–
–
V
High level input voltage terminals INP, INN, VIH
EN
–
–
3.5
1.5
–
–
VIL,SIGI
Low level input voltage terminal SIGI
High level input voltage terminal SIGI
Low level output voltage terminal SIGO
High level output voltage terminal SIGO
Low level output voltage terminal /FLT
–
VIH,SIGI
3.5
0.3
VVCC1
0.3
0.3
–
V OL,SIGO
V OH,SIGO
VOL,FLT
VGND1
IIL,SIGO = 3 mA
IIH,SIGO = - 3 mA
IIL,pin = 3 mA
IIL,pin = 3 mA
0.1
4.7
0.08
0.1
4.3
–
–
VOL,RDY1
VOL,RDY2
IIH,INP
,
Low level output voltage terminals RDY1,
RDY2
VINP = 5 V
Input bias current INP
30
30
-1200
6
60
60
-700
10
–
100
100
-350
16
–
µA
ns
IIH,EN
VEN = 5 V
Input bias current EN
IIL,INN
VINN = 0V
Input bias current INN
IIH,SPEED
TFILIN
VSPEED = 5 V
VTERMINAL = 5 V
VEN = 5 V
Input bias current SPEED
Input filter time terminals INP, INN, SIGI
Input filter time terminal EN
Fault reset duration terminal EN
Propagation delay EN to ON (Turn-On)
22
45
870
–
TFILEN
TEN,RST
TEN,ON
TEN,SOFF
–
–
VEN = 0V, VVEE2=0V
–
–
530
530
–
VVEE2 = 0 V
Shut down propagation delay EN to SOFF
(Turn-Off)
–
680
4.3.3
Gate driver
Table 9
Gate driver
Parameter
Symbol
Values
Typ.
Unit Test condition
Min.
Max.
VRSENSE
VVCC2
0.165
-
VVCC2
0.197
-
VVCC2
0.230
-
VSPEED = 3.3 V
VSPEED = 2.91 V
VSPEED = 2.63 V
VSPEED = 2.35 V
VSPEED = 2.08 V
Voltage of sense resistor for gate current
level 1
V
Voltage of sense resistor for gate current
level 2
VVCC2
-
VVCC2
-
VVCC2-
0.324
0.250
0.287
Voltage of sense resistor for gate current
level 3
VVCC2
-
VVCC2
-
VVCC2-
0.413
0.340
0.376
Voltage of sense resistor for gate current
VVCC2
-
VVCC2
-
VVCC2-
0.512
1
level 4
0.420
0.466
Voltage of sense resistor for gate current
level 5
VVCC2
-
VVCC2
-
VVCC2-
0.601
0.510
0.556
1 Default state after power on (VVCC1 > VUVLOH1
)
Final datasheet
24
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Voltage of sense resistor for gate current
level 6
VRSENSE
VVCC2
0.600
-
VVCC2
0.645
-
VVCC2
0.691
-
V
VSPEED = 1.80 V
VSPEED = 1.52 V
VSPEED = 1.25 V
VSPEED = 0.97 V
VSPEED = 0.69 V
VSPEED = 0 V
Voltage of sense resistor for gate current
level 7
VVCC2
-
VVCC2
-
VVCC2-
0.790
0.680
0.735
Voltage of sense resistor for gate current
level 8
VVCC2
-
VVCC2
-
VVCC2-
0.880
0.770
0.825
VVCC2
-
VVCC2
-
VVCC2-
0.999
Voltage of sense resistor for gate current
level 9
0.825
0.912
Voltage of sense resistor for gate current
level 10
VVCC2
-
VVCC2
-
VVCC2-
1.095
0.910
1.003
Voltage of sense resistor for gate current
level 11
VVCC2
-
VVCC2
-
VVCC2-
1.667
1.420
1.543
VSPEED hysteresis
VSPEED,hys
VOFFL
–
–
–
60
mV
V
VVEE2
VVEE2
+
IOFFL = 20 mA
IOFFL = 200 mA
IOFFL = 1 A
Low level output voltage terminal OFF
+0.03
0.09
VVEE2
+0.3
VVEE2
0.85
+
–
–
–
–
–
–
–
–
VVEE2
+2.3
VVEE2
6
+
VVEE2+
IOFFL = 2 A 1
–
7.6
VSOFFL
VVEE2
+0.06
VVEE2
0.18
+
+
+
ISOFFL = 20 mA
ISOFFL = 200 mA
ISOFFL = 500 mA
ISOFFL = 1 A 1
Low level output voltage terminal SOFF
VVEE2
+0.6
VVEE2
1.7
VVEE2
+1.9
VVEE2
4.9
VVEE2
+7.2
–
VON,ON
VVCC2
-
VVCC2 -
Turn-on clamping voltage terminal ON
6.5
5.0
Turn-off threshold voltage terminal GATE 2
Active Shut Down Voltage (VCC2 open)
–
–
3
VGATE,th
VACTSD
–
IOFF = 200 mA,
VVEE2 = 0 V,
1.4
2.4
ION+
tp=2 µs
Output current of terminal ON
Output current of terminal ON
Preboost time
Speed setting propagation delay1
Fall time1
50
–
–
–
mA
ION-
–
-50
180
120
-
TPRB
–
135
–
ns
µs
ns
TSPEED
TFALL
TPDON
TPDONt
–
IGBT is turn on
CLOAD = 1 nF
–
8
TA=25°C, VVEE2=0V
VVEE2 = 0V
Turn-on propagation delay without PMOS
–
500
–
540
570
Turn-on propagation delay over junction
temperature1
–
TPDOFF
TPDOFFt
TA=25°C, VVEE2=0V
VVEE2 = 0 V
Turn-off propagation delay
–
–
485
535
565
Turn-off propagation delay over junction
temperature1
–
Matching delay (TPDON - TPDOFF
)
MT
VVEE2 = 0 V
–
15
30
1 The Parameter is not subject to production test - verified by design / characterization
2 Reference to VVEE2
Final datasheet
25
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
4.3.4
Desaturation protection
Table 10
Desaturation protection
Parameter
Symbol
Values
Unit Test condition
Min.
8.4
450
–
Typ.
9
Max.
9.4
550
–
VDESAT
Desaturation trigger level
V
IDESAT,C
IDESAT,D
TDESATleb
TDESATFIL
TDESATFLT
TSOFF
VDESAT = 2 V
VDESAT = 6 V
Blanking capacitor charge current
Blanking capacitor discharge current
Desaturation leading edge blanking time 1
Desaturation filter time 1
500
12.5
400
230
760
360
µA
mA
ns
–
–
–
–
VVEE2 = 0 V
VVEE2 = 0 V
DESAT to /FLT propagation delay
–
995
540
DESAT shut down propagation delay to
SOFF
–
TDESATOFF
DESAT shut down watch dog
–
5.2
8
µs
OCOFF = low,
VVEE2 = 0 V
4.3.5
Overcurrent protection disable
Table 11
Overcurrent protection disable
Symbol
Parameter
Values
Unit Test condition
Min.
11.4
7
Typ.
12.5
7.5
Max.
13
VIH,OCOFF
VIL,OCOFF
IIH,OCOFF
High level input voltage terminal OCOFF
Low level input voltage terminal OCOFF
Input bias current OCOFF
V
8.2
VOCOFF = 15 V
150
250
µA
–
4.3.6
Current sense
Table 12
Current sense
Parameter
Symbol
Values
Unit Test condition
Min.
320
-200
–
Typ.
350
-125
420
280
760
Max.
380
-45
–
VCS
VSOFF < 5 V
VCS = 0 V
Current sense trigger threshold
Input bias current CS
Over current detection blanking time 1
Shut down propagation delay CS to SOFF 1
Propagation delay CS to /FLT 1
mV
µA
ns
IIH,CS
TCS,blank
TCS
540
995
–
TCS,FLT
–
1 The Parameter is not subject to production test
Final datasheet
26
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
4.3.7
Two-level turn-off
Table 13
Two-level turn-off
Parameter
Symbol
Values
Unit Test condition
Min.
Typ.
Max.
VTLTO
Terminal VZ
connected to VEE2
VZ open
Two-level voltage terminal VZ
10.7
11.4
12.1
V
9.6
8.6
–
10.3
9.3
2.5
-950
5
11.0
10.0
–
RVZ = 27 kΩ
Two-level turn-off threshold voltage 1
Two-level turn-off charging current
Two-level turn-off time limitation
Two-level voltage slope 2
VTLTO,th
ICZ
VCZ = VEE2 + 1V
VVEE2 = 0 V
-1150
3
-750
7
µA
TTLLIM
dVTLTO/dt
µs
CLOAD = 10 nF
20
V/µs
–
–
1 Referenced to VVEE2
2 The parameter is not subject to production test - verified by design / characterization
Final datasheet 27
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
5
Insulation characteristics
Insulation characteristics are guaranteed only within the safety maximum ratings which must be ensured by
protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.
Table 14
Insulation characteristics
Parameter
Symbol
Characteristic
Unit
Installation classification per EN 60664-1, Table 1
For rated mains voltage ≤ 150 Vrms
For rated mains voltage ≤ 300 Vrms
For rated mains voltage ≤ 600 Vrms
For rated mains voltage ≤ 1000 Vrms
Overvoltage categories
I-IV
I-IV
I-III
I-II
Climatic Classification according to IEC 68
Pollution degree (EN 60664-1)
Minimum external clearance
40 / 105 / 21
2
CLR
CPG
CTI
8.5
8.5
>400
mm
Minimum external creepage
Minimum Comparative Tracking Index
5.1
Tested according to VDE 0884-10 (Standard expired on Dec. 31, 2019,
1EDS20I12SV only)
While the standard has expired on Dec. 31, 2019, the 100% testing is continued although there is no continued
quarterly monitoring.
Table 15
Tested for reinforced isolation limits according to VDE 0884-10 (Standard expired on
Dec. 31, 2019, 1EDS20I12SV only)
Parameter
Symbol
VIORM
Characteristic
Unit
V
(peak)
Maximum Repetitive Insulation Voltage
1420
2662
Vpd(m)
Input to output test voltage, method b
Vpd(m) = VIORM * 1.875 , productive test, tm = 1 sec,
Partial discharge < 5 pC
VIOTM
VIOSM
RIO
Highest allowable overvoltage
Maximum Surge Isolation Voltage
Insulation resistance at Ts, VIO = 500 V
Notes
8000
>6000
> 109
Ω
This coupler is suitable only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
5.2
Recognized under UL 1577
(File E311313, 1EDS20I12SV and 1EDU20I12SV only)
Table 16
Recognized under UL 1577
Symbol
Parameter
Characteristic
5000
≥ 6000
Unit
VISO
VISO
V (rms)
V (rms)
Insulation withstand voltage / 1 min
Insulation test voltage / 1 s
Final datasheet
28
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
6
Timing diagrams
INP
ON
INN
ON
TPDON
TPDON
TPDOFF
TPDOFF
OFF
OFF
Figure 7
Timing of turn-on and turn-off propagation delay without two-level turn-off mode
TEN,SOFF
TEN,ON
EN
ON
EN
SOFF
Figure 8
Timing of EN turn-on and shut down propagation delay
INP
TP
INP
TP
SIGI
SIGI
TFILIN
TFILIN
SIGO
SIGO
Figure 9
Timing of short pulse suppression terminal INP and SIGI (TP < TFILIN)
TP
TP
INN
INN
TFILIN
TFILIN
SIGO
SIGO
Figure 10 Timing of short pulse suppression terminal INN (TP < TFILIN
)
Final datasheet
29
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
TP
TP
EN
EN
TFILIN
TFILIN
SIGO
SIGO
Figure 11 Timing of short pulse suppression terminal EN (TP < TFILIN
)
TP > TEN,RST
TP
EN
TEN,RST
/FLT
Figure 12 Timing for fault reset at terminal EN
TCS,blank
VCS
CS
TCS
TCS,FLT
SOFF
/FLT
TEN,RST
EN
Figure 13 Timing of CS events incl. terminals SOFF, /FLT and EN
Final datasheet
30
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
INP
TSOFF
SOFF
OFF
TDESATOFF
TDESATFIL
TDESATleb
TDESATleb
VDESAT
DESAT
TDESATFLT
/FLT
EN
TEN,RST
Figure 14 Timing for DESAT events incl. terminals SOFF, /FLT and EN (timing is same for related INN
input signal)
INP
TTLTO,th
CZ
VTLTOx
TTLSET
OFF
TTLSET
TTLLIM
ON
INP
TTLTO,th
CZ
TTLSET>TTLLIM
VTLTOx
TTLSET
TTLLIM
OFF
ON
Figure 15 Timing for two-level turn-off incl. terminals CZ and OFF
(top: TTLSET < TTLLIM, bottom: TTLSET > TTLLIM
)
Final datasheet
31
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
7
Package
7.1
PG-DSO-36-64
Figure 16 Package drawing
Final datasheet
32
<Revision 2.3>, 31.1.2020
EiceDRIVER™ 1EDS-SRC family
Slew rate control IGBT driver IC
Dimension [mm³]
Material
25.0 31.5 1.5
therm [W/mK]
FR4
0.3
35
Metallization [µm]
Vias
388
= 0.3 mm; plating 25 µm; 14 pcs.
Solder
Package Attach [50µm]
55
Figure 17 PCB reference layout (left: top layer, right: bottom layer)
Thermal performance may change significantly with layout and heat dissipation of components in close
proximity.
Final datasheet
33
<Revision 2.3>, 31.1.2020
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Published by Infineon Technologies AG
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