1EDN9550B [INFINEON]
1-channel non-isolated gate-driver IC family with truly differential inputs;
| 型号： | 1EDN9550B |
| 厂家： | 
Infineon |
| 描述： | 1-channel non-isolated gate-driver IC family with truly differential inputs |
| 文件： | 总31页 (文件大小：1295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
Description
EiceDRIVER™1EDNx550 is part of the TDI family of single-channel high-
side and low-side gate driver ICs. The TDI family has a fully differential
input circuitry. The truly differential inputs (TDI) provide excellent
common-mode robustness (CMR) and eliminates the risk of false
triggering. The small package footprints enable versatile layout in
both low-side and high-side driving.
SOT23-6
TSNP-6
Product features
Topologies
•
Very large common-mode input voltage
range (CMR static) up to ±200 V, configurable
with common mode resistors
Separate low impedance source (4 A) and
sink (8 A) outputs
45 ns propagation delay (-7/+10 ns accuracy)
Four UVLO options: 4 V, 8 V, 12 V and 15 V
SOT23-6 or TSNP-6 small packages
Fully qualified according to JEDEC for
industrial grade applications
•
•
•
•
•
•
4-pin Kelvin-source MOSFETs in boost PFCs
Low-side driving with high PCB parasitic inductance
High-side driving in switched tank converters
High and low-side driving in half and full-bridges
Driving SJ and SiC MOSFETs, GaN HEMTs
•
•
•
•
•
Switches requiring negative drive voltage
Applications
•
•
•
Server, telecom and industrial SMPS
DC-DC converters and bricks
Power tools, motor control
Table 1
Product portfolio
Part number Package UVLO ON/OFF Output current Max. CMR static 1)
Max. CMR dynamic 1)
1EDN7550U PG-TSNP-6
4.2 V / 3.9 V
1EDN7550B
1EDN8550B
1EDN6550B
1EDN9550B
8.0 V / 7.0 V
12.2 V / 11.5 V
14.9 V / 14.4 V
-8 A / +4 A
±200 V
± 400 V
PG-
SOT23-6
Driving Kelvin source MOSFET
Driving medium voltage half-bridge
VBUS
EiceDRIVER™
1EDNx550
Dboot
VDD
SGND
Rboot
D
Rin-HS
4-pin
MOSFET
IN-
OUT_SNK
EiceDRIVER™
1EDNx550
VDD
SGND
RgOFF_HS
RgON_HS
Controller
GND OUT_SRC
ZVDD
Controller
G
Rin+HS
RIN-
D
S
IN+
VDD
GND
IN-
GND OUT_SRC
IN+
VDD
OUT_SNK
RgOFF
RgON
PWM1
Cboot
SGND
DVRin
G
Vphase
PWM_Out
EiceDRIVER™
1EDNx550
RIN+
PWM2
GND
RVDD
CVDD
vLS
LS
D
S
Rin-LS
SS
IN-
OUT_SNK
S
RgOFF_LS
RgON_LS
SGND
GND OUT_SRC
PGND
G
Rin+LS
IN+
VDD
CVDD
PGND
Figure 1
EiceDRIVER™ 1EDNx550 driving Kelvin-source MOSFET and half-bridge power stages
1
CMR static and dynamic for the application depends on input resistors. Please see Chapter 6.1
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
Table of contents
Table of contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
2
Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Truly differential input (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common-mode input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Supply voltage and undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.1.1
3.2
3.3
4
Electrical characteristics and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
4.3
4.4
4.5
5
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Application and implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input resistor dimensioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Half-bridge driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Switches with Kelvin-source connection (4-pin packages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Applications with significant parasitic PCB-inductances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Switches with bipolar gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
6.2
6.3
6.4
6.5
7
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PG-SOT23-6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
PG-TSNP-6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8.1
8.2
8.3
9
List of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Datasheet
2
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
1 Pin configuration and description
1
Pin configuration and description
The pin configuration for both SOT23-6 and TSNP-6 package is illustrated in Figure 2 and a description is given
in Table 2 . For functional details, please read Chapter 3.
SOT23-6
TSNP-6
IN-
OUT_SNK
1
2
3
6
5
4
OUT_SNK
OUT_SRC
VDD
IN-
1
2
6
5
4
GND
GND OUT_SRC
IN+
3
VDD
IN+
Figure 2
Table 2
Pin configuration SOT23-6 and TSNP-6 6-pin packages (top view)
Pin description
Pin number Pin name
Description
1
2
3
4
5
6
IN-
Negative input
connected to controller PWM or ground via input resistor (see Chapter 6)
GND
Ground
negative gate drive voltage ("off" state voltage)
IN+
Positive input
connected to controller PWM or ground via input resistor (see Chapter 6)
VDD
Supply voltage
positive gate drive voltage ("on" state voltage)
OUT_SRC
OUT_SNK
Driver output source
low-impedance switch to VDD (4 A/0.85 Ω)
Driver output sink
low-impedance switch to GND (8 A/0.35 Ω)
Datasheet
3
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
2 Block diagram
2
Block diagram
A simplified functional block diagram of EiceDRIVER™ 1EDNx550 is given in Figure 3.
UVLO
VDD
IN+
OUT_SRC
OUT_SNK
Differential
Schmitt
Trigger
Diff. Amp.
+ LPF
Logic
IN-
GND
Figure 3
Simplified block diagram of EiceDRIVER™ 1EDNx550
Datasheet
4
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
3 Functional description
3
Functional description
EiceDRIVER™ 1EDNx550 is a family of high-side and low-side non-isolated gate drivers whose application ranges
into fields usually reserved for isolated and level shiꢀer drivers, resulting in significant cost benefits. This is
made possible by the unique truly differential input (TDI) stage concept. The TDI input stage allows controlling
the driver even if a common-mode voltage is present on the input differential pair. Common-mode voltages up
to ±200 V DC and ±400 V AC peak between ground reference (GND) and driver inputs (IN-, IN+) are possible.
EiceDRIVER™ 1EDNx550 is suited for any application with unwanted voltage shiꢀs between driver and system
ground and in high-side driving within the allowed static common-mode range (±200 V max., see Chapter 6.1).
Switches requiring a bipolar driving voltage can be operated easily as well, taking advantage of the common
mode voltage handling capability of the TDI.
3.1
Truly differential input (TDI)
Figure 4 depicts the signal path from the controller’s PWM output to the logic gate driver signal input as
implemented in 1EDNx550.
Controller
PWM
1EDNx550
VS
Rin1
2kW
0
IN+
15pF
15pF
1kW
1kW
Cp1
Cp2
12 MHz
2nd order
Lowpass
Differential
Schmitt
Trigger
Pulse
Extender
Av = 4.5
DVRin
DVRin / k
IN-
SGND
Rin2
2kW
GND
k = (Rin [kW] + 3) / 3
Figure 4
Functional principle of the EiceDRIVER™ 1EDNx550 with truly differential inputs (TDI)
The two input resistors Rin1 and Rin2 are mandatory for correct operation of EiceDRIVER™ 1EDNx550 since this
gate driver IC cannot be used as a standard low-side driver with IN- directly connected to GND pin. The PWM
pin of the controller shall be connected to IN+ pin of EiceDRIVER™ 1EDNx550 through resistor Rin1, while the
SGND pin of the controller (or PWM in case of half-bridge configurations) shall be connected to IN- pin through
resistor Rin2. The two resistors Rin1 and Rin2, together with the 2 kΩ and 1 kΩ resistors inside the driver, allow
to implement a high common-mode rejection ratio (CMRR) differential amplifier that functionally decouples the
controller outputs from ground of the gate driver.
Rin1 and Rin2 input resistors shall be chosen as a function of the maximum ΔVRin and the required static
common-mode voltage between the driver ground and the controller ground, according to Table 16.
As an example, for maximum ΔVRin = 3.3 V, Rin1 and Rin2 should be 33 kΩ, resulting in a static divider ratio of
k = 12 at the driver inputs, as per the following voltage divider formula:
k = (Rin [kΩ] + 3)/3
(1)
(2)
For ΔVRin other than 3.3 V, Rin1 and Rin2 must fulfill the relation:
Rin1 = Rin2 = (10.9 * VS − 3) [kΩ]
Datasheet
5
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
3 Functional description
where VS is the high voltage level of the PWM signal, usually equal to the controller supply voltage. A lookup
table is also available in Table 16 as a guide for selecting the value, form factor and tolerance of resistors Rin1
and Rin2
.
The input signal is then amplified by a factor of 4.5 from the high-CMRR amplifier and filtered by a 2nd
order low-pass filter. Considering also the passive differential RC filter in front of the high-CMRR amplifier, the
overall input signal experiences 3rd order filtering with a corner frequency at 12 MHz. The suppression of high
frequencies is important to dampen ringing at 100 MHz and above in fast-switching power systems and also
makes the driver robust against any mismatch of Cp1 and Cp2 input parasitic capacitance (50 to 100 fF range).
The filtered signal is then applied to the differential Schmitt-Trigger that feeds a pulse extender. The pulse
extender avoids the transfer of PWM signals shorter than 25 ns to the output stage, improving noise immunity.
Overall typical input-to-output propagation delay is 45 ns. A propagation delay accuracy of +10/-7 ns is
achieved.
3.1.1
Common-mode input range
Due to the passive low-pass filtering at the input side, the CMR (common-mode robustness, i.e. the maximum
allowed voltage difference between controller outputs PWM/SGND and driver reference GND) can be split
into CMR static and CMR dynamic parameters, depending on the common-mode voltage frequency content.
Provided a certain input resistor and controller voltage configuration, the CMR static describes the capability of
the driver to withstand DC voltages, while the CMR dynamic describes the capability of the driver to withstand
AC voltages due to overshoots or ringing.
The CMR capabilities strongly depend on input resistors Rin1 and Rin2. The value and accuracy of resistors must
allow to meet the maximum device voltage ratings at IN+/IN- pins while their form factor shall be chosen to
meet power dissipation and creepage requirements.
In more detail, CMR static is limited by the operating voltage at the input pins IN+/IN- (+6 V/-7 V) to allow input
stage to work in linear mode. CMR dynamic is limited by the absolute maximum ratings (+10 V/-10 V) on the
same pins. As an example, if 33 kΩ, 0.1% tolerance, 0603 form factor resistors and 3.3 V controller supply voltage
are used, this translates into a static CMR range of + 72/- 84 V. Under the same conditions, the maximum input
voltage ratings at pins IN+/IN- of ±10 V results in a dynamic CMR range of ±150 V.
In case of 127 kΩ, 0.1% tolerance, 1206 form factor resistors and 12 V maximum PWM voltage, the maximum
CMR static is ± 200 V and the maximum CMR dynamic is ± 400 V.
In case of different PWM voltages and input resistor configurations, please refer the lookup table in Chapter 6.1.
The lookup table helps to select the proper resistor parameters (value, form factor, tolerance) depending on
the needed CMR parameters and PWM voltage, or to check the maximum allowed CMR depending on the PWM
output voltage and input resistors.
Please be aware that a perfectly symmetric layout of the input signal path is mandatory to reach the full CMR
ranges mentioned above. Any parasitic imbalance in the signal path converts a common-mode signal into a
differential signal, resulting in reduced CMR performances. Layout recommendations can be found in Chapter 7.
3.2
Driver outputs
The rail-to-rail driver output stage made with complementary MOS transistors can provide a typical 4 A sourcing
and 8 A sinking current.
The low on-resistance associated with high driving current is particularly beneficial for fast switching of low
RdsON MOSFETs. With a RON of 0.85 Ω for the sourcing pMOS and 0.35 Ω for the sinking nMOS transistor, the
driver can be considered to behave as an ideal switch.
The p-channel sourcing transistor allows real rail-to-rail behavior without suffering from the voltage drop that is
common for n-channel output stages.
In case of unconnected inputs, the driver output is actively clamped to the “low” level (GND).
Datasheet
6
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
3 Functional description
3.3
Supply voltage and undervoltage lockout (UVLO)
The undervoltage lockout function ensures that the output can be switched only if the supply voltage VDD
exceeds the UVLO threshold voltage. Thus, this feature can ensure that the power switch is not operated with
low driving voltage, achieving a complete and fast transition to the "on" state and avoiding excessive power
dissipation.
Table 3
Logic table
ΔVRin
x
L 3)
H 5)
UVLO
active 2)
inactive 4)
inactive 4)
OUT_SRC
high impedance
high impedance
H
OUT_SNK
L
L
high impedance
EiceDRIVER™ 1EDNx550 is available in two different packages; the SOT23-6 version offers four UVLO threshold
levels to support switches with a broad range of gate source voltages:
•
•
•
•
1EDN7550 with a typical UVLO threshold of 4.2 V (0.3 V hysteresis)
1EDN8550 with a typical UVLO threshold of 8 V (1 V hysteresis)
1EDN6550 with a typical UVLO threshold of 12.2 V (0.7 V hysteresis)
1EDN9550 with a typical UVLO threshold of 14.9 V (0.5 V hysteresis)
In addition, the maximum VDD of 20 V makes this driver family well-suited for a broad variety of power switch
types such as OptiMOS™ CoolMOS™, CoolGaN™ and CoolSiC™.
2
VDD < UVLOoff
ΔVRin < ΔVRinL
VDD > UVLOon
ΔVRin > ΔVRinH
3
4
5
Datasheet
7
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
4 Electrical characteristics and parameters
4
Electrical characteristics and parameters
Note:
The absolute maximum ratings are listed in Table 4 . Stresses beyond these values may cause
permanent damage to the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
4.1
Absolute maximum ratings
Table 4
Absolute maximum ratings
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
-0.3
Max.
Supply voltage
VDD
VIN
–
22
10
V
Voltage between VDD to
GND
Voltage at pins IN+ and IN-
Voltage at pin OUT_SRC
-10
–
–
V
V
–
VOUT_SRC -24
0.3
OUT = low; referred to
VDD pin, DC
-24
VOUT_SNK -0.3
-2
–
–
–
–
–
2
V
V
V
A
A
OUT = low; referred to
VDD pin < 200 ns
Voltage at pin OUT_SNK
24
24
–
OUT = high; referred to
GND pin, DC
OUT = high, referred to
GND pin < 200 ns
Peak reverse current at
OUT_SNK
ISNK_rev
ISRC_rev
-5
–
< 500 ns
Peak reverse current at
OUT_SRC
5
< 500 ns
Junction temperature
Storage temperature
ESD capability
TJ
-40
-55
–
–
–
–
150
150
2
°C
°C
kV
–
–
TS
VESD_HBM
Human Body Model
(HBM)6)
ESD capability
VESD_CDM
–
–
1
kV
Charged Device Model
(CDM)7)
6
According to ANSI/ESDA/JEDEC JS-001 (discharging 100 pF capacitor through 1.5 kΩ resistor)
According to ANSI/ESDA/JEDEC JS-002
7
Datasheet
8
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
4 Electrical characteristics and parameters
4.2
Thermal characteristics
Table 5
Thermal characteristics SOT23-6 package
Parameter
Symbol
Values
Typ.
Unit
Note or Test Condition
Min.
Max.
Thermal resistance junction- RthJA25
–
–
–
–
–
165.1
–
–
–
–
–
K/W
K/W
K/W
K/W
K/W
–
–
–
–
–
ambient 8)
Thermal resistance junction- RthJC25
79.9
65.2
14
case (top) 9)
Thermal resistance junction- RthJB25
board 10)
Characterization parameter ΨthJC25
junction-case (top) 11)
Characterization parameter ΨthJB25
junction-board 12)
51
Table 6
Thermal characteristics TSNP-6 package
Parameter
Symbol
Values
Typ.
Unit
Note or Test Condition
Min.
Max.
Thermal resistance junction- RthJA25
–
–
–
–
–
141
–
–
–
–
–
K/W
K/W
K/W
K/W
K/W
–
–
–
–
–
ambient 8)
Thermal resistance junction- RthJC25
81
36
80
36
case (top) 9)
Thermal resistance junction- RthJB25
board 10)
Characterization parameter ΨthJC25
junction-case (top) 11)
Characterization parameter ΨthJB25
junction-board 12)
8
Obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment
described in JESD51-2a
Obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a
close description can be found in the ANSI SEMI standard G30-88
Obtained by simulation in an environment with a ring cold plate fixture to control the PCB temperature, as
described in JESD51-8
Estimates the junction temperature of a device in a real system and is extracted from the simulation data
for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
Estimates the junction temperature of a device in a real system and is extracted from the simulation data
for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7)
9
10
11
12
Datasheet
9
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
4 Electrical characteristics and parameters
4.3
Operating range
Table 7
Operating range
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
4.5
Max.
Supply voltage
VDD
–
–
–
20
6
V
Min defined by UVLO
Voltage at pins IN+ and IN-
Junction temperature
VIN
TJ
-7
V
–
13)
-40
150
°C
4.4
Electrical characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits, respectively. They
are valid within the full operating range. The supply voltage is VDD = 12 V unless otherwise specified. Typical
values are given at TJ = 25°C
Table 8
Power supply
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
VDD quiescent current
VDD quiescent current
VDD quiescent current
VDD quiescent current
IVDDh
IVDDh
IVDDl
IVDDl
–
–
–
–
1.1
–
–
–
–
mA
mA
mA
mA
OUT = high
VDD = 12 V
1.3
0.9
1.0
OUT = high
VDD = 18 V 14)
OUT = low
VDD = 12 V
OUT = low
VDD = 18 V 14)
Table 9
Undervoltage Lockout 1EDN7550x (Logic level MOSFET)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
3.9
Max.
4.5
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
4.2
V
V
V
–
–
–
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
3.6
3.9
0.3
–
UVLO threshold hysteresis
UVLOhys 0.25
0.35
13
Continuous operation above 125°C may reduce life time
Parameter verified by design/characterization, not 100% tested in production
14
Datasheet
10
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
4 Electrical characteristics and parameters
Table 10
Undervoltage Lockout 1EDN8550B (Standard MOSFET)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
7.4
Max.
8.6
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
8.0
V
V
V
–
–
–
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
6.6
7.0
1.0
–
UVLO threshold hysteresis
UVLOhys 0.8
1.2
Table 11
Undervoltage Lockout 1EDN6550B (12 V UVLO option)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
11.7
Max.
12.7
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
12.2
V
V
V
–
–
–
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
11.0
11.5
0.7
–
UVLO threshold hysteresis
UVLOhys 0.5
0.9
Table 12
Undervoltage Lockout 1EDN9550B (15 V UVLO option)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
14.4
Max.
15.4
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
14.9
V
V
V
–
–
–
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
13.9
14.4
0.5
–
UVLO threshold hysteresis
UVLOhys 0.3
0.7
Table 13
Inputs IN+, IN-
Parameter
Symbol
Values
Typ.
1.7
Unit Note or Test Condition
Min.
Max.
Differential input voltage
threshold for transition LH (at
input resistor)
∆VRinH
–
–
–
–
–
–
V
Independent of VDD
Rin1 = Rin2 = 33 kΩ 15)
Differential input voltage
threshold for transition HL (at
input resistor)
∆VRinL
1.5
36
V
Independent of VDD
Rin1 = Rin2 = 33 kΩ 15)
Total input resistance on each Rin1, Rin2
leg
kΩ
Rin1 = Rin2 = 33 kΩ 15)
15
see Figure 1
Datasheet
11
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
4 Electrical characteristics and parameters
Table 14
Static output characteristics
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
Max.
High-level (sourcing) output
resistance
Ron_SRC
ISRC_pk
–
–
0.85
–
–
Ω
A
ISRC = 50 mA
16)
Sourcing output current
4.0
5.2
VDD = 12 V
16)
Sourcing output current
ISRC_pk
–
–
A
VDD = 18 V
Low-level (sinking) output
resistance
Ron_SNK
ISNK_pk
–
–
0.35
-8.0
–
–
Ω
A
ISNK = 50 mA
17)
Sinking output current
VDD = 12 V
17)
Sinking output current
ISNK_pk
–
-9.4
–
A
VDD = 18 V
Table 15
Dynamic characteristics
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input-to-output propagation tPDon
38
38
–
45
55
55
15
ns
ns
ns
CL = 200 pF
delay turn-on
Input-to-output propagation tPDoff
delay turn-off
45
CL = 200 pF
18)
Rise time
Fall time
Rise time
trise
tfall
trise
6.5
4.5
1
CL = 1.8 nF
18)
–
–
15
5
ns
ns
CL = 1.8 nF
18)
CL = 200 pF
18)
Fall Time
tfall
tPW
–
–
1
5
–
ns
ns
CL = 200 pF
18)
Minimum input pulse width
that changes output state
25
CL = 1.8 nF
For an illustration of the dynamic characteristics see Figure 6 and Figure 7
Figure 5 gives the circuit used for parameter testing
16
Actively limited to approx. 5.2 Apk; not subject to production test - verified by design/characterization
Actively limited to approx. -10.4 Apk; not subject to production test - verified by design/characterization
Parameter verified by design, not 100% tested in production
17
18
Datasheet
12
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
4 Electrical characteristics and parameters
EiceDRIVER™
1EDNx550
VDD
33k
IN-
OUT_SNK
SGND
33k
DVRin
GND OUT_SRC
VDD
IN+
CVDD
CL
Figure 5
Test circuit
4.5
Timing diagram
Figure 6 depicts rise, fall and delay times as given in the Chapter 4.
1.7
1.5
IN+ - IN-
50%
90%
10%
OUTx
tPDoff
tPDon
trise
tfall
Figure 6
Propagation delay, rise and fall time
Figure 7 illustrates the undervoltage lockout function.
UVLOon
UVLOoff
VDD
OUTx
Figure 7
UVLO behavior (output state high)
Datasheet
13
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
5 Typical characteristics
5
Typical characteristics
1.
Undervoltage lockout threshold (1EDN7550) 2.
vs temperature
Undervoltage lockout threshold (1EDN8550)
vs temperature
4.5
8.8
UVLO on
UVLO off
UVLO on
UVLO off
8.4
8.0
7.6
7.2
6.8
6.4
4.3
4.1
3.9
3.7
-50
0
50
100
150
-50
0
50
100
150
T [°C]
j
T [ °C]
j
3.
Undervoltage lockout threshold (1EDN6550) 4.
vs temperature
Undervoltage lockout threshold (1EDN9550)
vs temperature
Datasheet
14
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
5 Typical characteristics
5.
Differential input voltage threshold vs
temperature
6.
Typical quiescent current vs temperature
2.5
ON threshold
OFF threshold
2.3
2.1
1.9
1.7
1.5
1.3
1.1
VDD=12V
Vin=3.3V
-50
0
50
100
150
T [°C]
j
7.
Typical quiescent current vs supply voltage 8.
Total operating current consumption with
capacitive load vs frequency
50
1.6
VDD 4.5V
VDD 12V
VDD 20V
OUT High
OUT Low
Duty Cycle 50%
CL = 1.8nF
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
40
30
20
10
0
0
200
400
600
800
1000
0
5
10
15
20
25
Frequency [kHz]
VDD [V]
Datasheet
15
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
5 Typical characteristics
9.
Typical propagation delay vs temperature
10. Typical rise and fall time vs temperature
Datasheet
16
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
6 Application and implementation
6
Application and implementation
Note:
The following information is given as an example for the implementation of the device only and shall
not be regarded as a description or warranty of a certain functionality, condition or quality of the
device
6.1
Input resistor dimensioning
Table 16 is a lookup table that shows the required input resistor configuration for Rin1 and Rin2 (values, form
factor and accuracy) depending on the controller PWM output voltage and the required ground shiꢀ robustness
(static and dynamic CMR). It can be also used to check the maximum allowed CMR, given a certain resistor and
controller configuration.
Table 16
Input resistor configuration lookup table
Input resistor configuration
Ground shiꢀ robustness
CMR static 20)
CMR dynamic
-30 V/+30 V ±150 V
Controller PWM
output voltage
Value
Tolerance
1%
Form factor19)
2.5 V
3.3 V
5 V
24 kΩ
≥0402
0.1%
1%
≥0603
-54 V/+63 V
-40 V/+40 V
±150 V
±150 V
±150 V
±150 V
±200 V
±200 V
±400 V
±400 V
±200 V
±400 V
±400 V
33 kΩ
51 kΩ
≥0402
0.1%
1%
≥0603
-72 V/+84 V
≥0603
-60 V/+60 V
0.1%
1%
≥0805
-108 V/+126 V
-140 V/+140 V
-140 V/+140 V
-200 V/+200 V
-150V/+150 V
-175 V/+175 V
-200 V/+200 V
12 V
127 kΩ
≥0805
1%
≥1206
0.1%
1%
≥1206
15 V
160 kΩ
≥0805
1%
≥1206
0.1%
≥1206
™
Note:
For further information please see the Application Note of EiceDRIVER 1EDNx550 single channel with
truly differential inputs found in reference [1]
6.2
Half-bridge driving
The EiceDRIVER™ 1EDNx550 is designed to drive low-side MOSFETs in applications with AC ground-shiꢀ between
the controller IC and the driver. However, its properties also make it suitable for use in half-bridge or full-bridge
configurations, as shown in Figure 8. The EiceDRIVER™ 1EDNx550 can effectively drive high-side devices,
replacing level-shiꢀ gate driver ICs in half and full-bridge topologies.
In the half-bridge structure in Figure 8, when the high-side switch is conducting, a DC offset equal to VBUS occurs
between the ground of the high-side driver (i.e. the phase node) and the controller ground. The differential
19
Please check PWM signal duty cycle and resistor power rating
Driver ground to system ground
20
Datasheet
17
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
6 Application and implementation
behavior of the EiceDRIVER™ 1EDNx550 enables to handle the floating voltage at the switching node up to the
CMR static level stated in Table 16 (e.g. up to 84 V for 3.3 V PWM outputs and 33 kΩ ±0.1% input resistors in
0603 form factor). Common applications are buck converters, full-bridge converters, synchronous rectifiers and
motor drive stages.
VDD
EiceDRIVER™
1EDNx550
Dboot
Rboot
VBus
SGND
D
S
Rin-HS
IN-
OUT_SNK
OUT_SRC
VDD
PGND
RgOFF_HS
RgON_HS
GND
IN+
Controller
G
Rin+HS
PWM1
Cboot
Vphase
EiceDRIVER™
1EDNx550
PWM2
GND
RVDD
D
S
Rin-LS
IN-
OUT_SNK
OUT_SRC
VDD
RgOFF_HS
RgON_HS
SGND
GND
IN+
G
Rin+LS
CVDD
PGND
Figure 8
EiceDRIVER™ 1EDNx550 in half-bridge applications
6.3
Switches with Kelvin-source connection (4-pin packages)
The 4-pin configuration depicted in Figure 9 is a very effective measure to improve the switching performance
of transistors in packages with high source inductance LS as is typical for the widely used TO packages. Although
the Kelvin-source connection SS solves the problem of the largely increased switching losses due to LS, it is
evident that the gate driver reference potential moves by an inductive voltage drop, VLS with respect to the
system ground, SGND. In fast-switching applications at high current, VLS can reach 100 V and above. This is the
reason 4-pin systems so far either used isolated drivers or external filters with relatively low corner frequency
that add significant signal delay. The EiceDRIVER™ 1EDNx550 is effective in this use case and provides an
optimum solution.
Figure 9 also indicates that the usually SGND-related VDD cannot be used directly as the driver supply. But
due to the high frequency of VLS (> 100 MHz), a filter composed of impedance ZVDD together with the bypass
capacitor CVDD is well suited to generate a sufficiently stable driver supply. ZVDD can be either a resistor (e.g. 22 Ω
with a typical CVDD of 1 µF) or a proper ferrite bead.
Datasheet
18
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
6 Application and implementation
MOSFET
EiceDRIVER™
1EDNx550
VDD
Controller
ZVDD
Rgoff
D
Rin1
SGND
IN- OUT_SNK
GND OUT_SRC
GND
SGND
G
Rgon
CVDD
DVRin
VDD
IN+
PWM_Out
Rin2
SS
vLS
LS
S
PGND
Figure 9
EiceDRIVER™ 1EDNx550 driving a Kelvin-source 4 pin MOSFET
6.4
Applications with significant parasitic PCB-inductances
In fast switching power systems the parasitic inductance associated with any electrical connection may cause
significant inductive voltage drops, particularly if the PCB-layout cannot be optimized or if the controller and
the power stage are located on two different PCBs.
In such situations, the high robustness of EiceDRIVER™ 1EDNx550 against switching noise and ground shiꢀs is
extremely valuable and allows good performances even in systems with poor PCB layouts.
Figure 10 indicates the most relevant parasitic PCB-inductances and how the EiceDRIVER™ 1EDNx550 can be
configured in this application.
MOSFET
EiceDRIVER™
1EDNx550
VDD
Controller
ZVDD
Rgoff
D
Rin1
SGND
IN-
OUT_SNK
GND
G
GND OUT_SRC
DVRin
Rgon
VDD
IN+
PWM_Out
S
Rin2
CVDD
Lpar2
Lpar3
Lpar1
SGND
Figure 10
EiceDRIVER™ 1EDNx550 in applications with significant PCB inductances
Datasheet
19
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
6 Application and implementation
6.5
Switches with bipolar gate drive
Although most power switches operate at zero “off” gate to source voltage, a negative Vgs could be required
for some devices by specifications or to prevent induced turn-on in case of fast voltage transients or charge
injection on the gate node. Consequently, a bipolar supply voltage rail can be required for the gate driver to
ensure proper MOSFETs, SiC, and GaN driving.
EiceDRIVER™ 1EDNx550 can easily drive power switches requiring bipolar Vgs voltage: Figure 11 shows a layout-
effective method to create two supplies out of a single one through a biased Zener diode. In this simple
configuration, the bias voltage VB defines the positive Vgs driving voltage, while the negative Vgs driving voltage
is given by the voltage difference VB - VDD
.
EiceDRIVER™
1EDNx550
MOSFET
Controller
VDD
D
Rin1
RgON
SGND
IN-
OUT_SNK
SGND
GND OUT_SRC
G
RgOFF
DVRin
PWM_Out
S
IN+
VDD
Rin2
Cs1
Cs2
VB
PGND
Rs
VSS
Figure 11
Bipolar gate drive for 3-pin MOSFET
Datasheet
20
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
7 Layout guidelines
7
Layout guidelines
It is well-known that the layout of a fast-switching power system is a critical task with strong influence on the
overall performance. This is why there exists a huge number of rules, recommendations, guidelines, tips and
tricks that should help to finally end up with a proper system layout.
EiceDRIVER™ 1EDNx550 simplifies the design of the grounding network. Maximum performance and CMR
capabilities provide a specific input resistor configuration and can be achieved by the following design rules:
•
place input resistors Rin close to the driver and make layout of input signal path as symmetric and as
compact as possible
•
•
use a low-ESR decoupling capacitance for the VDD supply and place it as close as possible to the driver
minimize power loop inductance as the most critical limitation of switching speed due to the resulting
unavoidable voltage overshoots
A layout recommendation for the input path of the SOT23-6 package version is given in Figure 12.
RGOFF
DRV_GND
RIN1
IN_N
IN_P
IN-
GND
IN+
OUT_SNK
OUT_SRC
VDD
OUT
RGON
CVDD
RVDD
RIN2
VIN
Figure 12
Layout recommendation for SOT23-6 package
As in the case of the TSNP-6 package routing in a single PCB layer is not possible, the layout can be changed
according to Figure 13 . The chosen form factor of the input resistors (0603) allows to utilize the full dynamic
common-mode input range of ±150 V.
DRV_GND
RGOFF
RIN1
IN_N
IN_P
1EDN7550U
GND
OUT_SRC
OUT
RGON
CVDD
RIN2
VIN
RVDD
Figure 13
Layout recommendation for TSNP-6 package with SMD resistor 0603
Datasheet
21
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
7 Layout guidelines
For applications that do not require the maximum CMR an even more compact layout utilizing resistors of form
factor 0402 is shown in Figure 14.
RGOFF
DRV_GND
RIN1
1EDN7550U
IN_N
IN_P
OUT
GND
OUT_SRC
RGON
CVDD
RIN2
RVDD
VIN
Figure 14
Layout recommendation for TSNP-6 package with SMD resistor 0402
For further layout recommendations for TSNP-6, see Recommendations for Printed Circuit Board Assembly of
Infineon TSLP/TSSLP/TSNP Packages [2].
When conductive pollution could occur, please consider coating for PCB in order to prevent the leakage current
over external resistor pair that might reduce its accuracy.
Datasheet
22
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
8 Package information
8
Package information
8.1
Device numbers and markings
Table 17
Device numbers and markings
Part number
1EDN7550U
1EDN7550B
1EDN8550B
1EDN6550B
1EDN9550B
Orderable part number (OPN)
Device marking
1EDN7550UXTSA1
1EDN7550BXTSA1
1EDN8550BXTSA1
1EDN6550BXTSA1
1EDN9550BXTSA1
70
70
80
60
90
8.2
PG-SOT23-6 package
1)
1)
2.9
1.6
0.15 C A-B
2x
0.15 C D 2x
0.45±0.1
2.8
C
0.1 C
COPLANARITY
0.2 C
6x
SEATING
D
PLANE
0.4±0.1
0.2
C A B
6x
BOTTOM VIEW
A
6
4
6
4
1
3
3
1
INDEX
MARKING
B
0.95
1) DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.15 MAX. PER SIDE
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 15
PG-SOT23-6 outline
Datasheet
23
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
8 Package information
0.95
0.5
0.95
0.5
copper
solder mask
stencil apertures
ALL DIMENSIONS ARE IN UNITS MM
Figure 16
PG-SOT23-6 footprint
4
4
0.25
PIN 1
INDEX MARKING
3.3
1.55
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 17
PG-SOT23-6 packaging
Datasheet
24
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
8 Package information
Type code
Pin 1 marking
Date code (YW)
Figure 18
Package marking (PG-SOT23-6)
Note:
Date code digits Y and W in Table 18 and Table 19
Table 18
Year date code marking - digit "Y"
Year
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
Y
0
1
2
3
4
5
6
7
8
9
Year
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
Y
0
1
2
3
4
5
6
7
8
9
Year
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
Y
0
1
2
3
4
5
6
7
8
9
Table 19
Week date code marking - digit "W"
Week
W
A
B
C
D
E
Week
12
W
N
P
Q
R
S
Week
23
W
4
5
6
7
a
b
c
Week
W
h
j
Week
45
46
47
48
49
50
51
52
–
W
v
x
1
34
35
36
37
38
39
40
41
42
43
44
2
13
24
3
14
25
k
l
y
z
4
15
26
5
16
27
n
p
q
r
8
9
2
3
–
–
–
6
F
17
T
28
7
G
H
J
18
U
V
29
8
19
30
d
e
f
9
20
W
Y
31
s
10
11
K
L
21
32
t
–
22
Z
33
g
u
–
Datasheet
25
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
8 Package information
8.3
PG-TSNP-6 package
1.1±0.05
0.375±0.025
0.3±0.05
A
0.1 A
6x
3
2
1
4
5
6
INDEX MARKING
(LASERED)
0.6
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 19
PG-TSNP-6 outline
Optional solder mask dam
0.35
0.6
0.6
copper
solder mask
stencil apertures
ALL DIMENSIONS ARE IN UNITS MM
Figure 20
PG-TSNP-6 footprint
Datasheet
26
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
8 Package information
4
PIN 1
INDEX MARKING
4
0.5
1.3
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 21
PG-TSNP-6 packaging
Pin 1 marking
Date code (YW)
Type code
Figure 22
Package marking (PG-TSNP-6)
Note:
Date code digits Y and W in Table 18 and Table 19
Further information on packages: www.infineon.com/packages
Datasheet
27
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
9 List of abbreviations
9
List of abbreviations
Table 20
List of abbreviations
Acronym
CMR
CMRR
ESD
Description
common-mode robustness
common-mode rejection ratio
electrostatic discharge
equivalent series resistance
ground
ESR
GND
GaN
LPF
gallium nitride
low pass filter
OPN
PCB
orderable part number
printed circuit board
silicon carbide
SiC
SOT
small outline transistor
surface mount device
truly differential input
transistor outline
SMD
TDI
TO
TSNP
UVLO
thin small discrete package
undervoltage lockout
Datasheet
28
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
References
References
[1]
InfineonApplications of 1EDNx550 single-channel low-side EiceDRIVER™with truly differential inputs
(Rev.1.1), 2019-08-07, [Infineon-ApplicationNote_EiceDRIVER_1EDN_TDI_1EDNx550]
Infineon Recommendations for Printed Circuit Board Assembly of Infineon TSLP/TSSLP/TSNP Packages,
June 2010, [Recommendations for printed circuit board assembly of Infineon TSLP/TSSLP/TSNP
packages
[2]
Datasheet
29
Rev.2.3
2021-11-12
™
EiceDRIVER 1EDNx550
Single-channel high-side and low-side gate driver with high-CMR TDI inputs
Revision history
Revision history
Document
version
Date of
release
Description of changes
Rev.2.3
2021-11-12
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Specifications of 1EDN7550B, 1EDN8550B and 1EDN7550U not changed
Added new product variants 1EDN6550B and 1EDN9550B
Updated maximum CMR range to ±200 V static, ±400 V dynamic
Editorial enhancement of layout and descriptions on front cover
Editorial enhancement of Pin configuration Table 2
Editorial enhancement of Functional description in Chapter 3
Corrected typo ISNK_rev Table 4
Added UVLOoff min. values for all product variants
Corrected typos in Test circuit Figure 5
Updated Figure: Typical propagation delay vs temperature in Chapter 5
Editorial enhancement in Application and implementation Chapter 6
Added Table 16 in Chapter 6.1
Added Half-bridge driving in Chapter 6.2
Editorial enhancement in Layout guidelines Chapter 7
Chapter Device numbers and markings moved to Chapter 8.1
Added list of abbreviations in Chapter 9
Rev.2.2
2019-12-19
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Added new product 1EDN7550U with package TSNP-6
On front cover "Features", added reference to application note
(Applications of 1EDNx550 single-channel lowside EiceDRIVER™ with truly
differential inputs.) for input PWM signal voltage levels other than 3.3 V
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Added Table 3, Logic table
Corrected footnote in Table 4 VESD_HDM
Updated Max. value in Table 4 VESD_CDM and added footnote
Updated Thermal characteristics in Table 5 and added Table 6
Updated Typ. values for Table 8 and added footnotes for Table 15
Added Figure 5 for Test circuit
Added layout recommendations for TSNP package Figure 13 and Figure 14
Added package marking for SOT23 Figure 18 and code marking tables
Table 18, Table 19
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•
Added package marking for TSNP Figure 22
Added Chapter 8.1, Device numbers and markings
Rev. 2.1
2019-11-28
•
Parameter split in Table 4 Voltage at pins OUT_SRC and OUT_SNK →
Voltage at pin OUT_SRC and Voltage at pin OUT_SNK and specified min.
and max.
•
•
Corrected typo in Table 4 VESD_CDM
To match pin configurations in Figure 2 update of Figure 1 as well as in
Chapter 5 the Figure 9 to former Figure: 1EDNx550 as a high-side driver in
former Chapter: High-side switches
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Updated diagram according to number of OUT pins → OUTx, Figure 7
CLoad → CL for Fig 12 and Fig 14
Updated to latest package diagrams, Chapter 8
Rev. 2.0
2018-05-14
Final Datasheet created
Datasheet
30
Rev.2.3
2021-11-12
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Edition 2021-11-12
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