2ED24427N01F [INFINEON]

EiceDRIVER™ 24 V dual-channel low-side non-inverting gate driver for MOSFETs or IGBTs with typical 10 A source and sink currents in a DSO-8 package with thermally efficient, exposed power pad. 2ED24427N01F enables higher power and faster switching frequencies in multiple applications with a reduced PCB footprint and increased reliability by simplifying high power density system design.;


型号：	2ED24427N01F
厂家：	Infineon
描述：	EiceDRIVER™ 24 V dual-channel low-side non-inverting gate driver for MOSFETs or IGBTs with typical 10 A source and sink currents in a DSO-8 package with thermally efficient, exposed power pad. 2ED24427N01F enables higher power and faster switching frequencies in multiple applications with a reduced PCB footprint and increased reliability by simplifying high power density system design. PC 驱动双极性晶体管
文件：	总21页 (文件大小：1267K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2ED24427N01F

10 A dual-channel low-side gate driver IC

Features

Product summary



10 A sink and 10 A source driver capability

11.5 V under voltage lockout

24 V maximum supply voltage

Enable function

CMOS Schmitt-triggered inputs

Output in phase with input

3.3 V, 5 V and 15 V input logic compatible

2 kV ESD HBM

V_CC= 12.5 V to 24 V

I_o+pk/ I_{o- pk}(typ.) =+ 10 A/ - 10 A

t_ON/ t_OFF(max.) = 40 ns/ 55 ns

Package

RoHS compliant

Potential applications

Driving high current IGBTs, enhancement mode N-Channel MOSFETs

directly or through a gate drive transformer in various power electronic

applications in single or parallel combinations

Power Pad DSO-8

Typical Infineon recommendations are as below:

Electric vehicle (EV) charging stations and battery management systems

DC-DC converters

Industrial Drives

Industrial SMPS

Motor control

Industrial applications

General purpose low-side gate driver



Product validation

Qualified for industrial applications according to the relevant tests of JEDEC JESD47/22 and J-STD-020.

Ordering information

Standard pack

Form

Base part number

Package type

Orderable part number

Quantity

2ED24427N01F

PG-DSO-8-900

Tape and Reel

2500

2ED24427N01FXUMA1

Datasheet

www.infineon.com/gdLowSide

Please read the Important Notice and Warnings at the end of this document

Page 1 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Description

The 2ED24427N01F is a low-voltage, power MOSFET and IGBT non-inverting gate driver. Proprietary latch

immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with

standard CMOS or LSTTL output. The output driver features a current buffer stage. The output drivers feature a

high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays between

two channels are matched. Internal circuitry on VCC pin provides an under voltage lockout protection that

holds output low until Vcc supply voltage is within operating range.

* This diagram shows electrical connections only. Please refer to our application notes and design tips for proper circuit board layout.

Figure 1

Typical application block diagram

Datasheet

www.infineon.com/gdLowSide

2 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Table of contents

Product summary ........................................................................................................................................................1

Description……………. ...............................................................................................................................................2

Table of contents ................................................................................................................... 3

Block diagram........................................................................................................................ 4

Pin configuration, functionality and logic truth-table ................................................................ 5

Pin configuration.....................................................................................................................................5

Pin functionality ......................................................................................................................................5

Input/output logic truth table ................................................................................................................5

3.1

3.2

3.3

Electrical parameters ............................................................................................................. 6

Absolute maximum ratings.....................................................................................................................6

Recommended operating conditions.....................................................................................................6

Static electrical characteristics...............................................................................................................7

Dynamic electrical characteristics..........................................................................................................7

4.1

4.2

4.3

4.4

Application information and additional details.......................................................................... 8

Gate driver ...............................................................................................................................................8

Bridge tied gate transformer driver (BT-GTD)........................................................................................8

Driving circuitry design: thermal considerations.................................................................................11

Bias and transient conditions...............................................................................................................11

System functionality with improved thermal behavior.......................................................................12

Square input pulse distortion...............................................................................................................12

Bypass capacitor ...................................................................................................................................13

Additional Details ..................................................................................................................................13

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Qualification information.......................................................................................................15

7.1

7.2

Package details.....................................................................................................................16

Tape and reel details: PG-DSO8-900.....................................................................................................17

Part marking information .....................................................................................................................17

Related products...................................................................................................................18

Additional documentation and resources.................................................................................19

9.1

Infineon online forum resources ..........................................................................................................19

Revision history ....................................................................................................................20

Datasheet

www.infineon.com/gdLowSide

3 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Block diagram

Figure 2

Block diagrams

Datasheet

www.infineon.com/gdLowSide

4 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Pin configuration, functionality and logic truth-table

3.1

Pin configuration

OUTA

VCC

INA

COM

INB

OUTB

8-Lead Power Pad DSO-8 (150 mil)

2ED24427N01F

Figure 3

2ED24427N01Fpin assignments (top view)

3.2

Pin functionality

Table 1

Pin no.

Symbol

Description

INA

Enable pin

Logic input for gate driver output (OUTA), in phase

Ground

COM

INB

Logic input for gate driver output (OUTB), in phase

OUTB

VCC

Gate drive output B

Supply voltage

OUTA

Gate drive output A

No connection

3.3

Input/output logic truth table

Table 2

Input/output logic truth table

INA

INB

OUTA

OUTB

This table is held true in the voltages ranges defined in the recommended conditions section.

Datasheet

www.infineon.com/gdLowSide

5 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Electrical parameters

4.1

Absolute maximum ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM lead. Stresses beyond those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. These are stress ratings only; and functional operation of the device

at these or any other condition beyond those indicated in the ―Recommended Operating Conditions‖ is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal

resistance and power dissipation ratings are measured under board mounted and still air conditions. Ambient

temperature (T_A) is 25°C, unless otherwise specified.

Table 3

Absolute maximum ratings

Definition

Symbol

V_CC

Min

– 0.3

—

– 55

—

Max

5.5

150

300

Units

Fixed supply voltage

V_O

V_IN

V_EN

Rth_JC

T_J

Output voltage

Logic input voltage

Logic enable voltage

Thermal resistance, junction to case

Junction temperature

°C/W

°C

T_S

T_L

Storage temperature

Lead temperature (soldering, 10 seconds)

4.2

Recommended operating conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute

voltages referenced to COM.

Table 4

Recommended operating conditions

Definition

Symbol

V_CC

Min

Max

Units

Fixed supply voltage

V_O

V_IN

Output voltage

Logic input voltage

V_CC

V_EN

Logic enable voltage

T_A

R_G

C_BP

Ambient temperature

External gate resistance

VCC to COM bypass capacitance – X7R dielectric type

– 40

2.5

125

°C

Ω

µF

Datasheet

www.infineon.com/gdLowSide

6 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

4.3

Static electrical characteristics

Unless otherwise specified, these specifications apply for an operating junction temperature range of Ta = 25°C and power

supply V_CC=15 V. The V_INand I_INparameters are referenced to COM and are applicable to input leads: INA and INB. The V_O

and I_Oparameters are referenced to COM and are applicable to the output leads: OUTA and OUTB.

Table 5

Static electrical characteristics

Symbol Definition

Min

—

2.5

0.8

—

2.5

0.8

—

Typ

—

Max

0.8

—

0.8

—

Units Test Conditions

V_IL

V_IH

Logic “0” input voltage

Logic “1” input voltage

V_HYS-IHInput voltage hysteresis

V_ENLLogic “0” enable voltage

V_ENHLogic “1” enable voltage

V_HYS-ENEnable voltage hysteresis

ROH Source output resistance

ROL Sink output resistance

—

450

mΩ

Ta = +25°C

VOH Output high level voltage (V_CC– V_O)

VOL Output low level voltage V_O

Ta = +25°C ,

I_O= 100 mA

V_IN= 5 V, V_CC= 15 V

V_IN= 0 V, V_CC= 15 V

V_CC= 15 V, INA &

INB not switching

µA

I_IN+

I_IN-

Logic “1” input bias current

Logic “0” input bias current

—

I_QCC

Quiescent supply current

0.5

1.2

2.4

V_CCUV+Vcc supply undervoltage turn on threshold

V_CCUV-Vcc supply undervoltage turn off threshold

V_CCUVHVcc supply undervoltage lockout hysteresis

10.5

9.0

—

11.5

10.0

1.5

12.6

11.0

—

I_O+

I_O-

Output sourcing short circuit pulsed current

Output sinking short circuit pulsed current

V_CC= 15 V

PW ≤ 10 µs

4.4

Dynamic electrical characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of Ta = 25°C with bias

conditions of V_CC= 15 V, C_L= 4700 pF. Refer to Figure T2 for switching time definition and to Figure T3 for switching time test

circuit.

Table 6

Dynamic electrical characteristics

Symbol Definition

Min

—

Typ

—

Max

Units

Test Conditions

t_on

t_off

Turn-on propagation delay

Turn-off propagation delay

t_on-enEnable turn-on propagation delay

t_off-enEnable turn-off propagation delay

—

C_BP= 10

µF

t_r

t_f

Turn-on rise time

Turn-off fall time

—

Datasheet

www.infineon.com/gdLowSide

7 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Application information and additional details

Information regarding the following topics is included as subsections within this section of the datasheet.

•

Gate driver

Bridge tied gate transformer driver (BT-GTD)

Driving circuitry design: thermal considerations

Bias and transient conditions

System functionality with improved thermal behavior

Square input pulse distortion

Bypass capacitor

Additional information

5.1

Gate driver

The 2ED24427N01F is a high current gate driver for single ended applications. Due to its very high output current and low

thermal resistance vs. pcb, it is capable to drive Mosfets with very large input capacitance at frequencies up to fsw = 200

kHz or higher without the need of negative supply. The following Figure 4 shows the typical application schematic:

Figure 4

Typical gate driver application

Rg values have to be selected based on the requested tr and tf of the application and may vary between 2.5 Ω and 20 Ω,

while the input capacitance of the fets can go up to 20 nF or more depending on the switching frequency. Since the

very high peak output current, the bypass capacitor Cpb has to be mounted in the close proximityof the Vcc and COM

pins and a ceramic type with low ESR has to be chosen.

5.2

Bridge tied gate transformer driver (BT-GTD)

This is a popular configuration that allows driving high side fets using a low side gate driver, the Figure 5 shows the typical

schematic for a single fet drive:

Figure 5

Bridge tied gate driver configuration

In this configuration the gate transformer parameters have a very important role, most manufacturers indicate the

following in their datasheets:

Datasheet

www.infineon.com/gdLowSide

8 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC



V*µs ratings: this factor must be respected, in bipolar drive application (like the one shown in Figure 5) a

maximum of up to twice that parameter is still acceptable for most manufacturers, this factor then must be

chosen accordingly to the following formula:

ꢀ푝ꢁꢂ푚∗훿

(

)

푉 ∗ µ푠 푟푎푡푖푛푔 ∗ 2 ≥

(1)

푓ꢃ푤

where Vprim is the voltage applied to the primary, δ is the duty cycle and fsw the switching frequency of the

application.



N, turns ratio: usually 1:1, in some cases 1:2 or 1:1:1 (dual driver) this determines the voltage ratio between

primary and secondary.

Lp, primary inductance: this value determines the magnetizing inductance as follows:

퐿ꢄ = 퐿ꢅ ∗ 퐾

(2)

where K is the coupling factor between primary and secondary windings.

L_LK, leakage inductance: this parameter, usually indicated at primary, is equal to:

퐿_ꢆꢇ= 퐿ꢅ ∗ (1 − 퐾)



(3)

The higher Lm is, the lower is the magnetizing current flowing into the transformer and consequent power losses into the

driver. On the other hand the lower L_LKis, the lower and shorter will be the ringing of the secondary LC network created by

L_LK, and Ciss of the fet, damped by Rgss and much lower overshot will appear on the Vgs across the Fet during transition.

Then a too high Lm requires a very good mechanical construction of the gate transformer to achieve high K and

consequent low L_LK.

In a gate driver application running in the range of 50 kHz-200 kHz and using the 2ED24427N01F, a good choice is usually a

Lm between 300 µH and 2 mH and a L_LK< 1µH. This translate for the formula (2) and (3) above in a coupling factor K

between 0.9940 and 0.9995

For good operation and to reduce unneeded power losses into the 2ED24427N01F driver, the magnetizing current has to

be kept I_LM< 0.5 A, from this then derives a minimum Lm to be calculated as follows:

ꢀꢉ

0.5

훿

퐿ꢄ_푚ꢂꢈ

∗

(4)

푓ꢃ푤

Where Vg is the gate driving voltage of the Fet

Figure 6 shows a good design waveform obtained with the following parameters:

Vg =+/-15 V, Lm = 400 µH, L_LK= 0.4 µH, N = 1, fsw = 100 kHz, Ciss_FET= 10 nF, Rg,ps = 3Ω, Rg,ss = 4Ω, and Cdec = 1 µF

Cdec is the AC coupling capacitor needed to reset the driver transformer flux, its value has to be calculated in a way that

the voltage across it can be considered constant during normal operation. The higher the fsw the smaller will be Cdec. A

ceramic capacitor is normally used.

Datasheet

www.infineon.com/gdLowSide

9 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Figure 6

Bridge Tied Gate Driver waveforms

The waveforms in Figure 6 show that:



The lower L_LKis, the lower and shorter is the ringing on the Fets gate voltage, particular care must be paid to

guarantee that the max Vgs voltage of the Fet is not exceeded during operation.

The lower L_LKis, the shorter the propagation delay is from the driver to the gate of the Fet and the higher the peak

current is into its gate.

The higher Lm is, the lower I_LMis; at the primary side the gate peak current, summed to ILM, constitute the total

current flowing out of the gate driver.

Datasheet

www.infineon.com/gdLowSide

10 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

5.3

Driving circuitry design: thermal considerations

The following design example shows how to get a proper design of the gate driving circuitry considering the following

target application data:



Switching frequency 150 kHz

Load capacitance range [10-100] nF

Supply voltage Vcc = 12 V

The switching losses due to the charge/discharge of the capacitive load CL represent the main component of the IC power

dissipation. These losses are proportionally shared between the IC output resistance and the external gate resistance Rg.

As a consequence the thermal behavior of the IC, with the constraint of a maximum junction temperature equal to

150°C, is one of the key points in dimensioning the system parameters. 0 shows the power that is dissipated inside the IC

as a function of load capacitance CL. The external resistance Rg has been chosen in order to keep the product RL*Cg as

constant and equal to 300 ns (refer to Figure 4 for switching circuit schematic).

For a given parameter sizing the value of Pow allows to calculate the junction temperature Tj as:

푇 = 푇 + 푃표ꢊ ∗ 푅_{ꢋℎꢌ퐽퐴}

(5)

퐽

퐴

Where T_Ais the ambient temperature and R_thJAis the junction to ambient thermal resistance.

Figure 7

Simulated IC power dissipation as a function of load capacitance.

5.4

Bias and transient conditions

The input pins of the IC are protected by ESD events with the circuitry shown into ―”Functional block diagram” section at

par. Input/Output/Enable Pin Equivalent Circuit Diagrams. This shows that an ESD diode is placed in between each of

these pins and Vcc.

In case Vcc voltage will be lower than one of the voltage applied to these pins the diode will conduct. Because of its power

dissipation the junction temperature will increase. In order to avoid dangerous working conditions it is recommended to

keep the Vcc voltage always higher or equal to the INA/INB/Enable pin voltages; it is remind that input voltage must

respect the defined absolute maximum rating limits.

Datasheet

www.infineon.com/gdLowSide

11 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

5.5

System functionality with improved thermal behavior

The PG-DSO8-900 package is characterized by a metal thermal pad whose functionality is to reduce the junction to case

thermal resistance. In order to better exploit this feature it is necessary to reduce as much as possible the thermal pad to PCB

thermal resistance (RthTP-PCB in 0).

Two possible ways are suggested:

a. Foresee a footprint on layout that allows to solder the thermal pad to the PCB.

b. Use thermal material filling the air gap in between the thermal pad and the PCB.

Figure 8

Steady state equivalent thermal circuit

5.6

Square input pulse distortion

The following chapter provides a characterization of pulse width distortion. This is defined as the ratio between the output

pulse width with respect to input pulse width. Characterization is done with no load on OUTA and OUTB and it is

applicable to both INA, INB and EN input pulses.

Figure 9 and Figure 10 show the output pulse length with respect to input pulse length. In particular, Figure 10 describes

the pulse distortion in case of a short turn-on input pulse (e.g. low duty cycle condition); while Figure 11 shows the pulse

distortion in case of a turn-off input pulse (e.g. high duty cycle condition).

Figure 9

Output pulse distortion in case of a short turn-on input pulse

Datasheet

www.infineon.com/gdLowSide

12 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Figure 10 Output pulse distortion in case of a short turn-off input pulse

5.7

Bypass capacitor

The bypass capacitor stores an electrical charge that is released to the power line whenever a transient voltage spike

occurs. It provides a low-impedance supply source and it minimizes the noise generated by the switching of the outputs.

It is recommended to place the bypass capacitor as close as possible to the gate driver in order to improve its effectiveness

by reducing the effect of parasitic inductance of PCB lines.

The value of bypass capacitor is related to:

a. The current that the gate driver has to provide to the OUTA/B loads during turn-on switching condition;

b. The speed at which the output pin is driven;

c. The maximum allowed drop on power supply pins.

For instance, if it considered that outputs OUTA and OUTB provide 6 A source current with 20 ns rise time and the

maximum wished drop on VCC pin is 0.1 V, then the bypass capacitance can be calculated as:

퐶 = 푛 ∗ 퐼 ^∆ꢍ= 2 ∗ 6 ꢎ ^{ꢏ0 ꢈꢃ}= 2.4 µ퐹

∆ꢀ

0.ꢐ ꢀ

(6)

5.8

Additional Details

Figure 11 Input/output Timing Diagram

Datasheet

www.infineon.com/gdLowSide

13 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Figure 12 Switching Time Waveform Definitions

Figure 13 Switching time test circuit and test conditions

Figure 14 Input/Output/Enable pin equivalent circuit diagrams

Datasheet

www.infineon.com/gdLowSide

14 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Qualification information

Industrial ¹⁾

Comments: This family of ICs has passed JEDEC’s Industrial

qualification. Consumer qualification level is granted by

Qualification level

Moisture sensitivity level

ESD

extension of the higher Industrial level.

MSL3 ²⁾260°C

(per JEDEC standard J-STD-020)

1000 V (Class C3)

(per ANSI/ESDA/JEDEC standard JS-002)

Charged device model

Human body model

2 kV

(per ANSI/ESDA/JEDEC standard JS-001)

Class II, Level A

IC latch-up test

RoHS compliant

(per JESD78)

Yes

Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon

sales representative for further information.

Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales

representative for further information.

Datasheet

www.infineon.com/gdLowSide

15 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

Package details

Figure 15 8 - Lead Power Pad DSO (2ED24427N01F)

Datasheet

www.infineon.com/gdLowSide

16 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

7.1

Tape and reel details: PG-DSO8-900

LOADED TAPE FEED DIRECTION

NOTE : CONTROLLING

DIMENSION IN MM

CARRIER TAPE DIMENSION FOR 8SOICN

Metric Imperial

Code

Min

7.90

3.90

11.70

5.45

6.30

5.10

1.50

Max

8.10

4.10

12.30

5.55

6.50

5.30

n/a

Min

Max

0.318

0.161

0.484

0.218

0.255

0.208

n/a

0.311

0.153

0.46

0.214

0.248

0.200

0.059

1.60

0.062

REEL DIMENSIONS FOR 8SOICN

Metric

Imperial

Code

Min

329.60

20.95

12.80

1.95

98.00

n/a

14.50

12.40

Max

330.25

21.45

13.20

2.45

102.00

18.40

17.10

14.40

Min

12.976

0.824

0.503

0.767

3.858

n/a

Max

13.001

0.844

0.519

0.096

4.015

0.724

0.673

0.566

0.570

0.488

Figure 16 Tape and reel details

7.2

Part marking information

Front Side

Part number

2ED24427

Infineon logo

Date code

H YYWW

Pin 1

identifier

(may vary)

Figure 17 Marking information PG-DSO-900 (Power Pad-DSO-8)

Datasheet

www.infineon.com/gdLowSide

17 of 21

V 2.0

2019-11-10

2ED24427N01F

10 A dual-channel low-side gate driver IC

2ED24427N01F [INFINEON]

相关型号：

2ED300C17-S

2ED300C17-S

2ED300C17-ST

2ED300C17-ST

2ED300C17SROHSBPSA1

2ED300C17STROHSBPSA1

2ED4820-EM

2EDB7259Y

2EDF7175F

2EDF7175FXUMA2

2EDF7235K

2EDF7275F