2EDL8024G3C [INFINEON]

2EDL8024G3C is a high-side and low-side driver designed for advanced switching converters such as in telecom and datacom applications. 2EDL8024G3C takes in independent inputs with built-in hysteresis for enhanced noise immunity. 2EDL8024G3C have an integrated 120 V boot-strap diode as well as a precise channel-to-channel propagation delay matching <6 ns that ensures volt-second balance and avoids magnetic core saturation. The driver comes in small 3x3 industry-standard leadless package and pin-out.;


型号：	2EDL8024G3C
厂家：	Infineon
描述：	2EDL8024G3C is a high-side and low-side driver designed for advanced switching converters such as in telecom and datacom applications. 2EDL8024G3C takes in independent inputs with built-in hysteresis for enhanced noise immunity. 2EDL8024G3C have an integrated 120 V boot-strap diode as well as a precise channel-to-channel propagation delay matching <6 ns that ensures volt-second balance and avoids magnetic core saturation. The driver comes in small 3x3 industry-standard leadless package and pin-out.
文件：	总26页 (文件大小：1270K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate

Driver ICs

Features



Level-shift high-side low-side dual channel driver

(2EDL802x) Independently controlled high-side and low-side gate drivers

(2EDL812x) Differential input for superb robustness with inherent shoot-through protection

3 A (2EDL8x23) or 4 A (2EDL8x24) source current capability for both high side and low side drivers

Strong 5 A high side / 6 A low side sink current capability

120 V on-chip bootstrap diode

Support operating frequency up to 1 MHz

VDD/VHB under voltage lockout (UVLO)

-10 V to 20 V Input pin capability for increased robustness

(2EDL812x) -8 V to 15 V input pin common mode rejection

-5 A output pin reverse current capability



8 V to 17 V supply voltage operating range

Fast propagation delay

<6 ns delay matching

Offered in VDSON-8 (4 mm x 4 mm) and

VSON-10 (3 mm x 3mm) package

Lead free RoHS compliant package

Feature Comparison



Potential Applications

Typical Application Diagram



DC-to-DC converter

Isolated bus converter

Synchronous rectification for SMPS

Class-D Audio Amplifiers

Product Validation

Qualified for industrial applications according

to the relevant tests of JEDEC47/20/22

Description

2EDL8x2x is a high-side low-side driver designed for advanced switching converters such as in telecom and

datacom applications. 2EDL802x takes in independent inputs with built-in hysteresis for enhanced noise

immunity, whereas 2EDL812x takes in differential input with built-in hysteresis for enhanced noise immunity.

2EDL812x’s inherent shoot-through protection ensures the robustness of the system. 6 ns maximum delay

matching ensures volt-second balance and avoids magnetic core saturation.

Datasheet

Please read the Important Notice and Warnings at the end of this document

Rev. 2.8

www.infineon.com

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Table of contents

Features ........................................................................................................................................ 1

Applications................................................................................................................................... 1

Description .................................................................................................................................... 1

Table of contents............................................................................................................................ 2

1.1

1.2

Package Information .............................................................................................................. 3

Ordering Information ..............................................................................................................................3

Pin Configuration and Descriptions........................................................................................................3

Block Diagram ....................................................................................................................... 5

Functional Description............................................................................................................ 6

Supply Voltage.........................................................................................................................................6

Input Control ...........................................................................................................................................6

Driver Outputs .........................................................................................................................................7

Under Voltage Lockout (UVLO) ...............................................................................................................7

Minimum Pulse Width .............................................................................................................................7

Transient Detector ..................................................................................................................................8

3.1

3.2

3.3

3.4

3.5

3.6

Characteristics....................................................................................................................... 9

Absolute Maximum Ratings ....................................................................................................................9

ESD Ratings..............................................................................................................................................9

Recommended Operating Conditions....................................................................................................9

Static Electrical Characteristics ............................................................................................................10

Dynamic Electrical Characteristics .......................................................................................................11

Thermal Mechanical Characteristics ....................................................................................................11

4.1

4.2

4.3

4.4

4.5

4.6

Descriptive Illustration ..........................................................................................................12

Typical Characteristics ..........................................................................................................13

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.3

Application and Guidelines.....................................................................................................16

Typical Application Diagram.................................................................................................................16

Design Guidelines..................................................................................................................................17

Bootstrap Capacitor Selection ........................................................................................................18

VDD Bypass Capacitor Selection......................................................................................................19

Bootstrap Resistor Selection ...........................................................................................................19

External Bootstrap Diode Selection ................................................................................................19

Gate Resistor Selection....................................................................................................................19

PCB Layout Guidelines ..........................................................................................................................20

8.1

8.2

Outline Dimensions ...............................................................................................................22

PG-VDSON-8-4 Package Outline ...........................................................................................................22

PG-VSON-10-4 Package Outline............................................................................................................23

Reel and Tape .......................................................................................................................24

References ...........................................................................................................................25

Revision history………………………………………………………………………………………………………26

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Package Information

PG-VDSON-8-4

PG-VSON-10-4

1.1

Ordering Information

Standard Pack

Base Part Number

Package Type

Orderable Part Number

Form

Quantity

6000

3000

6000

3000

6000

3000

6000

3000

2EDL8023G

2EDL8023G3C

2EDL8024G

2EDL8024G3C

2EDL8123G

2EDL8123G3C

2EDL8124G

PG-VDSON-8-4

PG-VSON-10-4

PG-VDSON-8-4

PG-VSON-10-4

PG-VDSON-8-4

PG-VSON-10-4

PG-VDSON-8-4

PG-VSON-10-4

Tape and Reel

2EDL8023GXUMA1

2EDL8023G3CXUMA1

2EDL8024GXUMA1

2EDL8024G3CXUMA1

2EDL8123GXUMA1

2EDL8123G3CXUMA1

2EDL8124GXUMA1

2EDL8124G3CXUMA1

2EDL8124G3C

1.2

Pin Configuration and Descriptions

Figure 1

Pin Configuration of PG-VDSON-8-4, Top Transparent View

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Package Information

Figure 2

Pin Configuration of PG-VSON-10-4, Top Transparent View

VDSON-8 VSON-10

Pin Description

Pin Name

Pin #

VDD

N/C

VSS

---

2,6

Gate drive supply

Not Connected

High-side gate driver bootstrap rail

High-side gate driver output

High-side FET source connection

High-side driver control input

Low-side driver control input

Ground return, internally connected to exposed pad

low-side gate driver output

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Block Diagram

A simplified functional block diagram is given in the figure below

VDD

HB UVLO

BANDGAP

REFERENCE

driver

HV Level

Shift

VDD3V0

3.3V

Regulator

POR

PWM_HS

PWM_LS

PADS

VDD

VDD UVLO

driver

LV Level

Shift

VSS

EXPOSED PAD

Figure 3

Block Diagram

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Functional Description

The device is a level-shifted 2-channel driver designed to support topologies with high-side and low-side

configurations. The high side is level shifted by the combination of an on-chip 120 V rated bootstrap diode and

an external bootstrap capacitor. The device provides 3 A (2EDL8x23) or 4 A (2EDL8x24) peak source current

capability for both high-side and low-side and a strong 5 A high-side and 6 A low-side sink current capability.

This allows driving large power MOSFETs with minimum or optimized switching losses during the transition

through the MOSFET's Miller Plateau.

2EDL802x’s input pins support TTL logic levels independently of supply voltage. They are capable to withstand

voltages from -10 V to 20 V, allowing the device to interface with a broad range of analog and digital controllers.

The input stage features built-in hysteresis for enhanced noise immunity. The low-side and high-side gate

drivers are independently controlled and matched to typical 2 ns between the turn on and turn off of each

other.

2EDL812x’s input pins support TTL logic levels independently of supply voltage. They are capable to withstand

voltages from -10 V to 20 V and ground potential shifts from -8 V to 15 V, allowing the device to interface with a

broad range of analog and digital controllers. The input stage features built-in hysteresis for enhanced noise

immunity. The low-side and high-side gate drivers are differentially controlled and matched to typical 2 ns

between the turn on and turn off of each other. The differential inputs provide inherent shoot-through

protection and ensure high-side and low-side outputs are never on at the same time.

The switching node (HS pin) is able to handle negative voltages down to –(24 - V_DD) V which allows the high-side

channel to be protected from inherent negative voltages caused by parasitic inductance and stray capacitance.

Under-voltage lockout circuits are provided for both high- and low-side drivers. UVLO protects the system by

forcing the output low when the supply voltage is lower than the specified threshold.

The following sections describe key functionalities.

3.1

Supply Voltage

The absolute maximum supply voltage is 20 V. The minimum operating supply voltage is set by the under

voltage lockout function to a typical default value of 7.0 V. This lockout function protects power MOSFETs from

running into linear mode with subsequent high power dissipation.

3.2

Input Stage

2EDL802x device responds to the two inputs signals (HI and LI) independently according to the following truth

table.

Table 1

2EDL802x Truth Table

The high-side and low-side outputs respond to high-side and low-side inputs independently.

2EDL812x device responds to the combination of two inputs signals (HI and LI) according to the following truth

table.

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Functional Description

Table 2

2EDL812x Truth Table

True differential input comes with inherent shoot through protection by preventing both low and high side to

be on at the same time. It also provides noise immunity against ground bounce. The input stage is designed to

operate reliably against –8 V / +15 V ground voltage drift. Input logic hysteresis also helps combat disturbances

to the input signal.

The differential voltage between the two input pins is rated at 8 V maximum because of the back-to-back ESD

diodes that connect the two input pins together. Above this voltage, the ESD diodes start clamping which

causes a current flow from the high voltage potential input pin to the low voltage potential input pin.

3.3

Driver Outputs

The low output impedances allow fast transition of the load transistor. Specifically, the ultra-low impedance

pull down resistances, typically 0.5 Ω for the high side and 0.35 Ω for the low side, keep the gate of the load

transistor down during fast transient events – avoiding dv/dt induced re-turn-on.

3.4

Under Voltage Lockout (UVLO)

The under voltage lockout function ensures that the output can be switched to its high level only if the supply

voltage exceeds the UVLO rising threshold voltage. Thus it can be guaranteed, that the switch transistor is not

switched on if the driving voltage is too low to completely switch on the device, thereby avoiding excessive

power dissipation. The UVLO level is set to a typical value of 7.0 V with 0.5 V hysteresis for supply voltage (V_DD)

and 5.75 V with 0.25 V hysteresis for high side boot voltage (V_HB).

UVLO threshold trigger is synchronous. The clock gating ensures minimum pulse width set by the controller is

obeyed at all times. This increases robustness of the integrated boot diode due to the controllability of the

reverse recovery behavior.

A 5 us delay time and a PWM synchronization scheme are implemented in the high-side UVLO to ensure that the

load transistor is not operated with marginal gate drive voltage which can lead to high power dissipation. The

synchronization is done in such a way that the HO output is blocked when UVLO is released while the HI is high.

HO is only propagated when the UVLO is released while the HI is low.

Figure 4

High-side UVLO implementation

3.5

Minimum Pulse Width

The device responds to input level according to the truth table in section 3.2 as long as the logic signal complies

with the minimum pulse width requirement. Signal pulse longer than the minimum allowable input pulse width

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Functional Description

yields valid output. Any output in response to shorter pulses or glitches should be disregarded and filtered out

by the user. Under all allowable operation above input minimum pulse width of 40 ns, the output behaves one

to one to the input with minimal pulse width distortion.

100 ns

40 ns

100 ns

TON_IN

Figure 5

Minimum Pulse Width Input-output On-time Transfer Function

This diagram is illustrative only with typical value. Actual value and pulse width distortion is subject to process

variation. Output pulse width could in some case be shortened or extended to prevent retoggling. See transient

detector section below.

3.6

Transient Detector

The transient detector block is designed to prevent re-toggling of the HO output in case of potential instability

of the level shifter caused by phase node movement. For example, a fast-rising phase node voltage could pull

the power ground (PGND) down. This could result in potential between HI and PGND higher than the rising

threshold of the high-side signal. Such a glitch or noise can be picked up by the driver and propagate through

which can lead to a shoot-through event, transformer volt-second imbalance, and potential device destruction.

The following describes the basic operation of the block.



The transient detector monitors the phase node and tracks its movement, and the rate of change over time

for both rising and falling edge.

Whenever the rate of change is larger than a certain dv/dt threshold¹, the transient detector is active and

blocks the HO output from changing state.

A High-side Input (HI) toggle triggers a decision to change the state, but HO waits until the transient

detector’s active state is removed, then the decision is propagated through.

Additional propagation delay caused by the transient detector is limited to one-half of the oscillation period, as

the signal always propagates through whenever the transient detector sees a peak or valley where dv/dt

approaches zero. See link to Understanding the transient detector [1] for more information.

¹Reference slew rate threshold versus temperature under Section 6 Typical Characteristics

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Characteristics

4.1

Absolute Maximum Ratings

Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions may affect device reliability.

Symbol

Description

Driver Supply Voltage¹

Min

-0.3

Max

Unit

V_DD

Phase Voltage (DC)

-1

V_HB+ 0.3

120

V_HS

Phase Voltage (Repetitive pulse < 100 ns)²

High Side Bootstrap Voltage²

LI and HI Input Voltage

-(24 - V_DD)

-0.3

V_HB

V_HI, V_LI

V_I

-10

Differential Input Voltage³

---

V_LO

V_HO

I_OR

Output voltage on LO

-0.3

V_DD+ 0.3

V_HB+ 0.3

Output voltage on HO

V_HS– 0.3

---

LO and HO Peak Reverse Current⁴

Operating Junction Temperature

Storage Temperature

T_J

-40

150

°C

T_S

-55

150

4.2

ESD Ratings

Symbol

ESD_HBM

ESD_CDM

Description

Value

2000

1000

Unit

Human Body Model sensitivity as per ANSI/ESDA/JEDEC JS-001

Charged Device Model sensitivity as per ANSI/ESDA/JEDEC JS-002

4.3

Recommended Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation and reliability of

the device. All parameters specified in the subsequent tables refer to these operating conditions.

Symbol

Description

Min

Typ

---

Max

Unit

Phase Voltage (DC)

-1

V_HS

Phase Voltage (Repetitive pulse < 100 ns)

Driver Supply Voltage

-(24 - V_DD)

---

V_DD

V_HB

T_J

-0.3

-40

---

High Side Bootstrap Voltage

Junction Temperature

---

125

°C

V/ns

dv/dt

V_I

HS Slew Rate

---

Differential Input Voltage

Input Signal Common Mode Rejection (2EDL812x)

3.3

---

V_ICMR

-8 + V_I/2

15 – V_I/2

¹All voltage ratings in this section referenced to ground

²Not subject to production test. Verified by design/characterization

³Absolute voltage difference between HI and LI (|V_HI-V_LI|)

⁴For < 500 ns pulses

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Characteristics

4.4

Static Electrical Characteristics

V_DD= V_HB= 12 V, V_HS=V_SS=0V. T_C= 25^oC unless otherwise specified. The V_INand I_INparameters are referenced to

V_SS.

Symbol

V_DDR

Description

Min

6.6

---

Typ

7.0

Max Units Conditions

V_DDUVLO Rising Threshold

V_DDUVLO Threshold Hysteresis

V_HBUVLO Rising Threshold¹

V_HBUVLO Threshold Hysteresis

7.4

---

V_DDH

0.5

V_HBR

5.5

---

5.75

6.0

---

V_HBH

0.27

I_HB

Boot voltage Quiescent Current

Boot voltage Operating Current

---

0.55

2.8

0.7

3.1

V_LI=V_HI=0V

I_HBO

f=500kHz, C_LOAD=0nF,

2EDL8x23

---

2.9

3.2

f=500kHz, C_LOAD=0nF,

2EDL8x24

I_DD

V_DDQuiescent Current

V_DDOperating Current

---

0.55

2.8

0.7

3.1

V_LI=V_HI=0V

I_DDO

f=500kHz, C_LOAD=0nF,

2EDL8x23

---

2.9

3.2

f=500kHz, C_LOAD=0nF,

2EDL8x24

R_IN

V_IR

Input Pulldown Resistance

1.6

1.0

---

2.25

1.65

0.6

2.9

2.3

---

kΩ

Rising Input Voltage Threshold

Falling Input Voltage Threshold

Input Logic Voltage Hysteresis

High Side Pull Up Resistance

V_IF

V_IH

R_PUH

1.45

1.0

Ω

2EDL8x23

2EDL8x24

R_PDH

R_PUL

High Side Pull Down Resistance

Low Side Pull Up Resistance

0.5

Ω

1.45

1.0

2EDL8x23

2EDL8x24

R_PDL

Low Side Pull Down Resistance

0.35

Ω

¹HB (high side bootstrap) related ratings referenced to V_HS

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Characteristics

4.5

Dynamic Electrical Characteristics

V_DD= V_HB= 12 V, V_HS=V_SS=0V. T_C= 25^oC unless otherwise specified.

Symbol

Description

Min

---

Typ

Max Units Conditions

---

V_HO= 0 V , 2EDL8x23

I_PUH

High Side Peak Pull Up Current¹

---

V_HO= 0 V , 2EDL8x24

High Side Peak Pull Down

Current¹

I_PDH

I_PUL

---

V_HO= 12 V

---

V_LO= 0 V , 2EDL8x23

V_LO= 0 V , 2EDL8x24

V_LO= 12 V

Low Side Peak Pull Up Current¹

Low Side Peak Pull Down Current¹

Rising Propagation Delay^{2 3}

Falling Propagation Delay⁴

Delay Matching⁵

Minimum Input Pulse Width⁶

Bootstrap Diode Turn off Time⁷

I_PDL

T_DR

T_DF

C_LOAD= 0

T_DM

T_PW

T_DRR

---

I_F= 20 mA, I_PRR= 0.5 A

4.6

Thermal Mechanical Characteristics

Symbol

Description

Min Typ Max Units Conditions

R_thJC

Junction to Case Thermal

Resistance

VDSON-8

VSON-10

---

°C/W Bottom

°C/W Top

5.8

°C/W Bottom

°C/W Top

R_thJA

Device on PCB

6 cm²cooling area⁸

VDSON-8

VSON-10

°C/W

¹Not subject to production test.

²Rising propagation delay from LI to LO and from HI to HO

³A transient detector blocks the toggling of the high side output when it detects moving phase node (due to transition and/or

oscillation). It prevents unwanted retoggling but may increase propagation delay. See transient detector activation in Figure 7.

⁴Falling propagation delay from LI to LO and from HI to HO

⁵Consolidated delay matching (1) ON: between LO rising and HO falling and (2) OFF: between LO falling and HO rising

⁶Minimum input pulse width that produces valid output signal

⁷External schottky boot diode in parallel recommended for high dv/dt application

⁸Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm²(one layer, 70 µm thick) copper area for drain connection. PCB vertical in

still air

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Descriptive Illustration

3.3V / 5.0V

VSS

Dt_IN

VDD

PGND

t_LH

t_HL

t_LH

t_HL

Dt_OUT

Figure 6

Propagation delay

Figure 7

UVLO behavior

Transient

Detector

Response

Active

Inactive

dv/dt

Slew-rate

Threshold

Figure 8

Transient Detector Response³

³Reference slew rate threshold versus temperature under Section 6 Typical Characteristics

Datasheet 12

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Typical Characteristics

Quiescent Current vs. V_DD

Diode Current vs. Voltage

1.00E-01

1.00E-02

1.00E-03

1.00E-04

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

IVDD

IHB

T_J= 25 °C

1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7

10 11 12 13 14 15 16 17

V_DD[V]

V_DIODE[V]

I_DDOperating Current vs. Temperature

I_HBOperating Current vs. Temperature

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0pF, -40°C

V_DD= 12 V

0pF, 25°C

0pF, -40°C

0pF, 25°C

0pF, 150°C

1nF, -40°C

1nF, 25°C

1nF, 150°C

4.7nF, -40°C

4.7nF, 25°C

4.7nF, 150°C

V_DD= 12 V

0.06

0.05

0.04

0.03

0.02

0.01

0pF, 150°C

1nF, -40°C

1nF, 25°C

1nF, 150°C

4.7nF, -40°C

4.7nF, 25°C

4.7nF, 150°C

1.00E+04

1.00E+05

Switching Frequency [Hz]

1.00E+06

1.00E+04

1.00E+05

Switching Frequency [Hz]

1.00E+06

LO Output Voltage (Pull-up) vs.

Temperature

HO Output Voltage (Pull-up) vs.

Temperature

V_DD= 12V

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

0.24

0.21

0.18

0.15

0.12

0.09

0.06

0.03

V_DD= 12V

2EDL8x24

2EDL8x23

-50

100

150

-50

100

150

Junction Temperature [°C]

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Typical Characteristics

LO Output Voltage (Pull-down) vs.

Temperature

HO Output Voltage (Pull-down) vs.

Temperature

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

V_DD= 12V

2EDL8x24

2EDL8x23

-50

100

150

-50

100

150

Junction Temperature [°C]

Input Threshold vs. Supply Voltage

Input Threshold vs. Temperature

2.5

1.5

0.5

Vth_H

Vth_L

Vth_H

Vth_L

T_J= 25 °C

150

T_J= 25 °C

V_DD[V]

100

Junction Temperature [°C]

UVLO Threshold vs. Temperature

UVLO Threshold Hysteresis vs.

Temperature

0.6

0.5

0.4

0.3

0.2

0.1

VTH_rise_hb

VTH_fall_hb

VTH_rise_vdd

VTH_fall_vdd

HYST_HB

HYST_VDD

-50

100

150

100

150

Junction Temperature [°C]

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Typical Characteristics

Propagation Delay vs. Temperature

Propagation Delay vs. V_DD

56.00

54.00

52.00

50.00

48.00

46.00

44.00

42.00

40.00

del_rise_HI_HO

del_fall_HI_HO

del_rise_LI_LO

del_fall_LI_LO

del_rise_HI_HO

del_fall_HI_HO

del_rise_LI_LO

del_fall_LI_LO

V_DD= 12 V

150

T_J= 25 °C

-50

100

V_DD[V]

Junction Temperature [°C]

Delay Matching vs.Temperature

Transient Detector Threshold vs.

Temperature

0.3

0.25

0.2

del_match_ton

del_match_toff

nom

0.15

0.1

-2

-4

-6

-8

0.05

V_DD= 12 V

100 150

V_DD= 12 V

150

-50

100

-50

Junction Temperature [°C]

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Application and Guidelines

7.1

Typical Application Diagram

Figure 9

Typical Application 1 – Primary Side Half-bridge

Figure 10

Typical Application 2 – Full-bridge Secondary Side Rectification

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Application and Guidelines

7.2

Design Guidelines

In a half-bridge configurations, a high-side bias which is referenced to the switch node is needed in order to

drive the gate of the high-side mosfet. One of the most common solutions due to its simplicity and low cost is

the usage of a bootstrap circuit consisting of a resistor, a diode (internal to the driver) and a capacitor as seen in

Figure 11. However, this method imposes limitation on the power converter’s duty cycle due to the

requirement of recharging the bootstrap capacitor. This limitation can be mitigated through the proper

selection of the bootstrap components.

Figure 11 Gate drive circuitry using 2EDL8x2x to drive mosfet in a half-bridge configuration

The bootstrap circuit operation is defined by two main periods:

Charging period: When the low-side mosfet ( Q2 ) is ON and the high-side mosfet ( Q1) is OFF, the switch node /

HS pin is pulled to ground creating a charging path for the bootstrap capacitor ( C_boot) through the Vdd bypass

capacitor ( C_Vdd), and the internal bootstrap diode. For high dV/dt application, it is recommended to use an

extrenal bootstrap diode.

Discharging period: When the low-side mosfet ( Q2 ) is turned OFF and the high-side mosfet ( Q1 ) starts

conducting, the switch node / HS pin is pulled to the high voltage V_inthus the internal bootstrap diode gets

reverse biased. The bootstrap capacitor ( C_boot) will then discharge some of its stored charges to the gate of the

high-side mosfet as well as to other contributing factors such as the mosfet’s gate-source leakage current,

floating section quiescent current, floating section leakage current and the internal bootstrap diode reverse

bias leakage current.

Typical waveform for the voltage across C_bootas a function of time is shown in Figure 12 where the various

contributions have been distinguished. The voltage across C_bootincreases during the charging period and then it

drops with a high negative dV/dt as it charges the gate of the high-side mosfet ( Q1 ). After which, the C_boot

voltage continues to drop but with a much lower slope because only the high-side bias current and some

leakage current is discharing the C_bootduring this phase.

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Application and Guidelines

Figure 12

Typical C_bootwaveform

7.2.1

Bootstrap Capacitor Selection

The bootstrap capacitor provides the necessary charge to drive the high-side mosfet and thus it needs to be

sized in such a way that the maximum voltage drop across this capacitor will not fall below the high-side UVLO

threshold during transient and normal operations. First, determine the maximum allowable voltage drop

(ΔV_{Cboot_max}) when the high-side mosfet (Q1) is on which is given by the following formula:

ꢀꢁ_{ꢂꢃꢄꢄꢅ_ꢆꢇꢈ}= ꢁ_ꢉꢉ− ꢁ_ꢊ− ꢁ_ꢋꢌꢍ− ꢁ_ꢋꢌꢋ

(1)

Where:

V_dd= Gate driver supply voltage

V_F= Bootstrap diode forward voltage drop with typical value of 1.25 V at

I_F=100 uA and 2.15 V at I_F=100 mA , T_J=25°C

V_HBR= HB UVLO rising threshold

V_HBH= HB UVLO threshold hysteresis

Next, determine the total charge (Q_T) that must be delivered by the bootstrap capacitor at maximum duty cycle.

As mentioned, there are several factors that contribute to the discharge of the bootstrap capacitor such as the

Q1’s total gate charge, Q1’s gate-source leakage current, HB quiescent current, HB leakage current, bootstrap

diode reverse bias leakage current and bootstrap capacitor leakage current ( if using an electrolytic capacitor ).

For sake of simplicity, only Q1’s total gate charge and HB quiescent and leakage current are considered as the

other sources of leakage are negligible in comparison.

ꢑ_ꢋꢌ

ꢕ_ꢆꢇꢈ

ꢎ_ꢏ= ꢎ_ꢐ+

+ ꢑ_ꢋꢌ

(2)

ꢒ

ꢓꢔ

ꢒ

ꢓꢔ

Where:

Q_G= high-side mosfet (Q1) total gate charge

I_HB= HB maximum quiescent current

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Application and Guidelines

I_HBS= HB to VSS leakage current with a typical value of 1.25 mA at 90 V HB

voltage and T_J=25°C

D_max= maximum duty cycle

F_sw= switching frequency

The minimum bootstrap capacitor value can then be calculated using the formula:

ꢎ_ꢏ

ꢖ_{ꢃꢄꢄꢅ_ꢆꢗꢘ}

≥

(3)

ꢀꢁ_{ꢂꢃꢄꢄꢅ ꢆꢇꢈ}

7.2.2

VDD Bypass Capacitor Selection

The Vdd bypass capacitor provides the charge for the bootstrap capacitor during the charging period. As a rule

of thumb, the Vdd bypass capacitor should be sized to be atleast 10~20 times larger than the bootstrap

capacitor. This equates to a voltage ripple of 5~10% in the Vdd capacitor.

ꢖ_ꢙꢉꢉ≥ 10~20 × ꢖ_ꢃꢄꢄꢅ

(4)

7.2.3

Bootstrap Resistor Selection

The bootstrap resistor limits the current in the bootstrap diode during start-up when the bootstrap capacitor is

initially completely discharged. The peak current through this resistor is given by:

ꢁ_ꢜꢜ− ꢁ_ꢊ

ꢑ_{ꢚꢛ_ꢍꢃꢄꢄꢅ}

(5)

ꢝ_ꢃꢄꢄꢅ

The bootstrap resistor together with the bootstrap capacitor introduces a time constant and should be sized

appropriately to achieve the desired start-up time. For this calculation, it is assumed that the bootstrap

capacitor is fully charged after 4 time constant. With this, R_bootcan be calculated using the following formula:

ꢞ_ꢆꢗꢘ

ꢝ_ꢃꢄꢄꢅ

≤

(6)

4 × ꢖ_ꢃꢄꢄꢅ

Where:

t_min= minimum on time of the low-side mosfet (Q2)

7.2.4

External Bootstrap Diode Selection

For high dV/dT applications, an external bootstrap diode is recommended to be in parallel with the internal

bootstrap diode. A fast recovery or schottky diode with low forward voltage drop is recommended in order to

minimize the losses and leakage current. It should be chosen such that it can handle the peak transient current

from Equation (5) during start-up conditions and the blocking voltage rating should be higher than the

maximum input voltage (V_in) with enough derating.

7.2.5

Gate Resistor Selection

The turn-on and turn-off external gate resistors control the turn-on and turn-off current of the gate driver

providing an external way to control the switching speed of the mosfet for purposes such as voltage overshoot

control, ringing reduction, EMI mitigation, spurious turn-on protection, shoot –through protection etc. The

following formulas shows the effect of the external gate resistor to the output current capability of the gate

driver.

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Application and Guidelines

ꢁ_ꢜꢜ− ꢁ_ꢊ

ꢑ_ꢋꢟꢍꢂ

ꢑ_ꢋꢟꢡꢢ

ꢑ_ꢣꢟꢍꢂ

(7)

(8)

ꢝ_ꢚꢠꢋ+ ꢝ_{ꢐ_ꢋꢟ}+ ꢝ_{ꢐ_ꢗꢘꢅ}

ꢁ_ꢜꢜ− ꢁ_ꢊ

ꢝ_ꢚꢜꢋ+ ꢝ_{ꢐ_ꢋꢟ}+ ꢝ_{ꢐ_ꢗꢘꢅ}

ꢁ_ꢜꢜ

(9)

ꢝ_ꢚꢠ+ ꢝ_{ꢐ_ꢣꢟ}+ ꢝ_{ꢐ_ꢗꢘꢅ}

ꢁ_ꢜꢜ

ꢑ_ꢣꢟꢡꢢ

(10)

ꢝ_ꢚꢜꢣ+ ꢝ_{ꢐ_ꢣꢟ}+ ꢝ_{ꢐ_ꢗꢘꢅ}

Where:

I_HSRC= High-side peak source current

I_HSNK= High-side peak sink current

I_LSRC= Low-side peak source current

I_LSNK= Low-side peak sink current

R_PUH= High-side pull-up resistance

R_PDH= High-side pull-down resistance

R_PUL= Low-side pull-up resistance

R_PDL= Low-side pull-down resistance

V_DD= Gate driver supply voltage

V_F= Bootstrap diode forward voltage drop

R_{G_HS}= High-side external gate resistance

R_{G_LS}= Low-side external gate resistance

R_{G_int}= Mosfet internal gate resistance

For a detailed discussion on how to optimize the gate resistors, a dedicated application note with link in the

reference section, e.g. [2], can be viewed.

7.3

PCB Layout Guidelines

In order to maximize the performance of EiceDRIVER^TM2EDL8x2x, below are some recommendations on how to

optimize the PCB layout



Use a low-ESR decoupling capacitors on VDD-GND and HB-HS and placed it as close as possible to the VDD-

GND and HB-HS pins of the driver



An option for a series boot resistor is recommended to control the high side mosfet slew rate and therefore

the low side mosfet overshoot. The boot loop path including the VDD capacitor, boot diode, boot series

resistor and boot capacitor should be as small as possible



It is recommended to have an external boot diode placement for high dv/dt application.

Placement for gate resistor is also recommended to control the switching speed of the mosfet. Both the gate

resistor and the mosfet should be placed as close as possible to the driver in order to minimize the gate loop

inductance.



Use copper plane underneath the exposed GND pad of the driver and connect it to buried copper plane(s)

with multiple thermal vias for better heat dissipation into the PCB.

Connection to the HS pin of the driver from the high side mosfet source and low side mosfet drain should be

as short and wide as possible and avoid connecting it directly through the high switching current path.



LO and HO traces should be as short and wide as possible

Avoid letting the LI and HI signal trace to come close to high dV/dT traces which might induce significant

noise.

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Application and Guidelines

Figure 13

2EDL8x2x Layout Example

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Outline Dimensions

8.1

PG-VDSON-8-4 Package Outline

Figure 14

PG-VDSON-8-4 Outline Dimensions

Figure 15

PG-VDSON-8-4 Footprint Dimensions

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Outline Dimensions

8.2

PG-VSON-10-4 Package Outline

Figure 16

PG-VSON-10-4 Outline Dimensions

Figure 17

PG-VSON-10-4 Footprint Dimensions

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V Boot, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

Reel and Tape

Reel  330 mm: 6000 pcs/ reel

Figure 18

PG-VDSON-8-4 Reel and Tape

Figure 19

PG-VSON-10-4 Reel and Tape

Datasheet

Rev. 2.8

2022.06.29

EiceDRIVER^TM2EDL8x2x

120 V, 3 A / 4 A, Junction-Isolated High Side and Low Side Gate Driver ICs

References

[1]

[2]

Alan Huang, Understanding the transient detector, Infineon Technologies AG, Neubiberg 2020

A2015-06 EiceDRIVER^TM– gate resistor for power devices

Datasheet

Rev. 2.8

2022.06.29

120VꢀBoot,ꢀ3A/4A,ꢀJunction-IsolatedꢀHighꢀSideꢀandꢀLowꢀSideꢀGateꢀDriverꢀICs

2EDL8x2x

RevisionꢀHistory

2EDL8x2x

Revision:ꢀ2022-09-23,ꢀRev.ꢀ2.8

Previous Revision

Revision Date

Subjects (major changes since last revision)

2.2

2.3

Separate table for ESD rating and remove footnote 1 under Abs Max Rating

2020-07-28

2020-10-20

Update footprint, LO/HO Pull-up resistance, LO/HO Output voltage, maximum delay

spec, HB operating current and remove external diode in diagrams.

2.4

2.5

2.6

Update Tape and Reel specification

Include VSON-10 3x3 package details

2020-12-30

2021-10-11

Add repetitive pulse note, minimum DC rating for HS, differential input voltage, minimum

input rising threshold, maximum input falling, description leakage current, removed

2EDL812x voltage description, rename "input control" and fix footnote numbering.

2022-04-25

2.7

2.8

Update marking pin in Tape and Reel and 3D drawing for PG-VSON-10-4

Update UVLO illustration and description.

2022-05-12

2022-09-23

Trademarks

Allꢀreferencedꢀproductꢀorꢀserviceꢀnamesꢀandꢀtrademarksꢀareꢀtheꢀpropertyꢀofꢀtheirꢀrespectiveꢀowners.

WeꢀListenꢀtoꢀYourꢀComments

Anyꢀinformationꢀwithinꢀthisꢀdocumentꢀthatꢀyouꢀfeelꢀisꢀwrong,ꢀunclearꢀorꢀmissingꢀatꢀall?ꢀYourꢀfeedbackꢀwillꢀhelpꢀusꢀtoꢀcontinuously

improveꢀtheꢀqualityꢀofꢀthisꢀdocument.ꢀPleaseꢀsendꢀyourꢀproposalꢀ(includingꢀaꢀreferenceꢀtoꢀthisꢀdocument)ꢀto:

erratum@infineon.com

Publishedꢀby

InfineonꢀTechnologiesꢀAG

81726ꢀMünchen,ꢀGermany

AllꢀRightsꢀReserved.

LegalꢀDisclaimer

Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ

(“Beschaffenheitsgarantie”)ꢀ.

Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe

product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation

warrantiesꢀofꢀnon-infringementꢀofꢀintellectualꢀpropertyꢀrightsꢀofꢀanyꢀthirdꢀparty.

Inꢀaddition,ꢀanyꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀisꢀsubjectꢀtoꢀcustomer’sꢀcomplianceꢀwithꢀitsꢀobligationsꢀstatedꢀinꢀthis

documentꢀandꢀanyꢀapplicableꢀlegalꢀrequirements,ꢀnormsꢀandꢀstandardsꢀconcerningꢀcustomer’sꢀproductsꢀandꢀanyꢀuseꢀofꢀthe

productꢀofꢀInfineonꢀTechnologiesꢀinꢀcustomer’sꢀapplications.

Theꢀdataꢀcontainedꢀinꢀthisꢀdocumentꢀisꢀexclusivelyꢀintendedꢀforꢀtechnicallyꢀtrainedꢀstaff.ꢀItꢀisꢀtheꢀresponsibilityꢀofꢀcustomer’s

technicalꢀdepartmentsꢀtoꢀevaluateꢀtheꢀsuitabilityꢀofꢀtheꢀproductꢀforꢀtheꢀintendedꢀapplicationꢀandꢀtheꢀcompletenessꢀofꢀtheꢀproduct

informationꢀgivenꢀinꢀthisꢀdocumentꢀwithꢀrespectꢀtoꢀsuchꢀapplication.

Information

Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon

TechnologiesꢀOfficeꢀ(www.infineon.com).

Warnings

Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,

pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.

TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or

automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa

failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand

aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare

intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis

reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.

Rev.ꢀ2.8,ꢀꢀ2022-09-23

2EDL8024G3C [INFINEON]

相关型号：

2EDL8123G3C

2EDL8124G3C

2EDN7424

2EDN7424F

2EDN7424R

2EDN7523F

2EDN7523G

2EDN7523R

2EDN7524F

2EDN7524F_15

2EDN7524F_16

2EDN7524G