2EDR7259X [INFINEON]
The EiceDRIVER™ 2EDR7259X is a reinforced isolated gate driver IC for control over the mandatory safe isolation barrier in SMPS. The strong 5 A/9 A source/sink dual-channel gate driver comes with a very high 150 V/ns CMTI (common mode transient immunity) for robust operation with CoolGaN™ GIT HEMTs and high-power switching noise environment.;
| 型号： | 2EDR7259X |
| 厂家： | 
Infineon |
| 描述： | The EiceDRIVER™ 2EDR7259X is a reinforced isolated gate driver IC for control over the mandatory safe isolation barrier in SMPS. The strong 5 A/9 A source/sink dual-channel gate driver comes with a very high 150 V/ns CMTI (common mode transient immunity) for robust operation with CoolGaN™ GIT HEMTs and high-power switching noise environment. 驱动 |
| 文件： | 总34页 (文件大小：4376K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X is a family of dual-channel isolated gate driver ICs, designed
to drive Si and SiC MOSFETs and GaN HEMTs power switches. All products are available in a DSO package with
8 mm input-to-output creepage and provide reinforced isolation by means of on-chip coreless transformer (CT)
technology. 2EDRx259X and 2EDRx258X variants in a 14-pin DSO package offer increased channel-to-channel
creepage. They are suited for use in applications with higher bus voltage or higher pollution degree and,
in general, can ease PCB routing. All versions offer optional shoot-through protection (STP) and dead-time
control (DTC) functionality. This allows the operation as dual-channel low-side, dual-channel high-side or
half-bridge gate driver with a configurable dead-time. With excellent common-mode transient immunity (CMTI),
low part-to-part skew and fast signal propagation, the products are best suited for use in fast-switching power
conversion systems.
Features
Table 1
Portfolio
•
2-channel isolated gate driver for Si and SiC
MOSFETs and GaN HEMTs power switches
Part number UVLO EN/DIS Package
•
Fast input-to-output propagation (38 ns) with
excellent stability (+9/-5 ns)
2EDR8259H
2EDR7259X
2EDR8259X
2EDR9259X
2EDR8258X
2EDR6258X
2EDR9258X
8 V
DIS
DIS
DIS
DIS
EN
DSO16-300mil
DSO14-300mil
DSO14-300mil
DSO14-300mil
DSO14-300mil
DSO14-300mil
DSO14-300mil
4 V
•
•
•
•
•
•
Strong output stage: 5 A/9 A source/ sink
Fast output clamping for VDDA/B < UVLO
Fast UVLO recovery time (< 2 μs)
8 V
15 V
8 V
Four VDDA/B UVLO options: 4 V, 8 V, 12 V, 15 V
CMTI > 150 V/ns
12 V
15 V
EN
Available in 16/14-pin 300 mil DSO package
EN
Isolation and safety certificates
•
Potential applications
UL1577 with VISO = 5700 VRMS (certification n.
E311313)
VDE0884-11 with VIOTM = 8000 Vpk, VIORM = 1767 Vpk
VIOSM = 6875 Vpk (certification n. 40052310)
IEC 60747-17 (certification n. 40055138)
IEC62368-1 (certification n. 40052310, appendix
500Z1)
•
•
•
•
•
Server, telecom SMPS
EV Off-board chargers
Low-voltage drives and power tools
Solar micro inverter, solar optimizer
Industrial power supply (SMPS, Residential UPS)
•
,
•
•
Product validation
Fully qualified for industrial applications
HV BUS
1
2
3
4
5
14
13
PWM1
INA
VDDA
OUTA
GNDA
Floating
Gate Driver
ChA
PWM2
VDD
INB
VDDI
GNDI
DIS
12
functional
Ch-Ch
Logic
input
isolation
GPIOx
6
11
10
Floating
Gate Driver
ChB
DTC
N.C.
VDDB
7
8
OUTB
GNDB
9
VDDI
reinforced in-out
isolation
Figure 1
Application diagram
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power supply and Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input stage - INA, INB, DISABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Shoot-through protection and configurable dead-time - STP/DTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Gate driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Fast active output clamping in UVLO conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CT communication and input to output data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
3.2
3.3
3.4
3.5
4
5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package DSO16-300mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package DSO14-300mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
6.2
6.3
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Datasheet
2
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
1 Pin configuration and description
1
Pin configuration and description
INA
INB
VDDA
OUTA
GNDA
N.C.
INA
INB
VDDA
OUTA
GNDA
INA
INB
VDDA
OUTA
GNDA
1
2
3
4
5
6
7
16
15
14
13
12
11
1
2
3
4
5
6
7
14
13
12
1
2
3
4
5
6
7
14
13
12
VDDI
GNDI
VDDI
GNDI
VDDI
GNDI
2EDRx259X
2EDR8259H
2EDRx258X
DIS
N.C.
DIS
EN
STP/DTC
VDDB
OUTB
GNDB
STP/DTC
VDDB
OUTB
GNDB
STP/DTC
VDDB
OUTB
GNDB
11
11
N.C.
N.C.
N.C.
10
9
10
9
10
9
VDDI
8
VDDI
8
VDDI
8
Figure 2
Table 2
Pin configuration (top side view)
Pin description
Pin
Pin
Symbol Description
16-pin
14-pin
1
2
1
2
INA
INB
Input signal channel A
Logic input with TTL compatible thresholds and internal pull-down resistor
Input signal channel B
Logic input with TTL compatible thresholds and internal pull-down resistor
3,8
4
3,8
4
VDDI
Input-side supply voltage (operating range: 3 V to 17 V)
GNDI
Ground primary-side
5
5
DIS/ EN
Disable input channel A and B (active high)
If DIS is low or lef open, OUTA/OUTB are controlled by INA/INB
DIS high causes OUTA/OUTB low
ENABLE input channel A and B (active high)
If EN is high, OUTA/OUTB are controlled by INA/INB
EN low or lef open causes OUTA/OUTB low
6
6
STP/DTC Shoot-through Protection (STP) and Dead-Time Control (DTC)
If STP/DTC is high or lef open, OUTA and OUTB can overlap (SPT and DTC
disabled).
If STP/DTC is connected to GNDI with a resistance RDTC, OUTA and OUTB
cannot overlap and a “safe dead-time” can be configured: tdt [ns] = 10
x RDTC [kΩ]
If STP/DTC is connected to GNDI, OUTA and OUTB cannot overlap (STP only
enabled)
Connecting capacitors to the DTC pin must be avoided.
7,12,13
7
N.C.
No internal connection
9
9
GNDB
OUTB
Ground secondary-side channel B
10
10
Output secondary-side channel B
Low-impedance output with source and sink capability
11
14
11
12
VDDB
GNDA
Supply secondary-side channel B (operating range: UVLO to 20 V)
Ground secondary-side channel A
(table continues...)
Datasheet
3
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
1 Pin configuration and description
Table 2
(continued) Pin description
Symbol Description
Pin
Pin
16-pin
14-pin
15
13
OUTA
Output secondary-side channel A
Low-impedance output with source and sink capability
16
14
VDDA
Supply secondary-side channel A (operating range: UVLO to 20 V)
For package drawing details see Chapter 6.
Datasheet
4
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
2
Functional description
2.1
Block diagram
A simplified functional block diagram for EiceDRIVER™ 2EDR8259H, 2EDRx259X is given in Figure 3.
NC
7
1
UVLO
16
15
VDDA
INA
VDDI
VDDA
RX
TX
OUTA
GNDA
Active
Clamping
3,8
5
UVLO
14
11
Dead
Time
Control
Channel to Channel Isolation
DISABLE
UVLO
VDDB
INB
2
6
VDDB
10
9
RX
TX
OUTB
GNDB
STP/DTC
Active
Clamping
4
GNDI
Figure 3
Block diagram
2.2
Power supply and Undervoltage Lockout (UVLO)
Due to the input-to-output and channel-to-channel isolation, three power domains with independent power
management are required. Undervoltage Lockout (UVLO) functions for both input and output supplies ensure a
defined startup and robust functionality under all operating conditions.
2.2.1
Input supply voltage
The input die is powered via VDDI and supports a wide supply voltage range from 3 V to 17 V. A ceramic
bypass capacitor must be placed between VDDI and GNDI in close proximity to the device; a minimum bypass
capacitance of 100 nF is recommended.
Power consumption to some extent, depends on switching frequency, as the input signal is converted into a
train of repetitive current pulses to drive the coreless transformer. Due to the chosen robust encoding scheme
the average repetition rate of these pulses and thus the average supply current depends on the switching
frequency, fsw. However, for fsw < 500 kHz this effect is very small.
The Undervoltage Lockout function for the input supply VDDI ensures that, as long as VDDI is below UVLO (e.g. in
startup), no data is transferred to the output side and the gate driver output is held low (safety Lock-down at
startup). When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output
side is ready (not in UVLO condition), the output reacts according to the logic input.
2.2.2
Output supply voltage
The two output dies are powered via two independent supply voltages VDDA and VDDB (up to 20 V).
Two ceramic bypass capacitors must be placed between VDDA and GNDA and between VDDB and GNDB in close
proximity to the device. A minimum capacitance of 20 x Ciss (MOSFET input capacitance) is recommended to
ensure an acceptable ripple (5% of VDDO) on the supply pin.
The minimum supply voltage is set by the Undervoltage Lockout (UVLO) function. The gate driver output
can be switched only if the output supply voltage (VDDA, VDDB) exceeds the output-side UVLO. Thus, it can be
guaranteed that the switch transistor is not operated if the driving voltage is too low to achieve a complete
and fast transition to the "on" state. Low driving voltage, in fact, could cause the power MOSFET to enter its
saturation (ohmic) region with potentially destructive power dissipation; the output UVLO ensures that the
Datasheet
5
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
switch transistor always stays within its Safe Operating Area (SOA). Versions with 4 V, 8 V, 12 V and 15 V UVLO
thresholds for the output supply are currently available. Table 3 shows the recommended UVLO levels for
different Infineon power switch families.
Table 3
Recommended UVLO levels for typical use-cases
Inputs
Examples of part number
Recommended driver
Logic level OptiMOS™
BSC010N04LS6, BSZ070N08LS5, ..
2EDR7259 (4 V UVLO)
Normal level OptiMOS™ BSC040N10NS5, BSZ084N08NS5, ..
2EDR825x (8 V UVLO)
CoolMOS™
IPP60R099C7, IPB60R600P6, ..
2EDR825x (8 V UVLO)
650 V CoolSiC™
650 V CoolGaN™
IMZA65R027M1H, IMW65R107M1H, ..
IGOT60R070D1, IGLD60R070D1, ..
2EDR6258/ 2EDR925x (12/15 V UVLO)
2EDR7259 (4 V UVLO for unipolar driving)
2EDR825x (8 V UVLO for bipolar driving)
2.3
Input stage - INA, INB, DISABLE
The inputs INA and INB control two independent PWM channels. The input signal is transferred non-inverted to
the corresponding gate driver outputs OUTA and OUTB. All inputs are compatible with LV-TTL threshold levels
and provide a hysteresis of typically 0.8 V. The hysteresis is independent of the supply voltage VDDI
.
The PWM inputs are internally pulled down to a logic low voltage level (GNDI). In case the PWM-controller
signals have an undefined state during the power-up sequence, the gate driver outputs are forced to the
"off"-state (low).
If the DIS/EN input is at high/low state, this unconditionally drives both channel outputs to low state regardless
of the state of INA or INB.
Table 4 and Table 5 shows the INA, INB, DIS/EN driver logic in case of sufficiently high supply voltage. Otherwise
the outputs of the driver are determined by the Undervoltage Lockout (UVLO) and Output Active Clamping
functionalities as shown in Table 8.
Table 4
Logic table in case of sufficient bias power - INA, INB, DIS
Inputs
INA
DIS
Supplies
VDDI
VDDA
Outputs
Note
INB
,
,
OUTA OUTB
VDDB
L
L
L or lef open
L or lef open
L or lef open
> UVLOVDDx,on
(active)
L
L
H
L
L
L
–
L
H
H
H
H
L
–
H
DTC/STP pin tied to VDDI or lef open
DTC/STP pin tied to GNDI via RDTC
Input pins internally pulled down
Lef
open open
Lef
L or lef open
L
x
x
H
L
L
Outputs disabled via DIS high
Datasheet
6
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
Table 5
Logic table in case of sufficient bias power - INA, INB, EN
Inputs
INA
EN
Supplies
VDDI
VDDA
Outputs
Note
INB
,
,
OUTA OUTB
VDDB
L
L
H
H
H
> UVLOVDDx,on
(active)
L
L
H
L
L
L
–
L
H
H
H
H
L
–
H
DTC/STP pin tied to VDDI or lef open
DTC/STP pin tied to GNDI via RDTC
Input pins internally pulled down
Lef
open open
Lef
H
L
x
x
L or lef open
L
L
Outputs disabled via EN low
Datasheet
7
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
2.4
Shoot-through protection and configurable dead-time - STP/DTC
The shoot-through protection pulls down the outputs OUTA and OUTB when both input signals INA, INB are at
high state. Its activation is recommended when the driver is used as half-bridge driver to prevent dangerous
shoot-through due to unwanted overlap of INA and INB. A dead-time can be ensured and configured via pin
STP/DTC as shown in Table 6.
Table 6
STP/DTC logic table
Conditions on the STP/DTC pin
Shoot-through
protection
Configurable dead-time
Tied to VDDI or lef open
Disabled
Enabled
Disabled
Connected to GNDI via resistor RDTC
Enabled with tdt [ns] = 10 x RDTC
[kΩ]; allowed RDTC range is 1kΩ to
100kΩ
Connected to GNDI
Enabled
Disabled
The driver dead-time logic is triggered during the falling edge of an input and delays the rising transition of the
other input. The delay is only assigned if the driver configured dead-time is longer than the inputs signals’ own
dead-time.
The dead-time can be configured by changing the current fed into the STP/DTC pin via an external resistance
according to the formula: tdt [ns] = 10 x RDTC [kΩ]. It is recommended to use resistors with 1% accuracy in the
1 kΩ to 100 kΩ range. Connecting capacitors to the DTC pin must be avoided.
INA
INB
tdt
tdt
tdt
OUTA
tdt
tdt
tdt
OUTB
A
B
D
F
C
E
Figure 4
Table 7
Logic for STP/DTC pin connected to GNDI via resistance RDTC
Logic for STP/DTC pin connected to GNDI via resistance RDTC
Condition
STP/DTC logic
A, B
The driver logic assigns the configured dead-time since it is longer than the input
signals’ dead-time
C, D
E, F
The driver logic does not assign the configured dead-time since it is shorter than
the input signals’ dead-time
The shoot-through protection pulls down the outputs OUTA, OUTB until one of the
outputs goes low. At this point, afer the configured driver dead-time, the other
output is allowed to go high
Datasheet
8
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
2 Functional description
2.5
Gate driver outputs
The rail-to-rail output stage realized with complementary MOS transistors is able to provide a typical 5 A
sourcing and 9 A sinking peak current. The low on-resistance coming together with high driving current is
particularly beneficial for fast switching of very large MOSFETs. With a Ron of ∼1 Ω for the sourcing pMOS and
∼0.5 Ω for the sinking nMOS transistor the driver can in most applications be considered as a nearly ideal
switch. The p-channel sourcing transistor enables real rail-to-rail behavior without suffering from the voltage
drop unavoidably associated with nMOS source follower stages.
In case of floating inputs or insufficient supply voltage not exceeding the UVLO thresholds, the driver outputs
are actively clamped to the "low" level (GNDA, GNDB).
2.6
Fast active output clamping in UVLO conditions
The Undervoltage Lockout (UVLO) ensures that the gate driver output is not operated if the supplies are below
the UVLO thresholds. However, this is not sufficient to guarantee that the output of the driver is kept low.
Transients or noise in the power stage may pull-up the output node of the driver and the gate voltage causing
an unwanted turn-on of the switch; this is particularly critical in system using bootstrapping since, during
start-up, the supply of the high-side channel is delayed, while the low-side MOSFET is already switching. In
resonant topologies (as LLC), the half-bridge switching node may be pulled up afer the turn-off of the low-side
switch. When the low-side MOSFET is turned on again, the high-side gate voltage increase induced by dV/dt
event cannot be clamped by the driver RDSON,sink if the bootstrap supply is not yet available.
With a fast output clamping circuit in the output stage, the driver ensures safe operation against output
induced overshoots in all UVLO situations. This structure allows fast reaction and effective clamping of the
output pins (OUTA, OUTB). The exact reaction time depends on the output supply (VDDA, VDDB) and on the
output voltage levels; however, already for very low supply levels (~1 V), the active output clamp is able to react
in some tens of ns.
Undervoltage Lockout together with the output active clamping ensures that the outputs are actively held low
in case of insufficient supply voltages.
Table 8
Logic table in case of insufficient bias power - INA, INB, DISABLE
Inputs
DIS
Supplies
Outputs
INA INB
VDD
VDDA
VDDB
OUTA
OUTB
x
x
x
x
x
x
x
x
x
< UVLOVDDI,on
> UVLOVDDI,on
> UVLOVDDI,on
x
x
L
L
L
L
L
< UVLOVDDI,on
> UVLOVDDI,on
< UVLOVDDI,on
< UVLOVDDI,on
Follows
INA
x
x
x
> UVLOVDDI,on
< UVLOVDDI,on
> UVLOVDDI,on
L
Follows
INB
2.7
CT communication and input to output data transmission
A coreless transformer (CT) based communication module is used for PWM signal transfer between input
and output. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog
timeout at the receiver side enables recovery from communication fails and ensures safe system shut-down in
failure cases.
Datasheet
9
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
3
Electrical characteristics
The absolute maximum ratings are listed in Table 9. Stresses beyond these values may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
3.1
Absolute maximum ratings
Table 9
Parameter
Absolute maximum ratings
Symbol
Min.
Values
Typ.
Unit Note or condition
Max.
Input supply voltage
VDDI
-0.3
-0.3
–
–
18
22 1)
V
V
–
–
Output supply voltage at
pins VDDA, VDDB
VDDA, VDDB
Voltage at pins INA, INB,
DIS/EN (DC)
VIN
VIN
-0.3
-5
–
–
18
V
V
–
Voltage at pins INA, INB,
DIS/EN (transient)
–
transient for 50 ns 3)
2)
Voltage at pin DTC
VDTC
VOUT
–
–
VDDI + 0.3
V
V
–
–
Voltage at pins OUTA,
OUTB (DC)
-0.3
VDDA/B
+
0.3
Voltage at pins OUTA,
OUTB (transient)
VOUT
-2
-5
–
–
–
–
VDDA/B
1.5
+
V
transient for 200 ns 3)
Reverse current peak at
pins OUTA, OUTB
ISRC_rev
ISNK_rev
–
Apk transient for 500 ns 3)
Apk transient for 500 ns 3)
Reverse current peak at
pins OUTA, OUTB
5
Junction temperature
Storage temperature
Soldering temperature
ESD capability
TJ
-40
-65
–
–
–
–
–
150
150
260
0.5
°C
°C
°C
kV
–
TSTG
–
TSOL
reflow 4)
VESD_CDM
–
Charged Device Model
(CDM) 5)
ESD capability
VESD_HBM
–
–
2
kV
Human Body Model
(HBM) 6)
1)
2)
3)
4)
5)
6)
Maximum positive supply voltage already complies with derating guidelines.
Minimum is given by internal regulation when DTC is operating (DTC pin connected to GND via resistance).
Not subject to production test - verified by design/characterization.
According to JEDEC-020E.
According to ANSI/ESDA/JEDEC JS-002.
According to ANSI/ESDA/JEDEC JS-001 (discharging 100 pF capacitor through 1.5 kΩ resistor).
Datasheet
10
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
3.2
Thermal characteristics
Thermal characteristics are obtained from simulation with 65 mW applied to the driver input-side and 200 mW
applied to any output channel.
Table 10
Thermal characteristics at TA = 25°C
Parameter
Symbol
Value
1s0p 1)
46
Unit
Note or
condition
2s2p 2)
Thermal
RthJC
46
K/W
–
resistance
junction-case
(top) 3)
Thermal
RthJA25
RthJA85
107
95
69
65
K/W
K/W
–
–
resistance
junction
ambient 4)
Thermal
RthJB
–
27
10
23
K/W
K/W
K/W
–
–
–
resistance
junction board 5)
Characterization
parameter
Ψ
11
21
thJT
junction-top 6)
Characterization
parameter
Ψ
thJB25
junction-board 6)
1) Two-layer board as specified in JESD51-3 JEDEC-standard: no copper planes and no thermal vias for cooling, "package-alone" parameters
2) High-K board as specified in JESD51-7 JEDEC-standard: four-layers board with 2-oz inner layers copper planes and with no thermal vias for cooling
3) Obtained by simulating a cold plate test on the package top. No specific JEDEC standard exists, but a close description can be found in the ANSI
SEMI standard G30-88
4) Obtained by simulating a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2
5) Obtained by simulating a JEDEC-standard high-K board, as specified in JESD51-7, in an environment described in JESD51-8 with a ring cold plate
fixture to control the PCB temperature
6) Estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining Rth, using a procedure
described in JESD51-2a (sections 6 and 7)
Datasheet
11
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
3.3
Operating range
Operating range
Symbol
Table 11
Parameter
Values
Typ.
Unit Note or condition
Min.
Max.
Input supply voltage at pin VDDI
3
–
–
–
–
17
V
V
V
V
V
Min. defined by UVLOVDDI
4 V UVLO option
VDDI
Output supply voltage at
pin VDDA and VDDB
VDDA, VDDB
4.5
8.5
20 1)
20 1)
20 1)
20 1)
Output supply voltage at
pin VDDA and VDDB
VDDA, VDDB
VDDA, VDDB
VDDA, VDDB
8 V UVLO option
Output supply voltage at
pin VDDA and VDDB
12.9
15.6
12 V UVLO option
15 V UVLO option
Output supply voltage at
pin VDDA and VDDB
–
–
Input voltage at pins INA, VIN
INB, DIS/EN
0
17
V
V
–
2)
Input voltage at pin DTC
VDTC
–
VDDI
–
–
Junction temperature
Ambient temperature
TJ
TA
-40
40
–
–
150 3)
125
°C
°C
1)
2)
3)
Maximum positive supply voltage already complies with derating guidelines.
Minimum is given by internal regulation when DTC is operating (DTC pin connected to GND via resistance).
Continuous operation above 125°C may reduce lifetime.
3.4
Electrical characteristics
Unless otherwise noted, the electrical characteristics are given for VDDI = 3.3 V, VDDA/B =12 V and no load. Typical
values are given at TJ = 25°C whilst min. and max., instead, are the lower and upper limits, respectively, within
the full operating range.
Table 12
Power supply
Symbol
Parameter
Values
Typ.
Unit Note or condition
Min.
Max.
2.12
IVDDI quiescent current
IVDDIq
–
–
–
–
–
1.67
mA no switching
IVDDA/B quiescent current IVDDA/Bq
IVDDA/B quiescent current IVDDA/Bq
IVDDA/B quiescent current IVDDA/Bq
IVDDA/B quiescent current IVDDA/Bq
0.62
0.66
0.76
0.9
0.86
0.89
1.0
mA OUT = low, VDDA/B = 12 V
mA OUT = low, VDDA/B = 18 V
mA OUT = high, VDDA/B = 12 V
mA OUT = high, VDDA/B = 18 V
1.14
Datasheet
12
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 13
Undervoltage Lockout VDDI
Symbol
Parameter
Values
Typ.
Unit Note or condition
Min.
Max.
2.95
Undervoltage Lockout
(UVLO) turn-on threshold
VDDI
UVLOVDDI,on
–
2.85
V
V
V
–
–
–
Undervoltage Lockout
(UVLO) turn-off threshold
VDDI
UVLOVDDI,off 2.55
2.7
–
UVLO threshold hysteresis UVLOVDDI,hys 0.10
VDDI
0.15
0.20
Table 14
Undervoltage Lockout VDDA, VDDB for 4 V UVLO option
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
4.4
Undervoltage Lockout
(UVLO) turn-on threshold UVLOVDDB,on
VDDA, VDDB
UVLOVDDA,on
–
4.2
V
V
V
–
–
–
Undervoltage Lockout
UVLOVDDA,off 3.7
3.9
0.3
–
(UVLO) turn-off threshold UVLOVDDB,off
VDDA, VDDB
UVLO threshold hysteresis UVLOVDDA,hys 0.2
VDDA, VDDB
0.4
UVLOVDDB,hys
Table 15
Undervoltage Lockout VDDA, VDDB for 8 V UVLO option
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
8.5
Undervoltage Lockout
(UVLO) turn-on threshold UVLOVDDB,on
VDDA, VDDB
UVLOVDDA,on
–
8.0
V
V
V
–
–
–
Undervoltage Lockout
UVLOVDDA,off 6.6
7.0
1
–
(UVLO) turn-off threshold UVLOVDDB,off
VDDA, VDDB
UVLO threshold hysteresis UVLOVDDA,hys 0.7
VDDA, VDDB
1.3
UVLOVDDB,hys
Table 16
Undervoltage Lockout VDDA, VDDB for 12 V UVLO option
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
12.8
Undervoltage Lockout
UVLOVDDA,on
–
12.2
V
–
(UVLO) turn-on threshold UVLOVDDB,on
VDDA, VDDB
(table continues...)
Datasheet
13
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 16
(continued) Undervoltage Lockout VDDA, VDDB for 12 V UVLO option
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
Undervoltage Lockout
UVLOVDDA,off 10.8
11.5
–
V
V
–
–
(UVLO) turn-off threshold UVLOVDDB,off
VDDA, VDDB
UVLO threshold hysteresis UVLOVDDA,hys 0.5
VDDA, VDDB
0.7
0.9
UVLOVDDB,hys
Table 17
Undervoltage Lockout VDDA, VDDB for 15 V UVLO option
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
15.5
Undervoltage Lockout
(UVLO) turn-on threshold UVLOVDDB,on
VDDA, VDDB
UVLOVDDA,on
–
14.9
V
V
V
–
–
–
Undervoltage Lockout
UVLOVDDA,off 13.7
14.4
0.5
–
(UVLO) turn-off threshold UVLOVDDB,off
VDDA, VDDB
Duplicate of UVLO
UVLOVDDA,hys 0.3
0.7
threshold hysteresis VDDA, UVLOVDDB,hys
VDDB
Table 18
Logic inputs INA, INB, DISABLE
Symbol
Parameter
Values
Typ.
Unit Note or condition
Min.
Max.
Input voltage threshold for VINH
–
2.0
1.2
0.8
22
2.36
V
V
V
–
–
–
transition LH
Input voltage threshold for VINL
transition HL
0.9
–
Input voltage threshold
hysteresis
VIN_hys
0.38
1.2
27
–
High-level input leakage
current
IIN
–
–
µA INA/INB pin tied to VDDI
kΩ
Input pull-down resistor
RIN,PD
150
–
Table 19
Dead-time control (DTC) and shoot-through protection (STP)
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
115
Dead-time
Dead-time
Dead-time
tdt
tdt
tdt
85
100
ns
ns
ns
RDTC = 10 kΩ
RDTC = 30 kΩ
RDTC = 100 kΩ 1)
255
800
300
950
345
1100
(table continues...)
Datasheet
14
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 19
(continued) Dead-time control (DTC) and shoot-through protection (STP)
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
Channel-to-channel dead- ∆tdt,Ch-Ch
0
0
0
0
0
0
–
–
–
–
–
–
10
14
40
20
55
ns
ns
ns
ns
ns
ns
RDTC = 10 kΩ
time mismatch
Channel-to-channel dead- ∆tdt,Ch-Ch
time mismatch
RDTC = 30 kΩ
Channel-to-channel dead- ∆tdt,Ch-Ch
time mismatch
RDTC = 100 kΩ 1)
RDTC = 10 kΩ 2)
RDTC = 30 kΩ 2)
RDTC = 100 kΩ 1) 2)
Part-to-part dead-time
mismatch
∆tdt,p-p
∆tdt,p-p
∆tdt,p-p
Part-to-part dead-time
mismatch
Part-to-part dead-time
mismatch
105
1)
2)
Not subject to production test - verified by design/characterization.
The parameter gives the difference in the dead-time inserted from different samples under the same conditions, including same
ambient temperature.
Table 20
Static output characteristics
Parameter
Symbol
Min.
Values
Typ.
Unit Note or condition
Max.
1.5
High-level (sourcing)
output resistance
Ron_SRC
0.6
0.95
Ω
A
ISRC = 50 mA
Peak sourcing output
current
ISRC_pk
–
5
–
CLOAD = 22 nF 1)
ISNK = 50 mA
Low-level (sinking) output Ron_SNK
resistance
0.24
0.39
-9
0.62
–
Ω
A
Peak sinking output
current
ISNK_pk
CLOAD = 22 nF 1)
1)
Not subject to production test - verified by design/characterization.
Table 21
Dynamic characteristics
Symbol
Parameter
Values
Typ.
Unit Note or condition
Min.
Max.
INx to OUTx turn-on
propagation delay
tPDon,INx
tPDoff,INx
33
30
38
47
46
ns
ns
See Figure 5, Figure 6
See Figure 5, Figure 6
INx to OUTx turn-off
propagation delay
36
(table continues...)
Datasheet
15
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 21
(continued) Dynamic characteristics
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
Max.
1)
Part-to-part turn-on
propagation delay
mismatch
∆tPDon,p-p
0
0
–
–
–
–
6
8
4
3
ns
1)
Part-to-part turn-off
propagation delay
mismatch
∆tPDoff,p-p
ns
2)
Channel-to-channel turn- tPDon,ChA-ChB -4
on propagation delay
mismatch
ns
ns
See Figure 7
See Figure 7
See Figure 8
2)
3)
Channel-to-channel turn- ∆tPDoff,ChA-
off propagation delay
mismatch
-5.5
ChB
Pulse width distortion
tPWD
-5
-5
2
5.5
1
ns
ns
4) 5)
Channel turn-off
to channel turn-on
propagation delay
mismatch
tDTD
-2
See Figure 9
6)
Rise time
trise
tfall
tPW
–
7.5
6
14
11
25
ns
ns
ns
CLOAD = 1.8 nF,
see Figure 10
6)
Fall time
–
CLOAD = 1.8 nF,
see Figure 10
Minimum input pulse
width that changes output
state
10
17
See Figure 11
6)
Input-side start-up time
tSTART,VDDI
tSTOP,VDDI
–
3.5
5
–
µs
ns
see Figure 12
6)
Input-side deactivation
time
600
750
see Figure 12
6)
Output-side start-up time tSTART,VDDA/B
–
2.5
5
–
µs
ns
see Figure 13
6)
Output-side deactivation tSTOP,VDDA/B
time
500
800
see Figure 13
1)
The parameter gives the difference in the propagation delay between different samples switching in the same direction under
same conditions, including same ambient temperature; therefore, is an indication of the production spread. The limits given are
valid for all channels combination: tPD_ChA - tPD_ChA, tPD_ChB - tPD_ChB, tPD_ChA - tPD_ChB, tPD_ChB - tPD_ChA
.
2)
3)
4)
The parameter gives the difference in the propagation delay of channel A and channel B switching in the same direction in the
same sample.
The parameter gives the difference between ON and OFF propagation delay in the same channel (ChA or ChB), in the same sample
at same ambient temperature.
The parameter gives the difference between the ON propagation delay of one channel and the OFF propagation delay of the other
channel, in the same sample at same room temperature. This parameter represents the distortion of the inputs dead-time only
when the driver DTC is not used or not enforced otherwise, please refer to Table 19.
Not subject to production test - verified by characterization.
5)
6)
Not subject to production test - verified by design/characterization.
Datasheet
16
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 22
Common-Mode Transient Immunity (CMTI)
Parameter
Symbol
Values
Typ.
Unit Note or condition
Min.
150
Max.
Static Common-Mode
Transient Immunity
|CMStatic,H
|
–
–
–
–
V/ns VCM = 1500 V; INA, INB
tied to VDDI (logic high
1) 2)
inputs)
Static Common-Mode
Transient Immunity
|CMStatic,L
|
150
V/ns VCM = 1500 V; INA, INB
tied to GNDI (logic low
1) 2)
inputs)
1)
2)
Minimum slew rate of a common-mode voltage that is able to cause an incorrect output signal
Verified by characterization according to VDE0884-11 standard definitions and test-methods
3.5
Isolation specifications
Table 23
Isolation specifications
Symbol
Parameter
Value
Unit
Note or condition
External input-to-output
creepage 1)
CRP
8
mm
Shortest distance over package surface
from any input pin to any output pin
according to IEC 60664-1
External input-to-output
clearance 1)
CLR
8
mm
Shortest distance in air from any input pin
to any output pin according to IEC 60664-1
Comparative tracking index
Material group
CTI
–
> 400
II
V
–
–
–
–
–
According to DIN EN 60112 (VDE 0303-11)
According to IEC 60112
Pollution degree
–
II
According to IEC 60664-1
Overvoltage category (for
reinforced isolation)
–
I - IV
I - IV
I - III
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
–
–
Input-to-output isolation according to UL1577 Ed.5 2)
Input-to-output isolation
voltage
VISO
5700
VRMS
VTEST = VISO for t = 60 s (qualification);
VTEST = 1.2 x VISO for t = 1 s (100%
productive tests)
Input-to-output isolation according to DIN VDE V0884-11 3) and IEC 60747-17 4)
Maximum impulse voltage
VIMP
8000
8000
Vpk
Vpk
According to IEC 60664-1
Maximum rated transient
isolation voltage
VIOTM
VTEST = VIOTM for tini = 60 s (type tests and
quarterly monitoring)
VTEST = 1.2 x VIOTM for tini = 1 s (100%
productive tests)
Maximum rated repetitive
isolation voltage
VIORM
1767
Vpk
According to Time Dependent Dielectric
Breakdown (TDDB) Test for reinforced
isolation
(table continues...)
Datasheet
17
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 23
(continued) Isolation specifications
Parameter
Symbol
Value
Unit
Note or condition
Apparent charge
qPD
< 5
pC
Vini,b1= 1.2 x VIOTM (100% productive
tests) and Vini,b1 = VIOTM (type tests
preconditioning) for tini =1s
Vpd(m) = 1.875 x VIORM for tm = 1 s 5)
Afer subgroup 1 life tests (type test) and in
quarterly monitoring
Vini,a = VIOTM for tini = 60 s
Vpd(m) = 1.6 x VIORM for tm = 10 s
Afer subgroup 2, 3 endurance tests (type
test)
Vini,a = VIOTM for tini = 60 s
Vpd(m) = 1.2 x VIORM for tm = 10 s
Maximum surge isolation
voltage 6)
VIOSM
6875
Vpk
Vpk
VIOSM_TEST = 1.6 x VIOSM for reinforced
isolation according VDE 0884-11
11000
VIOSM_TEST = 11 kVpk ≥ 1.3 x VIOSM for
reinforced isolation according IEC
60747-17
Isolation resistance input-to- RIO
output 7)
1012
1011
Ω
Ω
VIO = 500 Vdc for t = 60 s, TA = 25°C (type
tests subgroup 1)
VIO = 500 Vdc for t = 60 s, TA = 125°C (type
tests preconditioning, type test subgroup 4
and quarterly monitoring)
109
Ω
VIO = 500 Vdc for t = 60 s, TA = 25°C (type
tests subgroup 1, 2, 3) or TA = TS (type tests
subgroup 4 and quarterly monitoring)
Capacitance input-to-output CIO
2
pF
f = 1 MHz
7)
1) Creepage and clearance requirements depend on the application and related end-equipment isolation standard. Care should be taken to keep the
required creepage and clearance value on printed-circuit-board level.
2) See UL 1577 certificate n. E311313.
3) See VDE 0884-11 certificate n. 40052310.
4) See IEC 60747-17 certificate n. 40055138.
5) The partial discharge voltage VPD(m) applied during production tests is greater (4411 Vpk > 1.875 x VIORM ) to include the F4 factor required by
end equipment standards IEC 60664-1, IEC 62368-1 (VPD(m) = F1 x F2 x F3 x F4 x VIORM = 1.875 x F4 x VIORM).
6) The surge test is performed in insulation oil to determine the intrinsic surge immunity of the insulation barrier.
7) The parameters apply to the product converted in a two terminals device with all terminals on side 1 connected together and all terminals on side
2 connected together.
Table 24
Output channel-to-channel isolation specifications
Parameter
Symbol Value
Unit
Note or condition
External channel-to-channel creepage1)
CRPCh-Ch, 3.3
14pin
mm
Shortest distance over package
surface between any output
(table continues...)
Datasheet
18
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
3 Electrical characteristics
Table 24
(continued) Output channel-to-channel isolation specifications
Parameter
Symbol Value
Unit
Note or condition
CRPCh-Ch, 2.5
16pin
mm
channel A pin and any output
channel B pin
1) Creepage and clearance requirements depend on the application and related end-equipment isolation standard. Care should be taken to keep the
required creepage and clearance value on printed-circuit-board level
Datasheet
19
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
4 Timing diagrams
4
Timing diagrams
Figure 5 illustrates the input-to-output propagation delays as observed at the capacitively loaded output.
DISABLE
Low logic level
VINH
VINL
INA/B
90%
10%
OUTA/B
tPDon
tPDoff
Figure 5
INx to OUTx propagation delays
Figure 6 illustrates the disable-to-output propagation delays as observed at the capacitively loaded output.
VINH
VINL
DISABLE
INA/B
OUTA/B
90%
10%
tPDoff,DIS
tPDon,DIS
Figure 6
DISABLE to OUTx propagation delays
Figure 7 illustrates the channel-to-channel propagation delay mismatch at the unloaded outputs. This
parameter is relevant when the channels drive parallel switches as it represents the delay in the two driving
signals.
INA/B
tPDon_ChA
tPDoff_ChB
OUTA
OUTB
∆tPDoff
∆tPDon
tPDon_ChB
tPDoff_ChB
Figure 7
Channel-to-channel propagation delay mismatch
Figure 8 illustrates the pulse width distortion at the unloaded output. Ideally the width of the input pulse
(tPW_INx) equals the width of the output pulse (tPW_OUTx); however, the driver introduces an output pulse
distortion tPW given by the difference between ON and OFF propagation delay.
Datasheet
20
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
4 Timing diagrams
tPW_INx
INA/B
tPDoff
tPDon
ideal
tPWD
OUTA/B
tPW_OUTx
= tPW_INx -tPWD
Figure 8
Pulse width distortion
Figure 9 illustrates the dead-time distortion at the unloaded outputs. This parameter is relevant in operation
with complementary signals, as for the half-bridge driving when a certain dead-time tDT_INx is set on the inputs
INA, INB. Ideally the dead-time on the driver output (tDT_OUTx) equals the input dead-time; however, the driver
introduces a distortion tDTC given by the difference between the OFF propagation delay of one channel and the
ON propagation delay of the other channel.
tDT_INx
INA
INB
tPDoff_ChA
OUTA
tPDon_ChB
ideal
OUTB
tDTD
tDT_OUTx
= tDT_INx -tDTD
Figure 9
Channel turn-off to channel turn-on propagation delay mismatch
Figure 10 illustrates the rise and fall time as observed at the capacitively loaded output.
90%
10%
OUTA/B
trise
tfall
Figure 10
Rise and fall time
Figure 8 illustrates the behavior or the deglitch filter that filters spurios pulses on INA, INB with duration shorter
than tPWmin
.
DISABLE
Low logic level
VINH
VINH
VINL
VINL
INA/B
tPW > tPWmin
t
PW < tPWmin
OUTA/B
Figure 11
Minimum pulse that changes the output state
Datasheet
21
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
4 Timing diagrams
Figure 12 illustrates the input-side supply UVLO behavior. It depicts the reaction time to UVLO events when VDDI
crosses the UVLO thresholds during rising or falling transitions (power-up, power-down, supply noise).
INA/INB
High logic level
High logic level
VDDA
UVLOVDDI,on
UVLOVDDI,off
VDDI
OUTA/OUTB
tSTART,VDDI
tSTOP,VDDI
Figure 12
VDDI UVLO behavior, start-up and deactivation time
Figure 13 illustrates the output-side supply UVLO behavior. It depicts the reaction time to UVLO events when
VDDA/B crosses the UVLO thresholds during rising or falling transitions (power-up, power-down, supply noise).
INA
High logic level
High logic level
VDDI
UVLOVDDA,on
UVLOVDDA,off
VDDA
OUTA
tSTART,VDDA
tSTOP,VDDA
Figure 13
VDDA,VDDB UVLO behavior, start-up and deactivation time
Figure 14 illustrates the shoot-through protection and dead-time logic. When enabled, the dead-time is added
on top of the turn-off propagation delay if the driver dead-time is longer than the signals' own dead-time.
DISABLE
Low logic level
µC dead-time
VINH
VINL
INA
INB
VINH
VINL
90%
10%
OUTA
OUTB
tPDoff
90%
tPDoff
10%
µC dead-time
Dead-time set by
the input signals´s
dead-time
tdt
Shoot-through
protection pulls
down INA, INB
Dead-time
set by the
driver via
RDTC
Figure 14
Shoot-through and configurable dead-time
Datasheet
22
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
5 Typical characteristics
5
Typical characteristics
VDDI = 3.3 V, VDDA/B = 12 V, TA = 25°C, fsw = 1 MHz, no load unless otherwise noted
1.8
1.7
1.6
1.5
6
5
4
3
2
1
0
VDDI = 3.3V
VDDI = 12V
VDDI = 17V
fsw = 100 KHz
fsw = 1MHz
fsw = 3MHz
V
DDI=3.3V, no load,
no switching
square wave input
-50
50
Tj [ C]
150
-50
50
Tj [ C]
150
Typical IVDDIq quiescent current
vs. temperature
Typical IVDDIq switching current vs.
temperature
7
no switching
fsw = 100 kHz
fsw = 1 MHz
fsw = 3 MHz
TJ = 25°C
6
5
4
3
2
1
0
2
6
10
DDI [V]
14
18
V
Typical IVDDI current vs. input-
supply voltage VDDI
Figure 15
Input-side supply current
Datasheet
23
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
5 Typical characteristics
0.8
0.7
0.6
0.5
1.1
0.9
0.7
0.5
VDDA/B = 5V
VDDA/B = 8V
VDDA/B = 12V
VDDA/B = 18V
VDDA/B = 5V
VDDA/B = 8V
VDDA/B =12V
VDDA/B = 18V
OUT LOW
OUT HIGH
-50
0
50
100
150
-50
0
50
Tj [ C]
100
150
Tj [ C]
Typical IVDDA/B quiescient current (OUT low)
vs. temperature
Typical IVDDA/B quiescent current (OUT high)
vs. temperature
10
30
no load, TA = 25°C,
square wave input
fsw = 100kHz
fsw = 1MHz
fsw = 3MHz
VDDO = 5V
VDDO = 12V
VDDO = 20V
no load, VDDA/B = 12V,
square wave input
8
6
4
2
0
20
10
0
-50
50
TJ [ C]
150
0
2
4
6
8
10
f
sw [MHz]
Typical IVDDA/B switching current
vs. temperature
Typical IVDDA/B switching current
vs. frequency
2.0
40
30
20
10
0
VDDO = 5V
VDDO = 5V
VDDO = 12V
VDDO = 20V
square wave input,
TA = 25°C, fsw = 1KHz
square wave input,
VDDO = 12V
TA = 25°C, fsw = 100KHz
VDDO = 20V
1.5
1.0
0.5
0.0
0
5
10
0
5
10
C
load [nF]
C
load [nF]
Typical IVDDA/B switching current
vs. capacitive load (1 kHz frequency)
Typical IVDDA/B switching current
vs. capacitive load (100 kHz frequency)
Figure 16
Output-side supply current
Datasheet
24
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
5 Typical characteristics
3.0
ON threshold
OFF threshold
UVLO on
UVLO off
2.9
2.7
2.5
2.5
2.0
1.5
1.0
0.5
-50
0
50
Tj [ C]
100
150
-50
0
50
Tj [ C]
100
150
Typical input voltage thresholds
vs. temperature
Typical Undervoltage Lockout
thresholds VDDI vs. temperature
4.5
4.3
4.1
3.9
3.7
8.8
8.4
8.0
7.6
7.2
6.8
6.4
UVLO on
UVLO off
UVLO on
UVLO off
-50
0
50
Tj [ C]
100
150
-50
0
50
Tj [ C]
100
150
Typical Undervoltage Lockout VDDA/B
thresholds vs. temperature (4 V version)
Typical Undervoltage Lockout VDDA/B
thresholds vs. temperature (8 V version)
12.8
12.4
12.0
11.6
11.2
10.8
15.2
UVLO on
UVLO off
UVLO on
UVLO off
14.8
14.4
14.0
-50
0
50
Tj [ C]
100
150
-50
0
50
Tj [ C]
100
150
Typical Undervoltage Lockout VDDA/B
thresholds vs. temperature (12 V version)
Typical Undervoltage Lockout VDDA/B
thresholds vs. temperature (15 V version)
Figure 17
Input voltage thresholds and Undervoltage Lockout
Datasheet
25
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
5 Typical characteristics
6
5
4
3
2
1
0
2.0
1.5
1.0
0.5
0.0
Ron_src
Ron_snk
Tj=25°C
TJ=85°C
TJ=125°C
C
LOAD =22nF,
series resistance
RS = 0.1 Ω
0
5
10
15
20
-50
0
50
Tj [ C]
100
150
VOUT [V]
Typical output resistance
vs. temperature
Typical sourcing output current
vs. output voltage
12
11
10
9
10
8
VDDA/B=8V
VDDA/B=12V
VDDA/B=20V
TJ=25°C
TJ=85°C
Tj=125°C
8
7
6
6
5
4
4
3
2
1
0
2
CLOAD =22nF,
TA = 25°C, CLOAD =22nF,
series resistanceRS = 0.1 Ω
series resistance RS = 0.1 Ω
0
-50
0
50
Tj [ C]
100
150
0
5
10
V
15
20
OUT [V]
Typical peak sourcing output current vs.
temperature
Typical sinking output current
vs. output voltage
14
12
10
8
12
VDDA/B=8V
VDDA/B=12V
VDDA/B=18V
ISRC_pk
ISNK_PK
10
8
6
6
4
V
DDO = 12V, TA = 25°C,
4
2
C
LOAD =22nF,
CLOAD =22nF,
series resistance RS = 0.1 Ω
series resistance RS = 0.1 Ω
2
0
-50
0
50
Tj [ C]
100
150
4
8
12
16
20
V
DDO [V]
Typical peak sinking output current
vs. temperature
Typical peak output current vs.
supply voltage
Figure 18
Typical output static characteristics
Datasheet
26
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
5 Typical characteristics
2
ON
OFF
ON
44
OFF
1
42
40
0
38
-1
36
34
-2
-50
0
50
Tj [ C]
100
150
-50
0
50
Tj [ C]
100
150
Typical input-to-output propagation
delay vs. temperature
Typical channel-to-channel propagation
delay mismatch vs. temperature
Figure 19
Typical propagation delays
Datasheet
27
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
5 Typical characteristics
102
101
100
99
320
310
300
290
280
Rdt= 300 kΩ
Rdt= 100 kΩ
-50
0
50
Tj [ C]
100
150
-50
0
50
Tj [ C]
100
150
Typical Dead-time vs.
temperature (Rdt = 10kΩ)
Typical Dead-time vs.
temperature (Rdt = 30kΩ)
1100
1050
1000
950
5
4
3
2
1
0
Rdt= 1000 kΩ
Rdt= 100kOhm
Rdt= 300kOhm
Rdt= 1000kOhm
900
-50
0
50
Tj [ C]
100
150
-50
0
50
100
150
Tj [ C]
Typical channel-to-channel Dead-time
matching vs. temperature
Typical Dead-time vs.
temperature (Rdt = 100kΩ)
Figure 20
Typical dead-time
Datasheet
28
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
6 Package outline dimensions
6
Package outline dimensions
6.1
Device numbers and markings
Table 25
Device numbers and markings
Part number
2EDR8259H
2EDR7259X
2EDR8259X
2EDR9259X
2EDR6258X
2EDR8258X
2EDR9258X
Orderable part number (OPN)
2EDR8259HXUMA1
2EDR7259XXUMA1
2EDR8259XXUMA1
2EDR9259XXUMA1
2EDR6258XXUMA1
2EDR8258XXUMA1
2EDR9258XXUMA1
Device marking
2R8259A
2R7259A
2R8259A
2R9259A
2R6258A
2R8258A
2R9258A
6.2
Package DSO16-300mil
Figure 21
DSO16-300mil outline
Datasheet
29
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
6 Package outline dimensions
Figure 22
DSO16-300mil footprint
Figure 23
DSO16-300mil packing
Green Product (RoHS compliant)
To meet the worldwide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e. Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further
information on packages: https://www.infineon.com/packages
Datasheet
30
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
6 Package outline dimensions
6.3
Package DSO14-300mil
Figure 24
DSO14-300mil outline
Figure 25
DSO14-300mil footprint
Datasheet
31
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
6 Package outline dimensions
Figure 26
DSO14-300mil packing
Green Product (RoHS compliant)
To meet the worldwide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e. Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further
information on packages: https://www.infineon.com/packages
Datasheet
32
Rev. 1.3
2022-02-27
EiceDRIVER™ 2EDR8259H, 2EDRx259X, 2EDRx258X
Dual-channel isolated gate driver ICs in 300 mil DSO package
7 Revision history
7
Revision history
Revision
Date
Description of changes
Rev 1.3
2023-02-27
Added condition "DTC pin connected to ground"
Fixed typo in the OPN of Table 25
Rev 1.2
Rev 1.1
2023-01-19
2022-12-12
Fixed typo in channel-to-channel propagation delay mismatch
Removed watermark "restricted"
"Dead-time distortion" renamed as "Channel turn-off to channel
turn-on propagation delay mismatch" in Table 21
Rev 1.0
2022-12-09
Initial release
Datasheet
33
Rev. 1.3
2022-02-27
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-02-27
Published by
Infineon Technologies AG
81726 Munich, Germany
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Document reference
IFX-jqf1648202404767
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相关型号：
2EDR8259X
The EiceDRIVER™ 2EDR8259X is a reinforced isolated gate driver IC for control over the mandatory safe isolation barrier in SMPS. The strong 5 A/9 A source/sink dual-channel gate driver comes with a very high 150 V/ns CMTI (common mode transient immunity) for robust operation with CoolMOS™, CoolGaN™ GIT HEMTs and high-power switching noise environment.
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