6ED003L06C2X1SA1 [INFINEON]
Half Bridge Based MOSFET Driver;
| 型号： | 6ED003L06C2X1SA1 |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based MOSFET Driver 驱动 接口集成电路 |
| 文件： | 总25页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™ Compact
High voltage gate driver IC
6ED family - 2nd generation
Chip product
3 phase 600 V gate drive IC
6ED003L06-C2
6EDL04I06PC
6EDL04I06NC
6EDL04N06PC
EiceDRIVER™ Compact
datasheet
<Revision 2.5>, 20.04.2015
Industrial Power Control
Edition 20.04.2015
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual
property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
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persons may be endangered.
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 2.5>, 20.04.2015
all
revised wording of test temperature
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™,
CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™,
EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™,
PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™,
SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
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AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™
of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™
of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR
STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc.
MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc.
MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE
OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd.
Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company
Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments
Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2010-10-26
datasheet
3
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
Table of Contents
1
Overview .............................................................................................................................................7
2
Blockdiagram......................................................................................................................................9
3
Chip size, bondpad configuration and description ......................................................................11
Mechanical data .................................................................................................................................11
Pad description...................................................................................................................................12
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) ................................................................13
EN (Gate Driver Enable, Pin 10)........................................................................................................13
FAULT (Fault Feedback, Pin 8) .........................................................................................................13
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) .........................................................14
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ......................................................................14
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) .............................................14
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) ...............................14
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
Electrical Parameters.......................................................................................................................15
Absolute Maximum Ratings ...............................................................................................................15
Required operation conditions ...........................................................................................................16
Operating Range................................................................................................................................16
Static logic function table ...................................................................................................................17
Static parameters ...............................................................................................................................17
Dynamic parameters..........................................................................................................................20
4.1
4.2
4.3
4.4
4.5
4.6
5
6
Quality disclaimer ............................................................................................................................21
Timing diagrams...............................................................................................................................22
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6ED family - 2nd generation chip product
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Typical Application ...............................................................................................................................8
Block diagram for 6ED003L06-C2, and 6EDL04I06NC (with ultra fast BS diodes).............................9
Block Diagram for 6EDL04I06PC, and 6EDL04N06PC.....................................................................10
Bond pad configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1) ..........11
Input pin structure for negative logic (left) and positive logic (right)...................................................13
Input filter timing diagram for negative logic (left) and positive logic (right).......................................13
EN pin structures................................................................................................................................13
FAULT pin structures .........................................................................................................................14
Timing of short pulse suppression (6EDL04I06NC, 6ED003L06-C2)................................................22
Figure 10 Timing of short pulse suppression (6EDL04I06PC, 6EDL04N06PC)................................................22
Figure 11 Timing of of internal deadtime (input logic according to Table 1) ......................................................22
Figure 12 Enable delay time definition ...............................................................................................................23
Figure 13 Input to output propagation delay times and switching times definition (6EDL04I06NC, 6ED003L06-
C2)......................................................................................................................................................23
Figure 14 Input to output propagation delay times and switching times definition (6EDL04I06PC,
6EDL04N06PC)..................................................................................................................................23
Figure 15 Operating areas (6EDL04I06NC, 6EDL04I06PC, 6ED003L06-C2)...................................................23
Figure 16 Operating Areas (6EDL04N06PC).....................................................................................................24
Figure 17 ITRIP-Timing ......................................................................................................................................24
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6ED family - 2nd generation chip product
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Members of 6ED family – 2nd generation .............................................................................................7
Mechanical parameters......................................................................................................................11
Pad position and dimension...............................................................................................................11
Pad Description..................................................................................................................................12
Abs. maximum ratings........................................................................................................................15
Required Operation Conditions..........................................................................................................16
Operating range .................................................................................................................................16
Static parameters ...............................................................................................................................17
Dynamic parameters..........................................................................................................................20
datasheet
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EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
EiceDRIVER™ Compact
3 phase 600 V gate drive IC
1
Overview
Main features
Thin-film-SOI-technology
Maximum blocking voltage +600V
Separate control circuits for all six drivers
CMOS and LSTTL compatible input (negative logic)
Chip product
Signal interlocking of every phase to prevent cross-conduction
Detection of over current and under voltage supply
externally programmable delay for fault clear after over current detection
Product highlights
Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology
Ultra fast bootstrap diodes (except 6ED003L06-C2)
'shut down' of all switches during error conditions
Typical applications
Home appliances
Fans, pumps
General purpose drives
Product family
Table 1
Members of 6ED family – 2nd generation
high side control typ. UVLO-
Sales Name
Bootstrap diode Package
Replacement for
1st generation
input HIN1,2,3 and Thresholds
LIN1,2,3
6EDL04I06NC
6EDL04I06PC
6EDL04N06PC
6ED003L06-C2
negative logic
positive logic
positive logic
negative logic
11.7 V / 9.8 V Yes
11.7 V / 9.8 V Yes
9 V / 8.1 V Yes
11.7 V / 9.8 V No
sawn on foil No
sawn on foil No
sawn on foil No
sawn on foil Yes
Description
The device 6ED family – 2nd generation is a full bridge driver to control power devices like MOS-transistors or
IGBTs in 3-phase systems with a maximum blocking voltage of +600 V. Based on the used SOI-technology
there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the
device. Hence, no parasitic latch-up may occur at all temperatures and voltage conditions.
The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down
to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic and an over-
current detection. The over-current level is adjusted by choosing the resistor value and the threshold level at pin
ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut down off all six switches. An
error signal is provided at the FAULT open drain output pin. The blocking time after over-current can be
adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore,
the resistor RRCIN is optional. The typical output current can be given with 165 mA for pull-up and 375 mA for pull
down. Because of system safety reasons a 310 ns interlocking time has been realised. The function of input EN
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6ED family - 2nd generation chip product
can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1). The
monolithic integrated bootstrap diode structures between pins VCC and VBx can be used for power supply of
the high side.
DC-Bus
VCC
HIN1,2,3
LIN1,2,3
EN
VCC
VB1,2,3
HO1,2,3
HIN1,2,3
LIN1,2,3
EN
To Load
VS1,2,3
5V
FAULT
RCIN
FAULT
LO1,2,3
COM
RRCIN
CRCIN
ITRIP
VSS
RSh
VSS
Signals HIN1,2,3 and LIN1,2,3 according to Table 1
Typical Application
Figure 1
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6ED family - 2nd generation chip product
2
Blockdiagram
BOOTSTRAP DIODE-VB1
BIAS NETWORK / VDD2
VB1
INPUT NOISE
FILTER
BIAS NETWORK - VB1
HIN1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
z
HO1
VS1
UV-
DETECT
INPUT NOISE
FILTER
LIN1
BOOTSTRAP DIODE-VB2
BIAS NETWORK - VB2
VB2
INPUT NOISE
FILTER
HIN2
LIN2
HIN3
LIN3
EN
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
HO2
VS2
UV-
DETECT
INPUT NOISE
FILTER
BOOTSTRAP DIODE-VB3
BIAS NETWORK / VB3
INPUT NOISE
FILTER
VB3
HO3
VS3
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UV-
DETECT
INPUT NOISE
FILTER
>1
INPUT NOISE
FILTER
VCC
LO1
UV-
DETECT
VSS / COM
LEVEL-
Gate-
Drive
DELAY
SHIFTER
INPUT NOISE
FILTER
ITRIP
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
DELAY
LO2
S
Q
VDD2
SET
DOMINANT
LATCH
R
IRCIN
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
LO3
RCIN
COM
FAULT
VSS
>1
Figure 2
Block diagram for 6ED003L06-C2, and 6EDL04I06NC (with ultra fast BS diodes)
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EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
BOOTSTRAP DIODE-VB1
BIAS NETWORK / VDD2
VB1
INPUT NOISE
FILTER
BIAS NETWORK - VB1
HIN1
LIN1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
z
HO1
VS1
UV-
DETECT
INPUT NOISE
FILTER
BOOTSTRAP DIODE-VB2
BIAS NETWORK - VB2
VB2
INPUT NOISE
FILTER
HIN2
LIN2
HIN3
LIN3
EN
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
HO2
VS2
UV-
DETECT
INPUT NOISE
FILTER
BOOTSTRAP DIODE-VB3
BIAS NETWORK / VB3
INPUT NOISE
FILTER
VB3
HO3
VS3
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UV-
DETECT
INPUT NOISE
FILTER
>1
INPUT NOISE
FILTER
VCC
LO1
UV-
DETECT
VSS / COM
LEVEL-
Gate-
Drive
DELAY
SHIFTER
INPUT NOISE
FILTER
ITRIP
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
DELAY
LO2
S
Q
VDD2
IRCIN
SET
DOMINANT
LATCH
R
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
LO3
RCIN
COM
FAULT
VSS
>1
Figure 3
Block Diagram for 6EDL04I06PC, and 6EDL04N06PC
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6ED family - 2nd generation chip product
3
Chip size, bondpad configuration and description
3.1
Mechanical data
Table 2
Mechanical parameters
Raster size of die
Area total / active
Thickness
2544 x 1706
4.34 / 4.65
280
µm x µm
mm²
µm
Wafer size
200
mm
Max. possible chips per wafer
Passivation frontside
Backside (Note 2)
Reject ink dot diameter
5908
pcs
Polyimide
Grinded silicon
Min. 0.6 max 1.2
mm
Note1: Filler material inside the mould compound with sharp edges may harm the passivation.
Note2: Chip must be bonded onto an electrically isolated area
All pad openings are designed for gold wire ball bonds and not for aluminum wedge bonds.
y
x
Figure 4
Bond pad configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1)
Table 3
Pad position and dimension
Pad Name
Pad Number Voltage
Domain
Pad Center Coordinates /µm Active Pad Dimension /µm
X
Y
X
Y
VCC
HIN1
HIN2
HIN3
LIN1
LIN2
1
2
3
4
5
6
1
1
1
1
1
1
271
271
271
271
390
669
565
423
313
203
185
185
80
80
80
80
80
80
145
80
80
80
80
80
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6ED family - 2nd generation chip product
Table 3
Pad position and dimension
Pad Name
Pad Number Voltage
Domain
Pad Center Coordinates /µm Active Pad Dimension /µm
X
Y
X
Y
LIN3
FAULT
ITRIP
EN
7
1
862
185
80
80
80
80
80
80
100
80
80
80
140
80
80
80
80
80
80
80
140
140
---
8
1
1063
1210
1488
1637
2104
2305
2350
2350
2350
2217
2047
1877
1440
1270
1100
324
185
80
9
1
185
80
10
11
12
13
14
15
16
18
19
20
22
23
24
26
27
28
1
185
80
RCIN
VSS
COM
LO3
LO2
LO1
VS3
HO3
VB3
VS2
HO2
VB2
VS1
HO1
VB1
1
185
80
1
171
160
160
80
1
226
1
349
1
469
80
1
619
80
2
1325
1325
1325
1325
1325
1325
1325
1185
1014
---
140
140
140
140
140
140
140
80
2
2
3
3
3
4
4
294
4
294
80
Chip back side ---
floating
---
---
3.2
Pad description
Table 4
Symbol
VCC
Pad Description
Description
Low side power supply
Logic ground
VSS
/HIN1,2,3
/LIN1,2,3
/FAULT
EN
High side logic input (negative logic)
Low side logic input (negative logic)
Indicates over-current and under-voltage (negative logic, open-drain output)
Enable I/O functionality (positive logic)
ITRIP
Analog input for over-current shutdown, activates FAULT and RCIN to VSS
external RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR
Low side gate driver reference
RCIN
)
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
High side positive power supply
High side gate driver output
High side negative power supply
Low side gate driver output
Chip back side Floating back side (floats towards the highest momentarily active potential)
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6ED family - 2nd generation chip product
3.3
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 5 and Figure 6.
Vcc
Schmitt-Trigger
Schmitt-Trigger
INPUT NOISE
FILTER
INPUT NOISE
FILTER
HINx
LINx
HINx
LINx
UZ=10.5V
UZ=10.5V
5k
SWITCH LEVEL
VIH; VIL
SWITCH LEVEL
VIH; VIL
Figure 5
Input pin structure for negative logic (left) and positive logic (right)
An internal pull-up of about 75 k (negative logic) pre-biases the input during supply start-up and a ESD zener
clamp is provided for pin protection purposes. The zener diodes are therefore designed for single pulse stress
only and not for continuous voltage stress over 10V. For versions with positive, a 5 k pull-down resistor is used
for this function.
a)
b)
HIN
tFILIN
a)
b)
HIN
tFILIN
tFILIN
tFILIN
LIN
LO
LIN
LO
LIN
LIN
high
high
HO
LO
HO
LO
low
low
Figure 6
Input filter timing diagram for negative logic (left) and positive logic (right)
It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1 µs.
The 6ED family – 2nd generation provides additionally a shoot through prevention capability which avoids the
simultaneous on-state of two channels of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When
two inputs of a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe
state. Please refer to the application note AN-Gatedrive-6ED2-1 for a detailed description.
A minimum dead time insertion of typ. 310 ns is also provided, in order to reduce cross-conduction of the
external power switches.
3.4
EN (Gate Driver Enable, Pin 10)
The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW
logic level. The internal structure of the pin is given in Figure 7. The switching levels of the Schmitt-Trigger are
here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. There is an internal
pull down resistor (75 k), which keeps the gate outputs off in case of broken PCB connection.
IEN+, IEN-
EN
INPUT NOISE
FILTER
VEN,TH+
VEN,TH-
,
VZ= 10.5 V
6ED family – 2nd generation
Figure 7
EN pin structures
3.5
/FAULT (Fault Feedback, Pin 8)
/Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 8). The pin is
active (i.e. forces LOW voltage level) when one of the following conditions occur:
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6ED family - 2nd generation chip product
Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the
supply voltage condition returns in the normal operation range (please refer to VCC pin description for
more details).
Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and
RCIN input is released (please refer to ITRIP pin).
6ED family –
2nd generation
VDD
VCC
RON,FLT
from ITRIP-Latch
from uv-detection
FAULT
>1
Figure 8
/FAULT pin structures
3.6
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11)
The 6ED family – 2nd generation provides an over-current detection function by connecting the ITRIP input with
the motor current feedback. The ITRIP comparator threshold (typ 0.44 V) is referenced to VSS ground. A input
noise filter (typ. tITRIPMIN = 230 ns) prevents the driver to detect false over-current events.
Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault
feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As
soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The
capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon
as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 5.2 V, the fault condition releases and the driver
returns operational following the ontrol input pins according to section 3.3. Please refer to AN-Gatedrive-6ED2-1
for details on setting RCIN time constant.
3.7
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13)
VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input
logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is
referenced to COM ground. COM ground is floating respect to VSS ground with a maximum range of operation
of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VCCUV+ is present. The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below
VCCUV- = 9.8 V respectively 8.1 V. This prevents the external power switches from critically low gate voltage
levels during on-state and therefore from excessive power dissipation.
3.8
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28)
VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VCC.
The device operating area as a function of the supply voltage is given in Figure 15 and Figure 16. Details on
bootstrap supply section and transient immunity can be found in application note AN-Gatedrive-6ED2-1.
3.9
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT
and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high
side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs. In particular, after an under voltage
condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side
output, while after a under voltage condition of the VCC supply, the low side outputs switch to the state of their
respective inputs.
datasheet
14
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
4
Electrical Parameters
4.1
Absolute Maximum Ratings
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 5
Abs. maximum ratings
Parameter
Symbol Min.
Max.
Unit
VS
High side offset voltage(Note 1)
V
VCC-VBS-6
600
High side offset voltage (tp<500ns, Note 1)
VCC -VBS – 50 –
VB
High side offset voltage(Note 1)
VCC – 6
620
High side offset voltage (tp<500ns, Note 1)
VCC – 50
VCC-VBS-6
–
VBack
Chip back side
620
High side floating supply voltage (VB vs. VS) (internally clamped)
High side output voltage (VHO vs. VS)
-1
20
VHO
VCC
VB + 0.5
20
-0.5
-1
Low side supply voltage (internally clamped)
Low side supply voltage (VCC vs. VCOM
)
VCCOM
VCOM
VLO
-0.5
-5.7
-0.5
-1
25
Gate driver ground
5.7
Low side output voltage (VLO vs. VCOM
Input voltage LIN,HIN,EN,ITRIP
FAULT output voltage
)
VCCOM + 0.5
10
VIN
VFLT
VRCIN
TJ
VCC + 0.5
VCC + 0.5
125
-0.5
-0.5
–
RCIN output voltage
Junction temperature
°C
TS
Storage temperature
- 40
150
dVS/dt
offset voltage slew rate
50
V/ns
Note :The minimum value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VCC,
HINx, LINx, FAULT, EN, RCIN, ITRIP, VSS, COM, LOx) and pins connected inside each high side itself (VBx, HOx, VSx) is guaranteed up
to 1.5kV (Human Body Model).
Note 1 : In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VBx. Insensitivity of
bridge output to negative transient voltage up to –50V is not subject to production test – verified by design / characterization.
datasheet
15
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
4.2
Required operation conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 6
Required Operation Conditions
Parameter
Symbol Min.
Max. Unit
VB
High side offset voltage (Note 1)
V
7
620
25
Low side supply voltage (VCC vs. VCOM
)
VCCOM
10
4.3
Operating Range
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 7
Operating range
Parameter
Symbol Min.
Max. Unit
VS
VCC -
High side floating supply offset voltage
V
VBS -1
-1.0
13
550
High side floating supply offset voltage (VB vs. VCC, statically)
High side floating supply voltage (VB vs. VS, Note 1)
VBCC
550
6EDL04I06NC VBS
17.5
6EDL04I06PC
6ED003L06-C2
6EDL04N06PC
High side output voltage (VHO vs. VS)
VHO
VLO
VCC
10
0
VBS
Low side output voltage (VLO vs. VCOM
)
VCC
17.5
Low side supply voltage
6EDL04I06NC
6EDL04I06PC
6ED003L06-C2
13
6EDL04N06PC
10
-2.5
0
17.5
2.5
5
VCOM
VIN
Low side ground voltage
Logic input voltages LIN,HIN,EN,ITRIP (Note 2)
FAULT output voltage
VFLT
VRCIN
tIN
VCC
VCC
0
RCIN input voltage
0
Pulse width for ON or OFF (Note 3)
Ambient temperature
1
–
µs
°C
Ta
-40
95
Note 1 : Logic operational for VB (VB vs. VS) > 7,0V
Note 2 : All input pins (HINx, LINx) and EN, ITRIP pin are internally clamped (see abs. maximum ratings)
Note 3 : In case of input pulse width at LINx and HINx below 1µ the input pulse may not be transmitted properly
datasheet
16
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
4.4
Static logic function table
VCC
VBS
X
RCIN
X
ITRIP
ENABLE
X
FAULT
LO1,2,3
HO1,2,3
<VCCUV–
15V
X
0
0
0
<VBSUV–
15V
X
0
3.3 V
3.3 V
3.3 V
3.3 V
0
High imp
0
LIN1,2,3*
0
15V
0
0
0
<3.2 V
X
> VIT,TH+
15V
15V
0
0
LIN1,2,3*
0
0
HIN1,2,3*
0
> VRCIN,TH
> VRCIN,TH
15V
15V
0
0
High imp
High imp
15V
15V
* according to Table 1
4.5
Static parameters
VCC = VBS = 15V unless otherwise specified. All parameters are valid for Ta=25 °C.
Table 8
Static parameters
Parameter
Symbol
Values
Unit Test condition
Min.
1.7
0.7
1.9
1.1
380
45
-
Typ.
2.1
0.9
2.1
1.3
445
70
Max.
2.4
VIH
High level input voltage
V
VIL
Low level input voltage
1.1
VEN,TH+
VEN,TH-
VIT,TH+
VIT,HYS
VRCIN,TH
VRCIN,HYS
VIN,CLMAP
EN positive going threshold
EN negative going threshold
ITRIP positive going threshold
ITRIP input hysteresis
2.3
1.5
510
mV
RCIN positive going threshold
RCIN input hysteresis
5.2
2.0
10.3
6.4
-
V
-
Input clamp voltage
9
12
IIN = 4mA
(HIN and LIN acc. Table 1, EN, ITRIP)
Input clamp voltage at high impedance
(/HIN, /LIN negative logic only)
VIN,FLOAT
VOH
-
5.3
5.8
controller output
pin floating
High level output voltage
LO1,2,3
-
-
VCC -0.7 VCC -1.4
VB -0.7 VB -1.4
IO = 20mA
HO1,2,3
LO1,2,3
VOL
VCOM
+
VCOM+
IO = -20mA
Low level output voltage
-
0.2
0.6
VS+ 0.2 VS + 0.6
HO1,2,3
-
VCC and VBS supply
undervoltage positive
going threshold
VCCUV+
VBSUV+
6EDL04I06NC
6EDL04I06PC
6ED003L06-C2
6EDL04N06PC
11
11.7
12.5
8.3
9.5
9
9.8
VCC and VBS supply
undervoltage negative
going threshold
VCCUV–
6EDL04I06PC VBSUV–
6EDL04I06NC
9.8
10.8
V
6ED003L06-C2
6EDL04N06PC
7.5
8.1
8.8
datasheet
17
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
Table 8
Static parameters
Parameter
Symbol
Values
Typ.
Unit Test condition
Min.
Max.
VCC and VBS supply
undervoltage lockout
hysteresis
VCCUVH
VBSUVH
6EDL04I06NC
6EDL04I06PC
6ED003L06-C2
1.2
1.9
-
6EDL04N06PC
0.5
0.9
1
-
ILVS+
High side leakage current betw. VS and VSS
-
-
12.5
-
µA
VS = 600V
1
TJ = 125°C,
VS = 600V
High side leakage current betw. VS and VSS ILVS+
10
1
TJ = 125°C
High side leakage current between VSx and ILVS–
-
10
-
VSx - VSy = 600V
VSy (x=1,2,3 and y=1,2,3)
Quiescent current VBS supply (VB only)
Quiescent current VBS supply (VB only)
IQBS1
IQBS2
IQCC1
-
-
-
210
210
1.1
400
400
1.8
µA
HO=low
HO=high
VLIN=float.
Quiescent current VCC
6EDL04I06NC
6ED003L06-C2
mA
supply (VCC only)
6EDL04I06PC
6EDL04N06PC
-
-
0.75
1.3
0.75
1.3
0.75
70
1.5
2
Quiescent current VCC
supply (VCC only)
IQCC2
IQCC3
ILIN+
ILIN-
VLIN=0, VHIN=3.3 V
VLIN=3.3 V, VHIN=0
VLIN=3.3 V, VHIN=0
VLIN=3.3 V, VHIN=0
VLIN=3.3 V
6EDL04I06NC
6ED003L06-C2
6EDL04I06PC
6EDL04N06PC
1.5
2
Quiescent current VCC
supply (VCC only)
6EDL04I06NC
6ED003L06-C2
-
6EDL04I06PC
6EDL04N06PC
1.5
100
1100
200
Input bias current
Input bias current
Input bias current
Input bias current
6EDL04I06NC
6ED003L06-C2
-
µA
µA
6EDL04I06PC
6EDL04N06PC
400
-
700
110
0
6EDL04I06NC
6ED003L06-C2
VLIN=0
6EDL04I06PC
6EDL04N06PC
IHIN+
VHIN=3.3 V
6EDL04I06NC
6ED003L06-C2
-
70
100
6EDL04I06PC
6EDL04N06PC
400
-
700
110
0
1100
200
IHIN-
VHIN=0
6EDL04I06NC
6ED003L06-C2
6EDL04I06PC
6EDL04N06PC
IITRIP+
IEN+
VITRIP=3.3 V
VENABLE=3.3 V
VRCIN = 2 V
Input bias current (ITRIP=high)
Input bias current (EN=high)
45
45
2.8
120
120
-
IRCIN
Input bias current RCIN (internal current
source)
IO+
Mean output current for load capacity
120
165
-
mA CL=10 nF
1 Not subject of production test, verified by characterisation
datasheet
18
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EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
Table 8
Static parameters
Parameter
Symbol
Values
Typ.
Unit Test condition
Min.
Max.
charging in range from 3 V (20%) to 6 V
(40%)
1
IOpk+
Peak output current turn on (single pulse)
240
375
RL = 0 , tp <10 µs
IO-
Mean output current for load capacity
discharging in range from 12 V (80%) to 9 V
(60%)
250
-
CL=10 nF
1
IOpk-
Peak output current turn off (single pulse)
420
1.0
RL = 0 , tp <10 µs
VF,BSD
Bootstrap diode forward voltage between
VCC and VB (for types with bootstrap diode
only)
-
1.3
75
V
IF=0.5 mA
IF,BSD
VF=4 V
Bootstrap diode forward current between
VCC and VB (for types with bootstrap diode
only)
27
51
mA
RBSD
VF1=4 V, VF2=5 V
VRCIN=0.5 V
Bootstrap diode resistance (for types with
bootstrap diode only)
24
-
40
40
45
60
Ron,RCIN
Ron,FLT
RCIN low on resistance of the pull down
transistor
100
100
FAULT low on resistance of the pull down
transistor
-
VFAULT=0.5 V
1 Not subject of production test, verified by characterisation
datasheet
19
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
4.6
Dynamic parameters
VCC = VBS = 15 V, VS = VSS = VCOM unless otherwise specified. All parameters are valid for Ta=25 °C.
Table 9
Dynamic parameters
Parameter
Symbol
Values
Unit Test condition
Min.
400
360
Typ.
530
490
Max.
800
ton
Turn-on propagation delay
ns
VLIN/HIN = 0 or 3.3 V
toff
Turn-off propagation delay 6EDL04I06NC
6EDL04I06PC
760
6ED003L06-C2
6EDL04N06PC
Turn-on rise time
400
-
530
60
800
100
45
tr
VLIN/HIN = 0 or 3.3 V
CL = 1 nF
tf
Turn-off fall time
-
26
tEN
VEN=0
Shutdown propagation delay ENABLE
Shutdown propagation delay ITRIP
Input filter time ITRIP
-
780
670
230
420
300
600
1.9
1100
1000
380
700
-
tITRIP
tITRIPMIN
tFLT
VITRIP=1 V
400
155
-
Propagation delay ITRIP to FAULT
Input filter time at LIN/HIN for turn on and off
Input filter time EN
tFILIN
tFILEN
tFLTCLR
VLIN/HIN = 0 & 3.3 V
120
300
1.0
-
VLIN/HIN = 0 & 3.3 V
VITRIP = 0
Fault clear time at RCIN after ITRIP-fault,
(CRCin=1nF)
3.0
ms
ns
DT
VLIN/HIN = 0 & 3.3 V
Dead time
150
-
310
20
-
MTON
Matching delay ON, max(ton)-min(ton), ton
are applicable to all 6 driver outputs
100
external dead time
> 500 ns
MTOFF
PM
Matching delay OFF, max(toff)-min(toff), toff
are applicable to all 6 driver outputs
-
40
40
100
100
external dead time
>500 ns
Output pulse width
6EDL04I06NC
6EDL04I06PC
6ED003L06-C2
PWin > 1 µs
matching. Pwin-PWout
6EDL04N06PC
10
100
datasheet
20
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
5
Quality disclaimer
The described properties and parameters must be confirmed by specific qualification in the final system. The
results of the qualification must be open to Infineon. Otherwise Infineon does not give any design release or
warranty.
It is the responsibility of the customer to select the suitable set of materials and the manufacturing processes for
the final system, which complies to his requirements in respect of life time.
We recommend to avoid in particular:
during die separation - unwanted mechanical stress on the wafer, wear out of the cutting blade or any other
cutter misconfiguration possibly causing cracks, chipping and/or delamination of the passivation;
during/after die attachment – die attach delamination causing possibly unwanted high thermal resistance,
unwanted mechanical stress, or reduced electrical conductivity;
during/after die attachment – die attach voids causing possibly unwanted high thermal resistance, unwanted
mechanical stress, or reduced electrical conductivity;
during/after die attachment – unwanted ion migration possibly causing unwanted leakage or electrical
modification of the device;
during/after die attachment – unwanted ion migration causing possibly unwanted leakage or unwanted
electrical modification of the device;
during/after die attachment – unwanted increase of thermal conductivity possibly causing unwanted
overheating of the device;
during electrical interconnect, in particular wire bonding – mechanical overstress possibly causing sheared
wires and/or damaged pads;
during electrical interconnect, in particular wire bonding – lacking bond integrity, in particular non sticking
interconnects on pads possibly causing unwanted misfunction of the device and/or unwanted leakages;
during encapsulation of the device – unwanted shrink or extension of the mould compound possibly causing
corrosion;
during encapsulation of the device – unwanted ion migration causing unwanted leakage or unwanted
electrical modification of the device;
during encapsulation of the device – unsuitable mould, unsuitable moulding processes possibly causing
potentially wire sweep of electrical interconnects;
during encapsulation of the device – sharp moudl filler components possibly causing penetration of the
passivation, hence unwanted environmental influences like corrosion or ion migration etc.
during encapsulation of the device – unsuitable mould with unsuitable thermal conductivity possibly causing
overheating of the device, resulting in damage of single or multiple transistors/diodes causing non
functionality of the device, uncluding unwanted leakages;
during encapsulation of the device – unwanted low creepage distances, possibly bringing about the risk of
high voltage avalanche breakthroughs;
during encapsulation of the device – unsuitable mould and/or mouldling processes possibly causing
delamination, resulting in overheating, leackages, shorts, open accessible voltage carrying parts, shortend
lifetime etc.
during encapsulation of the device – unsuitable thermal behaviour of encapsulation (expansion/shrinking,
state change) possibly resulting in overheating, sheared wire, openly accessible voltage carrying parts.
datasheet
21
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
6
Timing diagrams
tFILIN
tIN
tFILIN
tIN
HIN/LIN
HIN/LIN
HO/LO
HIN/LIN
HO/LO
tIN < tFILIN
tIN < tFILIN
high
HO/LO
low
tIN
tIN
HIN/LIN
tIN > tFILIN
tIN > tFILIN
HO/LO
Figure 9
Timing of short pulse suppression (6EDL04I06NC, 6ED003L06-C2)
tFILIN
tIN
tFILIN
tIN
HIN/LIN
HIN/LIN
HO/LO
HIN/LIN
HO/LO
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HIN/LIN
HO/LO
low
tIN
tIN
tIN > tFILIN
tIN > tFILIN
Figure 10 Timing of short pulse suppression (6EDL04I06PC, 6EDL04N06PC)
LIN1,2,3
1.65V
1.65V
HIN1,2,3
HO1,2,3
12V
3V
DT
DT
3V
12 V
LO1,2,3
Figure 11 Timing of of internal deadtime (input logic according to Table 1)
datasheet
22
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
EN
tEN
HO1,2,3
LO1,2,3
3V
Figure 12 Enable delay time definition
PWIN
LIN1,2,3
HIN1,2,3
1.65V
1.65V
toff
ton
tr
tf
12V
12V
HO1,2,3
LO1,2,3
3V
3V
PWOUT
Figure 13 Input to output propagation delay times and switching times definition (6EDL04I06NC,
6ED003L06-C2)
PWIN
LIN1,2,3
1.65V
1.65V
HIN1,2,3
toff
ton
tr
tf
12V
12V
HO1,2,3
LO1,2,3
3V
3V
PWOUT
Figure 14 Input to output propagation delay times and switching times definition (6EDL04I06PC,
6EDL04N06PC)
VCCMAX , VBSMAX
20
V
17.5
vCC
vBS
13
VCCUV+, VBSUV+ 11.7
VCCUV-, VBSUV- 9.8
t
IC STATE
ON
Recommended
Area
ON
Recommended
Area
Forbidden
Area
OFF
ON
ON
ON
ON
OFF
Figure 15 Operating areas (6EDL04I06NC, 6EDL04I06PC, 6ED003L06-C2)
datasheet 23
<Revision 2.5>, 20.04.2015
EiceDRIVER(tm) Compact
6ED family - 2nd generation chip product
VCCMAX , VBSMAX
20
V
17.5
vCC
vBS
10.0
VCCUV+, VBSUV+ 9.0
VCCUV-, VBSUV- 8.1
t
IC STATE
OFF
ON
Recommended
Area
ON
Recommended
Area
Forbidden
Area
ON
ON
ON
ON
OFF
Figure 16 Operating Areas (6EDL04N06PC)
VRCIN,TH
RCIN
ITRIP
0.1V
0.1V
FAULT
1V
0.5V
tFLT
tFLTCLR
Any
output
3V
tITRIP
Figure 17 ITRIP-Timing
datasheet
24
<Revision 2.5>, 20.04.2015
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Published by Infineon Technologies AG
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