6EDL04I06PT_16 [INFINEON]
High voltage gate driver IC;
| 型号： | 6EDL04I06PT_16 |
| 厂家： | 
Infineon |
| 描述： | High voltage gate driver IC |
| 文件： | 总25页 (文件大小：818K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™
High voltage gate driver IC
6ED family - 2nd generation
3 phase 200 V and 600 V gate drive IC
6EDL04I06PT
6EDL04I06NT
6EDL04N06PT
6EDL04N02PR
EiceDRIVER™
datasheet
<Revision 2.6>, 05.08.2016
Industrial Power Control
Edition 05.08.2016
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical values stated herein and/or any information regarding the
application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any
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In addition, any information given in this document is subject to customer’s compliance with its obligations
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The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
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completeness of the product information given in this document with respect to such application.
Please note that this product is not qualified according to the AEC Q100 or AEC Q101 documents of the
Automotive Electronics Council.
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Due to technical requirements products may contain dangerous substances. For information on the types in
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personal injury.
EiceDRIVER™
6ED family - 2nd generation
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 2.6>, 05.08.2016
p.15
p.2
Increased the maximum operating ambient temperature to 105 °C
Updated disclaimer
pp.12
p.15
Delete links to application note
Corrected parameter VHO in section 4.3
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Last Trademarks Update 2010-10-26
datasheet
3
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
Table of Contents
1
Overview .............................................................................................................................................7
2
Blockdiagram......................................................................................................................................9
3
Pin configuration, description, and functionality .........................................................................11
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) ................................................................11
EN (Gate Driver Enable, Pin 10)........................................................................................................12
/FAULT (Fault Feedback, Pin 8) ........................................................................................................12
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) .........................................................13
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ......................................................................13
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) .............................................13
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) ...............................13
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4
Electrical Parameters.......................................................................................................................14
Absolute Maximum Ratings ...............................................................................................................14
Required operation conditions ...........................................................................................................15
Operating Range................................................................................................................................15
Static logic function table ...................................................................................................................16
Static parameters ...............................................................................................................................16
Dynamic parameters..........................................................................................................................19
4.1
4.2
4.3
4.4
4.5
4.6
5
Timing diagrams...............................................................................................................................20
6
6.1
6.2
Package.............................................................................................................................................23
PG-DSO-28........................................................................................................................................23
PG-TSSOP-28....................................................................................................................................24
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EiceDRIVER™
6ED family - 2nd generation
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Typical Application ...............................................................................................................................8
Block diagram for 6EDL04I06NT .........................................................................................................9
Block Diagram for 6EDL04I06PT, and 6EDL04N06PT / 6EDL04N02PR..........................................10
Pin Configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1)....................11
Input pin structure for negative logic (left) and positive logic (right)...................................................12
Input filter timing diagram for negative logic (left) and positive logic (right).......................................12
EN pin structures................................................................................................................................12
/FAULT pin structures ........................................................................................................................13
Timing of short pulse suppression (6EDL04I06NT)...........................................................................20
Figure 10 Timing of short pulse suppression (6EDL04I06PT, 6EDL04N06PT, 6EDL04N02PR)......................20
Figure 11 Timing of of internal deadtime (input logic according to Table 1) ......................................................20
Figure 12 Enable delay time definition ...............................................................................................................21
Figure 13 Input to output propagation delay times and switching times definition (6EDL04I06NT) ..................21
Figure 14 Input to output propagation delay times and switching times definition (6EDL04I06PT,
6EDL04N06PT, 6EDL04N02PR) .......................................................................................................21
Figure 15 Operating areas (6EDL04I06NT, 6EDL04I06PT) ..............................................................................21
Figure 16 Operating Areas (6EDL04N06PT, 6EDL04N02PR)...........................................................................22
Figure 17 ITRIP-Timing ......................................................................................................................................22
Figure 18 Package drawing................................................................................................................................23
Figure 19 PCB reference layout .........................................................................................................................23
Figure 20 Package drawing................................................................................................................................24
Figure 21 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint24
datasheet
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EiceDRIVER™
6ED family - 2nd generation
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Members of 6ED family – 2nd generation .............................................................................................7
Pin Description ...................................................................................................................................11
Abs. maximum ratings........................................................................................................................14
Required Operation Conditions..........................................................................................................15
Operating range .................................................................................................................................15
Static parameters ...............................................................................................................................16
Dynamic parameters..........................................................................................................................19
Data of reference layout.....................................................................................................................24
datasheet
6
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
EiceDRIVER™
3 phase 200 V and 600 V gate drive IC
1
Overview
Main features
Thin-film-SOI-technology
PG-DSO28
Maximum blocking voltage +600V
Separate control circuits for all six drivers
CMOS and LSTTL compatible input (negative logic)
Signal interlocking of every phase to prevent cross-conduction
Detection of over current and under voltage supply
externally programmable delay for fault clear after over current
detection
PG-TSSOP28
Product highlights
Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology
Ultra fast bootstrap diodes
'shut down' of all switches during error conditions
Typical applications
Home appliances
Fans, pumps
General purpose drives
Product family
Table 1
Members of 6ED family – 2nd generation
high side control input typ. UVLO-
Sales Name
Bootstrap Package
diode
HIN1,2,3 and LIN1,2,3
Thresholds
6EDL04I06NT
6EDL04I06PT
negative logic
11.7 V / 9.8 V Yes
11.7 V / 9.8 V Yes
DSO28
positive logic
DSO28
6EDL04N06PT / 6EDL04N02PR positive logic
9 V / 8.1 V
Yes
DSO28 / TSSOP28
Description
The device 6ED family – 2nd generation is a full bridge driver to control power devices like MOS-transistors or
IGBTs in 3-phase systems with a maximum blocking voltage of +600 V. Based on the used SOI-technology
there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the
device. Hence, no parasitic latch-up may occur at all temperatures and voltage conditions.
The six independent drivers are controlled at the low-side using CMOS resp. LSTTL compatible signals, down
to 3.3 V logic. The device includes an under-voltage detection unit with hysteresis characteristic and an over-
current detection. The over-current level is adjusted by choosing the resistor value and the threshold level at pin
ITRIP. Both error conditions (under-voltage and over-current) lead to a definite shut down off all six switches. An
error signal is provided at the FAULT open drain output pin. The blocking time after over-current can be
adjusted with an RC-network at pin RCIN. The input RCIN owns an internal current source of 2.8 µA. Therefore,
the resistor RRCIN is optional. The typical output current can be given with 165 mA for pull-up and 375 mA for pull
down. Because of system safety reasons a 310 ns interlocking time has been realised. The function of input EN
can optionally be extended with an over-temperature detection, using an external NTC-resistor (see Fig.1). The
datasheet
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EiceDRIVER™
6ED family - 2nd generation
monolithic integrated bootstrap diode structures between pins VCC and VBx can be used for power supply of
the high side.
DC-Bus
VCC
HIN1,2,3
LIN1,2,3
EN
VCC
VB1,2,3
HO1,2,3
HIN1,2,3
LIN1,2,3
EN
To Load
VS1,2,3
5V
FAULT
RCIN
FAULT
LO1,2,3
COM
RRCIN
CRCIN
ITRIP
VSS
RSh
VSS
Signals HIN1,2,3 and LIN1,2,3 according to Table 1
Typical Application
Figure 1
datasheet
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EiceDRIVER™
6ED family - 2nd generation
2
Blockdiagram
BOOTSTRAP DIODE-VB1
BIAS NETWORK - VB1
BIAS NETWORK / VDD2
VB1
HO1
VS1
INPUT NOISE
FILTER
HIN1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
z
UV-
DETECT
INPUT NOISE
FILTER
LIN1
BOOTSTRAP DIODE-VB2
BIAS NETWORK - VB2
VB2
INPUT NOISE
FILTER
HIN2
LIN2
HIN3
LIN3
EN
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
HO2
VS2
UV-
DETECT
INPUT NOISE
FILTER
BOOTSTRAP DIODE-VB3
BIAS NETWORK / VB3
INPUT NOISE
FILTER
VB3
HO3
VS3
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UV-
DETECT
INPUT NOISE
FILTER
>1
INPUT NOISE
FILTER
VCC
LO1
UV-
DETECT
VSS / COM
LEVEL-
Gate-
Drive
DELAY
SHIFTER
INPUT NOISE
FILTER
ITRIP
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
DELAY
LO2
S
Q
VDD2
SET
DOMINANT
LATCH
R
IRCIN
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
LO3
RCIN
COM
FAULT
VSS
>1
Figure 2
Block diagram for 6EDL04I06NT
datasheet
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EiceDRIVER™
6ED family - 2nd generation
BOOTSTRAP DIODE-VB1
BIAS NETWORK - VB1
BIAS NETWORK / VDD2
VB1
HO1
VS1
INPUT NOISE
FILTER
HIN1
LIN1
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
z
UV-
DETECT
INPUT NOISE
FILTER
BOOTSTRAP DIODE-VB2
BIAS NETWORK - VB2
VB2
INPUT NOISE
FILTER
HIN2
LIN2
HIN3
LIN3
EN
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
HO2
VS2
UV-
DETECT
INPUT NOISE
FILTER
BOOTSTRAP DIODE-VB3
BIAS NETWORK / VB3
INPUT NOISE
FILTER
VB3
HO3
VS3
DEADTIME &
SHOOT-THROUGH
PREVENTION
LATCH
Gate-
Drive
HV LEVEL-SHIFTER
+ REVERSE-DIODE
COMPAR
ATOR
UV-
DETECT
INPUT NOISE
FILTER
>1
INPUT NOISE
FILTER
VCC
LO1
UV-
DETECT
VSS / COM
LEVEL-
Gate-
Drive
DELAY
SHIFTER
INPUT NOISE
FILTER
ITRIP
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
DELAY
DELAY
LO2
S
Q
VDD2
IRCIN
SET
DOMINANT
LATCH
R
VSS / COM
LEVEL-
SHIFTER
Gate-
Drive
LO3
RCIN
COM
FAULT
VSS
>1
Figure 3
Block Diagram for 6EDL04I06PT, and 6EDL04N06PT / 6EDL04N02PR
datasheet
10
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EiceDRIVER™
6ED family - 2nd generation
3
Pin configuration, description, and functionality
1
2
3
4
5
6
7
8
9
VCC
VB1 28
HO1 27
VS1 26
HIN1
HIN2
HIN3
LIN1
nc
25
VB2 24
HO2 23
VS2 22
LIN2
LIN3
nc
FAULT
ITRIP
21
VB3 20
HO3 19
VS3 18
10 EN
11 RCIN
12 VSS
13 COM
14 LO3
17
nc
LO1 16
LO2 15
Figure 4
Pin Configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1)
Table 2
Symbol
VCC
xPin Description
Description
Low side power supply
VSS
Logic ground
HIN1,2,3
LIN1,2,3
/FAULT
EN
High side logic input (positive or negative logic according to Table 1)
Low side logic input (positive or negative logic according to Table 1)
Indicates over-current and under-voltage (negative logic, open-drain output)
Enable I/O functionality (positive logic)
ITRIP
Analog input for over-current shut down, activates FAULT and RCIN to VSS
RCIN
External RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR
Low side gate driver reference
)
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
nc
High side positive power supply
High side gate driver output
High side negative power supply
Low side gate driver output
Not connected
3.1
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 5 and Figure 6.
datasheet
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EiceDRIVER™
6ED family - 2nd generation
Vcc
Schmitt-Trigger
Schmitt-Trigger
INPUT NOISE
FILTER
INPUT NOISE
FILTER
HINx
LINx
HINx
LINx
UZ=10.5V
UZ=10.5V
5k
SWITCH LEVEL
VIH; VIL
SWITCH LEVEL
VIH; VIL
Figure 5
Input pin structure for negative logic (left) and positive logic (right)
An internal pull-up of about 75 k (negative logic) pre-biases the input during supply start-up and a ESD zener
clamp is provided for pin protection purposes. The zener diodes are therefore designed for single pulse stress
only and not for continuous voltage stress over 10V. For versions with positive, a 5 k pull-down resistor is used
for this function.
a)
b)
a)
b)
tFILIN
tFILIN
tFILIN
tFILIN
HIN
LIN
HIN
LIN
LIN
HIN
LIN
HIN
on
off
on
off
on
off
on
off
on
off
on
off
high
high
HO
LO
HO
LO
LO
HO
LO
HO
low
low
Figure 6
Input filter timing diagram for negative logic (left) and positive logic (right)
It is anyway recommended for proper work of the driver not to provide input pulse-width lower than 1 µs.
The 6ED family – 2nd generation provides additionally a shoot through prevention capability which avoids the
simultaneous on-state of two channels of the same leg (i.e. HO1 and LO1, HO2 and LO2, HO3 and LO3). When
two inputs of a same leg are activated, only one leg output is activated, so that the leg is kept steadily in a safe
state.
A minimum dead time insertion of typ. 310 ns is also provided, in order to reduce cross-conduction of the
external power switches.
3.2
EN (Gate Driver Enable, Pin 10)
The signal applied to pin EN controls directly the output stages. All outputs are set to LOW, if EN is at LOW
logic level. The internal structure of the pin is given in Figure 7. The switching levels of the Schmitt-Trigger are
here VEN,TH+ = 2.1 V and VEN,TH- = 1.3 V. The typical propagation delay time is tEN = 780 ns. There is an internal
pull down resistor (75 k), which keeps the gate outputs off in case of broken PCB connection.
IEN+, IEN-
EN
INPUT NOISE
FILTER
VEN,TH+
VEN,TH-
,
VZ= 10.5 V
6ED family – 2nd generation
Figure 7
EN pin structures
3.3
/FAULT (Fault Feedback, Pin 8)
/Fault pin is an active low open-drain output indicating the status of the gate driver (see Figure 8). The pin is
active (i.e. forces LOW voltage level) when one of the following conditions occur:
Under-voltage condition of VCC supply: In this case the fault condition is released as soon as the
supply voltage condition returns in the normal operation range (please refer to VCC pin description for
more details).
Over-current detection (ITRIP): The fault condition is latched until current trip condition is finished and
RCIN input is released (please refer to ITRIP pin).
datasheet
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EiceDRIVER™
6ED family - 2nd generation
6ED family –
2nd generation
VDD
VCC
RON,FLT
from ITRIP-Latch
from uv-detection
FAULT
>1
Figure 8
/FAULT pin structures
3.4
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11)
The 6ED family – 2nd generation provides an over-current detection function by connecting the ITRIP input with
the motor current feedback. The ITRIP comparator threshold (typ 0.44 V) is referenced to VSS ground. A input
noise filter (typ. tITRIPMIN = 230 ns) prevents the driver to detect false over-current events.
Over-current detection generates a hard shut down of all outputs of the gate driver and provides a latched fault
feedback at /FAULT pin. RCIN input/output pin is used to determine the reset time of the fault condition. As
soon as ITRIP threshold is exceeded the external capacitor connected to RCIN is fully discharged. The
capacitor is then recharged by the RCIN current generator when the over-current condition is finished. As soon
as RCIN voltage exceeds the rising threshold of typ VRCIN,TH = 5.2 V, the fault condition releases and the driver
returns operational following the ontrol input pins according to section 3.1.
3.5
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13)
VCC is the low side supply and it provides power both to input logic and to low side output power stage. Input
logic is referenced to VSS ground as well as the under-voltage detection circuit. Output power stage is
referenced to COM ground. COM ground is floating respect to VSS ground with a maximum range of operation
of +/-5.7 V. A back-to-back zener structure protects grounds from noise spikes.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VCCUV+ is present.
The IC shuts down all the gate drivers power outputs, when the VCC supply voltage is below VCCUV- = 9.8 V
respectively 8.1 V. This prevents the external power switches from critically low gate voltage levels during on-
state and therefore from excessive power dissipation.
3.6
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28)
VB to VS is the high side supply voltage. The high side circuit can float with respect to VSS following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VCC.
The device operating area as a function of the supply voltage is given in Figure 15 and Figure 16.
3.7
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive of IGBT
and MOSFET devices. Low side outputs (i.e. LO1,2,3) are state triggered by the respective inputs, while high
side outputs (i.e. HO1,2,3) are edge triggered by the respective inputs. In particular, after an under voltage
condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the respective high side
output, while after a under voltage condition of the VCC supply, the low side outputs switch to the state of their
respective inputs.
datasheet
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EiceDRIVER™
6ED family - 2nd generation
4
Electrical Parameters
4.1
Absolute Maximum Ratings
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 3
Abs. maximum ratings
Parameter
Symbol Min.
Max.
Unit
VS
High side offset voltage(Note 1)
DSO28
TSSOP28
V
VCC-VBS-6
600
180
High side offset voltage (tp<500ns, Note 1)
VCC -VBS – 50 –
VB
High side offset voltage(Note 1)
DSO28
TSSOP28
VCC – 6
620
200
High side offset voltage (tp<500ns, Note 1)
VCC – 50
-1
–
High side floating supply voltage (VB vs. VS) (internally clamped) VBS
20
High side output voltage (VHO vs. VS)
VHO
-0.5
-1
VB + 0.5
20
VCC
Low side supply voltage (internally clamped)
Low side supply voltage (VCC vs. VCOM
)
VCCOM
VCOM
VLO
-0.5
-5.7
-0.5
-1
25
Gate driver ground
5.7
Low side output voltage (VLO vs. VCOM
Input voltage LIN,HIN,EN,ITRIP
FAULT output voltage
)
VCCOM + 0.5
10
VIN
VFLT
VRCIN
PD
VCC + 0.5
VCC + 0.5
-0.5
-0.5
RCIN output voltage
–
–
Power dissipation (to package) Note 2
DSO28
TSSOP28
1.3
0.6
W
Rth(j-a)
–
–
Thermal resistance
(junction to ambient, see section 6)
DSO28
TSSOP28
75
165
K/W
°C
TJ
–
Junction temperature
125
150
50
TS
Storage temperature
- 40
dVS/dt
offset voltage slew rate (Note 3)
V/ns
Note :The minimum value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VCC,
HINx, LINx, FAULT, EN, RCIN, ITRIP, VSS, COM, LOx) and pins connected inside each high side itself (VBx, HOx, VSx) is guaranteed up
to 1.5kV (Human Body Model).
Note 1 : In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VBx. Insensitivity of
bridge output to negative transient voltage up to –50V is not subject to production test – verified by design / characterization.
Note 2: Consistent power dissipation of all outputs. All parameters inside operating range.
Note 3: Not subject of production test, verified by characterisation
datasheet
14
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
4.2
Required operation conditions
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 4
Required Operation Conditions
Parameter
Symbol Min.
Max. Unit
VB
High side offset voltage (Note 1)
DSO28
TSSOP28
V
7
620
200
Low side supply voltage (VCC vs. VCOM
)
DSO28
TSSOP28
VCCOM
10
25
4.3
Operating Range
All voltages are absolute voltages referenced to VSS -potential unless otherwise specified. All parameters are
valid for Ta=25 °C.
Table 5
Operating range
Parameter
Symbol Min.
Max. Unit
VS
VCC -
High side floating supply offset voltage
V
VBS -1
-1.0
13
500
High side floating supply offset voltage (VB vs. VCC, statically)
High side floating supply voltage (VB vs. VS, Note 1)
VBCC
VBS
500
6EDL04I06NT
6EDL04I06PT
17.5
6EDL04N06PT
6EDL04N02PR
10
17.5
High side output voltage (VHO vs. VS)
VHO
VLO
VCC
0
VBS
Low side output voltage (VLO vs. VCOM
)
0
VCC
17.5
Low side supply voltage
6EDL04I06NT
6EDL04I06PT
13
6EDL04N06PT
6EDL04N02PR
10
17.5
VCOM
VIN
Low side ground voltage
-2.5
0
2.5
5
Logic input voltages LIN,HIN,EN,ITRIP (Note 2)
FAULT output voltage
VFLT
VRCIN
tIN
VCC
VCC
0
RCIN input voltage
0
Pulse width for ON or OFF (Note 3)
Ambient temperature
1
–
µs
°C
Ta
-40
105
Note 1 : Logic operational for VB (VB vs. VS) > 7,0V
Note 2 : All input pins (HINx, LINx) and EN, ITRIP pin are internally clamped (see abs. maximum ratings)
Note 3 : In case of input pulse width at LINx and HINx below 1µ the input pulse may not be transmitted properly
datasheet
15
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
4.4
Static logic function table
VCC
VBS
X
RCIN
X
ITRIP
ENABLE
X
FAULT
LO1,2,3
HO1,2,3
<VCCUV–
15V
X
0
0
0
<VBSUV–
15V
X
0
3.3 V
3.3 V
3.3 V
3.3 V
0
High imp
0
LIN1,2,3*
0
15V
0
0
0
<3.2 V
X
> VIT,TH+
15V
15V
0
0
LIN1,2,3*
0
0
HIN1,2,3*
0
> VRCIN,TH
> VRCIN,TH
15V
15V
0
0
High imp
High imp
15V
15V
* according to Table 1
4.5
Static parameters
VCC = VBS = 15V unless otherwise specified. All parameters are valid for Ta=25 °C.
Table 6
Static parameters
Parameter
Symbol
Values
Unit Test condition
Min.
1.7
0.7
1.9
1.1
380
45
-
Typ.
2.1
0.9
2.1
1.3
445
70
Max.
2.4
VIH
High level input voltage
V
VIL
Low level input voltage
1.1
VEN,TH+
VEN,TH-
VIT,TH+
VIT,HYS
VRCIN,TH
VRCIN,HYS
VIN,CLMAP
EN positive going threshold
EN negative going threshold
ITRIP positive going threshold
ITRIP input hysteresis
2.3
1.5
510
mV
RCIN positive going threshold
RCIN input hysteresis
5.2
2.0
10.3
6.4
-
V
-
Input clamp voltage
9
12
IIN = 4mA
(HIN and LIN acc. Table 1, EN, ITRIP)
Input clamp voltage at high impedance
(/HIN, /LIN negative logic only)
VIN,FLOAT
VOH
-
5.3
5.8
controller output
pin floating
High level output voltage
LO1,2,3
-
-
VCC -0.7 VCC -1.4
VB -0.7 VB -1.4
IO = 20mA
HO1,2,3
LO1,2,3
VOL
VCOM
+
VCOM+
IO = -20mA
Low level output voltage
-
0.2
0.6
VS+ 0.2 VS + 0.6
HO1,2,3
-
VCC and VBS supply
undervoltage positive
going threshold
VCCUV+
VBSUV+
6EDL04I06NT
6EDL04I06PT
11
11.7
12.5
6EDL04N06PT
6EDL04N02PR
8.3
9
9.8
VCC and VBS supply
undervoltage negative
going threshold
VCCUV–
VBSUV–
6EDL04I06NT
6EDL04I06PT
9.5
7.5
9.8
8.1
10.8
8.8
V
6EDL04N06PT
6EDL04N02PR
datasheet
16
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
Table 6
Static parameters
Parameter
Symbol
Values
Typ.
Unit Test condition
Max.
Min.
VCC and VBS supply
undervoltage lockout
hysteresis
VCCUVH
VBSUVH
6EDL04I06PT
6EDL04I06PT
1.2
1.9
-
V
6EDL04N06PT
6EDL04N02PR
0.5
0.9
-
ILVS+
VS = 600V
High side leakage current betw. VS and VSS
1
12.5
µA
1
High side leakage current betw. VS and VSS ILVS+
-
-
10
10
-
-
TJ=125°C,VS=600V
1
TJ = 125°C
High side leakage current between VSx and ILVS–
VSx - VSy = 600V
VSy (x=1,2,3 and y=1,2,3)
Quiescent current VBS supply (VB only)
Quiescent current VBS supply (VB only)
IQBS1
IQBS2
IQCC1
-
-
-
-
210
210
1.1
400
400
1.8
HO=low
HO=high
Quiescent current VCC
VLIN=float. (all)
VVSx=50V (only
bootstrap types)
6EDL04I06NT
mA
supply (VCC only)
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
0.75
1.5
Quiescent current VCC
supply (VCC only)
IQCC2
VLIN=0, VHIN=3.3 V
VVSx=50V
6EDL04I06NT
-
-
1.3
2
VLIN=3.3 V, VHIN=0
VVSx=50V
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
0.75
1.5
Quiescent current VCC
supply (VCC only)
IQCC3
VLIN=3.3 V, VHIN=0
VVSx=50V
6EDL04I06NT
1.3
2
VLIN=3.3 V, VHIN=0
VVSx=50V
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
0.75
1.5
ILIN+
ILIN-
IHIN+
IHIN-
VLIN=3.3 V
Input bias current
Input bias current
Input bias current
Input bias current
6EDL04I06NT
-
70
100
µA
µA
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
400
700
1100
6EDL04I06NT
-
110
0
200
VLIN=0
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
6EDL04I06NT
-
70
100
VHIN=3.3 V
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
400
700
1100
6EDL04I06NT
-
-
110
0
200
VHIN=0
6EDL04I06PT
6EDL04N06PT
6EDL04N02PR
IITRIP+
IEN+
VITRIP=3.3 V
VENABLE=3.3 V
VRCIN = 2 V
Input bias current (ITRIP=high)
Input bias current (EN=high)
45
45
2.8
120
120
IRCIN
Input bias current RCIN (internal current
source)
1 Not subject of production test, verified by characterisation
datasheet
17
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
Table 6
Static parameters
Parameter
Symbol
Values
Typ.
Unit Test condition
Max.
Min.
IO+
Mean output current for load capacity
charging in range from 3 V (20%) to 6 V
(40%)
120
165
-
mA CL=10 nF
1
IOpk+
Peak output current turn on (single pulse)
240
375
RL = 0 , tp <10 µs
IO-
Mean output current for load capacity
discharging in range from 12 V (80%) to 9 V
(60%)
250
-
CL=10 nF
1
IOpk-
Peak output current turn off (single pulse)
420
1.0
RL = 0 , tp <10 µs
VF,BSD
Bootstrap diode forward voltage between
VCC and VB
-
1.3
75
V
IF=0.5 mA
IF,BSD
VF=4 V
Bootstrap diode forward current between
VCC and VB
27
51
mA
RBSD
VF1=4 V, VF2=5 V
VRCIN=0.5 V
Bootstrap diode resistance
24
-
40
40
60
Ron,RCIN
RCIN low on resistance of the pull down
transistor
100
Ron,FLT
VFAULT=0.5 V
FAULT low on resistance of the pull down
transistor
-
45
100
1 Not subject of production test, verified by characterisation
datasheet
18
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
4.6
Dynamic parameters
VCC = VBS = 15 V, VS = VSS = VCOM unless otherwise specified. All parameters are valid for Ta=25 °C.
Table 7
Dynamic parameters
Parameter
Symbol
Values
Unit Test condition
Min.
400
360
Typ.
530
490
Max.
800
ton
Turn-on propagation delay
ns
VLIN/HIN = 0 or 3.3 V
toff
Turn-off propagation delay 6EDL04I06NT
6EDL04I06PT
760
6EDL04N06PT
6EDL04N02PR
400
530
800
tr
VLIN/HIN = 0 or 3.3 V
Turn-on rise time
-
60
100
45
CL = 1 nF
tf
Turn-off fall time
-
26
tEN
VEN=0
Shutdown propagation delay ENABLE
Shutdown propagation delay ITRIP
Input filter time ITRIP
-
780
670
230
420
300
600
1.9
1100
1000
380
700
-
tITRIP
tITRIPMIN
tFLT
VITRIP=1 V
400
155
-
Propagation delay ITRIP to FAULT
Input filter time at LIN/HIN for turn on and off
Input filter time EN
tFILIN
tFILEN
tFLTCLR
VLIN/HIN = 0 & 3.3 V
120
300
1.0
-
VLIN/HIN = 0 & 3.3 V
VITRIP = 0
Fault clear time at RCIN after ITRIP-fault,
(CRCin=1nF)
3.0
ms
ns
Dead time
DT
150
-
310
20
-
VLIN/HIN = 0 & 3.3 V
Matching delay ON, max(ton)-min(ton), ton MTON
are applicable to all 6 driver outputs
100
external dead time
> 500 ns
Matching delay OFF, max(toff)-min(toff), toff MTOFF
are applicable to all 6 driver outputs
-
40
40
10
100
100
100
external dead time
>500 ns
Output pulse width
matching. Pwin-PWout
6EDL04I06NT PM
6EDL04I06PT
PWin > 1 µs
6EDL04N06PT
6EDL04N02PR
datasheet
19
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
5
Timing diagrams
tFILIN
tIN
tFILIN
tIN
HIN/LIN
HIN/LIN
HO/LO
HIN/LIN
HO/LO
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HIN/LIN
HO/LO
low
tIN
tIN
tIN > tFILIN
tIN > tFILIN
Figure 9
Timing of short pulse suppression (6EDL04I06NT)
tFILIN
tIN
tFILIN
tIN
HIN/LIN
HIN/LIN
tIN < tFILIN
tIN < tFILIN
high
HO/LO
HIN/LIN
HO/LO
HO/LO
HIN/LIN
HO/LO
low
tIN
tIN
tIN > tFILIN
tIN > tFILIN
Figure 10 Timing of short pulse suppression (6EDL04I06PT, 6EDL04N06PT, 6EDL04N02PR)
LIN1,2,3
1.65V
1.65V
HIN1,2,3
HO1,2,3
12V
3V
DT
DT
3V
12 V
LO1,2,3
Figure 11 Timing of of internal deadtime (input logic according to Table 1)
datasheet
20
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
EN
tEN
HO1,2,3
LO1,2,3
3V
Figure 12 Enable delay time definition
PWIN
LIN1,2,3
HIN1,2,3
1.65V
1.65V
toff
ton
tr
tf
12V
12V
HO1,2,3
LO1,2,3
3V
3V
PWOUT
Figure 13 Input to output propagation delay times and switching times definition (6EDL04I06NT)
PWIN
LIN1,2,3
1.65V
1.65V
HIN1,2,3
toff
ton
tr
tf
12V
12V
HO1,2,3
LO1,2,3
3V
3V
PWOUT
Figure 14 Input to output propagation delay times and switching times definition (6EDL04I06PT,
6EDL04N06PT, 6EDL04N02PR)
VCCMAX , VBSMAX
20
V
17.5
vCC
vBS
13
VCCUV+, VBSUV+ 11.7
VCCUV-, VBSUV- 9.8
t
IC STATE
ON
Recommended
Area
ON
Recommended
Area
Forbidden
Area
OFF
ON
ON
ON
ON
OFF
Figure 15 Operating areas (6EDL04I06NT, 6EDL04I06PT)
datasheet 21
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
VCCMAX , VBSMAX
20
V
17.5
vCC
vBS
10.0
VCCUV+, VBSUV+ 9.0
VCCUV-, VBSUV- 8.1
t
IC STATE
OFF
ON
Recommended
Area
ON
Recommended
Area
Forbidden
Area
ON
ON
ON
ON
OFF
Figure 16 Operating Areas (6EDL04N06PT, 6EDL04N02PR)
VRCIN,TH
RCIN
ITRIP
0.1V
0.1V
FAULT
1V
0.5V
tFLT
tFLTCLR
Any
output
3V
tITRIP
Figure 17 ITRIP-Timing
tITRIPMIN
tIN
tITRIPMIN
tIN
ITRIP
high
tFLTCLR
/FAULT
Figure 18 ITRIP Input Timing
datasheet
22
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
6
Package
6.1
PG-DSO-28
Figure 19 Package drawing
Dimensions
Material
80.0 80.0 1.5 mm³
therm [W/mK]
FR4
0.3
Metal (Copper) 70µm
388
Figure 20 PCB reference layout
datasheet
23
<Revision 2.6>, 05.08.2016
EiceDRIVER™
6ED family - 2nd generation
6.2
PG-TSSOP-28
Footprint for Reflow soldering
e = 0.65
A = 6.10
L = 1.30
B = 0.40
Figure 21 Package drawing
Figure 22 PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
Table 8
Data of reference layout
Dimensions
Material
Metal (Copper)
76.2 114.3 1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
datasheet
24
<Revision 2.6>, 05.08.2016
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
6EDL04X06XT
200 V and 600 V three-phase gate driver with Over Current Protection (OCP), Enable (EN), Fault and Integrated Bootstrap Diode (BSD)
INFINEON
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