AUIRS1170S [INFINEON]

AUIRS1170S 是一款通过汽车认证的智能次级侧驱动器 IC，该产品设计用于驱动在隔离谐振、反激和正向转换器中用作同步整流器的 N 通道功率 MOSFET。该 IC 可以控制一个或多个并联 N 通道 MOSFET，模拟肖特基二极管整流器行为。AUIRS1170S 可在 DCM 和 CCM 工作模式下运行。SYNC 引脚应在 CCM 模式下使用，通过次级或主控制器信号直接关断 MOSFET。该 IC 设计使用简单电容器耦合接口连接主控制器。除 SYNC 控制外，漏极到源极电压通过差分感测，确定电流极性并开关电源开关，近乎零电流转换。使用先进的消隐方案和双脉冲抑制实现稳健性和抗噪声能力，可在各种工作模式下可靠运行。;


型号：	AUIRS1170S
厂家：	Infineon
描述：	AUIRS1170S 是一款通过汽车认证的智能次级侧驱动器 IC，该产品设计用于驱动在隔离谐振、反激和正向转换器中用作同步整流器的 N 通道功率 MOSFET。该 IC 可以控制一个或多个并联 N 通道 MOSFET，模拟肖特基二极管整流器行为。AUIRS1170S 可在 DCM 和 CCM 工作模式下运行。SYNC 引脚应在 CCM 模式下使用，通过次级或主控制器信号直接关断 MOSFET。该 IC 设计使用简单电容器耦合接口连接主控制器。除 SYNC 控制外，漏极到源极电压通过差分感测，确定电流极性并开关电源开关，近乎零电流转换。使用先进的消隐方案和双脉冲抑制实现稳健性和抗噪声能力，可在各种工作模式下可靠运行。开关驱动控制器脉冲电源开关电容器肖特基二极管驱动器转换器
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中文：	中文翻译
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IR High Voltage IC

AUIRS1170S

Features

Product Summary

 Secondary side high speed SR controller

 Fly-back, Forward and Half-bridge topologies

 CCM operation with SYNC function

 200V proprietary IC technology

 Max 500KHz switching frequency

 Anti-bounce logic and UVLO protection

 6A peak turn off drive current

Flyback, Forward, Half

Bridge

Topology

V_D

200V

10.7 V

+3/-6A

V_OUT

I_O+& I_O-(typical)

 Micropower start-up & ultra low quiescent current

 10.7V gate drive clamp

 60ns turn-off propagation delay

 Vcc range from 11V to 20V

Turn on propagation

Delay

90ns (typical)

60ns (typical)

 Enable function synchronized with MOSFET VDS

Turn off propagation

Delay

transition

 Cycle by Cycle MOT Check Circuit prevents

multiple false trigger GATE pulses

 Automotive Qualified

Package

 Leadfree, RoHS compliant

Typical Applications

Synchronous rectification driver for:



Automotive DC-DC converters

Automotive SMPS

High power industrial SMPS

PSOP8L

Typical Application Connection

n:1

Vout

Cout

RCC

AUIRS1170S

VCC

SYNC

MOT

VCC

SYNC

MOT

CVCC

RMOT

GND

Standard Pack

Base Part Number

AUIRS1170S

Package Type

PSOP8L

Form

T&R

Quantity

2500

Orderable Part Number

AUIRS1170STR

2016-09-03

AUIRS1170S

Description

AUIRS1170S is an automotive qualified smart secondary-side driver IC designed to drive N-Channel power

MOSFETs used as synchronous rectifiers in isolated Resonant, Flyback and Forward converters. The IC can

control one or more paralleled Nch-MOSFETs to emulate the behavior of Schottky diode rectifiers.

The AUIRS1170S works in both DCM and CCM operation modes. The SYNC pin should be used in CCM mode

to directly turn-off the MOSFET by a signal from secondary or primary controller. The IC is designed to use simple

capacitor coupling interface with primary controller. In addition to the SYNC control, the drain to source voltage is

sensed differentially to determine the polarity of the current and turn the power switch on and off in proximity of

the zero current transition. Ruggedness and noise immunity are accomplished using an advanced blanking

scheme and double-pulse suppression which allow reliable operation in all operating modes.

The AUIRS1170S is intended for automotive systems that must meet ASIL requirements. In safety critical

applications power devices protection and their status monitoring is an important safety requirement which is

currently addressed with discrete circuitry. The AUIRS1170S includes specific features that simplify and

complement a proper system design, allowing users to achieve up to ASIL-D system rating.

Rev. 2.3

2016-09-03

AUIRS1170S

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to Vs lead. Stresses beyond those listed under

Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; and

functional operation of the device at these or any other condition beyond those indicated in the “Recommended

Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may

affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted

and still air conditions. Ambient temperature (T_A) is -40°C≤TA≤125°C, unless otherwise specified.

Symbol

Definition

Min.

Max. Units

Remarks

V_cc

Supply voltage

-0.3

V_EN

V_SYNC

V_GATE

V_D

Enable voltage

-0.3

-1

SYNC Voltage

Vcc=20V, Gate off

Gate voltage

Continuous Drain Sense Voltage

Pulse Drain Sense Voltage

SYNC Current

Thermal resistance, junction to case

Package power dissipation

Switching frequency

200

V_D

-5

I_SYNC

Rth_JC

P_D

-10

—

°C/W

Ta=25C

970

500

150

300

f_SW

kHz

Operating Junction temperature

Storage temperature

SOIC-8

T_J

-40

-55

—

SOIC-8, T_AMB=25C

T_S

°C

Lead temperature (soldering, 10 seconds)

T_L

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions. All voltage parameters are

absolute voltage referenced to Vs.

Symbol

Definition

Min.

Max.

Units

V_cc

V_D

Supply voltage

-3

200

125

500

Drain Sense Voltage

Junction temperature

Switching frequency

MOT pin resistor value

T_J

-25

---

°C

kHz

k

f_SW

R_MOT

Rev. 2.3

2016-09-03

AUIRS1170S

Static Electrical Characteristics

VCC=15V and -40°C≤TA≤125°C unless otherwise specified. The output voltage and current (Vo and Io)

parameters are referenced to Vs (pin6).

SUPPLY SECTION

Symbol

Definition

Min

Typ

Max

Units Test Conditions

V_CCUV+

Vcc Turn On Threshold

9.4

10.2

11.1

V_CCUV-

Vcc Turn Off Threshold (UVLO)

Vcc Turn On/Off Hysteresis

8.2

9.3

1.7

10.1

V_CCHYST

I_CC

I_QCC

Operating Current

Quiescent Current

Start-up Current

Sleep Current

1.8

2.4

200

3.4

C_LOAD=10nF,f_SW=400kHz

I_{CC START}

I_SLEEP

V_ENHI

100

150

2.70

VCC=VCCUV+ -0.1V

A

VEN=0V,

Enable Voltage High

2.15

1.2

V_ENLO

R_EN

Enable Voltage Low

1.6

1.5

2.2

Enable Pull-up Resistance

M

COMPARATOR SECTION

Symbol

Definition

Min Typ Max Units Test Conditions

V_TH1

V_TH2

Turn-off Threshold

Turn-on Threshold

-11

-5

Vcc = 18V

-150 -100 -60 mV

V_HYST

Hysteresis

V_D= - 20mV

Vcc = 18V

Ho = low

I_IBIAS1

Input Bias Current

A

Rev. 2.3

2016-09-03

AUIRS1170S

ONE SHOT SECTION

Symbol

Definition

Min Typ Max Units Test Conditions

t_BLANK

V_TH3

V_HYST3

T_B

Blanking pulse duration

7.8

3.9

s

Reset Threshold

Hysteresis *

Vcc=15V

V_TH3reset propagation delay**

400

* Guaranteed by design

** See MOT Protection Mode section

MINIMUM ON TIME SECTION

Symbol

Definition

Min

Typ Max Units Test Conditions

100

1.7

210

2.8

390

3.9

RMOT =5k

T_ONmin

Minimum On Time*

s

RMOT =75k

*See Pin Description section for R_MOTcalculation formula

Electrical Characteristics

VCC=15V and -40°C≤TA≤125°C unless otherwise specified. The output voltage and current (VO and IO)

parameters are referenced to Vs (pin6).

SYNC and ENABLE SECTION

Symbol

Definition

Min

Typ Max Units Test Conditions

V_SYHI

V_SYLO

SYNC Voltage High (disable)

SYNC Voltage Low (enable)

2.4

0.7

0.6

SYNC=high to low

C_LOAD=1nF

SYNC=low to high

C_LOAD=1nF

T_SYon

SYNC Turn-on Prop. Delay

SYNC Turn-off Prop. Delay

130

120

T_SYoff

T_SYPWf

I_synch

Minimum SYNC Pulse Width(*)

Synch pin input current

0.8

Td_{EN_on}

Td_{EN_off}

Delay from EN high to V_Ghigh

Delay from EN low to V_Glow (*)

EN_low >6us

300

(*) guaranteed by design

Rev. 2.3

2016-09-03

AUIRS1170S

GATE DRIVER SECTION

Symbol

Definition

Min

Typ Max Units Test Conditions

I_GATE=200mA,

Vcc = 12V

V_CC=12V-18V

(internally clamped)

C_LOAD=1nF

V_GLO

V_GTH

Gate Low Voltage

Gate High Voltage

0.19 0.29

10.7 11.9

9.4

t_r1

t_f1

Rise Time

ns C_LOAD=10nF, V_CC=15V

ns C_LOAD=1nF, V_CC=15V

Fall Time

T_Don

T_Doff

I_{O source}

I_{O sink}

Turn on Propagation Delay

Turn off Propagation Delay

Output Peak Current (source) (*)

Output Peak Current (sink) (*)

120

C_LOAD=10nF

(*) guaranteed by design

Rev. 2.3

2016-09-03

AUIRS1170S

Functional Block Diagram

Rev. 2.3

2016-09-03

AUIRS1170S

Input/Output/Enable Pin Equivalent Circuit Diagrams

Rev. 2.3

2016-09-03

AUIRS1170S

Lead Definitions

PIN #

Symbol

Description

VCC

SYNC

MOT

Supply Voltage

SYNC Input for direct turn off

Minimum On Time

Enable

FET Drain Sensing

FET Source Sensing and GND connection

Not connected

VGATE

ExpPad

Gate Driver Output

at Vs potential, use only for thermal dissipation.

Lead Assignment

VCC

SYNC

MOT

VGATE

Exposed pad

Rev. 2.3

2016-09-03

AUIRS1170S

Detailed Pin Description

VCC: Power Supply

This is the supply voltage pin of the IC and it is monitored by the under voltage lockout circuit. It is possible to turn

off the IC by pulling this pin below the minimum turn off threshold voltage, without damage to the IC.

To prevent noise problems, a bypass ceramic capacitor connected to Vcc and COM should be placed as close as

possible to the AUIRS1170. This pin is internally clamped.

SYNC: Direct Turn-off and Reset

SYNC is used to directly turn-off the SR MOSFET by an external signal. The gate output of AUIRS1170 is low

when SYNC voltage is higher than VSYHI threshold. The propagation delay from SYNC goes high to gate turns off

is 50ns maximum. The turn-off of SYNC is a direct control and it ignores the MOT time (override).

The SYNC pin will reset MOT and Blanking time when SYNC switches from low to high. It will reset MOT timer

and Blanking timer only at the rising edge of signal. This function is useful for very low output voltage condition

(such as overload or short circuit) where the VD voltage is too low to reach Vth3 threshold to reset the timers.

SYNC pin also can be used to control the turn-on time of SR MOSFET (adding additional delay time at turn-on for

noise immunity). If not used, SYNC pin should be connected to COM.

MOT: Minimum On Time

The MOT programming pin controls the amount of minimum on time. Once VTH2 is crossed for the first time, the

gate signal will become active and turn on the power FET. Spurious ringings and oscillations can trigger the input

comparator off. The MOT blanks the input comparator keeping the FET on for a minimum time. The MOT is

programmed between 200ns and 3us (typ.) by using a resistor referenced to COM and can be programmed using

the following formula:

푅_푀푂푇= 2.5 ∗ 10^ꢀꢁ푡_푀푂푇

EN: Enable

This pin is used to activate the IC “sleep” mode by pulling the voltage level below 1.6V (typ). In sleep mode the IC

will consume a minimum amount of current. All switching functions will be disabled and the gate will be inactive.

VD: Drain Voltage Sense

VD is the voltage sense pin for the power MOSFET Drain. This is a high voltage pin and particular care must be

taken in properly routing the connection to the power MOSFET drain. Additional Filtering is recommended; see

application section for details.

VS: Source Voltage Sense

VS is the differential sense pin for the power MOSFET Source and IC gnd connection. This pin must must be

connected as close as possible to the power MOSFET source pin. Good electrical connection must be done to

this pin since the internal devices and gate driver are referenced to this point.

VGATE: Gate Drive Output

This is the gate drive output of the IC. Drive voltage is internally limited and provides 2A peak source and 7A peak

sink capability. Although this pin can be directly connected to the power MOSFET gate, the use of minimal gate

resistor is recommended, especially when putting multiple FETs in parallel. Care must be taken in order to keep

the gate loop as short and as small as possible in order to achieve optimal switching performance.

Rev. 2.3

2016-09-03

AUIRS1170S

Functional Description

State Diagram

UVLO/Sleep Mode

The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold

voltage, VCC ON. During the time the IC remains in the UVLO state, the gate drive circuit is inactive and the IC

draws a quiescent current of ICC START. The UVLO mode is accessible from any other state of operation whenever

the IC supply voltage condition of VCC < VCC UVLO occurs.

The sleep mode is initiated by pulling the EN pin below 1.6V (typ). In this mode the IC is essentially shut down

and draws a very low quiescent supply current.

Normal Mode and Synchronized Enable Function

The IC enters in normal operating mode once the UVLO voltage has been exceeded and the EN voltage is above

VENHI threshold. When the IC enters the Normal Mode from the UVLO Mode, the GATE output is disabled (stays

low) until VDS exceeds VTH3 to activate the gate. This ensures that the GATE output is not enabled in the middle of

a switching cycle. This logic prevents any reverse currents across the device due to the minimum on time function

in the IC. The gate will continuously drive the SR MOSFET after this one-time activation. The Cycle by Cycle

MOT protection circuit is enabled in Normal Mode.

Rev. 2.3

2016-09-03

AUIRS1170S

MOT Protection Mode

If the secondary current conduction time is shorter than the MOT (Minimum On Time) setting, the next driver

output is disabled. This function can avoid reverse current that occurs when the system works at very low duty-

cycles or at very light/no load conditions and reduce system standby power consumption by disabling GATE

outputs. The Cycle by Cycle MOT Check circuit is always activated under Normal Mode and MOT Protection

Mode, so that the IC can automatically resume normal operation once the load increases to a level and the

secondary current conduction time is longer than MOT.

VG pulse can result shorter than MOT in case the sensed VDS voltage crosses both VTH1 and VTH3 before

MOT time is expired. In particular, VG signal is VTH3 dominant and it is reset when VDS crosses VTH3. Despite

the pulse length may result shorter, the MOT functionality is preserved and AUIRS1170S filters the following VDS

pulse out by keeping VG low. Figure M1 shows the behavior of AUIRS1170S at VG pin in this specific case

(continuous line) and in case VDS does not cross VTH3 before MOT is expired (dotted line).TP represents the

VDS pulse length, TA defines the time at which VDS crosses VTH3, TB is the intrinsic delay of VTH3 reset circuit

and TG is the VG pulse length. TB has been designed in order to filter out possible VDS noises due to switching

of the driven switch and it is in the order of 400ns.

VDS

Vth3

Vth1

Vth2

MOT

Figure M1: VG length as function of VDS in case it crosses VTH3 either

before (continuous line) or after (dotted line) MOT expires.

Rev. 2.3

2016-09-03

AUIRS1170S

Application Information

General Description

The AUIRS1170 Smart Rectifier IC can emulate the operation of diode rectifier by properly driving a Synchronous

Rectifier (SR) MOSFET. The direction of the rectified current is sensed by the input comparator using the power

MOSFET RDSon as a shunt resistance and the GATE pin of the MOSFET is driven accordingly. Internal blanking

logic is used to prevent spurious transitions. The Synchronous pin (SYNC) can directly take the signal sent from

primary controller to turn off the gate of SR MOSFET prior to the turn-on of primary MOSFET therefore prevent

negative current in SR circuit under CCM condition.

AUIRS1170 is suitable for Flyback, Forward and Resonant Half-Bridge topologies.

Figure 1: Input Comparator Threshold

Flyback Application

The modes of operation for a Flyback circuit differ mainly for the turn-off phase of the SR switch, while the turn-on

phase of the secondary switch (which corresponds to the turn off of the primary side switch) is identical.

Turn-on phase

When the conduction phase of the SR FET is initiated, current will start flowing through its body diode, generating

a negative VDS voltage across it. The body diode has generally a much higher voltage drop than the one caused

by the MOSFET on resistance and therefore will trigger the turn-on threshold VTH2. At that point the AUIRS1170

will drive the gate of MOSFET on which will in turn cause the conduction voltage VDS to drop down. This drop is

usually accompanied by some amount of ringing, that can trigger the input comparator to turn off; hence, a

Minimum On Time (MOT) blanking period is used that will maintain the power MOSFET on for a minimum amount

of time.

The programmed MOT will limit also the minimum duty cycle of the SR MOSFET and, as a consequence, the max

duty cycle of the primary side switch.

DCM/CrCM Turn-off phase

Once the SR MOSFET has been turned on, it will remain on until the rectified current will decay to the level where

VDS will cross the turn-off threshold VTH1. This will happen differently depending on the mode of operation. In DCM

the current will cross the threshold with a relatively low dI/dt. Once the threshold is crossed, the current will start

flowing again through the body diode, causing the VDS voltage to jump negative. Depending on the amount of

residual current, VDS may trigger once again the turn on threshold: for this reason VTH2 is blanked for a certain

amount of time (TBLANK) after VTH1 has been triggered.

The blanking time is internally set. As soon as VDS crosses the positive threshold VTH3 also the blanking time is

terminated and the IC is ready for next conduction cycle.

Rev. 2.3

2016-09-03

AUIRS1170S

Figure 2: Flyback primary and secondary currents and voltages for DCM mode

Figure 3: Flyback primary and secondary currents and voltages for CrCM mode

Vin

CVcc

RVcc

Vcc

Syn

MOT

Cout

Cin

RMOT

Cfil

Rfil

Rtn

Figure 4: AUIRS1170 in DCM/CrCM mode Flyback

Rev. 2.3

2016-09-03

AUIRS1170S

Figure 5: AUIRS1170 DCM/CrCM Sync Rect operation (with SYNC connected to COM)

CCM Turn-off phase

In CCM mode the turn on phase is identical to DCM or CrCM and therefore won’t be repeated here. The turn off

transition is much steeper and dI/dt involved is much higher (Figure 6). If the SR controller wait for the primary

switch to turn back on and turn the gate off according to the FET current crossing VTH1, it has high chance to get

reverse current in the SR MOSFET. A predictable turn-off prior to the primary turn-on is necessary. A decoupling

and isolation capacitor can be used to couple the primary gate signal to AUIRS1170 SYNC pin and turn-off the

SR MOSFET prior to the current slope goes to negative. Some turn-on delay to the primary MOSFET can

guarantee no shoot through between the primary and secondary.

In CCM application the connection of AUIRS1170 is recommended as shown in Figure 7.

Figure 6: Primary and secondary currents and voltages for CCM mode

Rev. 2.3

2016-09-03

AUIRS1170S

Figure 7: AUIRS1170 schematic in CCM mode Flyback

AUIRS1170 is designed to directly take the control information from primary side with capacitor coupling. A high

voltage, low capacitance capacitor is used to send the primary gate driver signal to the SYNC pin. To have the

circuit work properly, a Y cap is required between primary ground and secondary ground. No pulse transformer is

required for the SYNC function, helps saving cost and PCB area.

The turn-off phase with SYNC control is shown in Figure 8.

In this case a blanking period is not applied; SYNC logic high will reset blanking time.

Figure 8: Secondary side CCM operation

Rev. 2.3

2016-09-03

AUIRS1170S

Forward Application

The typical forward schematic with AUIRS1170 is shown in Figure 9. The operation waveform of SR in Forward is

similar to the CCM operation of Flyback.

Figure 9: Forward application circuit

Rev. 2.3

2016-09-03

AUIRS1170S

Resonant Half-Bridge Application

The typical application circuit of AUIRS1170 in LLC half-bridge is shown in Figure 10.

Figure 10: Resonant half-bridge application circuit

The SYNC pin can be tied to Vs in LLC converter. The turn-on phase and turn-off phase is similar to flyback

converter except the current shape is sinusoid. The typical operation waveform can be found below.

Figure 11: Resonant half-bridge operation waveforms (SYNC connected to Vs)

Rev. 2.3

2016-09-03

AUIRS1170S

Application details

Special care has to be taken here in the selection of M3 and M4 mosfets rdson and Qg, because of the current

shape. Being the current sinusoidal, a certain delay is expected from the time the M3 (M4) body diode will start

conducting to the time the M3 (M4) channel will be closed. This depends on the di/dt and on the forward recovery

time of the body diodes. In any case, it is necessary that diode forward voltage rises (in absolute value) above

Vth2 before the gate drive is activated.

Because the forward recovery time of the state of the art mosfets is very short (few tens nsec) and forward

recovery voltage may be several volts, this delay may be neglected, except in case of MHz operation.

So, in absence of any filter on pin Vd, the only significant delay at turn-on is due to the mosfet Qg, charged by the

peak current of the IC gate driver output (3A typ).

On the other side, as deeply discussed in AN1205, some filter is needed on pin Vd, which delays the fall time at

the IC Vd input; for that reason, AN1205 suggests the filter capacitor is quickly discharged trough a diode, whose

anode is connected to pin Vd and whose cathode is connected to the mosfet drain terminal, as shown in fig.12:

Fig.12: Vds filtering of noise generated by layout parasitics

At turn-off, because Vth1 is very low (few mV), very little delay is expected.

As said before, the turn-on delay introduced by the filter on Vd-Vs is deeply discussed in AN1205 and only few

guidelines how to calculate the filter and the relevant delay are given here.

Moreover, an example of estimation of the delay introduced by M3 (M4) rdson and Qg is given.

To such delays, the delay introduced by the Vd-Vs filter has, of course, to be added.

Vds filtering

In resonant and high power applications the synch. rect. switch signal Vds may be not so clean, because of

secondary stray inductances (see an example in figure 13 where dark blue is the voltage across the secondary

switch, called S1; green is the total secondary current, flowing into the two alternate branches of the rectifier, S1

and S2; purple is the primary current and light blue the gate signal of the AUIRS1170S which drives S1).

Except when working at exactly the resonant frequency, there will always be a phase shift between the half (or

full) bridge center tap voltage and the current. This is clearly visible in figure 13, where some extra Vds ringing

appears in the middle of the Vds pulse, caused by the commutation of the primary switches.

This extra ringing on Vds, if not properly filtered, may induce false or premature commutations of the

AUIRS1170S; to be more specific it may happen that at the primary switching transition the induced noise from

primary to secondary forces the turn-off of the active synch. rect Fet. This effect is more evident at low output

current when the signal across the synch. rect Fes is low.

Rev. 2.3

2016-09-03

AUIRS1170S

Figure 13: practical secondary waveforms in a LLC converter

To improve the noise rejection then a LP filter on Vds is suggested; the general rule is that filter cut-off frequency

has to be set according to the fundamental frequency of the ringings (Fring): because it is a first order filter, its -

3dB frequency shall be at least a decade below the ringing fundamental.

On the other side, the filter introduces delays at both turn-on and turn-off.

An example is shown in figure 14. A filter with a cut-off frequency of 1MHz (100pF - 1.5kOhm ) introduces a turn-

on delay of several hundred nsec (around 650ns).

Fortunately such delay can be easily compensated by introducing a diode in parallel to the filter resistance, which

quickly discharges Cf during the high to low Vds transition.

The effect of such diode is shown in figure 15, where the turn-on delay is now only 134nsec.

Neglecting for a moment the compensation enabled by the diode, the delay cannot become a significant part of

the switching half cycle. The delay introduced by the filter (0 to 90%) is 2.3 * R_f*C_f. Assuming as a starting point

that the delay must stay at least below 20% of the half PWM period (Tsw/2), which is about half of the delay

shown in Fig.14, we have that:

ꢀ

ꢀꢁ

≥

푓

= 10 ∗ 퐹ꢄꢅ

[1]

ꢂ.3∗ꢃ ∗퐶

푇푠푤

푓

The delay compensation forced by the diode will then further reduce the real delay, since the discharging

equivalent resistance "Rd" of the diode in forward conduction will be used.

Then the final approximated formula to determine the RC filter pole value is the following:

2.ꢆ ∗ 10

2 ∗ 휋

퐹푟ꢉ푛ꢊ

퐹ꢄꢅ ≤

= 퐹푝 ≤

2 ∗ 휋 ∗ 푅_ꢇꢈ_ꢇ

A final verification of the best working value has to be carried on in the real application and a good compromise

has to be found case by case.

Rev. 2.3

2016-09-03

AUIRS1170S

Figure 14: effect of Vds filter on turn-on delay.

Figure 15: diode-discharge compensation of filter induced turn on delay

In all cases, the choice of R_fand C_fis not free. R_fis directly in series with pin Vd on the AUIRS1170S. Because

the input Vd-Vs comparator is fed by an internal current source, adding too much external resistance may

severely impact the turn-on threshold. Therefore a R_fvalue < 1.5k - 2k Ohm is recommended.

Rev. 2.3

2016-09-03

AUIRS1170S

Turn-on delay and Mosfet selection

As said, the trigger of Vth2 threshold may be considered instantaneous, because of the forward recovery voltage

of the body diode. After a time Tdon, Vgs will start rising. Because the mosfet is turned-on at zero voltage, there is

no Miller plateau effect. Thus, the time the mosfet channel gets the whole current may be approximated as:

Tdelay_on= Tdon + Vgsth*Ciss/I_Osource

This delay is almost independent from the secondary current, provided the mosfet has enough transconductance.

A more precise estimation is:

ꢈꢉꢄꢄ

퐹ꢄꢅ

ꢋ푑푒푙푎푦 − 표푛 = ꢋ푑표푛 + (푉ꢊꢄ푡ℎ ∗

) /ꢌ1 − ꢊ푚 ∗ ꢈꢉꢄꢄ ∗ 2 ∗ 휋 ∗

∗ 퐼푝푘ꢍ

퐼표ꢄ표푢푟푐푒

Where gm is the mosfet transconductance (at low current levels) and Ipk is the secondary sinusoidal current peak

value.

Worth to say that, to keep the mosfet channel in conduction, the rdson of the mosfet must not be too low!

In fact, if at the expiration of the MOT the channel voltage drop:

Vds = Rdson*i(T_ONmin) < Vth1

the gate pulse will be immediately terminated and the whole current will go back to the body diode.

A good rule of thumb is then to choose the Mosfet Rdson so that the voltage dropout across it will be around

100mV at max output current.

Turn-off

Turn-off is a bit more critical because, if too long, some cross conduction may occur in the output rectification.

Turn-off will actually be initiated before the current zero crossing, at the time Rdson*i(t) reaches Vth1.

This “anticipation” is given by:

Dt^--= Vth1/(Rdson*2*π*Fsw*Ipk)

After the time Tdoff, due to the IC internal propagation delay, the gate driver will start to discharge the mosfet Qg.

The mosfet channel may be considered fully closed when Vgs approaches Vgs_th. Therefore:

Tfall = (Qg-Qgs₁)/I_Osink

Where Qg is the total gate charge and Qgs₁the gate charge to get to the Vgs_th.

The total turn-off delay must then be

Tdelay_off= Tdoff + Tfall < Dt^--

This theoretical calculation helps to identify the optimum Rds-on and Qg of the matching synch. rect Fet,

however an experimental verification is always needed to fine tune the application for proper operation.

Rev. 2.3

2016-09-03

AUIRS1170S

Synch functionality in resonant applications

The SYNC pin also can be connected to a control signal for special turn-on and/or turn-off control.

Figure 16 is an example where the SYNC function is used to add some delay to the turn-on phase.

Figure 17 shows instead the use of synch to reset at the end of each cycle when Vds is too low to reach Vth3.

Figure 16: Resonant half-bridge with SYNC control

Figure 17: Reset by SYNC when VD<V_th3

Rev. 2.3

2016-09-03

AUIRS1170S

MOT Protection Mode

The MOT protection prevents reverse current in SR MOSFET. This function works in all three topologies.

Figure 18 is an example in Flyback converter.

Figure 18: MOT Protection Mode

General Timing Waveforms

Figure 19: Timing waveforms

Rev. 2.3

2016-09-03

AUIRS1170S

Suggested pcb layout and footprint

The exposed pad on the bottom side of the package has been introduced to improve the power dissipation

capability of the device. It is weakly electrically connected to the IC substrate, which is at Vs potential.

Therefore, special care has to be taken when designing the board layout.

Figure 20 below show two possible footprints. In both cases, the pad has no pcb traces to any signal. It may be

connected to Vs (pin6), if needed for layout simplification.

Both layout examples use DirectFet™ as synch.rectification devices; as also reported in AN1205, it is important to

have gate connections very similar to each other when several mosfets in parallel are used to carry high currents.

To avoid different Tdon and Tdoff delays due to gate traces inductance.

In the bottom example, the gate connections are optimized from the above point of view.

Figure 20: suggested footprints

Rev. 2.3

2016-09-03

AUIRS1170S

Package Information

PSOP8L

Rev. 2.3

2016-09-03

AUIRS1170S

Qualification Information

Automotive

(per AEC-Q100)

Qualification Level

Comments: This part number passed Automotive qualification.

Industrial and Consumer qualification level is granted by extension of

the higher Automotive level.

Moisture Sensitivity Level

PSOP8L

MSL3

Class 1A (500V)*

(AEC-Q100-002, Rev. E)

Human Body Model

ESD

C6 (1000V)

(per AEC-Q100-011, Rev.C)

Charged Device Model

Class II, Level A

(per AEC-Q100-004)

IC Latch-UP Test

RoHS Compliant

Yes

* Limited by pin 5 (V_D), all other pins are rated at 1500V HBM.

Rev. 2.3

2016-09-03

AUIRS1170S

Published by

Infineon Technologies AG

81726 München, Germany

IMPORTANT NOTICE

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated

herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims

any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of

intellectual property rights of any third party.

In addition, any information given in this document is subject to customer’s compliance with its obligations stated

in this document and any applicable legal requirements, norms and standards concerning customer’s products

and any use of the product of Infineon Technologies in customer’s applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of

customer’s technical departments to evaluate the suitability of the product for the intended application and the

completeness of the product information given in this document with respect to such application.

For further information on the product, technology, delivery terms and conditions and prices please contact your

nearest Infineon Technologies office (www.infineon.com).

WARNINGS

Due to technical requirements products may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies office.

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized

representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications

where a failure of the product or any consequences of the use thereof can reasonably be expected to result in

personal injury.

Rev. 2.3

2016-09-03

AUIRS1170S [INFINEON]

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