AUIRS2336STR_技术文档

October 11, 2010

Automotive Grade

AUIRS2336S

3-PHASE BRIDGE DRIVER IC

Product Summary

Features

•

Drives up to six IGBT/MOSFET power devices

Topology

V_OFFSET

3 Phase

≤ 600 V

Gate drive supplies up to 20 V per channel

Over-current protection

Over-temperature shutdown input

Advanced input filter

Integrated deadtime protection

Shoot-through (cross-conduction) protection

Undervoltage lockout for V_CC& V_BS

Enable/disable input and fault reporting

Adjustable fault clear timing

V_OUT

10 V – 20 V

200 mA & 350 mA

530 ns & 530 ns

275 ns

I_o+& I _o-(typical)

t_ON& t_OFF(typical)

Deadtime (typical)

Separate logic and power grounds

3.3 V input logic compatible

Package Options

Tolerant to negative transient voltage

Designed for use with bootstrap power supplies

Matched propagation delays for all channels

-40°C to 125°C operating range

RoHS compliant

Lead-Free

Automotive

28-Lead SOIC Wide Body

qualified*

Typical Applications

•

HVAC compressor

Brushless automotive applications

Typical Connection Diagram

* Qualification standards can be found on IR’s web site www.irf.com

AUIRS2336S

Table of Contents

Page

3

Description

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Static Electrical Characteristics

Dynamic Electrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

4

5

6

7-8

9

10

11

12

Lead Assignments

13

Application Information and Additional Details

Parameter Temperature Trends

Package Details

14-29

30-33

34

Tape and Reel Details

35

Part Marking Information

Ordering Information

36

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2

AUIRS2336S

Description

The AUIRS2336S are high voltage, high speed, power MOSFET and IGBT gate drivers with three high-side and

three low-side referenced output channels for 3-phase applications. This IC is designed to be used with low-cost

bootstrap power supplies. Proprietary HVIC and latch immune CMOS technologies have been implemented in a

rugged monolithic structure. The floating logic input is compatible with standard CMOS or LSTTL outputs (down

to 3.3 V logic). A current trip function which terminates all six outputs can be derived from an external current

sense resistor. Enable functionality is available to terminate all six outputs simultaneously. An open-drain

FAULT signal is provided to indicate that a fault (e.g., over-current, over-temperature, or undervoltage shutdown

event) has occurred. Fault conditions are cleared automatically after a delay programmed externally via an RC

network connected to the RCIN input. The output drivers feature a high-pulse current buffer stage designed for

minimum driver cross-conduction. Shoot-through protection circuitry and a minimum deadtime circuitry have

been integrated into this IC. Propagation delays are matched to simplify the HVIC’s use in high frequency

applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high-side

configuration, which operate up to 600 V.

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3

AUIRS2336S

Qualification Information^†

Automotive

(per AEC-Q100^††)

Qualification Level

Comments: This family of ICs has passed an Automotive

qualification. IR’s Industrial and Consumer qualification

level is granted by extension of the higher Automotive level.

MSL3^†††260°C

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

Class M2 (200V)

(per AEC-Q100-003)

Class H1C (1500V)

Machine Model

ESD

Human Body Model

(

)

per AEC-Q100-002

Class C4 (1000V)

Charged Device Model

(per AEC-Q100-011)

Class II Level A

(per AEC-Q100-004)

Yes

IC Latch-Up Test

RoHS Compliant

†

††

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

Exceptions to AEC-Q100 requirements are noted in the qualification report.

††† Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

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4

AUIRS2336S

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. These are

stress ratings only, functional operation of the device at these or any other condition beyond those indicated in the

“Recommended Operating Condition” is not implied. Exposure to absolute maximum-rated conditions for extended

periods may affect device reliability. All voltage parameters are absolute voltages referenced to V_SSunless otherwise

stated in the table. The thermal resistance and power dissipation ratings are measured under board mounted and

still air conditions. Voltage clamps are included between V_CC& COM (25 V), V_CC& V_SS(20 V), and V_B& V_S(20 V).

Symbol

V_CC

Definition

Min

-0.3

Max

20^†

Units

Low side supply voltage

V_IN

V_RCIN

V_B

V_S

V_HO

Logic input voltage (HIN, LIN, ITRIP, EN)

RCIN input voltage

High-side floating well supply voltage

High-side floating well supply return voltage

Floating gate drive output voltage

Low-side output voltage

Fault output voltage

Power ground

Allowable V_Soffset supply transient relative to V_SS

High-side input pulse width

V_SS-0.3

-0.3

V_SS+5.2

V_CC+0.3

620^†

V_B+0.3

V_CC+0.3

50

V_B-20^†

V_S-0.3

COM-0.3

V_SS-0.3

V_CC-25

—

V

V_LO

V_FLT

COM

dV_S/dt

PW_HIN

P_D

V/ns

ns

W

500

—

1.6

Package power dissipation @ T_A≤+25ºC

Rth_JA

T_J

T_S

Thermal resistance, junction to ambient

Junction temperature

Storage temperature

—

-55

—

78

ºC/W

150

300

ºC

T_L

Lead temperature (soldering, 10 seconds)

†

All supplies are tested at 25 V. An internal 20 V clamp exists for each supply.

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AUIRS2336S

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters are

absolute voltages referenced to V_SSunless otherwise stated in the table. The offset rating is tested with supplies of

(V_CC-COM) = (V_B-V_S) = 15 V.

Symbol

V_CC

Definition

Low-side supply voltage

Min

10

Max

20

Units

V_IN

V_B

V_S

HIN, LIN, & EN input voltage

High-side floating well supply voltage

High-side floating well supply offset voltage^†

Transient high-side floating supply voltage^††

Floating gate drive output voltage

Low-side output voltage

Power ground

FAULT output voltage

RCIN input voltage

ITRIP input voltage

V_SS

V_S+10

COM-8

-50

V_s

COM

-5

V_SS

-40

V_SS+5

V_S+20

600

V_B

V_CC

5

V_CC

V_S(t)

V_HO

V_LO

COM

V_FLT

V_RCIN

V_ITRIP

T_A

V

V_SS+5

125

Ambient temperature

ºC

†

V

Logic operation for _Sof –8 V to 600 V. Logic state held for _Sof –8 V to –V_BS.

†† Operational for transient negative V_Sof V_SS- 50 V with a 50 ns pulse width. Guaranteed by design. Refer to

the Application Information section of this datasheet for more details.

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AUIRS2336S

Static Electrical Characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤ 125°C

with bias conditions of (V_CC-COM) = (V_B-V_S) = 15 V. The V_INand I_INparameters are referenced to V_SSand are

applicable to all six channels. The V_Oand I_Oparameters are referenced to respective V_Sand COM and are

applicable to the respective output leads HO or LO. The

parameters are referenced to V_SS. The

V_CCUV

V_BSUV

parameters are referenced to V_S.

Symbol

Definition

Min

Typ Max

Units Test Conditions

V_CCUV

V_CCsupply undervoltage positive going threshold

8

8.9

8.2

0.7

8.9

8.2

0.7

9.8

9

+

V_CCsupply undervoltage negative going

threshold

V_CCUV

7.4

0.3

8

-

V_CCUVHY

V_CCsupply undervoltage hysteresis

—

9.8

9

V

NA

V_BSUV+V_BSsupply undervoltage positive going threshold

V_BSsupply undervoltage negative going

threshold

V_BSUV-

7.4

0.3

V_BSUVHY

V_BSsupply undervoltage hysteresis

—

I_LK

I_QBS

—

High-side floating well offset supply leakage

Quiescent V_BSsupply current

50

120

V_B= V_S= 600 V

µA

70

All inputs are in the

off state

I_QCC

Quiescent V_CCsupply current

—

2

3

mA

V_OH

V_OL

High level output voltage drop, V_BIAS-V_O

Low level output voltage drop, V_O

—

0.90

0.40

1.5

0.6

V

I_O= 20 mA

V_O=0 V,V_IN=0 V,

PW ≤ 10 µs

V_O=15 V,V_IN=5 V,

PW ≤ 10 µs

I_o+

I_o-

Output high short circuit pulsed current

Output low short circuit pulsed current

75

150

2.5

—

200

350

—

mA

Logic “0” input voltage

Logic “1” input voltage

Logic “0” input voltage

V_IH

—

NA

V

V_IL

—

0.8

5.65

Input voltage clamp

V_IN,CLAMP

4.8

5.2

I_IN= 100 µA

(HIN, LIN, ITRIP and EN)

Input bias current (HO = High)

Input bias current (HO = Low)

Input bias current (LO = High)

Input bias current (LO = Low)

I_HIN+

I_HIN-

I_LIN+

I_LIN-

—

150

110

150

110

8

3

—

50

200

150

200

150

—

1

100

V_IN= 0 V

V_IN= 4 V

V_IN= 0 V

V_IN= 4 V

µA

V

V_RCIN,THRCIN positive going threshold

V_RCIN,HYRCIN hysteresis

I_RCIN

NA

RCIN input bias current

µA

Ω

V_RCIN= 0 V or 15 V

I = 1.5 mA

R_ON,RCINRCIN low on resistance

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7

AUIRS2336S

Static Electrical Characteristics (continued)

Symbol

V_IT,TH+ITRIP positive going threshold

V_IT,TH-ITRIP negative going threshold

V_IT,HYSITRIP hysteresis

I_ITRIP+“High” ITRIP input bias current

I_ITRIP-“Low” ITRIP input bias current

Definition

Min

Typ Max

Units Test Conditions

0.37 0.46

0.55

—

V

NA

0.4

—

0.07

—

5

20

1

V_IN= 4 V

V_IN= 0 V

µA

V

—

V_EN,TH+Enable positive going threshold

V_EN,TH-Enable negative going threshold

2.5

—

NA

0.8

—

I_EN+

I_EN-

“High” enable input bias current

“Low” enable input bias current

5

20

1

V_IN= 4 V

V_IN= 0 V

I = 1.5 mA

µA

—

R_ON,FLTFAULT low on resistance

50

100

Ω

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8

AUIRS2336S

Dynamic Electrical Characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤125°C

with bias conditions of V_CC= V_B= 15 V, V_S= V_SS= COM, T_A= 25^oC, and C_L= 1000 pF. The dynamic electrical

characteristics are measured using the test definitions shown in Figure .

Symbol

Definition

Turn-on propagation delay

Turn-off propagation delay

Turn-on rise time

Min

400

—

Typ

530

125

50

Max Units

Test Conditions

t_ON

t_OFF

t_R

750

320

120

V_IN= 0 V & 5 V

t_F

Turn-off fall time

—

Input filter time^†

ns

t_FIL,IN

t_EN

200

350

510

(HIN, LIN, ITRIP)

Enable low to output shutdown

propagation delay

350

100

1

460

200

1.65

650

V_IN,V_EN= 0 V or 5 V

t_FILTER,ENEnable input filter time

—

NA

FAULT clear time

RCIN: R = 2 MΩ, C = 1 nF

ITRIP to output shutdown

propagation delay

V_IN= 0 V or 5 V

V_ITRIP= 0 V

t_FLTCLR

2.5

ms

ns

t_ITRIP

500

750

1200

V_ITRIP= 5 V

t_BL

t_FLT

DT

ITRIP blanking time

ITRIP to FAULT propagation delay

Deadtime

—

400

190

—

400

600

275

—

V_IN= 0 V or 5 V

V_ITRIP= 5 V

950

420

100

V_IN= 0 V & 5 V without

external deadtime

DT matching^††

MDT

††

V_IN= 0 V & 5 V with external

deadtime larger than DT

MT

PM

—

50

Delay matching time (t_ON, t_OFF

Pulse width distortion^†††

)

100

PW input=10 µs

†

The minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of the

input filter is exceeded.

†† This parameter applies to all of the channels. Please see the application section for more details.

††† PM is defined as PW_IN- PW_OUT

.

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9

AUIRS2336S

Functional Block Diagram:

AUIRS2336

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AUIRS2336S

Input/Output Pin Equivalent Circuit Diagrams:

V_CC

ESD

Diode

ITRIP

or EN

ESD

R_PD

Diode

V_SS

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AUIRS2336S

Lead Definitions:

Symbol

Description

VCC

VSS

Low-side supply voltage

Logic ground

VB1

High-side gate drive floating supply (phase 1)

High-side gate drive floating supply (phase 2)

High-side gate drive floating supply (phase 3)

High voltage floating supply return (phase 1)

High voltage floating supply return (phase 2)

High voltage floating supply return (phase 3)

VB2

VB3

VS1

VS2

VS3

HIN1/N

HIN2/N

HIN3/N

LIN1/N

LIN2/N

LIN3/N

HO1

Logic inputs for high-side gate driver outputs (phase 1); input is out-of-phase with output

Logic inputs for high-side gate driver outputs (phase 2); input is out-of-phase with output

Logic inputs for high-side gate driver outputs (phase 3); input is out-of-phase with output

Logic inputs for low-side gate driver outputs (phase 1); input is out-of-phase with output

Logic inputs for low-side gate driver outputs (phase 2); input is out-of-phase with output

Logic inputs for low-side gate driver outputs (phase 3); input is out-of-phase with output

High-side driver outputs (phase 1)

HO2

High-side driver outputs (phase 2)

HO3

High-side driver outputs (phase 3)

LO1

Low-side driver outputs (phase 1)

LO2

Low-side driver outputs (phase 2)

LO3

Low-side driver outputs (phase 3)

COM

Low-side gate drive return

Indicates over-current, over-temperature (ITRIP), or low-side undervoltage lockout has occurred.

This pin has negative logic and an open-drain output. The use of over-current and over-

temperature protection requires the use of external components.

Logic input to shutdown functionality. Logic functions when EN is high (i.e., positive logic). No

effect on FAULT and not latched.

FAULT/N

EN

Analog input for over-current shutdown. When active, ITRIP shuts down outputs and activates

FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally

set time t_FLTCLR, then automatically becomes inactive (open-drain high impedance).

An external RC network input used to define the FAULT CLEAR delay (t_FLTCLR) approximately

equal to R*C. When RCIN > 8 V, the FAULT pin goes back into an open-drain high-impedance

state.

ITRIP

RCIN

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AUIRS2336S

Lead Assignments

SOIC-28L Wide Body

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AUIRS2336S

Application Information and Additional Details

Information regarding the following topics are included as subsections within this section of the datasheet.

•

IGBT/MOSFET Gate Drive

Switching and Timing Relationships

Deadtime

Matched Propagation Delays

Input Logic Compatibility

Undervoltage Lockout Protection

Shoot-Through Protection

Enable Input

Fault Reporting and Programmable Fault Clear Timer

Over-Current Protection

Over-Temperature Shutdown Protection

Truth Table: Undervoltage lockout, ITRIP, and ENABLE

Advanced Input Filter

Short-Pulse / Noise Rejection

Bootstrap Power Supply Design

Separate Logic and Power Grounds

Tolerant to Negative V_STransients

PCB Layout Tips

Additional Documentation

IGBT/MOSFET Gate Drive

The AUIRS2336S HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate

several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to

drive the gate of the power switch, is defined as I_O. The voltage that drives the gate of the external power switch is

defined as V_HOfor the high-side power switch and V_LOfor the low-side power switch; this parameter is sometimes

generically called V_OUTand in this case does not differentiate between the high-side or low-side output voltage.

V_B

(or V_CC

)

(or V_CC)

I_O+

HO

(or LO)

+

I_O-

V_HO(or V_LO)

-

V_S

(or COM)

Figure 1: HVIC sourcing current

Figure 2: HVIC sinking current

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AUIRS2336S

Switching and Timing Relationships

The relationship between the input and output signals of the AUIRS2336S is illustrated below in Figures 3. From

these figures, we can see the definitions of several timing parameters (i.e., PW_IN, PW_OUT, t_ON, t_OFF, t_R, and t_F)

associated with this device.

Figure 3: Switching time waveforms

The following two figures illustrate the timing relationships of some of the functionality of the AUIRS2336S; this

functionality is described in further detail later in this document.

During interval A of Figure 5, the HVIC has received the command to turn-on both the high- and low-side switches at

the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high-

and low-side output are held in the off state.

Interval B of Figures 5 and 6 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a

result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also

held low), the voltage on the RCIN pin has been pulled to 0 V, and a fault is reported by the FAULT output

transitioning to the low state. Once the ITRIP input has returned to the low state, the output will remain disabled and

the fault condition reported until the voltage on the RCIN pin charges up to V_RCIN,TH(see interval C in Figure 6); the

charging characteristics are dictated by the RC network attached to the RCIN pin.

During intervals D and E of Figure 5, we can see that the enable (EN) pin has been pulled low (as is the case when

the driver IC has received a command from the control IC to shutdown); this results in the outputs (HOx and LOx)

being held in the low state until the enable pin is pulled high.

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15

AUIRS2336S

B

C

D

A

E

HINx

LINx

EN

ITRIP

FAULT

RCIN

HOx

LOx

Figure 5: Input/output timing diagram for AUIRS2336S

Figure 6: Detailed view of B & C intervals

Deadtime

This HVIC features integrated deadtime protection circuitry. The deadtime for this ICs is fixed; other ICs within IR’s

HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time

period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure

that the power switch being turned off has fully turned off before the second power switch is turned on. This

minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes

larger than DT are not modified by the gate driver. Figure 7 illustrates the deadtime period and the relationship

between the output gate signals.

The deadtime circuitry of the AUIRS2336S is matched with respect to the high- and low-side outputs of a given

channel; additionally, the deadtimes of each of the three channels are matched. Figure 7 defines the two deadtime

parameters (i.e., DT₁and DT₂) of a specific channel; the deadtime matching parameter (MDT) associated with the

AUIRS2336S specifies the maximum difference between DT₁and DT₂. The MDT parameter also applies when

comparing the DT of one channel of the AUIRS2336S to that of another.

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AUIRS2336S

LINx

HINx

50%

LOx

HOx

DT

50%

Figure 7: Illustration of deadtime

Matched Propagation Delays

The AUIRS2336S is designed with propagation delay matching circuitry. With this feature, the IC’s response at the

output to a signal at the input requires approximately the same time duration (i.e., t_ON, t_OFF) for both the low-side

channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT).

Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side

channels and the propagation delays of the high-side channels are matched with each other; the MT specification

applies as well. The propagation turn-on delay (t_ON) of the AUIRS2336S is matched to the propagation turn-on delay

(t_OFF).

Input Logic Compatibility

The inputs of this IC are compatible with standard CMOS and TTL outputs. The AUIRS2336S has been designed to

be compatible with 3.3 V and 5 V logic-level signals. It features an integrated 5.2 V Zener clamp on the HIN, LIN,

ITRIP, and EN pins; Figure 8 illustrates an input signal, its input threshold values, and the logic state of the IC as a

result of the input signal.

V

IH

V

IL

High

Low

Figure 8: HIN & LIN input thresholds

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AUIRS2336S

Undervoltage Lockout Protection

This IC provides undervoltage lockout protection on both the V_CC(logic and low-side circuitry) power supply and the

V_BS(high-side circuitry) power supply. Figure 9 is used to illustrate this concept; V_CC(or V_BS) is plotted over time and

as the waveform crosses the UVLO threshold (V_CCUV+/-or V_BSUV+/-) the undervoltage protection is enabled or

disabled.

Upon power-up, should the V_CCvoltage fail to reach the V_CCUV+threshold, the IC will not turn-on. Additionally, if the

V_CCvoltage decreases below the V_CCUV-threshold during operation, the undervoltage lockout circuitry will recognize

a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low

state to inform the controller of the fault condition.

Upon power-up, should the V_BSvoltage fail to reach the V_BSUVthreshold, the IC will not turn-on the high-side gate

drive output. Additionally, if the V_BSvoltage decreases below the V_BSUVthreshold during operation, the undervoltage

lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is

sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be

driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this

could result in very high conduction losses within the power device and could lead to power device failure.

Figure 9: UVLO protection

Shoot-Through Protection

The AUIRS2336S is equipped with shoot-through protection circuitry (also known as cross-conduction prevention

circuitry). Figure 10 shows how this protection circuitry prevents both the high- and low-side switches from

conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth

table.

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AUIRS2336S

Shoo-t through

protection enabled

HIN

LIN

HO

LO

Figure 10: Illustration of shoot-through protection circuitry

HIN

0

LIN

0

HO

0

LO

0

1

0

1

0

1

0

Table 1: Input/output truth table

Enable Input

The AUIRS2336S is equipped with an enable input pin that is used to shutdown or enable the HVIC. When the EN

pin is in the high state the HVIC is able to operate normally (assuming no other fault conditions). When a condition

occurs that should shutdown the HVIC, the EN pin should see a low logic state. The enable circuitry of the

AUIRS2336S features an input filter; the minimum input duration is specified by t_FILTER,EN. Please refer to the EN pin

parameters V_EN,TH+, V_EN,TH-, and I_ENfor the details of its use. Table 2 gives a summary of this pin’s functionality and

Figure 11 illustrates the outputs’ response to a shutdown command.

Enable Input

Enable input high

Enable input low

Outputs enabled^*

Outputs disabled

Table 2: Enable functionality truth table

Figure 11: Output enable timing waveform

(*assumes no other fault condition)

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AUIRS2336S

Fault Reporting and Programmable Fault Clear Timer

The AUIRS2336S provides an integrated fault reporting output and an adjustable fault clear timer. There are two

situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of

V_CCand the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally

pulled to V_SS. The fault clear timer is activated only if ITRIP pin recognizes a fault: in this case the fault output stays

in the low state until the fault condition has been removed and the fault clear timer expires; once the fault clear timer

expires, the voltage on the FAULT pin will return to V_CC.

The length of the fault clear time period (t_FLTCLR) is determined by exponential charging characteristics of the

capacitor where the time constant is set by R_RCINand C_RCIN. In Figure 12 where we see that a fault condition has

occurred (UVLO or ITRIP), RCIN and FAULT are pulled to V_SS, and once the fault has been removed, the fault clear

timer begins. Figure 13 shows that R_RCINis connected between the V_CCand the RCIN pin, while C_RCINis placed

between the RCIN and V_SSpins.

Figure 12: RCIN and FAULT pin waveforms

Figure 13: Programming the fault clear timer

The design guidelines for this network are shown in Table 3.

≤1 nF

Ceramic

C_RCIN

0.5 MΩ to 2 MΩ

>> R_ON,RCIN

R_RCIN

Table 3: Design guidelines

The length of the fault clear time period can be determined by using the formula below.

v_C(t) = V_f(1-e^-t/RC

)

t_FLTCLR= -(R_RCINC_RCIN)ln(1-V_RCIN,TH/V_CC)

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AUIRS2336S

Over-Current Protection

The AUIRS2336S is equipped with an ITRIP input pin. This functionality can be used to detect over-current events

in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a

fault is reported through the FAULT pin, and RCIN is pulled to V_SS.

The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R₀, R₁,

and R₂) connected to ITRIP as shown in Figure 14, and the ITRIP threshold (V_IT,TH+). The circuit designer will need

to determine the maximum allowable level of current in the DC- bus and select R₀, R₁, and R₂such that the voltage

at node V_Xreaches the over-current threshold (V_IT,TH+) at that current level.

V_IT,TH+= R₀I_DC-(R₁/(R₁+R₂))

V_cc

HIN(x3)

V

B

(x3)

LIN(x3)

HO(x3)

EN

V

S

(x3)

FAULT

RCIN

ITRIP

LO(x3)

COM

VSS

V_X

R

1

R

2

R

0

I_DC-

Figure 14: Programming the over-current protection

For example, a typical value for resistor R₀could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to

exceed 5 V; if necessary, an external voltage clamp may be used.

Over-Temperature Shutdown Protection

The ITRIP input of the AUIRS2336S can also be used to detect over-temperature events in the system and initiate a

shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will

need to design the resistor network as shown in Figure 15 and select the maximum allowable temperature.

This network consists of a thermistor and two standard resistors R₃and R₄. As the temperature changes, the

resistance of the thermistor will change; this will result in a change of voltage at node V_X. The resistor values should

be selected such the voltage V_Xshould reach the threshold voltage (V_IT,TH+) of the ITRIP functionality by the time that

the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.

When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes

(e.g., DL4148) can be used. This network is shown in Figure 16; the OR-ing diodes have been labeled D₁and D₂.

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21

AUIRS2336S

Figure 15: Programming over-temperature

protection

Figure 16: Using over-current protection and over-

temperature protection

Truth Table: Undervoltage lockout, ITRIP, and ENABLE

Table 4 provides the truth table for the AUIRS2336S. The first line shows that the UVLO for V_CChas been tripped;

the FAULT output has gone low and the gate drive outputs have been disabled. is not latched in this case and

V_CCUV

, the FAULT output returns to the high impedance state.

when V_CCis greater than

V_CCUV

The second case shows that the UVLO for V_BShas been tripped and that the high-side gate drive outputs have been

disabled. After V_BSexceeds the , HO will stay low until the HVIC input receives a new falling

V_BSUVthreshold

transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP

trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported

through the fault pin. In the last case, the HVIC has received a command through the EN input to shutdown; as a

result, the gate drive outputs have been disabled.

VCC

VBS

—

ITRIP

—

0 V

>V_ITRIP

0 V

EN

—

5 V

0 V

RCIN

High

Low

FAULT

0

High impedance

0

LO

0

LIN

0

HO

0

HIN

0

<

UVLO V_CC

UVLO V_BS

Normal operation

ITRIP fault

V_CCUV

15 V

<

V_BSUV

15 V

High

High impedance

0

EN command

Table 4: UVLO, ITRIP, EN, RCIN, & FAULT truth table

Advanced Input Filter

The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject

noise spikes and short pulses. This input filter has been applied to the HIN, LIN, and EN inputs. The working

principle of the new filter is shown in Figures 17 and 18.

Figure 17 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms

(Example 1) show an input signal with a duration much longer then t_FIL,IN; the resulting output is approximately the

difference between the input signal and t_FIL,IN. The lower pair of waveforms (Example 2) show an input signal with a

duration slightly longer then t_FIL,IN; the resulting output is approximately the difference between the input signal and

t_FIL,IN

.

Figure 18 shows the advanced input filter and the symmetry between the input and output. The upper pair of

waveforms (Example 1) show an input signal with a duration much longer then t_FIL,IN; the resulting output is

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22

AUIRS2336S

approximately the same duration as the input signal. The lower pair of waveforms (Example 2) show an input signal

with a duration slightly longer then t_FIL,IN; the resulting output is approximately the same duration as the input signal.

Figure 17: Typical input filter

Figure 18: Advanced input filter

Short-Pulse / Noise Rejection

This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the

input signal is less than t_FIL,IN, the output will not change states. Example 1 of Figure 19 shows the output in the high

state with input positive noise spikes of durations less than t_FIL,IN; the output does not change states. Example 2 of

Figure 19 shows the output in the low state with input negative noise spikes of durations less than t_FIL,IN; the output

does not change states.

Figure 19: Noise rejecting input filters

Figures 20 and 21 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF

pulses.

The input filter characteristic is shown in Figure 20; the left side illustrates the narrow pulse ON (short negative

pulse) characteristic while the left shows the narrow pulse OFF (short positive pulse) characteristic. The x-axis of

Figure 20 shows the duration of PW_IN, while the y-axis shows the resulting PW_OUTduration. It can be seen that for a

PW_INduration less than t_FIL,IN, that the resulting PW_OUTduration is zero (e.g., the filter rejects the input signal/noise).

We also see that once the PW_INduration exceed t_FIL,IN, that the PW_OUTdurations mimic the PW_INdurations very well

over this interval with the symmetry improving as the duration increases. To ensure proper operation of the HVIC, it

is suggested that the input pulse width for the high-side inputs be ≥ 500 ns.

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23

AUIRS2336S

The difference between the PW_OUTand PW_INsignals of both the narrow ON and narrow OFF cases is shown in

Figure 21; the careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PW_IN,

while the y-axis shows the resulting PW_OUT–PW_INduration. This data illustrates the performance and near symmetry

of this input filter.

Narrow Pulse OFF

1000

PW_OUT

PW_IN

800

600

400

200

0

200

400

Time (ns)

600

800

1000

Figure 20: input filter characteristic

Figure 21: Difference between the input pulse and the output pulse

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24

AUIRS2336S

Bootstrap Power Supply Design

For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode)

please refer to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is

available at www.irf.com.

Separate Logic and Power Grounds

The AUIRS2336S has separate logic and power ground pin (V_SSand COM respectively) to eliminate some of the

noise problems that can occur in power conversion applications. Current sensing shunts are commonly used in

many applications for power inverter protection (i.e., over-current protection), and in the case of motor drive

applications, for motor current measurements. In these situations, it is often beneficial to separate the logic and

power grounds.

Figure 24 shows a HVIC with separate V_SSand COM pins and how these two grounds are used in the system. The

V_SSis used as the reference point for the logic and over-current circuitry; V_Xin the figure is the voltage between the

ITRIP pin and the V_SSpin. Alternatively, the COM pin is the reference point for the low-side gate drive circuitry. The

output voltage used to drive the low-side gate is V_LO-COM; the gate-emitter voltage (V_GE) of the low-side switch is the

output voltage of the driver minus the drop across R_G,LO

.

DC+ BUS

D_BS

V_B

(x3)

V_CC

C_BS

HO

R_G,HO

(x3)

V_S

(x3)

V_S1

V_S2

V_S3

LO

(x3)

R_G,LO

ITRIP

+

V_GE1

V_GE2

V_GE3

-

V_SS

COM

R₂

R₀

+

R₁

V_X

-

DC- BUS

Figure 24: Separate V_SSand COM pins

Tolerant to Negative V_STransients

A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage

as the power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is

shown in Figure 25; here we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figures 26 and 27) switches off, while the U phase current is flowing to

an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-

side switch of the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive DC bus

voltage to the negative DC bus voltage.

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25

AUIRS2336S

Figure 25: Three phase inverter

DC+ BUS

Q1

ON

I_U

V_S1

D2

Q2

OFF

DC- BUS

Figure 26: Q1 conducting

Figure 27: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 28 and 29), and Q4

IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

DC+ BUS

D3

Q3

OFF

I_V

V_S2

D4

Q4

OFF

DC- BUS

Figure 28: D3 conducting

Figure 29: Q4 conducting

However, in a real inverter circuit, the V_Svoltage swing does not stop at the level of the negative DC bus, rather it

swings below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”.

The circuit shown in Figure 30 depicts one leg of the three phase inverter; Figures 31 and 32 show a simplified

illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from

the die bonding to the PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the high-side switch is on,

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26

AUIRS2336S

V_S1is below the DC+ voltage by the voltage drops associated with the power switch and the parasitic elements of

the circuit. When the high-side power switch turns off, the load current momentarily flows in the low-side

freewheeling diode due to the inductive load connected to V_S1(the load is not shown in these figures). This current

flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage between

V_S1and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V_Spin).

Figure 30: Parasitic Elements

Figure 31: V_Spositive

Figure 32: V_Snegative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative V_Stransient

voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is

greater than in normal operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding

applications. The AUIRS2336S has been seen to withstand large negative V_Stransient conditions on the order of -

50 V for a period of 50 ns. An illustration of the AUIRS2336S performance can be seen in Figure 33. This

experiment was conducted using various loads to create this condition; the curve shown in this figure illustrates the

successful operation of the AUIRS2336S under these stressful conditions. In case of -V_Stransients greater then -20

V for a period of time greater than 100 ns, the HVIC is designed to hold the high-side outputs in the off state for 4.5

μs in order to ensure that the high- and low-side power switches are not on at the same time.

Figure 33: Negative V_Stransient results for an International Rectifier HVIC

Even though the AUIRS2336S has been shown able to handle these large negative V_Stransient conditions, it is

highly recommended that the circuit designer always limit the negative V_Stransients as much as possible by careful

PCB layout and component use.

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27

AUIRS2336S

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to the

floating voltage pins (V_Band V_S) near the respective high voltage portions of the device.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

34). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops

must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT

collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a

voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Figure 34: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand V_SSpins. This

connection is shown in Figure 35. A ceramic 1 μF ceramic capacitor is suitable for most applications. This

component should be placed as close as possible to the pins in order to reduce parasitic elements.

V_cc

HIN(x3)

V

B

(x3)

LIN(x3)

HO(x3)

EN

V

S

(x3)

FAULT

CIN

RCIN

ITRIP

LO(x3)

COM

VSS

Figure 35: Supply capacitor

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28

AUIRS2336S

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at

the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions,

it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side

emitter to negative bus rail stray inductance. However, where negative V_Sspikes remain excessive, further steps

may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between the V_Spin and the switch

node (see Figure 36), and in some cases using a clamping diode between V_SSand V_S(see Figure 37). See DT04-4

at www.irf.com for more detailed information.

Figure 36: V_Sresistor

Figure 37: V_Sclamping diode

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search

function and the document number to quickly locate them. Below is a short list of some of these documents.

DT97-3: Managing Transients in Control IC Driven Power Stages

AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04-4: Using Monolithic High Voltage Gate Drivers

AN-978: HV Floating MOS-Gate Driver ICs

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29

AUIRS2336S

Parameter Temperature Trends

Figures illustrated in this chapter provide information on the experimental performance of the AUIRS2336S HVIC.

The line plotted in each figure is generated from actual lab data. A large number of individual samples were tested

at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The line consists

of three data points (one data point at each of the tested temperatures) that have been connected together to

illustrate the understood trend. The individual data points on the Typ. curve were determined by calculating the

averaged experimental value of the parameter (for a given temperature).

700

650

600

550

500

700

650

600

550

500

Max.

Typ.

Min.

Max.

Typ.

Min.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 38: t_ONvs. temperature

Figure 39: t_OFFvs. temperature

400

350

300

250

200

1000

900

800

700

600

Max.

Typ.

M ax.

Typ.

Min.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 40: DT vs. temperature

Figure 41: t_ITRIPvs. temperature

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30

AUIRS2336S

800

700

600

500

400

600

550

500

450

400

Max.

Typ.

M in.

Max.

Typ.

Min.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 42: t_FLTvs. temperature

Figure 43: t_ENvs. temperature

250

200

150

100

50

100

75

50

25

0

Max.

Typ.

Min.

Max.

Typ.

Min.

-50

-25

0

25

50

75

-50

-25

0

25

50

75

Temperature (^oC)

Figure 44: Tr vs. temperature

Figure 45: Tf vs. temperature

80

60

40

20

0

16

12

8

Max.

Typ.

Min.

Typ.

Min.

4

0

-50

-25

0

25

50

75

-50

-25

0

25

50

75

Temperature (^oC)

Figure 46: PM vs. temperature

Figure 47: I_ITRIP+vs. temperature

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31

AUIRS2336S

4

3

2

1

0

100

80

60

40

20

Max.

Typ.

Max.

Typ.

Min.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 48: I_QCCvs. temperature

Figure 49: I_QBSvs. temperature

-0.05

-0.10

-0.15

-0.20

-0.25

0.50

0.40

0.30

0.20

0.10

Max

Typ.

Min.

Max

Typ.

Min.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 50: I_O+vs. temperature

Figure 51: I_O-vs. temperature

10.0

9.5

9.0

8.5

8.0

9.0

8.5

8.0

7.5

7.0

Max

Max.

Typ.

Min.

Typ.

Min.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 52: V_CCUV+vs. temperature

Figure 53: V_CCUV-vs. temperature

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32

AUIRS2336S

9.0

8.5

8.0

7.5

7.0

10.0

9.5

9.0

8.5

8.0

M ax.

Typ.

M in.

Typ.

M in.

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 54: V_BSUV+vs. temperature

Figure 55: V_BSUV-vs. temperature

500

450

400

350

300

600

550

500

450

400

Max

Max.

Typ.

Min.

Typ.

Min.

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 56: V_IT,TH+vs. temperature

Figure 57: V_IT,TH-vs. temperature

100

80

60

40

20

0

60

50

40

30

20

Max.

Typ.

Max.

Typ.

Min.

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

125

Temperature (^oC)

Figure 58: R_ON,RCINvs. temperature

Figure 59: R_ON,FLTvs. temperature

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33

AUIRS2336S

Package Details: SOIC28W

www.irf.com

34

AUIRS2336S

Package Details: Tape and Reel SOW28

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 28SOICW

Metric

Imperial

Code

A

B

C

D

E

F

G

H

Min

11.90

3.90

23.70

11.40

10.80

18.20

1.50

Max

12.10

4.10

24.30

11.60

11.00

18.40

n/a

Min

Max

0.476

0.161

0.956

0.456

0.433

0.724

n/a

0.468

0.153

0.933

0.448

0.425

0.716

0.059

1.50

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 28SOICW

Metric

Imperial

Min

Code

A

B

C

D

Min

329.60

20.95

12.80

1.95

Max

330.25

21.45

13.20

2.45

102.00

30.40

29.10

26.40

Max

13.001

0.844

0.519

0.096

4.015

1.196

1.145

1.039

12.976

0.824

0.503

0.767

3.858

n/a

E

F

98.00

n/a

G

H

26.50

24.40

1.04

0.96

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35

AUIRS2336S

Part Marking Information

Part number

Date code

AUIRS2336S

AYWW ?

IR logo

Pin 1

Identifier

? XXXX

Lot Code

(Prod mode –

4 digit SPN code)

?

MARKING CODE

P

Lead Free Released

Non-Lead Free Released

Assembly site code

Per SCOP 200-002

Ordering Information

Standard Pack

Package Type

Complete Part Number

Form

Quantity

Base Part Number

Tube/Bulk

25

AUIRS2336S

SOIC28W

Tape and Reel

1000

AUIRS2336STR

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36

AUIRS2336S

IMPORTANT NOTICE

Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR)

reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its

products and services at any time and to discontinue any product or services without notice. Part numbers

designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards to

product discontinuance and process change notification. All products are sold subject to IR’s terms and conditions of

sale supplied at the time of order acknowledgment.

IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance

with IR’s standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary

to support this warranty. Except where mandated by government requirements, testing of all parameters of each

product is not necessarily performed.

IR assumes no liability for applications assistance or customer product design. Customers are responsible for their

products and applications using IR components. To minimize the risks with customer products and applications,

customers should provide adequate design and operating safeguards.

Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this

information with alterations is an unfair and deceptive business practice. IR is not responsible or liable for such

altered documentation. Information of third parties may be subject to additional restrictions.

Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that

product or service voids all express and any implied warranties for the associated IR product or service and is an

unfair and deceptive business practice. IR is not responsible or liable for any such statements.

IR products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or in other applications intended to support or sustain life, or in any other application in which

the failure of the IR product could create a situation where personal injury or death may occur. Should Buyer

purchase or use IR products for any such unintended or unauthorized application, Buyer shall indemnify and hold

International Rectifier and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,

costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that IR was

negligent regarding the design or manufacture of the product.

IR products are neither designed nor intended for use in military/aerospace applications or environments unless the

IR products are specifically designated by IR as military-grade or “enhanced plastic.” Only products designated by

IR as military-grade meet military specifications. Buyers acknowledge and agree that any such use of IR products

which IR has not designated as military-grade is solely at the Buyer’s risk, and that they are solely responsible for

compliance with all legal and regulatory requirements in connection with such use.

IR products are neither designed nor intended for use in automotive applications or environments unless the specific

IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including

the designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in automotive

applications, IR will not be responsible for any failure to meet such requirements.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

www.irf.com

37


型号：	AUIRS2336STR
厂家：	Infineon
描述：	3-PHASE BRIDGE DRIVER IC 3相桥式驱动器IC 驱动器接口集成电路光电二极管
文件：	总37页 (文件大小：665K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AUIRS2336STR [INFINEON]

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