BGAU1A10 [INFINEON]
LTE / 3G LNAs;
| 型号： | BGAU1A10 |
| 厂家： | 
Infineon |
| 描述： | LTE / 3G LNAs LTE |
| 文件： | 总16页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BGAU1A10
BGAU1A10
Low Noise Amplifier with Gain Control
Features
• Operating frequencies: 5.15 - 5.925 GHz
• Insertion power gain: 20.5 dB
• Gain dynamic range: 27 dB
• Low noise figure: 1.6 dB
• Low current consumption: 5.0 mA
• Multi-state control: Gain- and Bypass-Modes
• Small ATSLP leadless package
1.1x1.5mm2
Application
The LTE data rate can be significantly improved by using the high gain LNA. The integrated gain control and
bypass function increases the overall system dynamic range and leads to more flexibility in the front-end. In
high gain mode the BGAU1A10 oꢀers best Noise Figure to ensure high data rates even on the LTE cell edge.
Closer to the basestation the bypass mode can be activated reducing current consumption. Thanks to the
MIPI control interface, control lines are reduced to a minimum.
Product Validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Block diagram
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Data Sheet
www.infineon.com
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Table of Contents
Table of Contents
Table of Contents
1
2
1
Maximum Ratings
2
3
4
5
6
DC Characteristics
3
RF Characteristics
3
MIPI RFFE Specification
Application Information
Package Information
6
10
12
Data Sheet
1
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Maximum Ratings
1 Maximum Ratings
Table 1: Maximum Ratings
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
-0.3
-1
Typ.
Max.
2.5
1
Supply Voltage VDD
Voltage at RFin
VDD
VRFI
VRFO
IDD
–
–
–
–
–
–
–
–
–
–
–
–
V
1
V
–
–
–
–
Voltage at RFout
-1
1
V
Current into pin VDD
RF input power
-30
–
–
mA
dBm
mW
◦C
◦C
◦C
V
PIN
25
Total power dissipation
Junction temperature
Ambient temperature range
Storage temperature range
ESD capability, HBM
RFFE Supply Voltage
Ptot
TJ
–
90
–
150
–
–
TA
-30
-55
-1000
-0.5
-0.7
85
TSTG
VESD_HBM
VIO
150
–
2
1000
2.7
V
–
–
VSCLK
,
VIO + 0.7
(max. 2.7)
V
RFFE Supply Voltage Levels
VSDATA
1All voltages refer to GND-Nodes unless otherwise noted
2Human Body Model ANSI/ESDA/JEDEC JS-001-2014 (R = 1.5 kΩ, C = 100 pF).
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Ex-
posure to conditions at or below absolute maximum rating but above the specified maximum operation conditions
may aꢀect device reliability and life time. Functionality of the device might not be given under these conditions.
Data Sheet
2
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
RF Characteristics
2 DC Characteristics
Table 3: DC Characteristics at TA = 25 ◦C
Parameter 1
Symbol
Values
Unit
Note / Test Condition
Min.
1.7
Typ.
1.8
5.0
0.1
1.8
–
Max.
1.9
Supply Voltage
Supply Current
VDD
IDD
V
–
3.0
–
7.0
mA
mA
V
G0-G3
G4
0.15
1.95
VIO
RFFE supply voltage
VIO
VIH
VIL
1.65
–
RFFE input high voltage2
RFFE input low voltage2
RFFE output high voltage3
RFFE output low voltage3
0.7 * VIO
V
–
0
–
0.3 * VIO
VIO
V
–
VOH
VOL
0.8 * VIO
–
V
–
0
–
–
0.2 * VIO
2
V
–
RFFE control input capacitance CCtrl
RFFE supply current IVIO
–
pF
µA
–
–
3
–
Idle State
1Based on the application described in Chapter 5
2SCLK and SDATA
3SDATA
3 RF Characteristics
Table 4: RF Characteristics in ON Mode at TA = 25 ◦C, VDD = 1.8 V, IVDD = 5.0 mA, f = 5.15– 5.925 GHz
Parameter
Symbol
Values
Typ.
20.5
17.5
9.0
-0.3
-3.0
-6.5
1.7
1.7
1.6
9.9
6.5
Unit
Note / Test Condition
Min.
18.5
15.5
7.0
-2.3
-5.0
-8.0
–
–
–
–
–
Max.
22.5
19.5
11.0
1.7
-1.0
-5.0
2.2
2.2
2.1
10.9
8.0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
G0
G1
G2
G3
Insertion power gain
f = 5500 MHz
2
1/|S21|
G3 in Bias0 mode
G4
G0
G1
G2
G3
G4
Noise figure
f = 5500 MHz
NF
Continued on next page
Data Sheet
3
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
RF Characteristics
Table 4: RF Characteristics – Continued from previous page
Parameter
Symbol
Values
Typ.
7
Unit
Note / Test Condition
Min.
4
Max.
–
dB
G0
4
10
4
7
20
8
–
–
–
dB
dB
dB
G1
G2
G3
Input Return Loss1
f = 5500 MHz
RLin
6
10
–
dB
G4
10
10
4
18
18
7
7
–
–
–
–
dB
dB
dB
dB
G0
G1
G2
G3
Output Return Loss
f = 5500 MHz
RLout
4
7
12
–
dB
G4
28
33
24
33
5
33
38
29
38
6.5
-18
-17
-6
–
–
–
–
dB
dB
dB
dB
G0
G1
G2
G3
Reverse Isolation
f = 5500 MHz
2
1/|S12|
–
dB
G4
-22
-21
-10
-1
–
–
–
–
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
G0
G1
G2
G3
Inband input 1dB-compression
point
f = 5500 MHz
IP1dB
+3
-8
-8
-13
-13
-7
+1
+25
-12
–
–
–
–
G0
G1
G2
G3
Inband input 3rd-order intercept
point2
IIP3
-2
+6
+30
–
–
dBm
◦
G4
Phase discontinuity between all
Gain Mode combinations
f = 5500 MHz
12
Part to part variation aꢁer com-
pensation in Base Band with
constant value
Stability
k
> 1
–
–
–
f = 20 MHz - 10 GHz
50 % last SCLK falling edge to
90 % ON, see Fig. 2
MIPI to RF time
tINT
1.5
2
µs
µs
Power Up Settling Time
tBC
–
10
25
Aꢁer power down mode
1For broadband matching, can be improved by using narrowband matching
2Input power = −30 dBm for each tone for modes G0-G3 / −15 dBm for mode G4, f = 5500 MHz, f = f + 1 MHz
1
2
1
Data Sheet
4
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
RF Characteristics
SDATA
TINT
SCLK
90%
RF Signal
Figure 1: MIPI to RF Time
VBAT
VIO
SDATA
SCLK
a)
T
PUP
VBAT
VIO
SDATA
SCLK
b)
T
PUP
Figure 2: Power-Up Settling Time Definition: a) when the device is already in Active Mode. b) when changing from Low Power
Mode to Active Mode.
Aꢁer Power-Up of VIO the device is set to Low Power Mode. An additional MIPI instruction is necessary to set the
device to Active Mode. This case is covered by b).
Data Sheet
5
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
MIPI RFFE Specification
4 MIPI RFFE Specification
All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’ document
version 2.0 - 25. September 2014.
Table 5: MIPI Features
Feature
Supported
Comment
MIPI RFFE 2.0 standard
Yes
Yes
Yes
Register 0 write command sequence
Register read and write command sequence
Extended register read and write command se- Yes
quence
Support for standard frequency range operations Yes
for SCLK
Up to 26 MHz for read and write
Up to 52 MHz for write
Support for extended frequency range operations Yes
for SCLK
Half speed read
Yes
Yes
Yes
Yes
Yes
Full speed read
Full speed write
Programmable Group SID
Programmable USID
Support for three registers write and extended write se-
quences
Trigger functionality
Broadcast / GSID write to PM TRIG register
Reset
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Via VIO, PM TRIG or soꢁware register
Status / error sum register
Extended product ID register
Revision ID register
Group SID register
USID_Sel pin
External pin for changing USID:
USID 12=00 → 1000,
USID 12=10 → 1001,
USID 12=01 → 1010,
USID 12=11 → 1011
USID selection via SDATA / SCLK swap feature
No
Table 6: Startup Behavior
Feature
State
Comment
Power status
Trigger function
Low power
Enabled
Lower power mode aꢁer start-up
Enabled aꢁer start-up. Programmable via behavior control register
Data Sheet
6
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
MIPI RFFE Specification
Table 7: Register Mapping, Table I
Register
Address
Register Name
Data Function
Bits
Description
Default
Broadcast_ID
Support
Trigger
Support
R/W
0x00
0x1C
REGISTER_0
PM_TRIG
7:0
7
MODE_CTRL
LNA control
00000000
1
No
Yes
No
R/W
R/W
PWR_MODE(1), Operation Mode
0: Normal operation (ACTIVE)
1: Low Power Mode (LOW POWER)
0: No action (ACTIVE)
Yes
6
5
4
3
PWR_MODE(0), State Bit Vector
TRIGGER_MASK_2
0
0
0
0
1: Powered Reset (STARTUP to ACTIVE
to LOW POWER)
0: Data masked (held in shadow REG)
No
1: Data not masked (ready for transfer
to active REG)
TRIGGER_MASK_1
0: Data masked (held in shadow REG)
1: Data not masked (ready for transfer
to active REG)
TRIGGER_MASK_0
0: Data masked (held in shadow REG)
1: Data not masked (ready for transfer
to active REG)
2
1
TRIGGER_2
TRIGGER_1
TRIGGER_0
PRODUCT_ID
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
Yes
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
0
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
0x1D
0x1E
0x1F
PRODUCT_ID
MAN_ID
7:0
This is a read-only register. However,
during the programming of the USID a
write command sequence is performed
on this register, even though the write
does not change its value.
00001110
No
No
No
No
No
No
R
R
R
7:0
MANUFACTURER_ID [7:0]
This is a read-only register. However,
during the programming of the USID, a
write command sequence is performed
on this register, even though the write
does not change its value.
00011010
MAN_USID
7:6
5:4
RESERVED
Reserved for future use
00
01
MANUFACTURER_ID [9:8]
These bits are read-only. However, dur-
ing the programming of the USID, a
write command sequence is performed
on this register even though the write
does not change its value.
3:0
USID[3:0]
Programmable USID. Performing
a
SeeTab.5
No
No
R/W
write to this register using the de-
scribed programming sequences will
program the USID in devices support-
ing this feature. These bits store the
USID of the device.
Data Sheet
7
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
MIPI RFFE Specification
Table 8: Register Mapping, Table II
Register
Address
Register Name
Data Function
Bits
Description
Default
Broadcast_ID
Support
Trigger
Support
R/W
0x20
0x21
EXT_PRODUCT_ID 7:0
EXT_PRODUCT_ID
MAIN_REVISION
SUB_REVISION
GSID0[3:0]
00000000
0001
No
No
No
No
R
REV_ID
7:4
3:0
7:4
3:0
7
R/W
0000
0000
0000
0
0x22
0x23
GSID
Primary Group Slave ID.
No
No
No
No
R/W
R/W
RESERVED
Reserved for secondary Group Slave ID.
UDR_RST
UDR_RST
Reset all configurable non-RFFE Re-
served registers to default values.
0: Normal operation
1: Soꢁware reset
6:0
7
RESERVED
Reserved for future use
Reserved for future use
0000000
0x24
ERR_SUM
RESERVED
0
0
No
No
R
6
COMMAND_FRAME_PARITY_ERR
Command Sequence received with par-
ity error − discard command.
Command length error.
5
4
3
2
1
COMMAND_LENGTH_ERR
ADDRESS_FRAME_PARITY_ERR
DATA_FRAME_PARITY_ERR
READ_UNUSED_REG
0
0
0
0
0
0
Address frame with parity error.
Data frame with parity error.
Read command to an invalid address.
Write command to an invalid address.
WRITE_UNUSED_REG
BID_GID_ERR
0
Read command with a BROADCAST_ID
or GROUP_ID.
0x78
DFT
7:0
DESIGN_FOR_TEST
Do not use.
–
–
–
–
Data Sheet
8
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
MIPI RFFE Specification
Table 9: Gain Modes of Operation (Truth Table, Register_0)
REGISTER_0 Bits
State
1
Mode
Gain G0
D6
1
D5
0
0
1
D4
0
1
D3
1
D2
x
D1
x
D0
x
2
3
4
5
Gain G1
1
1
x
x
x
Gain G2
1
0
1
1
x
x
x
Gain G3
1
1
0
1
x
x
x
Gain G4 (Bypass)
0
1
1
x
x
x
Table 10: Bias settings (Truth Table, Register_0)
REGISTER_0 Bits
State
9
Mode
D6
1
D5
x
D4
x
D3
x
D2
0
0
0
0
1
D1
0
0
1
D0
0
1
Bias0 (3.0 mA)
Bias1 (3.5 mA)
Bias2 (4.0 mA)
Bias3 (4.5 mA)
Bias4 (5.0 mA)1
Bias5 (5.5 mA)
Bias6 (6.0 mA)
Bias7 (6.5 mA)
10
11
1
x
x
x
1
x
x
x
0
1
12
1
x
x
x
1
13
1
x
x
x
0
0
1
0
1
14
1
x
x
x
1
15
1
x
x
x
1
0
1
16
1
x
x
x
1
1
1Target bias mode for Gain modes G0-G3
Data Sheet
9
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Application Information
5 Application Information
Pin Configuration and Function
ꢈ
ꢇ
ꢆ
ꢅ
ꢄ
ꢃ
ꢀꢉ
ꢀ
ꢁ
ꢂ
Figure 3: BGAU1A10 Pin Configuration (top view)
Table 11: Pin Definition and Function
Pin No.
1
Name
VDD
Function
Power supply
RF input port
USID select pin 1
MIPI RFFE supply
MIPI RFFE clock
MIPI RFFE data
Ground
2
3
4
5
6
7
8
9
10
RFin
USID1
VIO
SCLK
SDATA
GND
RFout
USID2
GND
RF output port
USID select pin 2
Ground
1 Leave unconnected if not used (do NOT connect to GND)
Data Sheet
10
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Application Information
Application Board Configuration
S
L1
S
RFin
RFout
C1
LNA
SDATA
SCLK
USID1
USID2
VDD
MIPI-RFFE
Control Interface
C2
VIO
C3
(optional)
Figure 4: BGAU1A10 Application Schematic
Table 12: Bill of Materials Table
Name
C1
Value
0.6 pF
10 nF
Package
0201
Manufacturer
muRata GJM type
Various
Function
Input matching1
RF bypass2
C2
0201
C3 (optional)
10 nF
0201
Various
RF bypass2
Input matching1
L1
0.8 nH
BGAU1A10
0201
muRata LQP type
Infineon
N1
ATSLP-10-3
Variable gainstep LNA
1The matching elements must be optimized with reference to the frequency band of interest.
2RF bypass recommended to mitigate power supply noise.
Data Sheet
11
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Package Information
6 Package Information
1.1±0.05
A
0.2±0.05
10x
0.1 A
5
6
4
3
2
1
7
8
9
10
0.4
0.6±0.05
INDEX MARKING
(LASERED)
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 5: ATSLP-10-3 Package Outline (top, side and bottom views)
TYPE CODE
DATE CODE
(YW)
PIN1 MARKING
(LASERED)
Figure 6: Marking Specification (top view)
Product Name
BGAU1A10
Marking
U1
Package
ATSLP-10-3
Data Sheet
12
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Package Information
Table 13: Year date code marking - digit "Y"
Year
"Y"
0
1
2
3
4
5
6
7
8
9
Year
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
"Y"
0
1
2
3
4
5
6
7
8
9
Year
"Y"
0
1
2
3
4
5
6
7
8
9
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
Table 14: Week date code marking - digit "W"
Week
"W"
A
B
C
D
E
Week
12
13
14
15
16
17
18
19
"W"
N
P
Q
R
S
T
U
V
W
Y
Week
23
24
25
26
27
28
29
30
31
32
33
"W"
4
5
6
7
a
b
c
d
e
f
Week
34
35
36
37
38
39
40
41
42
43
"W"
h
j
k
l
n
p
q
r
Week
45
46
47
48
49
50
51
"W"
v
x
y
z
8
9
2
3
1
2
3
4
5
6
7
8
9
10
11
F
G
H
J
K
L
52
53
20
21
22
s
t
u
M
Z
g
44
Data Sheet
13
Revision 3.0
2018-04-18
BGAU1A10
Low Noise Amplifier with Gain Control
Package Information
Optional solder mask dam
0.25
0.25
0.4
0.4
copper
solder mask
stencil apertures
ALL DIMENSIONS ARE IN UNITS MM
Figure 7: Footprint Recommendation
4
PIN 1
4
0.75
INDEX MARKING
1.3
ALL DIMENSIONS ARE IN UNITS MM
THE DRAWING IS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [
]
Figure 8: Carrier Tape
Data Sheet
14
Revision 3.0
2018-04-18
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 3.0, 2018-04-18
all
2
"Preliminary" removed
Maximum current into pin VDD updated
Maximum RF input power updated
Maximum total power dissipation updated
Footnotes updated in Table 11 (Bias settings)
Package outline drawing updated
Marking specification drawing updated
Date code marking tables added
2
2
9
12
12
13
14
14
15
Footprint recommendation drawing added
Carrier tape drawing added
Trademarks updated
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
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Published by
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81726 Munich, Germany
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the intended application and the completeness of the
product information given in this document with re-
spect to such application.
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