BGSA400ML10 [INFINEON]
天线相关器件;
| 型号： | BGSA400ML10 |
| 厂家： | 
Infineon |
| 描述： | 天线相关器件 |
| 文件： | 总24页 (文件大小：668K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R E S T R I C T E D
BGSA400ML10
Ultra high RF voltage antenna tuning switch
Features
• Low RON resistance of 2.0 Ω at each port in ON state
• Low COFF capacitance of 165 fF at each port in OFF state
• High RF operating peak voltage handling of typical 90 V in OFF state
• Low harmonic generation
• MIPI RFFE 2.1 control interface
• Extremely low current consumption of 22 µA
• 4 default USID addresses via external USID_SEL pin
• Small form factor 1.1 mm x 1.5 mm (MSL1, 260 °C per JEDEC J-STD-020)
Potential applications
• Impedance, antenna and inductance tuning
• Tunable filters
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Description
The BGSA400ML10 is a versatile shunt to ground 4xsingle-pole single-throw (4xSPST) RF antenna tuning switch. It is optimized
for low COFF as well as low RON enabling applications up to 7.125 GHz.
The BGSA400ML10 is ideal for antenna tuning application. This chip integrates on-chip CMOS logic and power supply
regulation. Its digital control interface is compliant with MIPI2.1 RFFE specification and each switch throw can be programmed
individually or all together in the same RFFE command frame. Up to 4 instantiations of the same device can be controlled
using the same RFFE bus thanks to its 4 states USID_SEL pin unique feature.
Block diagram
RF1 RF2 RF3 RF4
Voltage
regulator
VIO
SDATA
SCLK
MIPI
RFFE
Drivers
USID_SEL
Chargepump
GND
Type
Marking
Package
Ordering information
BGSA400ML10
4T
TSLP-10-3
BGSA 400ML10 E6327
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Revision 2.1
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Table of contents
Table of contents
1
2
3
4
5
6
7
Maximum ratings
2
4
DC characteristics
RF small signal characteristics
RF large signal characteristics
MIPI RFFE specification
Application information
Package information
5
7
9
17
19
Datasheet
1
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Maximum ratings
1 Maximum ratings
Table 1: Maximum ratings table at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Note / Test condition
Min.
0.4
-0.3
Typ.
–
–
Max.
7.125
2.2
1)
Frequency range
RFFE supply voltage 2)
f
VIO
GHz
V
Only for infrequent and short
duration time periods
–
Storage temperature range
RF peak voltage
TSTG
VRF_max
-55
–
–
–
150
90
°C
V
Short term peaks (1
duty cycle), exceeding typical
linearity, ON and COFF param-
µs in 0.1%
R
eters, in isolation mode, test
condition schematic in Fig. 1
ESD robustness, CDM 3)
ESD robustness, HBM 4)
Junction temperature
Thermal resistance junction - soldering point RthJS
Maximum DC-voltage on RF-Ports and RF- VRFDC
Ground
VESD
VESD
Tj
-1
-2
–
–
0
–
–
–
–
–
+1
+2
125
50
0
kV
kV
°C
K/W
V
CDM
HBM
–
–
No DC voltage allowed on RF-
Ports
–
RFFE control voltage levels
VSCLK
VSDATA
VUSID_SEL
,
-0.7
–
VIO+0.7
(max.
2.2)
V
,
1) Switch has a low-pass response. For higher frequencies, losses have to be considered for their impact on thermal heating. The DC voltage at RF ports VRFDC has
to be 0 V.
2) Note: Consider any ripple voltages on top of VIO. A high RF ripple at the VIO can exceed the maximum ratings by VIO = VDC + VRipple
.
3) Field-Induced Charged-Device Model ANSI/ESDA/JEDEC JS-002. Simulates charging/discharging events that occur in production equipment and processes.
Potential for CDM ESD events occurs whenever there is metal-to-metal contact in manufacturing.
4) Human Body Model ANSI/ESDA/JEDEC JS-001 (R=1.5 kΩ, C=100 pF).
Warning: Stresses above the max. values listed here may cause permanent damage to the device. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Exposure to conditions at or below absolute maximum rating but above the specified maximum operation conditions
may affect device reliability and life time. Functionality of the device might not be given under these conditions.
Datasheet
2
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Maximum ratings
Spectrum
analyzer
(Hx monitor)
50 Ohm
50 Ohm transmission line
Signal
source
Power
meter
Feed in - RFx ports (RF1 in this example)
RF1
RF2 RF3 RF4
Voltage
regulator
VIO
SDATA
SCLK
MIPI
RFFE
Driver
USID_SEL
Chargepump
GND
Figure 1: RF operating voltage and harmonic distortion measurement configuration
Datasheet
3
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
DC characteristics
2 DC characteristics
Table 2: DC characteristics at TA = −40 °C to 85 °C
Parameter
Symbol
Values
Unit
Note / Test condition
Min.
1.65
0.7*VIO
Typ.
1.8
–
Max.
1.95
VIO
RFFE supply voltage
VIO
VIH
VIL
VOH
VOL
V
V
V
V
V
pF
µA
–
–
–
–
–
–
RFFE input high voltage1
RFFE input low voltage1
RFFE output high voltage1
RFFE output low voltage1
0
–
–
–
–
0.3*VIO
VIO
0.2*VIO
2
0.8*VIO
0
–
–
RFFE control input capacitance CCtrl
22
40
ACTIVE mode,
≤ 35 dBm RF power
SECONDARY_ACTIVE mode
(LOW POWER) with analog
circuitry powered OFF
RFFE supply current 2
IVIO
–
–
2
8
µA
µA
0.5 3
1 3
1SCLK and SDATA
2No traffic on MIPI bus
3Supply current reduced aꢀer first MIPI RFFE command
Datasheet
4
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
RF small signal characteristics
3 RF small signal characteristics
Table 3: Parametric specifications for each SPST
Parameter
Symbol
Values
Typ.
2.0
Unit
Ω
State / Notes
Min.
–
Max.
2.2
RF1, RF2, RF3 or RF4 to GND
DC ON resistance
RF1, RF2, RF3 or RF4 to GND
OFF capacitance, 1 GHz
RF1, RF2, RF3 or RF4 to GND
DC OFF resistance
RON
SPST
VIO = 1.65 - 1.95 V,
TA = 25 °C,
Z0 = 50 Ω
COFF
–
165
260
180
–
fF
SPST
ROFF
170
kΩ
SPST
Datasheet
5
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
RF small signal characteristics
Table 4: RF electrical parameters
Isolation between adjacent RF ports (All OFF / Isolation mode) 1)
Frequency range
Symbol
Values
Typ.
37
33
31
29
27
24
23
Unit
State / Notes
Min.
30
28
26
23
21
19
17
15
15
Max.
600 - 960 MHz
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
dB
dB
dB
dB
1160 - 1300 MHz
1400 - 1700 MHz
1700 - 2200 MHz
2200 - 2700 MHz
3300 - 4200 MHz
4400 - 5000 MHz
5150 - 5925 MHz
5950 - 7125 MHz
State 0,
VIO = 1.65 − 1.95 V, Z0 = 50 Ω,
TA = −40 °C... + 85 °C
ISO
22
22
Isolation between non-adjacent RF ports (All OFF / Isolation mode) 1)
600 - 960 MHz
50
47
46
45
43
40
35
35
35
60
56
55
53
51
48
48
47
49
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
dB
dB
dB
dB
1160 - 1300 MHz
1400 - 1700 MHz
1700 - 2200 MHz
2200 - 2700 MHz
3300 - 4200 MHz
4400 - 5000 MHz
5150 - 5925 MHz
5950 - 7125 MHz
State 0,
VIO = 1.65 − 1.95 V, Z0 = 50 Ω,
TA = −40 °C... + 85 °C
ISO
Isolation between adjacent RF ports (RFx ON mode) 1)
600 - 960 MHz
30
28
25
23
21
19
17
15
15
47
42
39
36
33
28
26
24
22
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
dB
dB
dB
dB
1160 - 1300 MHz
1400 - 1700 MHz
1700 - 2200 MHz
2200 - 2700 MHz
3300 - 4200 MHz
4400 - 5000 MHz
5150 - 5925 MHz
5950 - 7125 MHz
State 1, 2, 4, 8,
VIO = 1.65 − 1.95 V, Z0 = 50 Ω,
TA = −40 °C... + 85 °C
ISO
Isolation between non-adjacent RF ports (RFx ON mode) 1)
600 - 960 MHz
50
48
46
45
43
35
33
30
28
67
61
58
56
53
49
47
45
43
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
dB
dB
dB
dB
1160 - 1300 MHz
1400 - 1700 MHz
1700 - 2200 MHz
2200 - 2700 MHz
3300 - 4200 MHz
4400 - 5000 MHz
5150 - 5925 MHz
5950 - 7125 MHz
State 1, 2, 4, 8,
VIO = 1.65 − 1.95 V, Z0 = 50 Ω,
TA = −40 °C... + 85 °C
ISO
1)On application board without any matching components
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
RF large signal characteristics
4 RF large signal characteristics
Table 5: RF large signal specifications at TA = −40 °C... + 85 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
–
Unit
Note / Test condition
Min.
–
Max.
85
RF operating voltage
VRF_opr
V
In isolation mode, 900MHz, Test
condition schematic in Fig. 1,
TA = 25 °C
Harmonic distortion, off mode
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
Second order harmonics
All RF ports
Third order harmonics
All RF ports
PH2
PH3
PH2
PH3
PH2
PH3
PH2
PH3
PH2
PH3
PH2
PH3
PH2
PH3
PHx
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-95
-100
-75
-82
-75
-83
-82
-88
-77
-90
-75
-85
-75
-85
–
-85
-90
-65
-72
-65
-73
-72
-78
-67
-80
-65
-75
-65
-75
-80
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
26 dBm, 50 Ω, f0 = 663 MHz
26 dBm, 50 Ω, f0 = 663 MHz
35 dBm, 50 Ω, f0 = 920 MHz
35 dBm, 50 Ω, f0 = 920 MHz
33 dBm, 50 Ω, f0 = 1910 MHz
33 dBm, 50 Ω, f0 = 1910 MHz
29 dBm, 50 Ω, f0 = 2690 MHz
29 dBm, 50 Ω, f0 = 2690 MHz
29 dBm, 50 Ω, f0 = 3600 MHz
29 dBm, 50 Ω, f0 = 3600 MHz
29 dBm, 50 Ω, f0 = 4400 MHz
29 dBm, 50 Ω, f0 = 4400 MHz
29 dBm, 50 Ω, f0 = 5000 MHz
29 dBm, 50 Ω, f0 = 5000 MHz
29 dBm, 50 Ω
> Third order harmonics
Datasheet
7
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
RF large signal characteristics
Table 6: RF large signal specifications at TA = −40 °C... + 85 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
Unit
Note / Test condition
Min.
Max.
Intermodulation distortion IIP2
IIP2, low
IIP2, high
Intermodulation distortion IIP3
IIP3
IIP2,l
IIP2,h
120
125
135
135
–
–
dBm
dBm
IIP2 conditions in Tab. 7
IIP3 conditions in Tab. 8
IIP3
74
82
–
dBm
Table 7: IIP2 conditions table
Band
In-band frequency
Blocker frequency 1
Blocker power 1
Blocker frequency 2
Blocker power 2
[MHz]
2140
2140
881.5
881.5
2655
2655
[MHz]
1950
1950
836.5
836.5
2535
2535
[dBm]
20
20
20
20
[MHz]
190
4090
45
1718
120
5910
[dBm]
Band 1 low
Band 1 high
Band 5 low
Band 5 high
Band 7 low
Band 7 high
0
0
0
0
0
0
20
20
Table 8: IIP3 conditions table
Band
In-band frequency
Blocker frequency 1
Blocker power 1
Blocker frequency 2
Blocker power 2
[MHz]
2140
881.5
2655
[MHz]
1950
836.5
2535
[dBm]
20
20
[MHz]
1760
791.5
2415
[dBm]
Band 1
Band 5
Band 7
0
0
0
20
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
5 MIPI RFFE specification
The MIPI RFFE interface is implemented according to the following specifications and documents:
- MIPI Alliance Specification for RF Front-End Control Interface Version 2.1 - 18 December 2017
- MIPI Alliance Errata 01 for MIPI RFFE Specification Version v2.1 - 24 February 2019
- Qualcomm RFFE Vendor Specification 80-N7876-1 Rev. Y (December 3, 2018)
Table 9: MIPI features
Feature
MIPI RFFE 2.1 standard
Supported
Yes
Comment
Backward compatible to MIPI 2.0 standard
Register 0 write command sequence
Register read and write command sequence
Extended register read and write command sequence
Masked write command sequence
Support for standard frequency range operations for
SCLK
Yes
Yes
Yes
Yes
Indicated as MW in below register mapping tables
Up to 26 MHz
Yes
Support for extended frequency range operations for
SCLK
Longer reach RFFE bus length feature
Programmable driver strength
Programmable Group SID
Programmable USID
Yes
Up to 52 MHz
Up to 80 pF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Trigger functionality
Extended triggers and trigger masks
Broadcast / GSID write to PM TRIG register
Reset
Status / error sum register
Extended product ID register
Revision ID register
Via VIO, PM TRIG or soꢀware register
Group SID register
USID select pin
See Tab. 16
Table 10: Startup behavior
Feature
State
Comment
Power status
Trigger function
Low power
Enabled
Device in SECONDARY_ACTIVE mode (LOW POWER) aꢀer start-up
Enabled aꢀer start-up. Programmable via behavior control register
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Table 11: Device control timing at VIO = 1.65 − 1.95 V, TA = 25 °C, PIN = 0 dBm
Parameter
Symbol
Values
Typ.
–
Unit
State / Notes
Min.
Max.
ON switching time
tST,ON
–
20
µs
50% last SCLK rising edge of the reg-
ister write command to 10% of RF
amplitude, see Fig. 2
OFF switching time
tST,OFF
–
–
5
µs
50% last SCLK rising edge of the reg-
ister write command to 90% of RF
amplitude, see Fig. 2
VIO
1)
>120ns
tST,ON
tST,OFF
SCLK
SDATA
Analog ON
command
50%
50%
Switch ON
command
Switch OFF
command
1)
timing starts @ VIO > VIOmin and ends @ SDATA /SCLK < VILmax (0.3 x VIO
)
10%
RF path
90%
RF path
Figure 2: BGSA400ML10 switching time behavior
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Table 12: Register mapping, table I
Register
address
Register name
Data Function
bits
Description
Default
Broadcast_ID
support
Trigger
support
R/W
0x00
0x01
0x1C
REGISTER_0
7:0
7:0
7
MODE_CTRL
RF switch control
00000000
No
No
Yes
Yes
Trigger 0-10
Yes
R/W
MW
R/W
MW
R/W
MW
REGISTER_1
PM_TRIG
MODE_CTRL
RF Switch Control
00000000
1
Trigger 0-10
No
PWR_MODE(1)
0: Normal operation (ACTIVE)
Operation mode
1: Low power mode
(SECONDARY_ACTIVE)
6
5
PWR_MODE(0)
State bit vector
TRIGGER_MASK_2
0: No action (ACTIVE)
0
0
1: Powered reset (ACTIVE to STARTUP)
0: Data masked (held in shadow REG)
No
1: Data not masked (ready for transfer to
active REG)
4
3
TRIGGER_MASK_1
TRIGGER_MASK_0
0: Data masked (held in shadow REG)
0
0
1: Data not masked (ready for transfer to
active REG)
0: Data masked (held in shadow REG)
1: Data not masked (ready for transfer to
active REG)
2
1
TRIGGER_2
TRIGGER_1
TRIGGER_0
PRODUCT_ID
0: No action (data held in shadow REG)
1: Data transferred to active REG
0: No action (data held in shadow REG)
1: Data transferred to active REG
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
Yes
0
0
0
0x1D
0x1E
0x1F
PRODUCT_ID
MAN_ID
7:0
This is a read-only register. However,
during the programming of the USID a
write command sequence is performed
on this register, even though the write
does not change its value.
11111100
No
No
No
No
R
R
7:0
7:4
3:0
MANUFACTURER_ID [7:0]
MANUFACTURER_ID [11:8]
USID[3:0]
This is a read-only register. However,
during the programming of the USID, a
write command sequence is performed
on this register, even though the write
does not change its value.
00011010
0001
MAN_USID
These bits are read-only. However, dur-
ingtheprogrammingoftheUSID, awrite
command sequence is performed on
this register even though the write does
not change its value.
USID_Sel pin
See
No
No
R/W
Tab. 16
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Table 13: Register mapping, table II
Register
address
Register name
Data Function
bits
Description
Default
Broadcast_ID
support
Trigger
support
R/W
0x20
EXT_PRODUCT_ID 7:0
EXT_PRODUCT_ID
Extension to PRODUCT_ID in register
0x1D. This is a read-only register. How-
ever, during the programming of the
USID a write command sequence is per-
formed on this register, even though the
write does not change its value.
00000000
No
No
R
0x21
0x22
0x23
REV_ID
GSID
7:4
3:0
7:4
3:0
7
MAIN_REVISION
SUB_REVISION
GSID0[3:0]
Chip main revision
0000
0000
0000
0000
0
No
No
Yes
No
No
No
R
Chip sub revision
Primary group slave ID.
Secondary group slave ID.
R/W
R/W
GSID1[3:0]
UDR_RST
UDR_RST
Reset all configurable non-RFFE Re-
served registers to default values.
0: Normal operation
1: Soꢀware reset
6:0
7
RESERVED
Reserved for future use
Reserved for future use
0000000
0x24
ERR_SUM
RESERVED
0
0
No
No
R
6
COMMAND_FRAME_PARITY_ERR
Command sSequence received with par-
ity error − discard command.
Command length error.
5
4
3
2
1
0
COMMAND_LENGTH_ERR
ADDRESS_FRAME_PARITY_ERR
DATA_FRAME_PARITY_ERR
READ_UNUSED_REG
0
0
0
0
0
0
Address frame with parity error.
Data frame with parity error.
Read command to an invalid address.
Write command to an invalid address.
WRITE_UNUSED_REG
BID_GID_ERR
Read command with a BROADCAST_ID
or GROUP_ID.
0x2B
BUS_LD
7:3
2:0
RESERVED
Reserved for future use
0x0
0x4
No
No
R/W
BUS_LD[2:0]
Program the drive strength of the SDATA
driver in readback modes.
0x0: 10 pF
0x1: 20 pF
0x2: 30 pF
0x3: 40 pF
0x4: 50 pF
0x5: 60 pF
0x6: 80 pF
0x7: 80 pF
0x8-0xF: reserved
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Table 14: Register mapping, table III
Register
address
Register name
Data Function
bits
Description
Default
Broadcast_ID
support
Trigger
support
R/W
0x2D
EXT_TRIG_MASK
7
6
5
4
3
2
1
0
TRIGGER_MASK_10
0: Data writes to registers tied to
EXT_TRIGGER_10 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_10 bit is set to 1.
1
No
No
R/W
1: Data writes to registers tied to
EXT_TRIGGER_10 are not masked. Data
writes go directly to the active registers.
MW
TRIGGER_MASK_9
TRIGGER_MASK_8
TRIGGER_MASK_7
TRIGGER_MASK_6
TRIGGER_MASK_5
TRIGGER_MASK_4
TRIGGER_MASK_3
0: Data writes to registers tied to
EXT_TRIGGER_9 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_9 bit is set to 1.
1
1
1
1
1
1
1
1: Data writes to registers tied to
EXT_TRIGGER_9 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_8 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_8 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_8 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_7 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_7 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_7 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_6 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_6 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_6 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_5 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_5 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_5 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_4 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_4 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_4 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_3 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_3 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_3 are not masked. Data
writes go directly to the active registers.
Datasheet
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Table 15: Register mapping, table IV
Register
address
Register name
Data Function
bits
Description
Default
Broadcast_ID
support
Trigger
support
R/W
R/W
MW
0x2E
EXT_TRIG
7
6
5
4
3
2
1
0
TRIGGER_10
TRIGGER_9
TRIGGER_8
TRIGGER_7
TRIGGER_6
TRIGGER_5
TRIGGER_4
TRIGGER_3
0: No action. Data is held in shadow reg-
isters.
0
Yes
No
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_10
0: No action. Data is held in shadow reg-
isters.
0
0
0
0
0
0
0
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_9
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_8
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_7
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_6
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_5
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_4
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_3
Datasheet
14
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Table 16: Default MIPI USID selection
Address
Symbol
Addr6
Addr7
Addr8
Addr9
External conditon at USID_SEL Pin
Ground
USID=0110
USID=0111
USID=1000
USID=1001
to VIO
Floating1)
220 kΩ to VIO1)
1) Total capacitance on the USID_SEL pin must be <5 pF.
Addr6=0110
Addr8=1000
Addr7=0111
Addr9=1001
GND
GND
GND
GND
SDATA
1
2
3
4
10
9
8
7
6
RF1
RF2
RF3
RF4
SDATA
1
2
3
4
10
9
8
7
6
RF1
RF2
RF3
RF4
SDATA
1
2
3
4
10
9
8
7
6
RF1
RF2
RF3
RF4
SDATA
1
2
3
4
10
9
8
7
6
RF1
RF2
RF3
RF4
SCLK
SCLK
SCLK
SCLK
USID_SEL
USID_SEL
USID_SEL
USID_SEL
220k
Ohms
VIO
5
5
VIO
5
5
VIO
VIO
GND
GND
GND
GND
Figure 3: BGSA400ML10 USID_Sel pin configuration
Datasheet
15
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
MIPI RFFE specification
Warning: Register_0 and Register_1 RF switch control bits are identical. Writing both registers Register_0 and Register_1 simultane-
ously will lead to undefined behavior. The unused register (Register_0 or Register_1) must remain 0x00.
Table 17: Modes of operation (Truth table, Register_0)
State
0
Mode
ALL OFF (Isolation)
RF1 ON
D7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
RF2 ON
3
4
RF1+RF2 ON
RF3 ON
5
6
7
8
RF1+RF3 ON
RF2+RF3 ON
RF1+RF2+RF3 ON
RF4 ON
9
RF1+RF4 ON
RF2+RF4 ON
RF1+RF2+RF4 ON
RF3+RF4 ON
RF1+RF3+RF4 ON
RF2+RF3+RF4 ON
RF1+RF2+RF3+RF4 ON
10
11
12
13
14
15
1)Do not care, x = 0 or 1
Table 18: Modes of operation (Truth table, Register_1)
State
0
Mode
ALL OFF (Isolation)
RF1 ON
D7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
RF2 ON
3
4
RF1+RF2 ON
RF3 ON
5
6
7
8
RF1+RF3 ON
RF2+RF3 ON
RF1+RF2+RF3 ON
RF4 ON
9
RF1+RF4 ON
RF2+RF4 ON
RF1+RF2+RF4 ON
RF3+RF4 ON
RF1+RF3+RF4 ON
RF2+RF3+RF4 ON
RF1+RF2+RF3+RF4 ON
10
11
12
13
14
15
1)Do not care, x = 0 or 1
Datasheet
16
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2022-01-31
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Application information
6 Application information
Pin configuration and function
GND
10
SDATA
SCLK
1
2
3
4
9
8
7
6
RF1
RF2
RF3
RF4
USID_SEL
VIO
5
GND
Figure 4: BGSA400ML10 pin configuration (top view)
Table 19: Pin definition and function
Pin No.
Name
SDATA
SCLK
USID_SEL
VIO
GND
RF4
RF3
RF2
Function
MIPI RFFE data input / output
MIPI RFFE clock input
USID default address selection pin (see Tab. 16)
1
2
3
4
5
6
7
8
9
10
Voltage supply compatible with MIPI RFFE specification
Ground
RF4 port
RF3 port
RF2 port
RF1 port
Ground
RF1
GND
Datasheet
17
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2022-01-31
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Application information
Evaluation board description
N1 BGSA400ML10
10 GND
SDATA
SCLK
RF1
RF2
RF3
9
1
2
SDATA
SCLK
USID
VIO
GND
RF1
RF2
RF3
RF4
8
7
R2
(optional)
3
4
USID
VIO
R1
(optional)
RF4
6
GND
C1
(optional)
5
GND
Figure 5: BGSA400ML10 application schematic
Table 20: Bill of materials
Name
Part type
Capacitor
BGSA400ML10
Resistor
Package
0402
TSLP-10-3
0402
Manufacturer
Various
Infineon
Function
De-coupling capacitor
Antenna tuner
Set USID default address
to 6 (GND)
C1 (1nF optional) 1)
N1
R1 (do not place)
R2 (0 Ohm)
Various
R1 (0 Ohm)
Resistor
Resistor
Resistor
0402
0402
0402
Various
Various
Various
Set USID default address
to 7 (VIO)
Set USID default address
to 8 (FLOATING)
Set USID default address
to 9 (220 kOhm to VIO)
R2 (do not place)
R1 (do not place)
R2 (do not place)
R1 (220 kOhm)
R2 (do not place)
1) This capacitor is optional and value is only indicative. Decoupling capacitor value has to be chosen in order VIO ramp-up time is within MIPI RFFE version
v2.1 specification.
Datasheet
18
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2022-01-31
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Package information
7 Package information
Figure 6: TSLP-10-3 package outline (top, side and bottom views)
Pin 1 marking
Date code (YW)
Type code
Figure 7: TSLP-10-3 marking specification (top view): date code digits Y and W defined in Tab. 21/22
Datasheet
19
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Package information
Table 21: Year date code marking - digit "Y"
Year
"Y"
0
1
2
3
4
5
6
7
Year
"Y"
0
1
2
3
4
5
6
7
Year
"Y"
0
1
2
3
4
5
6
7
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
8
9
8
9
8
9
Table 22: Week date code marking - digit "W"
Week
1
2
"W"
A
B
Week
12
13
"W"
N
P
Week
23
24
"W"
4
5
Week
34
35
"W"
h
j
Week
45
46
"W"
v
x
3
4
5
6
7
8
9
10
11
C
D
E
14
15
16
17
18
19
20
21
Q
R
S
T
U
V
W
Y
Z
25
26
27
28
29
30
31
32
6
7
a
b
c
d
e
f
36
37
38
39
40
41
42
43
k
l
n
p
q
r
s
t
u
47
48
49
50
51
52
53
y
z
8
9
2
3
M
F
G
H
J
K
L
22
33
g
44
Datasheet
20
Revision 2.1
2022-01-31
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BGSA400ML10
Ultra high RF voltage antenna tuning switch
Package information
Figure 8: TSLP-10-3 footprint recommendation
Datasheet
21
Revision 2.1
2022-01-31
RESTRICTED
BGSA400ML10
Ultra high RF voltage antenna tuning switch
Package information
Figure 9: TSLP-10-3 carrier tape
Datasheet
22
Revision 2.1
2022-01-31
Revision history
Page or item
Subjects (major changes since previous revision)
Revision 2.1, 2022-01-31
Title page
7
Package drawing added
Note / Test condition for parameter "RF operating voltage" updated
Trademarks
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Edition 2022-01-31
Published by
Infineon Technologies AG
81726 Munich, Germany
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