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BTN7030-1EPA [INFINEON]

The MOTIX™ single half-bridge ICs (NovalithIC™)Lite, MOTIX™ BTN7030-1EPA, is a part of the MOTIX™ single half-bridge ICs(NovalithIC™) family and it is a protected half-bridge with integrated driver, providing protection and diagnosis functions. The device is integrated in SMART7 technology. The MOTIX™ BTN7030-1EPA is an ideal device for many applications in the automotive body domain, such as door lock, trunk lock and cinching latch. Thanks to the half bridge partitioning, it is also the perfect device whenever an individual half bridge is needed;
BTN7030-1EPA
型号： BTN7030-1EPA
厂家： Infineon    Infineon
描述：

The MOTIX™ single half-bridge ICs (NovalithIC™)Lite, MOTIX™ BTN7030-1EPA, is a part of the MOTIX™ single half-bridge ICs(NovalithIC™) family and it is a protected half-bridge with integrated driver, providing protection and diagnosis functions. The device is integrated in SMART7 technology. The MOTIX™ BTN7030-1EPA is an ideal device for many applications in the automotive body domain, such as door lock, trunk lock and cinching latch. Thanks to the half bridge partitioning, it is also the perfect device whenever an individual half bridge is needed
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Features  
•
Low-side and high-side switch in half-bridge configuration with diagnosis and  
embedded protection  
•
•
•
Part of NovalithICTM family  
Switch ON capability while inverse current condition (InverseON)  
Green product (RoHS compliant)  
Protection features  
•
•
Temperature limitation with intelligent latch  
Overcurrent protection (tripping) with intelligent latch for both the low-side and  
high-side output stage  
•
•
Undervoltage shutdown  
Cross current protection  
Diagnostic features  
•
•
•
Proportional load current sense for high-side load currents  
Open load in ON and OFF state  
Short circuit to ground or battery  
Potential applications  
•
•
•
Replaces electromechanical relays, fuses and discrete circuits  
Suitable for driving motors and solenoids of a max. inductance of 3 mH at maximal current  
Temperature dependent overload detection current level with min. 17 A (TJ < 75°C), min. 15 A (TJ = 125°C)  
and min. 14 A (TJ = 150°C)  
•
Current sense diagnosis optimized for motor and solenoid applications  
TREV  
VS  
CVS  
DZ2  
VDD  
VDD  
VS  
BTN7030  
RIN  
REN  
GPIO  
GPIO  
GPIO  
IN  
EN  
DEN  
OUT  
RDEN  
M
COUT  
Microcontroller  
RA/D  
RIS_PROT  
IS  
ADC  
VSS  
GND  
CSENSE  
RSENSE  
DZ1  
Figure 1  
Potential application  
Package  
PG-TSDSO-14  
Product Type  
Marking  
BTN7030-1EPA  
BTN7030-1EPA  
Datasheet  
Please read the Important Notice and Warnings at the end of this document  
1.2  
www.infineon.com  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Description  
Description  
The BTN7030-1EPA is a protected half-bridge with integrated driver, providing protection and diagnosis  
functions. The device is integrated in SMART7 technology.  
Table 1  
Product Summary  
Parameter  
Symbol  
Values  
3.8 V  
3.5 V  
28 V  
Minimum operating voltage (at switch ON)  
Minimum operating voltage (cranking)  
Maximum operating voltage  
VS(OP)  
VS(UV)  
VS  
Minimum overvoltage protection (TJ ≥ 25°C)  
Maximum current in sleep mode (TJ ≤ 85°C)  
Maximum operative current  
VDS(CLAMP)_25  
IVS(SLEEP)_85_stdy  
IGND(ACTIVE)  
RDS(ON)_150(HS)  
RDS(ON)_150(LS)  
IL(OVL0)_-40(HS)  
IL(OVL0)_125(HS)  
IL(OVL0)_150(HS)  
kILIS  
35 V  
3 µA  
5 mA  
25.5 mΩ  
36.5 mΩ  
17 A  
Maximum ON-state resistance (TJ = 150°C) high-side  
Maximum ON-state resistance (TJ = 150°C) low-side  
Min. overload detection current at TJ < 75°C  
Min. overload detection current at TJ = 125°C  
Min. overload detection current at TJ = 150°C  
Typical current sense ratio at IL = IL(NOM)  
Nominal load current  
15 A  
14 A  
4300  
7 A  
IL(NOM)  
Product validation  
Qualified for automotive applications.  
Product validation according to AEC-Q100.  
Datasheet  
2
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Table of contents  
Table of contents  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2  
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2  
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
1
Block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
1.1  
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
2.1  
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.1  
3.2  
3.3  
4
Logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Input pin (IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10  
EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Diagnosis pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Electrical characteristics logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
4.1  
4.2  
4.3  
4.4  
5
5.1  
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
Electrical characteristics power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
5.1.1  
5.1.2  
5.1.3  
5.1.4  
5.2  
5.3  
6
6.1  
6.2  
6.2.1  
6.2.2  
6.3  
6.3.1  
6.3.2  
6.4  
Power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Output ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Output voltage limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
Advanced switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Inverse current behavior for the high-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Inverse current behavior for the low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18  
7
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Datasheet  
3
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Table of contents  
7.1  
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23  
7.2  
7.3  
Overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Protection and diagnosis in case of fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Intelligent latch strategy (INTLAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28  
Cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28  
Electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
7.3.1  
7.4  
7.4.1  
7.4.2  
7.5  
8
8.1  
8.2  
8.2.1  
8.2.2  
8.3  
8.3.1  
8.4  
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Current sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Fault current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Open load current (IIS(OLOFF)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
SENSE timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
8.5  
9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Application setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41  
External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Bidirectional loads and open load in OFF detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
9.1  
9.2  
9.3  
9.4  
10  
11  
Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Datasheet  
4
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Block diagram and terms  
1
Block diagram and terms  
VS  
Supply Voltage  
Supervision  
Voltage Sensor  
T
HS Over  
Temperature  
Over Voltage  
Clamping  
Internal Power Supply  
HS Gate Control  
+
Chargepump  
HS Over Current  
Protection  
Intelligent Latch  
SENSE output  
Load Current Sense  
driver  
logic  
IS  
OUT  
Output Voltage Limitation  
IN  
EN  
ESD  
Protection  
+
LS Over  
T
Temperature  
Input logic  
Over Voltage  
DEN  
Clamping  
LS Gate Control  
LS Over Current  
Protection  
GND  
Figure 2  
1.1  
Terms  
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.  
IVS  
VSIS  
VS  
IIN  
VDS(HS)  
IN  
IEN  
EN  
IL  
VS  
OUT  
IDEN  
DEN  
IS  
VIN  
IIS  
VEN  
VOUT  
VDS(LS)  
,
VDEN  
GND  
IGND  
VIS  
Figure 3  
Voltage and current convention  
Datasheet  
5
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Pin configuration  
2
Pin configuration  
n.c.  
EN  
DEN  
IS  
n.c.  
IN  
n.c.  
1
14  
13  
12  
11  
10  
9
GND  
GND  
GND  
n.c.  
OUT  
OUT  
OUT  
2
3
4
5
6
7
VS  
exposed pad (bottom)  
8
Figure 4  
Pin configuration  
2.1  
Pin definitions and functions  
Table 2  
Pin Definition  
Pin  
Symbol  
Function  
EP  
VS (exposed pad) Supply Voltage  
Battery voltage  
2
3
EN  
Enable  
Digital signal to enable the normal operational mode (active mode) of  
the BTN7030-1EPA and to clear the protection latch  
DEN  
Diagnostic Enable  
Digital signal to enable device diagnosis ("high" active) and to clear  
the protection latch  
If not used: connect to GND pin or to module ground with a 10 kΩ  
resistor  
4
6
IS  
SENSE current output  
Analog/digital signal for diagnosis If not used: leꢀ open  
IN  
Input  
Digital signal to switch ON either the low-side or high-side output  
stage of the half-bridge  
8-10  
OUT  
GND  
n.c.  
Output  
Protected half-bridge power output 1)  
12-14  
Ground  
Signal ground and ground connection for the low-side switch 1)  
1, 5, 7, 11  
Not connected, internally not bonded  
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally  
connected together. PCB traces have to be designed to withstand the maximum current which can flow.  
Datasheet  
6
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Absolute maximum ratings  
3
Absolute maximum ratings  
3.1  
Absolute maximum ratings  
Table 3  
Absolute maximum ratings  
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise  
specified); all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Not subject to production test - specified by design.  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min.  
Typ. Max.  
Supply pins  
Power supply voltage  
Load dump voltage  
VS  
-0.3  
–
–
28  
35  
V
V
–
PRQ-6  
PRQ-8  
VBAT(LD)  
–
Suppressed Load  
Dump acc. to  
ISO16750-2 (2010).  
Ri= 2 Ω  
Supply voltage for short  
circuit protection  
VBAT(SC)  
IDI  
0
–
–
24  
2
V
Setup acc. to AEC-  
Q100-012  
PRQ-9  
1)  
Current through DI pin  
-1  
mA  
PRQ-25  
IS pin  
Voltage at IS pin  
Current through IS pin  
VIS  
IIS  
-1.5  
-25  
–
–
VS  
V
IIS= 10 μA  
PRQ-26  
PRQ-28  
IIS(FAUL mA  
–
T),MAX  
Temperatures  
Junction temperature  
Storage temperature  
ESD Susceptibility  
TJ  
-40  
-55  
–
–
150  
150  
°C  
°C  
–
–
PRQ-29  
PRQ-30  
TSTG  
ESD susceptibility all pins  
(HBM)  
VESD(HBM)  
-2  
–
–
–
–
2
kV  
kV  
V
HBM 2)  
HBM 2)  
CDM 3)  
PRQ-31  
PRQ-32  
PRQ-34  
PRQ-35  
ESD susceptibility OUT vs  
GND and VS connected (HBM)  
VESD(HBM)_OUT -4  
4
ESD susceptibility all pins  
(CDM)  
VESD(CDM)  
-500  
500  
750  
ESD susceptibility corner pins VESD(CDM)_CRN -750  
(CDM)  
V
pins 1, 7, 8, 14  
CDM 3)  
Power stages - 12 mΩ high-side  
Load current, high-side  
switch  
|IL|(HS)  
–
–
IL(OVL),  
MAX  
A
–
PRQ-39  
Power stages - 20 mΩ low-side  
(table continues...)  
Datasheet  
7
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Absolute maximum ratings  
Table 3  
(continued) Absolute maximum ratings  
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise  
specified); all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Not subject to production test - specified by design.  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min.  
Typ. Max.  
Load current, low-side switch |IL|(LS)  
–
–
IL(OVL),  
A
–
PRQ-42  
MAX  
1) Maximum VDI to be considered for latch-up tests: 5.5 V  
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)  
3) ESD susceptibility, Charged Device Model "CDM" according JEDEC JESD22-C101  
•
•
Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
Integrated protection functions are designed to prevent IC destruction under fault conditions described in  
the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions  
are not designed for continuous repetitive operation.  
3.2  
Functional range  
Table 4  
Functional range  
Not subject to production test - specified by design.  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min.  
Typ. Max.  
Supply voltage range for  
normal operation  
VS(NOR)  
6
13.5  
18  
V
V
–
PRQ-43  
PRQ-44  
1)  
2)  
Lower extended supply  
voltage range for operation  
VS(EXT,LOW)  
3.5  
18  
–
6
parameter deviations  
possible  
1)  
Upper extended supply  
VS(EXT,UP)  
–
28  
V
PRQ-45  
voltage range for operation  
parameter deviations  
possible  
1) Protection functions still operative  
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.5 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 3.8 V  
Note:  
Within the functional or operating range, the IC operates as described in the circuit description. The  
electrical characteristics are specified within the conditions given in the Electrical Characteristics  
table.  
3.3  
Thermal resistance  
This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to  
www.jedec.org.  
Datasheet  
8
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Absolute maximum ratings  
Table 5  
Thermal resistance  
Not subject to production test - specified by design.  
Parameter Symbol  
Values  
Unit Note or condition  
P-Number  
Min.  
Typ. Max.  
1)  
Thermal resistance junction- RthJC(HS)  
–
–
–
–
2.7  
4.3  
1.5  
–
K/W  
PRQ-48  
PRQ-540  
PRQ-49  
PRQ-529  
to-case, high-side switch  
1)  
Thermal resistance junction- RthJC(LS)  
to-case, low-side switch  
0.95  
36  
K/W  
1)  
Thermal resistance junction RthJA(HS)  
to ambient, high-side switch  
K/W  
1)  
Thermal resistance junction RthJA(LS)  
to ambient, low-side switch  
32.5  
–
K/W  
1) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package)  
was simulated on a 76.2 × 114.3 × 1.5 mm board with two inner copper layers (2 × 70 µm Cu, 2 × 35 µm  
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.  
Simulation done at TAMB = 105°C and Pdissipation = 1 W.  
Figure 5  
Typical thermal impedance for Tambient = 85°C; Simulation with 1 W of power  
dissipation  
Datasheet  
9
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2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Logic pins  
4
Logic pins  
The device has 3 digital pins for direct control of the device.  
The logic thresholds for "low" and "high" states are defined by parameters VDI(TH) and VDI(HYS). The relationship  
between these two values is shown in Figure 6. The voltage VIN needed to ensure an "high" state is always  
higher than the voltage needed to ensure a "low" state. The digital input pins are compatible with 3.3 V and 5 V  
micro-controllers.  
VDI  
VDI(TH),MAX  
VDI(TH)  
VDI(HYS)  
VDI(TH),MIN  
t
Internal channel  
activation signal  
0
x
1
x
0
t
Figure 6  
Input Threshold voltages and hysteresis  
4.1  
Input pin (IN)  
The input pin IN activates either the low-side or the high-side output stage, in case the enable pin EN is set to  
"high" and no fault is present.  
4.2  
Enable pin (EN)  
The Enable (EN) pin activates the device. When EN pin is set to "high", the device is in Active mode. When it is set  
to "low", the device goes into Sleep mode, with the output stage set to tri-state (low-side and high-side switches  
are set OFF). The protection latch is cleared by a "low" signal with a minimum length of tDELAY(LR) at the EN pin.  
4.3  
Diagnosis Enable pin (DEN)  
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is set  
to "high", the diagnosis is enabled (see Chapter 8.2 for more details). When it is set to "low", the diagnosis is  
disabled (IS pin is set to high impedance).  
The transition from "high" to "low" of DEN pin clears the protection latch of the channel depending on the logic  
state of EN pin and DEN pulse length (see Chapter 7.3 for more details).  
Datasheet  
10  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Logic pins  
4.4  
Electrical characteristics logic pins  
Table 6  
Electrical characteristics logic pins  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C; Digital Input (DI) pins = IN, DEN, EN; all  
voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
Digital input voltage  
threshold  
VDI(TH)  
0.8  
1.3  
2
V
V
See Figure 6  
PRQ-52  
PRQ-53  
1)  
Digital input clamping  
voltage  
VDI(CLAMP1)  
–
7
–
IDI = 1 mA  
IDI = 2 mA  
Digital input clamping  
voltage  
VDI(CLAMP2)  
VDI(HYS)  
6.5  
–
7.5  
8.5  
–
V
V
PRQ-54  
PRQ-56  
1)  
Digital input hysteresis  
0.25  
See Figure 6  
VDI = 2 V  
VDI = 0.8 V  
Digital input current ("high") IDI(H)  
Digital input current ("low") IDI(L)  
2
2
10  
10  
25  
25  
µA  
µA  
PRQ-57  
PRQ-58  
1) Not subject to production test - specified by design  
Datasheet  
11  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power supply  
5
Power supply  
The BTN7030-1EPA is supplied by VS, which is used for the internal logic as well as supply for the power output  
stage. VS has an undervoltage detection circuit, which prevents the activation of the power output stage and  
diagnosis in case the applied voltage is below the undervoltage threshold.  
5.1  
Operation modes  
BTN7030-1EPA has three operation modes, with the transition between the operation modes is determined  
according to these variables:  
•
•
logic level at EN pin  
logic level at DEN pin  
The state diagram including the operation modes and the possible transitions is shown in Figure 7. The  
behavior of BTN7030-1EPA as well as some parameters may change in dependence from the operation mode of  
the device. Furthermore, due to the undervoltage detection circuitry which monitors VS supply voltage, some  
changes within the same operation mode can be seen accordingly. In case of a fault, the BTN7030-1EPA will not  
go into sleep mode, unitl the latch is cleared.  
Power-up  
Unsupplied  
V
S > VS(OP)  
EN = „low“  
& DEN = „low“  
EN = „high“  
Sleep  
EN = „low“ &  
DEN = „high“  
EN = „low“  
& DEN = „low“  
EN = „high“  
Active  
DEN = „high“  
Stand-by  
EN = „low“  
& DEN = „high“  
DEN = „low“  
Figure 7  
Operation mode state diagram  
5.1.1  
Unsupplied  
In this state, the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the  
undervoltage threshold.  
5.1.2  
Power-up  
The Power-up condition is entered when the supply voltage (VS) is applied to the device. The supply is rising  
until it is above the undervoltage threshold VS(OP) therefore the internal power-on signals are set.  
5.1.3  
Sleep mode  
The device is in Sleep mode when all Digital Input pins (IN, DEN, EN) are set to "low". When BTN7030-1EPA is  
in Sleep mode, both high-side and low-side power stages are OFF. The current consumption is minimum (see  
Datasheet  
12  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power supply  
parameter IVS(SLEEP)_85_stdy). No Overtemperature or Overload protection mechanism is active when the device is  
in Sleep mode, only the InverseON protection for the low-side power output stage is active (see Chapter 6.3.1  
for further details). In case of activation, the current consumption of the device is increased.The device can go in  
Sleep mode only if the protection is not active (latch = 0, see Chapter 7.3.1 for further details).  
5.1.4  
Stand-by mode  
The device is in Stand-by mode as long as DEN pin is set to "high" while the EN pin is set to "low". Both the  
high-side and low-side power stages are OFF, therefore only Open Load in OFF diagnosis is possible. Depending  
on the load condition, either a fault current IIS(FAULT) or an Open Load in OFF current IIS(OLOFF) may be present at  
IS pin. In such a situation, the current consumption of the device is increased.  
5.2  
Undervoltage on VS  
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active mode)  
and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the  
output channel.  
As soon as the supply voltage VS is above the operative threshold VS(OP), the channel is switched ON again with a  
hysteresis of VS(HYS)  
.
5.3  
Electrical characteristics power supply  
Table 7  
Electrical characteristics power supply  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit  
Note or condition  
P-Number  
Min. Typ. Max.  
Power supply undervoltage VS(UV)  
1.8  
2.0  
2.7  
3.0  
3.5  
3.8  
V
VS decreasing  
EN = "high"  
From VDS ≤ 0.5 V to  
VDS = VS  
PRQ-63  
shutdown  
Power supply minimum  
operating voltage  
VS(OP)  
V
VS increasing  
EN = "high"  
PRQ-65  
From VDS = VS to  
VDS ≤ 0.5 V  
1)  
Power supply undervoltage VS(HYS)  
–
-
0.3  
–
3
V
PRQ-67  
PRQ-70  
shutdown hysteresis  
VS(OP) - VS(UV)  
1)  
Power supply current  
consumption in sleep mode  
with loads at TJ ≤ 85°C aꢀer  
settling time  
IVS(SLEEP)_85_stdy  
0.01  
µA  
VS = 18 V  
EN = IN = DEN = “low”  
OUT = “floating”  
steady state  
TJ ≤ 85 °C  
(table continues...)  
Datasheet  
13  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power supply  
Table 7  
(continued) Electrical characteristics power supply  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit  
Note or condition  
P-Number  
Min. Typ. Max.  
1)  
Power supply current  
consumption in sleep mode  
with loads at TJ = 150°C  
aꢀer settling time  
IVS(SLEEP)_150_stdy  
-
8
20  
µA  
PRQ-72  
VS = 18 V  
EN = IN = DEN = “low”  
OUT = “floating”  
steady state  
TJ = 150°C  
Operating current in active IGND(ACTIVE)  
–
–
2
2
5
5
mA  
mA  
VS =18 V  
EN = IN = DEN = "high"  
PRQ-73  
PRQ-74  
mode (GND)  
Operating current in active IVS(ACTIVE)  
mode (VS)  
VS =18 V  
IN = "low"  
EN = DEN = "high"  
fault-latch ≠ 0  
Operating current in stand- IGND(STBY)  
–
–
1.2  
–
1.8  
5
mA  
mA  
VS = 18 V EN = IN =  
PRQ-76  
PRQ-77  
by mode/OLOFF  
"low"  
DEN = "high"  
Operating current during  
low-side inverseON  
activation  
IVS(INVON)(LS)  
VS = 6 V  
IL = -200 mA  
EN = IN = "low"  
1) Not subject to production test - specified by design  
Datasheet  
14  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
6
Power stages  
The high-side power stage is built using a N-channel vertical Power MOSFET with charge pump, while the  
low-side power stage uses no charge pump.  
6.1  
Output ON-state resistance  
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 8 shows the variation of  
RDS(ON) across the whole TJ range. The value "2" on the y-axis corresponds to the maximum RDS(ON) measured  
at TJ = 150°C.  
High-Side Switch  
Low-Side Switch  
2
24  
21  
18  
15  
12  
9
2
40  
35  
30  
25  
20  
15  
10  
5
1,75  
1,5  
1,25  
1
1,75  
1,5  
1,25  
1
0,75  
0,5  
0,25  
0
0,75  
0,5  
0,25  
0
6
3
typ.  
typ.  
0
0
-40  
0
40  
80  
120 160  
-40  
0
40  
80  
120 160  
junction Temperature (°C)  
junction Temperature (°C)  
Figure 8  
Typical RDS(ON) vs. junction temperature for low-side and high-side output stage  
6.2  
Switching loads  
6.2.1  
Switching times  
When switching resistive loads, the switching times and slew rates shown in Figure 9 and Figure 10 can be  
considered. The switch energy values EON(xS) and EOFF(xS) are proportional to the load resistance and times  
tON(xS) and tOFF(xS)  
.
Datasheet  
15  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
IN  
VIN(TH)  
VIN(HYS)  
t
VOUT  
tON(HS)  
90% of VS  
tDOFF(HS)  
70% of VS  
70% of VS  
30% of VS  
(dV/dt)OFF(HS)  
(dV/dt)ON(HS)  
30% of VS  
tDON(HS)  
tOFF(HS)  
10% of VS  
t
PDMOS(HS)  
EON(HS)  
EOFF(HS)  
t
Figure 9  
Switching a resistive load to ground (high-side), for EN="high"  
IN  
VIN(TH)  
VIN(HYS)  
t
VOUT  
tOFF(LS)  
90% of VS  
70% of VS  
tDON(LS)  
30% of VS  
70% of VS  
(dV/dt)ON(LS)  
(dV/dt)OFF(LS)  
30% of VS  
10% of VS  
tON(LS)  
tDOFF(LS)  
t
PDMOS(LS)  
EON(LS)  
EOFF(LS)  
t
Figure 10  
Switching a resistive load to supply voltage (low-side), for EN="high"  
6.2.2  
Output voltage limitation  
To increase the current sense accuracy of the high-side output stage, VDS voltage is monitored.  
Datasheet  
16  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
When the output current IL decreases while the channel is diagnosed (DEN pin set to "high" - see Figure 11)  
bringing VDS equal or lower than VDS(SLC)(HS), the output DMOS gate is partially discharged. This increases the  
output resistance so that VDS = VDS(SLC)(HS) even for very small output currents.  
EN  
IN  
t
DEN  
tsIS(ON)  
tsIS(OFF)  
t
IL  
t
VDS  
VS  
VDS(SLC)(HS)  
t
Figure 11  
Output voltage limitation activation during diagnosis, with EN="high"  
The VDS increase allows the current sensing circuitry to work more efficiently, providing better kILIS accuracy for  
output current in the low range.  
6.3  
Advanced switching characteristics  
6.3.1  
Inverse current behavior for the high-side switch  
When VOUT > VS, a current IINV flows into the high-side power output transistor (see Figure 12). Similar for VOUT  
< GND (0 V), a current IINV flows into the low-side power output transistor. This condition is known as "Inverse  
Current".  
If the channel is in OFF- state, the current flows through the intrinsic body diode generating high power losses  
therefore an increase of overall device temperature. If the channel is in ON- state, RDS(INV) can be expected and  
power dissipation in the output stage is comparable to normal operation in RDS(ON)  
.
With InverseON, it is possible to switch ON or OFF the high-side power output channel during inverse current  
condition.  
Datasheet  
17  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
VS  
BTN7xxx  
VS  
VDS(HS)  
VSIS(CLAMP)  
VDS(CLAMP)_HS  
IS  
IL  
L, RL  
VDS(CLAMP)_LS  
OUT  
GND  
VOUT,  
VDS(LS)  
Figure 12  
Inverse current circuitry for low-side and high-side  
6.3.2  
Inverse current behavior for the low-side switch  
With InverseON, the low-side power output channel is activated under all operational conditions for VOUT  
VINV(LS), also in case of any fault to protect the low-side power output transistor.  
<
The circuitry is active in any operational condition, fault condition, stand-by or sleep mode.  
The power supply consumption for voltage monitoring, without activation of the power output stage, is  
included in Table 7. In case of activation of the low-side power output stage, when switched on by the  
protection circuitry, an operating supply current of IVS(INVON)(LS) is required during activation.  
When VOUT is small again, the low-side output-stage is switched according to the EN and IN pin.  
Note:  
No protection mechanism like Overtemperature or Overload protection is active during applied  
Inverse Currents for both low-side and high-side output transistor.  
6.4  
Electrical characteristics power stages  
Table 8  
Electrical characteristics power stages switching  
TJ = -40°C to +150°C; Rload = 3.3 Ω, single pulse,  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
High-side switch timings  
Switch-ON delay, high-side tDON(HS)  
30  
10  
45  
60  
33  
85  
110 μs  
VS =13.5 V  
VOUT = 10% VS  
See Figure 9  
PRQ-146  
PRQ-147  
PRQ-148  
switch  
Switch-OFF delay, high-side tDOFF(HS)  
switch  
60  
μs  
VS =13.5 V  
VOUT = 90% VS  
See Figure 9  
Switch-ON time, high-side tON(HS)  
switch  
135 μs  
VS =13.5 V  
VOUT = 90% VS  
See Figure 9  
(table continues...)  
Datasheet  
18  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
Table 8  
(continued) Electrical characteristics power stages switching  
TJ = -40°C to +150°C; Rload = 3.3 Ω, single pulse,  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
Switch-OFF time, high-side tOFF(HS)  
switch  
25  
55  
82  
μs  
VS = 13.5 V  
VOUT = 10% VS  
See Figure 9  
PRQ-149  
Switch-ON/OFF matching  
tON-tOFF, high-side switch  
ΔtSW(HS)  
0
–
35  
20  
70  
–
μs  
μs  
VS = 13.5 V  
See Figure 9  
PRQ-150  
PRQ-528  
Blank time between  
switches activation HS to LS  
(to avoid cross-current)  
tBLANK(HS-LS)  
VS = 13.5 V  
Low-side switch timings  
Switch-ON delay, low-side tDON(LS)  
50  
10  
70  
25  
90  
33  
130 μs  
VS = 13.5 V  
VOUT = 90% VS  
See Figure 10  
PRQ-151  
PRQ-152  
PRQ-153  
PRQ-154  
switch  
Switch-OFF delay, low-side tDOFF(LS)  
switch  
60  
μs  
VS = 13.5 V  
VOUT = 10% VS  
See Figure 10  
Switch-ON time, low-side  
switch  
tON(LS)  
115 160 μs  
VS = 13.5 V  
VOUT = 10% VS  
See Figure 10  
Switch-OFF time, low-side tOFF(LS)  
switch  
55  
85  
μs  
VS = 13.5 V  
VOUT = 90% VS  
See Figure 10  
Switch-ON/OFF matching  
tON-tOFF, low-side switch  
ΔtSW(LS)  
25  
–
60  
40  
95  
–
μs  
μs  
VS = 13.5 V  
See Figure 10  
PRQ-155  
PRQ-156  
Blank time between  
switches activation LS to HS  
(to avoid cross-current)  
tBLANK(LS-HS)  
VS = 13.5 V  
High-side switch voltage slope  
Switch-ON slew rate, high- (dV/dt)ON(HS)  
side switch  
0.35 0.6  
0.35 0.6  
0.9  
0.9  
V/μs VS = 13.5 V  
VOUT = 30% to 70% of VS  
V/μs VS = 13.5 V  
VOUT = 70% to 30% of VS  
PRQ-157  
PRQ-158  
Switch-OFF slew rate, high- -(dV/dt)OFF(HS)  
side switch  
Low-side switch voltage slope  
Switch-ON slew rate, low-  
side switch  
-(dV/dt)ON(LS)  
0.35 0.6  
0.35 0.6  
0.9  
0.9  
V/μs VS =13.5 V  
VOUT = 70% to 30% of VS  
V/μs VS = 13.5 V  
VOUT = 30% to 70% of VS  
PRQ-160  
PRQ-161  
Switch-OFF slew rate, low- (dV/dt)OFF(LS)  
side switch  
High-side voltages  
(table continues...)  
Datasheet  
19  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
Table 8  
(continued) Electrical characteristics power stages switching  
TJ = -40°C to +150°C; Rload = 3.3 Ω, single pulse,  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
Output voltage drop  
limitation at small load  
currents  
VDS(SLC)(HS)  
2
7
18  
mV IOUT = IOUT(OL) = 20 mA PRQ-163  
IN=DEN=EN="high"  
Table 9  
Electrical characteristics - power output stages  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
12 mΩ high-side  
Output characteristics  
1)  
ON-state resistance at TJ = RDS(ON)_25(HS)  
25°C, high-side switch  
–
12  
–
mΩ  
PRQ-164  
TJ = 25 °C  
ON-state resistance at TJ = RDS(ON)_150(HS)  
–
–
–
–
25.5 mΩ TJ = 150°C  
PRQ-165  
PRQ-168  
150°C, high-side switch  
ON-state resistance in  
inverse current at TJ =  
150°C, high-side switch  
RDS(INV)_150(HS)  
IL(OFF)_85(HS)  
IL(OFF)_150(HS)  
26  
1
mΩ TJ = 150°C  
VS = 13.5 V  
IL = -4 A  
See Figure 12  
1)  
Output leakage current at  
TJ ≤ 85°C, high-side switch  
–
–
0.01  
16  
μA  
PRQ-169  
PRQ-170  
VOUT = 0 V  
EN = "low"  
TA ≤ 85°C  
Output leakage current at  
TJ = 150°C, high-side switch  
43  
μA VOUT = 0 V  
EN = "low"  
TA = 150°C  
Voltages  
1)  
Drain source diode voltage |VDS(DIODE)_-40(HS)  
|
–
–
800  
700  
–
–
mV  
PRQ-536  
PRQ-537  
PRQ-172  
at -40°C, high-side switch  
IL = -190 mA  
TJ = -40°C  
1)  
Drain source diode voltage |VDS(DIODE)_25(HS)  
at 25°C, high-side switch  
|
mV  
IL = -190 mA  
TJ = 25°C  
Drain source diode voltage |VDS(DIODE)_150(HS)| –  
at 150°C, high-side switch  
500 650 mV IL = -190 mA  
TJ = 150°C  
Switching energy  
(table continues...)  
Datasheet  
20  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
Table 9  
(continued) Electrical characteristics - power output stages  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
1)  
Switch-ON energy, high-  
side switch  
EON(HS)  
–
0.44  
–
mJ  
PRQ-173  
VS = 18 V  
See Figure 9  
1)  
Switch-OFF energy, high-  
side switch  
EOFF(HS)  
–
0.49  
–
mJ  
PRQ-174  
VS = 18 V  
See Figure 9  
20 mΩ low-side  
Output characteristics  
ON-state resistance at TJ = RDS(ON)_25(LS)  
–
–
–
20  
–
–
mΩ 1) TJ = 25°C  
PRQ-175  
PRQ-176  
PRQ-179  
25°C, low-side switch  
ON-state resistance at TJ = RDS(ON)_150(LS)  
150°C, low-side switch  
36.5 mΩ TJ = 150°C  
ON-state resistance in  
inverse current at TJ =  
150°C, low-side switch  
RDS(INV)_150(LS)  
IL(OFF)_85(LS)  
IL(OFF)_150(LS)  
–
40  
5
mΩ TJ = 150°C  
VS = 13.5 V  
IL = -4 A  
See Figure 12  
1)  
Output leakage current at  
TJ ≤ 85°C, low-side switch  
–
0.05  
μA  
PRQ-190  
VOUT = VS  
EN = "low"  
TA ≤ 85°C  
Output leakage current at  
TJ = 150°C, low-side switch  
–
–
–
2
117 μA VOUT = VS EN = "low" TA PRQ-181  
= 150°C  
Voltages  
1)  
Drain source diode voltage |VDS(DIODE)_-40(LS)  
at -40°C, low-side switch  
|
600  
700  
–
–
mV  
mV  
PRQ-539  
PRQ-538  
IL = -190 mA  
TJ = -40°C  
1)  
Drain source diode voltage |VDS(DIODE)_25(LS)  
at 25°C, low-side switch  
|
IL = -190 mA  
TJ = 25°C  
Drain source diode voltage |VDS(DIODE)_150(LS)  
|
–
–
500 650 mV IL = -500 mA  
PRQ-183  
PRQ-184  
at 150°C, low-side switch  
TJ = 150 °C  
1)  
Voltage threshold for first  
inverse current low-side  
activation, low-side switch  
VINV(LS)  
-300  
–
mV  
EN = IN = DEN = “low”  
VS = 6 V  
IL = -200 mA  
Switching energy  
(table continues...)  
Datasheet  
21  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Power stages  
Table 9  
(continued) Electrical characteristics - power output stages  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
1)  
Switch-ON energy, low-side EON(LS)  
switch  
–
0.42  
–
mJ  
PRQ-187  
VS = 18 V  
See Figure 10  
1)  
Switch-OFF energy, low-  
side switch  
EOFF(LS)  
–
0.46  
–
mJ  
PRQ-188  
VS = 18 V  
See Figure 10  
1) Not subject to production test - specified by design  
Datasheet  
22  
1.2  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
7
Protection  
The BTN7030-1EPA is protected against overtemperature, overload and overvoltage.  
Overtemperature and overload protections are working when the device is not in sleep mode.  
Overvoltage protection works in all operation modes.  
7.1  
Overtemperature protection  
An increase of the junction temperature TJ above the thresholds TJ(SD) switches OFF both the high-side and  
low-side output stages to prevent destruction. The channel remains switched OFF until the temperature has  
reached the "Restart" condition described in Table 10. The behavior is shown in Figure 13. From protection  
point of view, pins IN and EN are equivalent.  
EN  
IN  
t
DEN  
t
IL  
IL(OVL0)(HS)  
IL(NOM)  
t
TJ  
TJ(SD)  
t
IIS  
IIS(FAULT)  
IIS = IL / kILIS  
t
Internal  
latch  
0
1
t
Figure 13  
Overtemperature protection, with EN = "high" and load to GND  
When the overtemperature protection circuitry allows the channel to be switched ON again, the Intelligent latch  
strategy described in Chapter 7.3.1 is followed.  
Datasheet  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
7.2  
Overload protection  
The BTN7030-1EPA is protected in case of overload, short circuit to battery (low-side output stage) or short  
circuit to ground (high-side output stage). For the high-side output stage, two overload thresholds are defined  
(see Figure 14) and selected automatically depending on the voltage VDS across the power DMOS:  
Overload current thresholds variation with VDS for the high-side output stage  
•
•
IL(OVL0) when VDS < 13 V  
IL(OVL1) when VDS > 22 V  
Figure 14  
Typical Overload current thresholds variation with VDS for the high-side output stage  
In order to allow a higher load inrush at low ambient temperature, the overload threshold for the high-side  
output stage is maximum at low temperature and decreases when TJ increases (see Figure 15).  
For the high-side output stage, IL(OVL0) typical value remains constant up to a junction temperature of +75°C.  
Datasheet  
24  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
1,2  
IL(OVL0)  
1
0,8  
0,6  
0,4  
0,2  
low-side  
high-side  
0
-40  
-20  
0
20  
40  
60  
80  
100  
120  
140  
Junction Temperature (°C)  
Figure 15  
Overload current thresholds variation with TJ  
The power supply voltage VS can increase above 18 V for short time, for instance in load dump or in jump  
start condition. Whenever VS ≥ VS(JS), the overload detection current for the high-side output stage is set to  
IL(OVL_JS)(HS) as shown in Figure 16.  
Figure 16  
Overload detection current variation with VS voltage for the high-side output stage  
Datasheet  
25  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1), in either the low-side or high-side output stages) the output stage  
is switched OFF (both low-side and high-side). The output stage is allowed to be reactivated according to the  
strategy described in Chapter 7.3.  
7.3  
Protection and diagnosis in case of fault  
Any event that triggers a protection mechanism (either Overtemperature or Overload) has consequences:  
•
•
the output stage switches OFF and the internal latch is set to "1"  
if the diagnosis is active for the channel, a current IIS(FAULT) is provided by IS pin (see Chapter 8.2.2 for  
further details)  
If all the "restart" conditions described in Table 10 are fullfilled, the latch can be reset, thus the output stage can  
be switched ON again.  
Furthermore, the device has the intelligent latch to protect itself against unwanted repetitive restart in fault  
condition.  
Table 10  
Protection “restart” condition  
Fault condition  
Overtemperature  
Overload  
Switch OFF event  
TJ ≥ TJ(SD)  
"Restart" Condition  
TJ < TJ(SD) – TJ(HYS)  
IL < 50 mA  
IL ≥ IL(OVL)  
7.3.1  
Intelligent latch strategy (INTLAT)  
When EN is set to "high", the channel is switched ON. In case of fault condition the output stage latches OFF.  
There are two ways to de-latch the switch.  
With EN pin:  
It is necessary to set the pin to "low" for a time longer than tDELAY(LR) ("latch reset delay" time) to de-latch the  
channel. This is independent from the state of the IN pin. The channel can be allowed to restart only if the  
"restart" conditions for the protection mechanisms are fulfilled (see Table 10).  
During the "latch reset delay" time, if the pin is set to "high" the channel remains switched OFF and the timer  
tDELAY(LR) is reset and it is not started as long as the pin remains at "high". It restarts as soon as the pin is set to  
"low" again.  
The intelligent latch strategy is shown in Figure 17.  
With DEN pin:  
It is possible to "force" a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge  
followed by a falling edge) to the DEN pin while EN pin is "low". The pulse applied to DEN pin must have a  
duration longer than tDEN(LR) to ensure a reset of the internal latch.  
The timing is shown in Figure 18.  
Datasheet  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
tDELAY(LR)  
EN  
t
Short circuit  
to ground  
t
IL  
t
Internal  
latch  
0
1
0
1
t
DEN  
t
t
tsIS(DIAG)  
tON  
IIS(FAULT)  
IIS(FAULT)  
IIS  
Figure 17  
Intelligent latch timing diagram, with IN = ”high” and load to GND  
EN  
t
t
Short circuit  
to ground  
IL  
t
t
Internal  
latch  
0
1
0
1
t > tDEN(LR)  
t < tDEN(LR)  
DEN  
t
t
tsIS(DIAG)  
tsIS(DIAG)  
IIS(FAULT)  
tsIS(DIAG)  
IIS(FAULT)  
IIS(FAULT)  
IIS  
Figure 18  
Intelligent latch timing diagram with forced reset, with IN = “high” and load to GND  
Datasheet  
27  
1.2  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
7.4  
Additional protections  
Overvoltage protection  
7.4.1  
The clamping structure limits the negative / positive output voltage so that VDS(xS) = VDS(CLAMP), for both the  
high-side and low-side output stage. The clamping structure protects the device in all operative modes listed in  
Chapter Chapter 6.1.  
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistor is still operational and  
follows the input pin.  
In addition, there is a clamp mechanism available for Overvoltage protection for the logic and the output  
channel, monitoring the voltage between VS and GND pins (VS(CLAMP)).  
VS  
BTN7xxx  
VS  
VDS(HS)  
VSIS(CLAMP)  
VDS(CLAMP)_HS  
IS  
IL  
L, RL  
VDS(CLAMP)_LS  
OUT  
GND  
VOUT  
VDS(LS)  
,
Figure 19  
Output clamp concept  
7.4.2  
Cross current protection  
In half-bridge applications it has to be assured that the high-side and low-side power output stages are not  
conducting at the same time, connecting directly the battery voltage to GND. This is assured by a circuit in the  
driver logic, generating a so called dead time between switching off one power output stages and switching on  
the other. This is ensured by monitoring the state of the MOSFETs.  
7.5  
Electrical characteristics protection  
Datasheet  
28  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
Table 11  
Electrical characteristics protection  
VS = 6 V to 18 V, TJ = -40°C to +150°C; typical values: VS= 13.5 V, TJ = 25 °C; typical resistive load connected to the  
output for testing (unless otherwise specified): Rload = 3.3 Ω  
Parameter  
Symbol  
Values  
Unit  
Note or condition  
P-Number  
Min. Typ. Max.  
1)  
2)  
Thermal shutdown  
temperature  
TJ(SD)  
150 175 200 °C  
PRQ-191  
See Figure 13  
3)  
Thermal shutdown  
hysteresis  
TJ(HYS)  
–
30  
–
K
V
PRQ-193  
PRQ-144  
See Figure 13  
Drain to source clamping  
voltage at TJ = -40°C for HS  
and LS switches  
VDS(CLAMP)_-40  
33  
36.5 42  
IL = |5 mA|  
TJ = -40°C  
See Figure 19  
2)  
Drain to source clamping  
voltage at TJ ≥ 25 °C for HS  
and LS switches  
VDS(CLAMP)_25  
35  
38  
44  
V
PRQ-145  
IL = |5 mA|  
TJ ≥ 25°C  
See Figure 19  
Power supply clamping  
voltage at TJ = -40°C  
VS(CLAMP)_-40  
33  
35  
36.5 42  
V
V
IVS = 5 mA  
TJ = -40°C  
See Figure 19  
2)  
PRQ-197  
PRQ-198  
Power supply clamping  
voltage at TJ ≥ 25°C  
VS(CLAMP)_25  
38  
44  
IVS = 5 mA  
TJ ≥ 25 °C  
See Figure 19  
3)  
Power supply voltage  
threshold for overcurrent  
threshold reduction in case  
of short circuit  
VS(JS)  
20.5 22.5 24.5  
V
PRQ-199  
Setup acc. to AEC-  
Q100-012  
Protection timings  
1)  
3)  
Latch reset delay time aꢀer tDELAY(LR)  
fault condition  
40  
50  
70  
100 ms  
PRQ-200  
PRQ-201  
Minimum DEN Pulse  
tDEN(LR)  
100 150 µs  
duration for latch reset  
Protection power output stage - 12 mΩ high-side  
1)  
Overload detection current IL(OVL0)_-40(HS)  
at TJ = -40°C, high-side  
switch  
17  
21  
25  
A
PRQ-202  
TJ = -40°C  
dI/dt = 0.05 A/µs  
See Figure 15  
(table continues...)  
Datasheet  
29  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Protection  
Table 11  
(continued) Electrical characteristics protection  
VS = 6 V to 18 V, TJ = -40°C to +150°C; typical values: VS= 13.5 V, TJ = 25 °C; typical resistive load connected to the  
output for testing (unless otherwise specified): Rload = 3.3 Ω  
Parameter  
Symbol  
Values  
Unit  
Note or condition  
P-Number  
Min. Typ. Max.  
1)  
Overload detection current IL(OVL0)_25(HS)  
at TJ= 25°C, high-side  
switch  
17  
15  
14  
–
21  
25  
A
PRQ-203  
TJ = 25°C  
dI/dt = 0.05 A/µs  
See Figure 15  
3)  
Overload detection current IL(OVL0)_125(HS)  
at TJ= 125°C, high-side  
switch  
–
–
A
A
A
A
PRQ-535  
PRQ-204  
PRQ-205  
PRQ-206  
TJ = 125°C  
dI/dt = 0.05 A/µs  
See Figure 15  
3)  
Overload detection current IL(OVL0)_150(HS)  
at TJ = 150°C, high-side  
switch  
16.5 19  
TJ = 150°C  
dI/dt = 0.05 A/µs  
See Figure 15  
3)  
Overload detection current IL(OVL1)(HS)  
at high VDS, high-side  
switch  
15  
15  
–
–
dI/dt= 0.05 A/µs  
TJ = 25°C  
See Figure 15  
3)  
Overload detection current IL(OVL_JS)(HS)  
- jump start condition, high-  
side switch  
–
VS > VS(JS)  
dI/dt = 0.05 A/µs  
TJ = 25°C  
See Figure 16  
Protection power output stage - 20 mΩ low-side  
1)  
Overload detection current, IL(OVL0)(LS)  
16  
21  
28  
A
PRQ-207  
low-side switch  
dI/dt = 0.05 A/µs  
See Figure 15  
1) Functional test only  
2) Tested at TJ = 150°C only  
3) Not subject to production test - specified by design  
Datasheet  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
8
Diagnosis  
For diagnosis purpose, the BTN7030-1EPA provides a combination of digital and analog signals at pin IS.  
These signals are generically named SENSE and written IIS. In case of disabled diagnostic, IS pin becomes high  
impedance.  
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is  
used. A typical value is RSENSE = 1.2 kΩ.  
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS  
pin to the sense current output of other devices, if they are supplied by a different battery feed.  
8.1  
Overview  
Table 12 gives a quick reference for the state of the IS pin during BTN7030-1EPA operation.  
Table 12  
SENSE signal, function of application condition  
Application Condition  
Inputs  
Outputs  
Diagnostic Output  
(IS)  
EN IN DEN HSS  
LSS OUT (VOUT  
)
3)  
Stand-by operation  
Open Load  
0
X
1
OFF  
OFF  
OFF  
_
Z
IIS(FAULT) if latch ≠ 0  
OFF < VS - VDS(OLOFF)  
> VS - VDS(OLOFF)  
Z
IIS(OLOFF)  
IIS(FAULT) if latch ≠ 0  
Inverse current on LSS  
Inverse current on HSS  
Normal operation  
OFF  
OFF  
ON  
~ VINV = VOUT  
<
Z
VINV(LS)  
IIS(FAULT) if latch ≠ 0  
OFF ~ VINV = VOUT > VS  
IIS(OLOFF)  
IIS(FAULT) if latch ≠ 0  
1
0
1
X
X
0
1
OFF  
ON  
ON ~ GND  
Z (= IIS(OFF))  
OFF ~ VS  
IIS = IL / kILIS (> IIS(EN)  
IIS(FAULT)  
IIS(FAULT)  
IIS(FAULT)  
Z
)
3)  
Overcurrent at HS or LS  
Short circuit to GND  
Short circuit to VS  
OFF  
OFF  
OFF  
OFF  
OFF ~ GND  
OFF ~ VS  
~ VS  
~ GND  
IIS(FAULT)  
IIS(EN)  
1)  
Open Load  
1
1
ON  
ON  
OFF ~ VS  
2)  
Under load at HS (e.g. output  
voltage limitation condition)  
OFF ~ VS  
IIS(EN) < IIS < IL(NOM) /  
kILIS  
Overtemperature at HS or LS  
Inverse current on HSS  
Inverse current on LSS  
X
1
X
OFF  
ON  
OFF  
Z
IIS(FAULT)  
IIS(EN)  
−
OFF VOUT > VS  
X
X
OFF  
ON  
~ VINV = VOUT <  
VINV(LS)  
3)  
Undervoltage at VS  
Sleep Mode  
X
0
X
X
0
X
X
0
0
OFF  
OFF  
OFF  
OFF  
_
Z
Z
Z
Z
3)  
All conditions  
_
Datasheet  
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BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
1) The output current has to be lower than IL(OL)  
2) The output current has to be higher than IL(OL)  
3) load dependent  
Table 13  
Signal value explanation  
Inputs (EN, IN, DEN)  
0 = Logic "low"  
Switches (LSS, HSS)  
OFF = switched off  
ON = switched on  
Diagnostic Output (IS)  
Z = high Impedance  
1 = Logic "high"  
X = "low" or "high"  
All states  
VS < VUV(OFF)  
(decreasing)  
Unsupplied  
Power-up  
Undervoltage  
All states  
EN IN HSS LSS  
OFF OFF  
IS  
(except sleep)  
VS > VS(OP)  
X
X
Z
TJ > TJ(SD)  
VS < VS(UV)  
(decreasing)  
VS > VS(OP)  
(increasing)  
Overtemperature  
Sleep  
EN = 1  
DEN EN IN HSS LSS  
IS  
EN IN HSS LSS  
IS  
0
0
X
OFF OFF  
Z
X
X
OFF OFF IIS(fault)  
TJ > TJ(SD)  
DEN = EN = 0  
for t ≥ tstandby  
DEN = EN = 0  
for t = tstandby  
DEN = 1  
Tj < TJ(SD) - TJ(HYS) & reset fault  
Normal operation  
EN = 0  
All states  
EN IN HSS LSS  
IS  
Z
EN = 1  
I
VS > IL(OVLx)(HS)  
1
1
0
1
OFF ON  
ON OFF  
IL < 50 mA  
& reset fault  
CS  
Stand-by (OLOFF)  
Overload HS  
IL < 50 mA  
& reset fault  
I
GND > IL(OVLx)(LS)  
EN IN HSS LSS  
IS  
VOUT  
< VS - VDS(OLOFF)  
EN IN HSS LSS  
IS  
0
0
X
X
OFF OFF  
Z
X
X
OFF OFF IIS(fault)  
OFF OFF IIS(OLOFF) > VS - VDS(OLOFF)  
All states  
Overload LS  
(incl. Sleep)  
VOUT < ~0 V  
EN IN HSS LSS  
IS  
VOUT  
V
OUT ≥ ~0 V  
1
1
1
0
0
1
1
X
OFF OFF IIS(fault)  
Low-side  
freewheeling  
Prev. states  
OFF OFF  
Z
VS  
OFF OFF IIS(fault)  
OFF OFF IIS(fault)  
~ GND  
EN IN HSS LSS  
VOUT  
X
X
OFF ON  
< ~0V  
Figure 20  
Simplified State Diagram for DEN = "high" (unless otherwise specified)  
•
•
Grey arrow: Transition caused by change of environmental conditions.  
Black arrow: Possible transition by digital input pins (EN, DEN or IN pin).  
8.2  
Diagnosis in ON state  
A current proportional to the load current through the high-side output stage (ratio kILIS = IL / IIS) is provided at  
pin IS when the following conditions are fulfilled:  
Datasheet  
32  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
•
•
•
the power output stage is switched ON with VDS < 2 V  
the diagnosis is enabled  
no fault (as described in Chapter 7.3) is present or was present and not cleared yet (see Chapter 8.2.2 for  
further details)  
If a "hard" failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.  
8.2.1  
Current sense (kILIS)  
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL output  
current through the high-side switch until IL reaches the overload detection current IL(OVLx). In case of open load  
at the output stage (IL close to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified.  
This condition is shown in Figure 21. The blue line represents the ideal kILIS line, while the red lines show the  
behavior of a typical product.  
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple  
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).  
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and  
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:  
• a well-defined and precise current (IL(CAL)) is applied at the output during end of line test at customer side  
• the corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL)  
)
• within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by  
ΔkILIS  
The derating of kILIS aꢀer calibration is calculated using the formulas in Current sense ΔkILIS calculation  
formulas and it is specified by ΔkILIS  
Current sense ΔkILIS calculation formulas  
k
@I  
k
@I  
ILIS  
L CAL _L  
ILIS  
L CAL H  
∆ kILIS, MIN  
=
100 * MIN  
100 * MAX  
− 1,  
− 1  
k
@I  
k
@I  
ILIS  
L CAL  
ILIS  
L CAL  
Equation 1  
k
@I  
k
@I  
ILIS  
L CAL _L  
ILIS  
L CAL H  
∆ kILIS, MAX  
=
− 1,  
− 1  
k
@I  
k
@I  
ILIS  
L CAL  
ILIS  
L CAL  
Equation 2  
Datasheet  
33  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
IIS  
IIS(OL)  
IIS(EN)  
IL  
IL(OL)  
Figure 21  
Current sense ratio in open load at ON condition  
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the driꢀ over  
temperature as well as the driꢀ over the current range from IL(CAL)_L to IL(CAL)_H  
.
8.2.2  
Fault current (IIS(FAULT))  
As soon as a protection event occurs, the value of the internal latch (see Chapter 7.3 for more details) is  
changed from 0 to 1, a current IIS(FAULT) is provided by pin IS when DEN is set to "high"and both the high-side  
and low-side output stage of the affected channel are switched OFF.  
If the device is switched OFF by protection event and its EN pin is driven by PWM with pulse width < tDELAY(LR)  
,
the internal latch could not be reset, the current IIS(FAULT) is provided each time the device diagnosis is activated  
by DEN.  
If the device is OFF and the internal latch is not in the reset state, the current IIS(FAULT) is also provided each time  
the device diagnosis is checked.  
Figure 22 shows the relation between high-side current sense (IIS = IL / kILIS) and IIS(FAULT)  
.
Datasheet  
34  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
IIS  
IIS(FAULT),max  
IIS(FAULT)  
IIS(FAULT),min  
IL / kILIS  
IL(OVL),min  
IL(OVL),max  
IL  
Figure 22  
SENSE behavior - overview  
If present (EN = IN = DEN = 1, no fault present), the current sense signal can be differentiated from the fault  
current IIS(FAULT), up to the max. possible load current IL(OVL0)_-40(HS),max  
.
8.3  
Diagnosis in OFF state  
When a power output stage is in OFF state, the BTN7030-1EPA can measure the output voltage and compare it  
with a threshold voltage. In this way, using some additional external components (a pull-down resistor and a  
switchable pull-up current source) it is possible to detect if the load is missing or if there is a short circuit to  
battery. If a fault condition was detected by the device (the internal latch has a value different from the reset  
value, as described in Chapter 8.2.2) a current IIS(FAULT) is provided by IS pin each time the channel diagnosis is  
checked also in OFF state.  
8.3.1  
Open load current (IIS(OLOFF))  
In OFF state, when DEN pin is set to "high", the VDS voltage of the high-side switch is compared  
with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to  
battery, VDS(HS) ~ VS therefore VDS(HS) > VDS(OLOFF). When the diagnosis is active and VDS(HS) ≤ VDS(OLOFF), a  
current IIS(OLOFF) is provided by IS pin. Open Load in OFF detection is only possible for half-bridge configuration  
where the load is supposed to be connected between the OUT pin of the device and GND. Figure 23 shows the  
relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two currents don´t overlap making always  
possible to differentiate between open load in OFF and fault condition.  
Datasheet  
35  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
IIS  
IIS(FAULT)  
IIS(OLOFF)  
VDS  
VDS(OLOFF)  
Figure 23  
IIS in OFF State  
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the pin EN and the sensing at pin IS for  
open load in OFF diagnosis to allow the internal comparator to settle. In Figure 24 the timings for an open load  
detection are shown - the load is always disconnected.  
EN / IN  
t
DEN  
tIS(OLOFF)_D  
t
VOUT  
VDS(OLOFF)  
~ VS  
Load connected  
to GND  
t
IIS  
IIS(OLOFF)  
IIS(OL)  
t
Figure 24  
Open load in OFF timings - load disconnected  
Datasheet  
36  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
8.4  
SENSE timings  
Figure 25 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load  
change). As a proper signal cannot be established before the load current is stable (therefore before tON):  
tsIS(DIAG) = tsIS(ON) + tON  
IN  
OFF  
OFF  
ON  
t
t
DEN  
tOFF  
IL  
t
t
tsIS(LC)  
tsIS(OFF)  
tsIS(ON)  
tsIS(OFF)  
tsIS(DIAG)  
IIS  
Figure 25  
SENSE Settling / disabling timing, with EN = “high” and load to GND  
IN  
t
DEN  
IL  
t
t
tsIS(ON)_SLC  
tsIS(ON)  
tsIS(LC)_SLC  
IIS  
t
Figure 26  
SENSE Timing with Small Load Current, with EN = "high" and load to GND  
Datasheet  
37  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
8.5  
Electrical characteristics diagnosis  
Table 14  
Electrical characteristics diagnosis  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
SENSE leakage current  
when disabled  
IIS(OFF)  
–
0.01 0.5  
µA  
µA  
DEN = "low" IL ≥  
IL(NOM) VIS = 0 V  
1)  
PRQ-209  
PRQ-210  
SENSE leakage current  
when enabled at TJ ≤ 85 °C  
IIS(EN)_85  
–
0.2  
1
TJ ≤ 85°C  
DEN = "high"  
IL = 0 A  
See Figure 21  
SENSE leakage current  
IIS(EN)_150  
–
–
0.2  
0.5  
1
1
µA  
V
TJ = 150°C  
DEN = "high"  
IL = 0 A  
See Figure 21  
1)  
PRQ-211  
PRQ-212  
when enabled at TJ = 150 °C  
SENSE Signal Saturation  
Voltage for kILIS operation  
(VS-VIS)  
VSIS_k  
VS = 6 V  
EN = IN =DEN ="high"  
IL ≤ 1.5 * IL(NOM)  
Power supply to IS  
pin clamping voltage at  
TJ = -40°C  
VIS(CLAMP)_-40  
33  
35  
36.5 42  
V
V
IIS = 1 mA  
TJ = -40 °C  
See Figure 19  
2)  
PRQ-215  
PRQ-216  
Power supply to IS  
pin clamping voltage at  
TJ = 25°C  
VIS(CLAMP)_25  
38  
44  
IIS = 1 mA  
TJ ≥ 25 °C  
See Figure 19  
Electrical characteristics diagnosis  
SENSE fault current  
IIS(FAULT)  
4.4  
1.9  
30  
5.5  
2.5  
70  
10  
mA  
mA  
µs  
See Figure 22 and  
PRQ-217  
PRQ-218  
Figure 23  
SENSE open load in OFF  
current  
IIS(OLOFF)  
tIS(OLOFF)_D  
3.5  
120  
See Figure 22 and  
Figure 23  
SENSE open load in OFF  
delay time  
VDS < VOL(OFF) from EN PRQ-219  
falling edge to IIS  
IS(OLOFF),MIN * 0.9  
=
DEN = "high"  
latch = 0  
See Figure 24  
Open load VDS detection  
threshold in OFF state  
VDS(OLOFF)  
1.3  
1.8  
2.3  
V
See Figure 23  
PRQ-221  
(table continues...)  
Datasheet  
38  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
Table 14  
(continued) Electrical characteristics diagnosis  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
SENSE settling time with  
tsIS(ON)  
–
5
20  
µs  
µs  
IL = IL(CAL) from DEN  
rising edge to IIS = IL /  
(kILIS,MAX @ IL) * 0.9  
See Figure 25  
1)  
PRQ-222  
nominal load current stable  
SENSE settling time with  
small load current stable  
tsIS(ON)_SLC  
–
–
60  
PRQ-223  
IL = IL(CAL)_OL from DEN  
rising edge to IIS = IL /  
(kILIS,MAX @ IL) * 0.9  
See Figure 26  
1)  
SENSE disable time  
tsIS(OFF)  
–
–
5
5
20  
20  
µs  
µs  
PRQ-224  
PRQ-225  
From DEN falling edge  
to IIS = IIS(OFF)  
See Figure 25  
1)  
SENSE settling time aꢀer  
load change  
tsIS(LC)  
From IL = IL(CAL)_L  
to IL = IL(CAL) (see  
ΔkILIS(NOM)  
)
See Figure 25  
1)  
SENSE settling time aꢀer  
load change with small load  
current  
tsIS(LC)_SLC  
–
250  
400  
µs  
PRQ-226  
DEN = "high" from  
Load Change to  
IIS = IL / (kILIS @ IL)  
from IL(CAL) to IL(CAL)_OL  
See Figure 26  
Diagnosis power output stage - 15 mΩ high-side  
Open load output current at IL(OL)_4u  
IIS= 4 µA  
8
21  
35  
mA  
IIS = IIS(OL) = 4 µA  
See Figure 21  
PRQ-227  
Current sense ratio at  
IL=IL02  
kILIS02  
kILIS05  
kILIS08  
kILIS11  
kILIS14  
kILIS16  
-50% 4300 +50%  
-42% 4300 +42%  
-40% 4300 +40%  
-25% 4300 +25%  
-8% 4300 +8%  
-6% 4300 +6%  
IL02 = 20 mA  
IL05 = 100 mA  
IL08 = 250 mA  
IL11 = 1 A  
PRQ-232  
PRQ-235  
PRQ-238  
PRQ-241  
PRQ-244  
PRQ-246  
Current sense ratio at  
IL=IL05  
Current sense ratio at  
IL=IL08  
Current sense ratio at  
IL=IL11  
Current sense ratio at  
IL=IL14  
IL14 = 2.8 A  
IL16 = 5.5 A  
Current sense ratio at  
IL=IL16  
(table continues...)  
Datasheet  
39  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Diagnosis  
Table 14  
(continued) Electrical characteristics diagnosis  
VS = 6 V to 18 V, TJ = -40°C to +150°C; Typical values: VS = 13.5 V, TJ = 25°C  
Typical resistive load connected to the output for testing (unless otherwise specified): Rload = 3.3 Ω  
all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)  
Parameter  
Symbol  
Values  
Unit Note or condition  
P-Number  
Min. Typ. Max.  
-5% 4300 +5%  
1)  
Current sense ratio at  
IL=IL18  
kILIS18  
PRQ-248  
PRQ-249  
IL18 = 10 A  
1)  
SENSE Current Derating  
with Low Current  
Calibration  
ΔkILIS(OL)  
-30  
0
0
+30  
%
IL(CAL)_OL = IL05  
IL(CAL)_OL_H = IL08  
IL(CAL)_OL_L = IL02  
TA(CAL) = 25°C  
1)  
SENSE Current Derating  
with Nominal Current  
Calibration  
ΔkILIS(NOM)  
-4  
+4  
%
PRQ-250  
IL(CAL) = IL16  
IL(CAL)_H = IL18  
IL(CAL)_L = IL14  
TA(CAL) = 25°C  
1) Not subject to production test - specified by design  
2) Tested at TJ = 150°C  
Datasheet  
40  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Application information  
9
Application information  
Note:  
The following information is given as a hint for the implementation of the device only and shall not be  
regarded as a description or warranty of a certain functionality, condition or quality of the device.  
9.1  
Application setup  
TREV  
VS  
CVS  
DZ2  
VDD  
VDD  
VS  
BTN7030  
RIN  
REN  
ROL  
IN  
GPIO  
GPIO  
GPIO  
EN  
DEN  
OUT  
RDEN  
M
COUT  
RPD  
Microcontroller  
RA/D  
RIS_PROT  
IS  
ADC  
VSS  
GND  
CSENSE  
RSENSE  
DZ1  
Figure 27  
BTN7030-1EPA application diagram  
Note:  
This is a very simplified example of an application circuit. The function must be verified in the real  
application.  
9.2  
External components  
Table 15  
Suggested component values  
Reference Value  
Purpose  
REN  
RIN  
4.7 kΩ  
Protection of the microcontroller and device during overvoltage and during loss of  
ground.  
RDEN  
RPD  
47 kΩ  
1.5 kΩ  
100 nF  
Output polarization (pull-down, optional)  
Allows to detect if the OUT pin is shorted to VS.  
ROL  
Output polarization (pull-up, optional)  
Ensure polarization of BTN7030-1EPA output during open load in OFF diagnosis.  
COUT  
Protection of BTN7030-1EPA output during ESD events and BCI.  
(table continues...)  
Datasheet  
41  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Application information  
Table 15  
(continued) Suggested component values  
T1  
BC 807  
Switch the battery voltage for open load in OFF diagnosis. (optional)  
Filtering of voltage spikes on the battery line.  
Protection of BTN7030-1EPA during reverse polarity.  
Suppressor diode  
CVS  
TREV  
DZ2  
100 nF  
-
33 V Z-  
Diode  
Protection during overvoltage and in case of loss of battery while driving an inductive  
load.  
RSENSE  
1.2 kΩ  
4.7 kΩ  
SENSE resistor  
RIS_PROT  
Protection during overvoltage, reverse polarity, loss of ground.  
Value to be tuned according to microcontroller specifications, together with RA/D  
.
DZ1  
7 V Z-  
Diode  
Protection of the microcontroller during overvoltage.  
(Optional, depending on the microcontroller’s specification)  
RA/D  
4.7 kΩ  
Protection of microcontroller ADC input during overvoltage, reverse polarity, loss of  
ground.  
Value to be tuned according to microcontroller specifications, together with RIS_PROT  
.
CSENSE  
220 pF  
Sense signal filtering  
A time constant (RA/D ⋅ CSENSE) longer than 1 µs is recommended.  
The stray inductances have to be minimized in the power bridge design as it is necessary in all switched high  
power bridges. Therefore it is recommended to ensure that the offset between the BTN7030-1EPA’s ground  
(GND pin) and the microcontroller’s (signal) ground is minimized.  
It is recommended to do the freewheeling in the high-side path until the load current is 0, to avoid reverse  
currents through the low-side power stage, thus minimizing power dissipation and avoid an unnecessary stress  
of the device.  
If used in full bridge configuration, it is strongly recommended to change the direction of a motor not before the  
motor fully stopped thus motor current is 0 A, in order to avoid overvoltage at OUT due to back EMF, e.g. in load  
dump situations.  
If the load also can provide power to the device, e.g. a motor or inductance in generator mode, it is  
recommended not to use only a diode for reverse polarity but to allow a current flow back to the supply  
Vbat, to prevent the device from overvoltage situations. In such a scenario, the capacitor CVS between VS and  
GND pin has to be dimensioned accordingly.  
Note: The suggested component values above are determined for typical applications. Based on the application  
circuit and the used components connected to BTN7030-1EPA, it could be necessary to adjust the values above to  
stay below the maximum ratings for all components. (e.g. reverse battery, transients on battery, ...)  
9.3  
Bidirectional loads and open load in OFF detection  
A bidirectional load, like a motor or a solenoid, can be driven with two BTN7030-1EPA half-bridge in H-bridge  
configuration, as shown in Figure 28.  
In order to perform an open load in OFF detection, the high-side output stage of one half-bridge has to be  
switched on with IN = EN = "high" (right BTN7030-1EPA in Figure 28). As described in Chapter 8.3.1, and in  
combination with a pull-up resistor RPU (or alternatively a pull-down resistor RPD) the other half-bridge can  
check for open load condition.  
Datasheet  
42  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Application information  
VDD  
VS  
VDD  
TREV  
GPIO  
Microcontroller  
GPIO  
GPIO  
VSS  
RIN2  
CVS1  
DZ2  
CVS2  
RIN1  
REN2  
VS  
VS  
REN1  
BTN7030  
BTN7030  
RDEN2  
RDEN1  
IN  
IN  
EN  
EN  
OUT  
OUT  
M
DEN  
DEN  
COUT1  
COUT2  
RA/D  
RIS_PROT  
RPD  
IS  
IS  
GND  
GND  
CSENSE  
RSENSE  
DZ1  
Figure 28  
Note  
Application circuit: H-bridge with two BTN7030-1EPA  
This is a very simplified example of an application circuit. The function must be verified in the real application.  
9.4  
Further application information  
•
•
Please contact us for information regarding the Pin FMEA  
For further information you may contact http://www.infineon.com/  
Datasheet  
43  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
Package dimensions  
10  
Package dimensions  
1)  
4.9±0.1  
1)  
3.9±0.1  
D
0.1  
0.1  
2x  
2x  
C
0.08 C  
0.67±0.25  
14x  
SEATING COPLANARITY  
PLANE  
6±0.2  
0.2 D  
14x  
2)  
0.25±0.05  
0.25  
A-B C  
14x  
BOTTOMVIEW  
A
14  
8
8
14  
1
7
7
1
0.15  
0.15  
D
INDEX  
MARKING  
B
0.65  
4±0.1  
A-B  
1)DOES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF 0.15 MAX. PER SIDE  
2)DAMBAR PROTUSION SHALL BE MAXIMUM 0.1 MM TOTAL IN EXCESS OF LEAD WIDTH  
ALL DIMENSIONS ARE IN UNITS MM  
THE DRAWINGIS IN COMPLIANCE WITH ISO 128 & PROJECTION METHOD 1 [  
]
Figure 29  
PG-TSDSO-14 (thin (slim) dual small outline 14 pins) package outline  
Datasheet  
44  
1.2  
2021-06-24  
BTN7030-1EPA  
™
NovalithIC Lite – smart integrated half-bridge  
References  
0.65  
0.45  
0.65  
0.45  
1.075  
4
1.85  
copper  
solder mask  
stencil apertures  
ALL DIMENSIONS ARE IN UNITS MM  
Figure 30  
PG-TSDSO-14 (thin (slim) dual small outline 14 pins) package pads and stencil  
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with  
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e  
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).  
11  
References  
Revision history  
Table 16  
Revision history  
Document Date of  
Description of changes  
version  
release  
1.0  
2020-08-11 Initial release  
1.1  
2020-11-20 Chapter Open load current (IIS(OLOFF)): refined formulation for usage  
Chapter External components: refine explanation to RPD  
1.2  
2021-06-24 Block diagram updated  
Footnote links in table SENSE signal, function of application condition added  
Datasheet  
45  
1.2  
2021-06-24  
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Edition 2021-06-24  
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