C161RI_技术文档

Microcomputer Components

16-Bit CMOS Single-Chip Microcontroller

C161RI

Preliminary 05.98 Preliminary

C161RI

Revision History:

1998-05-01 Preliminary

Previous Releases:

1998-01 Advance Information

1997-12 Advance Information

Page

7

Subjects

XTAL pin numbers (MQFP) corrected.

34

V_DDMINcorrected, special threshold parameters added (V_ILS, V_IHS, HYS).

35, 37

41

Specification of I_IDOimproved.

ADCTC value in converter timing example timing corrected.

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

mcdocu.comments@siemens-scg.com

Edition 1998-05-01

Published by Siemens AG,

Bereich Halbleiter, Marketing-

Kommunikation, Balanstraße 73,

81541 München

©

Siemens AG 1998.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes

and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will

take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-

curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

1

2

Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems with the express

written approval of the Semiconductor Group of Siemens AG.

1

A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2

Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

C166-Family of

High-Performance CMOS 16-Bit Microcontrollers

C161RI

Preliminary

C161RI 16-Bit Microcontroller

● High Performance 16-bit CPU with 4-Stage Pipeline

● 125 ns Instruction Cycle Time at 16 MHz CPU Clock

● 625 ns Multiplication (16 × 16 bits), 1.25 µs Division (32 / 16 bit)

● Enhanced Boolean Bit Manipulation Facilities

● Additional Instructions to Support HLL and Operating Systems

● Register-Based Design with Multiple Variable Register Banks

● Single-Cycle Context Switching Support

● Clock Generation via Prescaler or via Direct Clock Input

● Up to 8 MBytes Linear Address Space for Code and Data

● 1 KByte On-Chip Internal RAM (IRAM)

● 2 KBytes On-Chip Extension RAM (XRAM)

● Programmable External Bus Characteristics for Different Address Ranges

● 8-Bit or 16-Bit External Data Bus

● Multiplexed or Demultiplexed External Address/Data Bus

● 5 Programmable Chip-Select Signals

● 1024 Bytes On-Chip Special Function Register Area

● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event

Controller (PEC)

● 16-Priority-Level Interrupt System, 11 External Interrupts

● 4-Channel 8-bit A/D Converter, conversion time down to 7.625 µs

● 2 Multi-Functional General Purpose Timer Units with five 16-bit Timers

● Synchronous/Asynchronous Serial Channel (USART)

● High-Speed Synchronous Serial Channel

● I²C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed)

● Up to 76 General Purpose I/O Lines

● Programmable Watchdog Timer

● On-Chip Real Time Clock

● Idle and Power Down Modes with Flexible Power Management

● Ambient temperature range – 40 to 85 °C

● Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler

Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer

Disassemblers, Programming Boards

● On-Chip Bootstraploader

● 100-Pin MQFP / TQFP Package

This document describes the SAB-C161RI-LM, the SAB-C161RI-LF, the SAF-C161RI-LM and the

SAB-C161RI-LF.

For simplicity all versions are referred to by the term C161RI throughout this document.

Semiconductor Group

3

1998-05-01

C161RI

Introduction

The C161RI is a new derivative of the Siemens C166 Family of 16-bit single-chip CMOS

microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with

high peripheral functionality and enhanced IO-capabilities. The C161RI derivative is especially

suited for cost sensitive applications.

V_{DD SS}V_AREFV_AGND

V

PORT0

16 bit

XTAL1

XTAL2

PORT1

16 bit

RSTIN

RSTOUT

Port 2

8 bit

NMI

EA

Port 3

15 bit

C161RI

Port 4

7 bit

ALE

RD

WR/WRL

Port 6

8 bit

Port 5

6 bit

Figure 1

Logic Symbol

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required

product. This ordering code identifies:

● the derivative itself, i.e. its function set

● the specified temperature range

● the package

● the type of delivery.

For the available ordering codes for the C161RI please refer to the

“Product Information Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Semiconductor Group

4

1998-05-01

C161RI

Pin Configuration MQFP Package

(top view)

P5.2/AN2

P5.3/AN3

P5.14/T4EUD

P5.15/T2EUD

1

2

3

4

5

6

7

8

NMI

RSTOUT

RSTIN

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

DD

V

SS

V

SS

XTAL1

XTAL2

P1H.7/A15

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

V

DD

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

C161RI

DD

P3.6/T3IN

P3.7/T2IN

V

SS

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

P3.8/MRST

P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT

V

SS

V

DD

P4.0/A16

P4.1/A17

P4.2/A18

P4.3/A19

P4.4/A20

Figure 2

Semiconductor Group

5

1998-05-01

C161RI

Pin Configuration TQFP Package

(top view)

P5.14/T4EUD

P5.15/T2EUD

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

1

2

3

4

5

6

7

8

DD

SS

V

P1H.7/A15

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

SS

XTAL1

XTAL2

V

DD

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V

DD

SS

P3.6/T3IN

P3.7/T2IN

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

C161RI

P3.8/MRST

P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P3.15/CLKOUT

V

SS

V

DD

P4.0/A16

P4.1/A17

Figure 3

Semiconductor Group

6

1998-05-01

C161RI

Pin Definitions and Functions

Symbol Pin No. Pin No. Input Function

TQFP MQFP Outp

P5.0 –

P5.3,

P5.14 – 1 –

97 –

100,

99 –

2,

3 –

4

I

Port 5 is a 6-bit input-only port with Schmitt-Trigger

characteristics. The pins of Port 5 also serve as the (up to 4)

analog input channels for the A/D converter, where P5.x

equals ANx (Analog input channel x, x=0...3).

P5.15

2

The following pins of Port 5 also serve as timer inputs:

P5.14

P5.15

T4EUD

T2EUD

GPT1 Timer T4 Ext.Up/Down Ctrl.Input

GPT1 Timer T5 Ext.Up/Down Ctrl.Input

XTAL1

XTAL2

4

5

6

7

I

XTAL1:

Input to the oscillator amplifier and input to the

internal clock generator

Output of the oscillator amplifier circuit.

O

XTAL2:

To clock the device from an external source, drive XTAL1,

while leaving XTAL2 unconnected. Minimum and maximum

high/low and rise/fall times specified in the AC

Characteristics must be observed.

P3.0 –

P3.13,

P3.15

7 –

20,

21

9 –

22,

23

I/O

Port 3 is a 15-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

The following Port 3 pins also serve for alternate functions:

7

8

9

10

11

12

9

I/O

I

O

I

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

SCL0

I²C Bus Clock Line 0

10

11

12

13

14

SDA0

CAPIN

T3OUT

T3EUD

T4IN

I²C Bus Data Line 0

GPT2 Register CAPREL Capture Input

GPT1 Timer T3 Toggle Latch Output

GPT1 Timer T3 Ext.Up/Dwn Ctrl.Input

GPT1 Timer T4 Input for

I

Count/Gate/Reload/Capture

13

14

15

16

I

P3.6

P3.7

T3IN

T2IN

GPT1 Timer T3 Count/Gate Input

GPT1 Timer T2 Input for

Count/Gate/Reload/Capture

15

16

17

18

19

17

18

19

20

21

I/O

O

I/O

O

I/O

O

P3.8

P3.9

P3.10

P3.11

P3.12

MRST

MTSR

T×D0

R×D0

BHE

SSC Master-Rec./Slave-Transmit I/O

SSC Master-Transmit/Slave-Rec. O/I

ASC0 Clock/Data Output (Asyn./Syn.)

ASC0 Data Input (Asyn.) or I/O (Syn.)

Ext. Memory High Byte Enable Signal,

Ext. Memory High Byte Write Strobe

SSC Master Clock Outp./Slave Cl. Inp.

WRH

SCLK

20

21

22

23

P3.13

P3.15

Note:

CLKOUT System Clock Output (=CPU Clock)

Pins P3.0 and P3.1 are open drain outputs only.

Semiconductor Group

7

1998-05-01

C161RI

Pin Definitions and Functions (cont’d)

Symbol Pin No. Pin No. Input Function

TQFP MQFP Outp

P4.0 –

P4.6

24 –

30

26 -

32

I/O

Port 4 is a 7-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

In case of an external bus configuration, Port 4 can be used

to output the segment address lines:

24

...

30

26

...

32

O

...

O

P4.0

...

P4.6

A16

...

A22

Least Significant Segment Addr. Line

...

Most Significant Segment Addr. Line

RD

31

33

O

External Memory Read Strobe. RD is activated for every

external instruction or data read access.

WR/WRL 32

READY 33

34

O

External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL-mode

this pin is activated for low byte data write accesses on a 16-

bit bus, and for every data write access on an 8-bit bus. See

WRCFG in register SYSCON for mode selection.

35

I

Ready Input. When the Ready function is enabled, a high

level at this pin during an external memory access will force

the insertion of memory cycle time waitstates until the pin

returns to a low level.

ALE

EA

34

35

36

37

O

I

Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the

multiplexed bus modes.

External Access Enable pin. A low level at this pin during and

after Reset forces the C161RI to begin instruction execution

out of external memory. A high level forces execution out of

the internal ROM. The C161RI must have this pin tied to ‘0’.

Note: This pin is expected to be used to accept the

programming voltage for OTP versions of the C161RI.

Semiconductor Group

8

1998-05-01

C161RI

Pin Definitions and Functions (cont’d)

Symbol Pin No. Pin No. Input Function

TQFP MQFP Outp

PORT0:

P0L.0 – 38 –

P0L.7,

P0H.0 - 48 –

P0H.7

I/O

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of external bus configurations, PORT0 serves as the

address (A) and address/data (AD) bus in multiplexed bus

modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

40 –

47,

50 –

57

45,

55

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

D0 – D7

I/O

16-bit

D0 - D7

D8 - D15

Multiplexed bus modes:

Data Path Width:

P0L.0 – P0L.7:

P0H.0 – P0H.7:

8-bit

AD0 – AD7

A8 - A15

16-bit

AD0 - AD7

AD8 - AD15

PORT1:

I/O

PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state. PORT1 is used as the 16-

bit address bus (A) in demultiplexed bus modes and also

after switching from a demultiplexed bus mode to a

multiplexed bus mode.

P1L.0 – 56 –

P1L.7, 63,

P1H.0 - 66 –

58 -

65,

68 -

75

P1H.7

73

RSTIN

76

78

I

Reset Input with Schmitt-Trigger characteristics. A low level

at this pin for a specified duration while the oscillator is

running resets the C161RI. An internal pullup resistor permits

power-on reset using only a capacitor connected to V_SS.

In bidirectional reset mode (enabled by setting bit BDRSTEN

in register SYSCON) the RSTIN line is internally pulled low

for the duration of the internal reset sequence upon a

software reset, a WDT reset and a hardware reset. ¹⁾

RSTOUT 77

79

80

O

I

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or

a watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

78

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI

pin must be low in order to force the C161RI to go into power

down mode. If NMI is high, when PWRDN is executed, the

part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

Semiconductor Group

9

1998-05-01

C161RI

Pin Definitions and Functions (cont’d)

Symbol Pin No. Pin No. Input Function

TQFP MQFP Outp

P6.0 –

P6.7

79 –

86

81 –

88

I/O

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

The Port 6 pins also serve for alternate functions:

79

...

81

...

O

...

P6.0

...

CS0

...

Chip Select 0 Output

...

83

84

85

86

85

86

87

88

O

P6.4

P6.5

P6.6

P6.7

Note:

CS4

SDA1

SCL1

SDA2

Chip Select 4 Output

I²C Bus Data Line 1

I²C Bus Clock Line 1

I²C Bus Data Line 2

I/O

Pins P6.5-P6.7 are open drain outputs only.

P2.8 –

P2.15

87 –

94

89 –

96

I/O

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

The following Port 2 pins also serve for alternate functions:

87

...

94

89

...

96

I

...

I

P2.8

...

P2.15

EX0IN

...

EX7IN

Fast External Interrupt 0 Input

...

Fast External Interrupt 7 Input

V_AREF

V_AGND

V_DD

95

96

97

98

-

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

6, 23, 8, 25,

37, 47, 39, 49,

65, 75 67, 77

Digital Supply Voltage:

+ 5 V during normal operation and idle mode.

≥ 2.5 V during power down mode

V_SS

3, 22, 5, 24,

36, 46, 38, 48,

64, 74 66, 76

-

Digital Ground.

¹⁾The following behavior differences must be observed when the bidirectional reset is active:

● Bit BDRSTEN in register SYSCON cannot be changed after EINIT.

● After a reset bit BDRSTEN is cleared.

● The reset indication flags always indicate a long hardware reset.

● The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader

may be activated when P0L.4 is low.

● Pin RSTIN may only be connected to external reset devices with an open drain output driver.

● A short hardware reset is extended to the duration of the internal reset sequence.

Semiconductor Group

10

1998-05-01

C161RI

Functional Description

The C161RI is a low cost downgrade of the high performance microcontroller C167CR with OTP or

internal ROM, reduced peripheral functionality and a high performance Capture Compare Unit with

an additional functionality.

The architecture of the C161RI combines advantages of both RISC and CISC processors and of

advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an

overview of the different on-chip components and of the advanced, high bandwidth internal bus

structure of the C161RI.

Note: All time specifications refer to a CPU clock of 16 MHz

(see definition in the AC Characteristics section).

&ꢁꢂꢂꢃ&RUH

ꢀꢁ

&38ꢀ&RUH

&38

3(&

,QWHUUXSWꢂ&RQWUROOHU

Figure 4

Block Diagram

Semiconductor Group

11

1998-05-01

C161RI

Memory Organization

The memory space of the C161RI is configured in a Von Neumann architecture which means that

code memory, data memory, registers and I/O ports are organized within the same linear address

space which includes 16 MBytes. The entire memory space can be accessed bytewise or

wordwise. Particular portions of the on-chip memory have additionally been made directly

bitaddressable.

1 KByte of on-chip Internal RAM is provided as a storage for user defined variables, for the system

stack, general purpose register banks and even for code. A register bank can consist of up to 16

wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose

Registers (GPRs).

1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register

areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling

and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for

future members of the C166 family.

In order to meet the needs of designs where more memory is required than is provided on chip, up

to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller.

Semiconductor Group

12

1998-05-01

C161RI

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller

(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or

to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for

input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory

Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the

user the adaption of a wide range of different types of memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /

BUSCONx) which allow to access different resources with different bus characteristics. These

address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and

BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows

are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue

logic. Access to very slow memories is supported via a particular ‘Ready’ function.

For applications which require less than 8 MBytes of external memory space, this address space

can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no

address lines at all. It outputs all 7 address lines, if an address space of 8 MBytes is used.

Semiconductor Group

13

1998-05-01

C161RI

Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit

(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide

unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161RI’s instructions can be executed in just one

machine cycle which requires 125 ns at 16 MHz CPU clock. For example, shift and rotate

instructions are always processed during one machine cycle independent of the number of bits to

be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast

as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in

10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution

time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

CPU

16

Internal

RAM

SP

STKOV

STKUN

MDH

MDL

R15

Exec. Unit

Instr. Ptr.

Instr. Reg.

Mul/Div-HW

Bit-Mask Gen

General

Purpose

Registers

R15

ALU

32

4-Stage

Pipeline

(16-bit)

ROM

Barrel - Shifter

Context Ptr.

R0

PSW

SYSCON

BUSCON 0

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

16

R0

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

Data Page Ptr.

Code Seg. Ptr.

MCB02147

Figure 5

CPU Block Diagram

Semiconductor Group

14

1998-05-01

C161RI

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are

physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the

base address of the active register bank to be accessed by the CPU at a time. The number of

register banks is only restricted by the available internal RAM space. For easy parameter passing,

a register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack

is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)

register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack

pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized

by a programmer via the highly efficient C161RI instruction set which includes the following

instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.

A variety of direct, indirect or immediate addressing modes are provided to specify the required

operands.

Semiconductor Group

15

1998-05-01

C161RI

Interrupt System

With an interrupt response time within a range from just 315 ns to 750 ns (in case of internal

program execution), the C161RI is capable of reacting very fast to the occurrence of non-

deterministic events.

The architecture of the C161RI supports several mechanisms for fast and flexible response to

service requests that can be generated from various sources internal or external to the

microcontroller. Any of these interrupt requests can be programmed to being serviced by the

Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and

a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU

activity to perform a PEC service. A PEC service implies a single byte or word data transfer between

any two memory locations with an additional increment of either the PEC source or the destination

pointer. An individual PEC transfer counter is implicity decremented for each PEC service except

when performing in the continuous transfer mode. When this counter reaches zero, a standard

interrupt is performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data. The C161RI

has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an

interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each

source can be programmed to one of sixteen interrupt priority levels. Once having been accepted

by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For

the standard interrupt processing, each of the possible interrupt sources has a dedicated vector

location.

Fast external interrupt inputs are provided to service external interrupts with high precision

requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling

edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number.

Semiconductor Group

16

1998-05-01

C161RI

The following table shows all of the possible C161RI interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Source of Interrupt or

PEC Service Request

Request

Flag

Enable

Flag

Interrupt

Vector

Location

Trap

Number

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

External Interrupt 7

GPT1 Timer 2

CC8IR

CC9IR

CC10IR

CC11IR

CC12IR

CC13IR

CC14IR

CC15IR

T2IR

CC8IE

CC9IE

CC10IE

CC11IE

CC12IE

CC13IE

CC14IE

CC15IE

T2IE

CC8INT

CC9INT

CC10INT

CC11INT

CC12INT

CC13INT

CC14INT

CC15INT

T2INT

00’0060_H

00’0064_H

00’0068_H

00’006C_H

00’0070_H

00’0074_H

00’0078_H

00’007C_H

00’0088_H

00’008C_H

00’0090_H

00’0094_H

00’0098_H

00’009C_H

00’00A0_H

00’00A4_H

00’00A8_H

00’011C_H

00’00AC_H

00’00B0_H

00’00B4_H

00’00B8_H

00’00BC_H

00’0100_H

00’0104_H

00’0108_H

00’010C_H

18_H

19_H

1A_H

1B_H

1C_H

1D_H

1E_H

1F_H

22_H

23_H

24_H

25_H

26_H

27_H

28_H

29_H

2A_H

47_H

2B_H

2C_H

2D_H

2E_H

2F_H

40_H

41_H

42_H

43_H

GPT1 Timer 3

T3IR

T3IE

T3INT

GPT1 Timer 4

T4IR

T4IE

T4INT

GPT2 Timer 5

T5IR

T5IE

T5INT

GPT2 Timer 6

T6IR

T6IE

T6INT

GPT2 CAPREL Register CRIR

A/D Conversion Complete ADCIR

CRIE

CRINT

ADCIE

ADEIE

S0TIE

S0TBIE

S0RIE

S0EIE

SCTIE

SCRIE

SCEIE

XP0IE

XP1IE

XP2IE

XP3IE

ADCINT

ADEINT

S0TINT

S0TBINT

S0RINT

S0EINT

SCTINT

SCRINT

SCEINT

XP0INT

XP1INT

XP2INT

XP3INT

A/D Overrun Error

ASC0 Transmit

ASC0 Transmit Buffer

ASC0 Receive

ADEIR

S0TIR

S0TBIR

S0RIR

S0EIR

SCTIR

SCRIR

SCEIR

XP0IR

XP1IR

XP2IR

XP3IR

ASC0 Error

SSC Transmit

SSC Receive

SSC Error

I²C Data Transfer Event

I²C Protocol Event

X-Peripheral Node 2

PLL Unlock / RTC

Semiconductor Group

17

1998-05-01

C161RI

The C161RI also provides an excellent mechanism to identify and to process exceptions or error

conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate

non-maskable system reaction which is similar to a standard interrupt service (branching to a

dedicated vector table location). The occurence of a hardware trap is additionally signified by an

individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in

progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap

services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-

time:

Exception Condition

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

Hardware Reset

Software Reset

Watchdog Timer Overflow

RESET

00’0000_H

00_H

III

Class A Hardware Traps:

Non-Maskable Interrupt

Stack Overflow

NMI

STKOF

STKUF

NMITRAP 00’0008_H

STOTRAP 00’0010_H

STUTRAP 00’0018_H

02_H

04_H

06_H

II

Stack Underflow

Class B Hardware Traps:

Undefined Opcode

Protected Instruction

Fault

UNDOPC BTRAP

00’0028_H

0A_H

I

PRTFLT

BTRAP

Illegal Word Operand

Access

ILLOPA

BTRAP

00’0028_H

0A_H

I

Illegal Instruction Access

Illegal External Bus

Access

ILLINA

ILLBUS

BTRAP

00’0028_H

0A_H

I

Reserved

[2C_H– 3C_H] [0B_H– 0F_H]

Any Any

Software Traps

Current

TRAP Instruction

[00’0000_H– [00_H– 7F_H] CPU

00’01FC_H]

in steps

of 4_H

Priority

Semiconductor Group

18

1998-05-01

C161RI

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used

for many different time related tasks such as event timing and counting, pulse width and duty cycle

measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1

and GPT2. Each timer in each module may operate independently in a number of different modes,

or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four

basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode.

In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable

prescaler, while Counter Mode allows a timer to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of

a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has

one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the

timers in module GPT1 is 500 ns (@ 16 MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be

altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the

incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction

and count signals are internally derived from these two input signals, so the contents of the

respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can

be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/

underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring

of external hardware components, or may be used internally to clock timers T2 and T4 for

measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture

registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The

contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins

(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or

by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to

alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM

signal, this signal can be constantly generated without software intervention.

With its maximum resolution of 250 ns (@ 16 MHz), the GPT2 module provides precise event

control and time measurement. It includes two timers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via

a programmable prescaler. The count direction (up/down) for each timer is programmable by

software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,

which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can

additionally be used to cause a reload from the CAPREL register. The CAPREL register may

capture the contents of timer T5 based on an external signal transition on the corresponding port pin

Semiconductor Group

19

1998-05-01

C161RI

(CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute

time differences to be measured or pulse multiplication to be performed without software overhead.

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer

T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental

Interface Mode.

U/D

T2EUD

Interrupt

Request

GPT1 Timer T2

CPU Clock

2ⁿn = 3...10

T2

Mode

Control

Reload

T2IN

Capture

CPU Clock

2ⁿn = 3...10

Toggle FF

T3OTL

T3

Mode

Control

GPT1 Timer T3

T3IN

U/D

T3EUD

Interrupt

Request

Capture

Reload

T4

Mode

Control

T4IN

CPU Clock

2ⁿn = 3...10

Interrupt

Request

GPT1 Timer T4

U/D

T4EUD

MCB02141

Figure 6

Block Diagram of GPT1

Semiconductor Group

20

1998-05-01

C161RI

CPU

Clock

T5

Mode

Control

2ⁿn=2...9

Interrupt

Request

GPT2 Timer T5

Clear

Capture

CAPIN

Interrupt

Request

GPT2 CAPREL

GPT2 Timer T6

Interrupt

Request

CPU

Clock

T6

Mode

Control

2ⁿn=2...9

T6OTL

Figure 7

Block Diagram of GPT2

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to

prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time

interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up

procedure is always monitored. The software has to be designed to service the Watchdog Timer

before it overflows. If, due to hardware or software related failures, the software fails to do so, the

Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low

in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.

The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in

WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced

by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals

between 31 µs and 525 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval

after reset is 8.2 ms (@ 16 MHz).

Semiconductor Group

21

1998-05-01

C161RI

Real Time Clock

The Real Time Clock (RTC) module of the C161RI consists of a chain of 3 divider blocks, a fixed

8-bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers

RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided

by 32 via a separate clock driver and is therefore independent from the selected clock generation

mode of the C161RI. All timers count up.

The RTC module can be used for different purposes:

● System clock to determine the current time and date

● Cyclic time based interrupt

● 48-bit timer for long term measurements

T14REL

Reload

f_RTC

T14

8:1

Interrupt

Request

RTCL

Figure 7-1

RTC Block Diagram

Note: The registers associated with the RTC are not effected by a reset in order to maintain the

correct system time even when intermediate resets are executed.

Semiconductor Group

22

1998-05-01

C161RI

A/D Converter

For analog signal measurement, an 8-bit A/D converter with 4 multiplexed input channels and a

sample and hold circuit has been integrated on-chip. It uses the method of successive

approximation. The sample time (for loading the capacitors) and the conversion time is

programmable and can so be adjusted to the external circuitry.

Overrun error detection is provided for the conversion result register (ADDAT): an interrupt request

will be generated when the result of a previous conversion has not been read from the result register

at the time the next conversion is complete.

For applications which require less than 4 analog input channels, the remaining channel inputs can

be used as digital input port pins.

The A/D converter of the C161RI supports two different conversion modes. In the standard Single

Channel conversion mode, the analog level on a specified channel is sampled once and converted

to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel

is repeatedly sampled and converted without software intervention.

The 8-bit result can be left-aligned or right-aligned within a 10-bit result area.

The Peripheral Event Controller (PEC) may be used to automatically store the conversion results

into a table in memory for later evaluation, without requiring the overhead of entering and exiting

interrupt routines for each data transfer.

I²C Module

The integrated I²C Bus Module handles the transmission and reception of frames over the two-line

I²C bus in accordance with the I²C Bus specification. The on-chip I²C Module can receive and

transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or

in multi-master mode.

Several physical interfaces (port pins) can be established under software control. Data can be

transferred at speeds up to 400 Kbit/sec.

Two interrupt nodes dedicated to the I²C module allow efficient interrupt service and also support

operation via PEC transfers.

Note: The port pins associated with the I²C interfaces feature open drain drivers only, as required

by the I²C specification.

Semiconductor Group

23

1998-05-01

C161RI

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral

components is provided by two serial interfaces with different functionality, an Asynchronous/

Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families

and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex

synchronous communication at up to 2 MBaud @ 16 MHz CPU clock.

A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.

For transmission, reception and error handling 4 separate interrupt vectors are provided. In

asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and

terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish

address from data bytes has been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock

which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is

available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase the

reliability of data transfers. A parity bit can automatically be generated on transmission or be

checked on reception. Framing error detection allows to recognize data frames with missing stop

bits. An overrun error will be generated, if the last character received has not been read out of the

receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock.

It may be configured so it interfaces with serially linked peripheral components. A dedicated baud

rate generator allows to set up all standard baud rates without oscillator tuning. For transmission,

reception and error handling 3 separate interrupt vectors are provided.

The SSC transmits or receives characters of 2…16 bits length synchronously to a shift clock which

can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can

start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock

edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase the

reliability of data transfers. Transmit and receive error supervise the correct handling of the data

buffer. Phase and baudrate error detect incorrect serial data.

Semiconductor Group

24

1998-05-01

C161RI

Parallel Ports

The C161RI provides up to 76 IO lines which are organized into six input/output ports and one input

port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)

programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports

which are switched to high impedance state when configured as inputs. The output drivers of three

IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control

registers. The other IO ports operate in push/pull mode, except for the I²C interface pins which are

open drain pins only. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them.

PORT0 and PORT1 may be used as address and data lines when accessing external memory,

while Port 4 outputs the additional segment address bits A22/19/17...A16 in systems where

segmentation is enabled to access more than 64 KBytes of memory.

Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE

and the system clock output (CLKOUT).

Port 5 is used for the analog input channels to the A/D converter or timer control signals.

Port 6 provides the optional chip select signals and interface lines for the I²C module.

All port lines that are not used for these alternate functions may be used as general purpose IO

lines.

Semiconductor Group

25

1998-05-01

C161RI

Instruction Set Summary

The table below lists the instructions of the C161RI in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation of the

instructions, parameters for conditional execution of instructions, and the opcodes for each

instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Instruction Set Summary

Mnemonic

ADD(B)

Description

Bytes

2 / 4

2

Add word (byte) operands

ADDC(B)

SUB(B)

Add word (byte) operands with Carry

Subtract word (byte) operands

SUBC(B)

MUL(U)

DIV(U)

Subtract word (byte) operands with Carry

(Un)Signed multiply direct GPR by direct GPR (16-16-bit)

(Un)Signed divide register MDL by direct GPR (16-/16-bit)

(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)

Complement direct word (byte) GPR

Negate direct word (byte) GPR

2

DIVL(U)

CPL(B)

2

NEG(B)

AND(B)

2

Bitwise AND, (word/byte operands)

Bitwise OR, (word/byte operands)

Bitwise XOR, (word/byte operands)

Clear direct bit

2 / 4

2

OR(B)

XOR(B)

BCLR

BSET

Set direct bit

2

BMOV(N)

BAND, BOR, BXOR

BCMP

Move (negated) direct bit to direct bit

AND/OR/XOR direct bit with direct bit

Compare direct bit to direct bit

4

BFLDH/L

Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data

4

CMP(B)

CMPD1/2

CMPI1/2

PRIOR

Compare word (byte) operands

2 / 4

2

Compare word data to GPR and decrement GPR by 1/2

Compare word data to GPR and increment GPR by 1/2

Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR

SHL / SHR

ROL / ROR

ASHR

Shift left/right direct word GPR

2

Rotate left/right direct word GPR

Arithmetic (sign bit) shift right direct word GPR

Semiconductor Group

26

1998-05-01

C161RI

Instruction Set Summary (cont’d)

Mnemonic

MOV(B)

Description

Bytes

Move word (byte) data

2 / 4

MOVBS

Move byte operand to word operand with sign extension

Move byte operand to word operand. with zero extension

Jump absolute/indirect/relative if condition is met

Jump absolute to a code segment

2 / 4

MOVBZ

2 / 4

4

JMPA, JMPI, JMPR

JMPS

4

J(N)B

Jump relative if direct bit is (not) set

4

JBC

Jump relative and clear bit if direct bit is set

Jump relative and set bit if direct bit is not set

Call absolute/indirect/relative subroutine if condition is met

Call absolute subroutine in any code segment

4

JNBS

4

CALLA, CALLI, CALLR

CALLS

4

PCALL

Push direct word register onto system stack and call

absolute subroutine

4

TRAP

Call interrupt service routine via immediate trap number

Push/pop direct word register onto/from system stack

2

4

PUSH, POP

SCXT

Push direct word register onto system stack and update

register with word operand

RET

Return from intra-segment subroutine

Return from inter-segment subroutine

2

RETS

RETP

Return from intra-segment subroutine and pop direct

word register from system stack

RETI

Return from interrupt service subroutine

Software Reset

2

4

SRST

IDLE

Enter Idle Mode

PWRDN

Enter Power Down Mode

(supposes NMI-pin being low)

SRVWDT

DISWDT

EINIT

Service Watchdog Timer

4

Disable Watchdog Timer

4

Signify End-of-Initialization on RSTOUT-pin

Begin ATOMIC sequence

4

ATOMIC

EXTR

2

Begin EXTended Register sequence

Begin EXTended Page (and Register) sequence

Begin EXTended Segment (and Register) sequence

Null operation

2

EXTP(R)

EXTS(R)

NOP

2 / 4

2

Semiconductor Group

27

1998-05-01

C161RI

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C161RI in alphabetical order.

Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended

SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within

on-chip X-Peripherals (I²C) are marked with the letter “X” in column “Physical Address”.

An SFR can be specified via its individual mnemonic name. Depending on the selected addressing

mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its

short 8-bit address (without using the Data Page Pointers).

Name

Physical 8-Bit

Address Address

Description

Reset

Value

ADCIC

b FF98_H

CC_H

A/D Converter End of Conversion Interrupt

Control Register

0000_H

ADCON

ADDAT

b FFA0_H

D0_H

50_H

0C_H

0D_H

0E_H

0F_H

CD_H

A/D Converter Control Register

A/D Converter Result Register

Address Select Register 1

Address Select Register 2

Address Select Register 3

Address Select Register 4

0000_H

FEA0_H

ADDRSEL1 FE18_H

ADDRSEL2 FE1A_H

ADDRSEL3 FE1C_H

ADDRSEL4 FE1E_H

ADEIC

b FF9A_H

A/D Converter Overrun Error Interrupt Control

Register

BUSCON0 b FF0C_H

BUSCON1 b FF14_H

BUSCON2 b FF16_H

BUSCON3 b FF18_H

BUSCON4 b FF1A_H

86_H

8A_H

8B_H

8C_H

8D_H

25_H

C4_H

C5_H

C6_H

C7_H

C8_H

C9_H

CA_H

CB_H

08_H

Bus Configuration Register 0

0000_H

FC00_H

Bus Configuration Register 1

Bus Configuration Register 2

Bus Configuration Register 3

Bus Configuration Register 4

CAPREL

CC8IC

CC9IC

CC10IC

CC11IC

CC12IC

CC13IC

CC14IC

CC15IC

CP

FE4A_H

b FF88_H

b FF8A_H

b FF8C_H

b FF8E_H

b FF90_H

b FF92_H

b FF94_H

b FF96_H

FE10_H

GPT2 Capture/Reload Register

External Interrupt 0 Control Register

External Interrupt 1 Control Register

External Interrupt 2 Control Register

External Interrupt 3 Control Register

External Interrupt 4 Control Register

External Interrupt 5 Control Register

External Interrupt 6 Control Register

External Interrupt 7 Control Register

CPU Context Pointer Register

Semiconductor Group

28

1998-05-01

C161RI

Name

Physical 8-Bit

Address Address

Description

Reset

Value

CRIC

CSP

b FF6A_H

FE08_H

B5_H

04_H

GPT2 CAPREL Interrupt Control Register

0000_H

CPU Code Segment Pointer Register

(8 bits, not directly writeable)

DP0L

DP0H

DP1L

DP1H

DP2

b F100_HE 80_H

b F102_HE 81_H

b F104_HE 82_H

b F106_HE 83_H

P0L Direction Control Register

P0H Direction Control Register

P1L Direction Control Register

P1H Direction Control Register

Port 2 Direction Control Register

Port 3 Direction Control Register

Port 4 Direction Control Register

Port 6 Direction Control Register

CPU Data Page Pointer 0 Register (10 bits)

CPU Data Page Pointer 1 Register (10 bits)

CPU Data Page Pointer 2 Register (10 bits)

CPU Data Page Pointer 3 Register (10 bits)

External Interrupt Control Register

I²C Address Register

00_H

b FFC2_H

b FFC6_H

b FFCA_H

b FFCE_H

FE00_H

E1_H

E3_H

E5_H

E7_H

00_H

01_H

02_H

03_H

0000_H

00_H

DP3

DP4

DP6

00_H

DPP0

DPP1

DPP2

DPP3

EXICON

ICADR

ICCFG

ICCON

ICRTB

ICST

0000_H

0001_H

0002_H

0003_H

0000_H

0XXX_H

XX00_H

0000_H

XX_H

FE02_H

FE04_H

FE06_H

b F1C0_HE E0_H

ED06_HX ---

ED00_HX ---

I²C Configuration Register

ED02_HX ---

I²C Control Register

ED08_HX ---

I²C Receive/Transmit Buffer

I²C Status Register

ED04_HX ---

0000_H

09XX_H

1820_H

0000_H

00_H

IDCHIP

IDMANUF

IDMEM

IDPROG

ISNC

F07C_HE 3E_H

F07E_HE 3F_H

F07A_HE 3D_H

F078_HE 3C_H

b F1DE_HE EF_H

Identifier

Interrupt Subnode Control Register

CPU Multiply Divide Control Register

CPU Multiply Divide Register – High Word

CPU Multiply Divide Register – Low Word

Port 2 Open Drain Control Register

Port 3 Open Drain Control Register

Port 6 Open Drain Control Register

Constant Value 1’s Register (read only)

MDC

b FF0E_H

FE0C_H

87_H

06_H

07_H

MDH

MDL

FE0E_H

ODP2

ODP3

ODP6

ONES

b F1C2_HE E1_H

b F1C6_HE E3_H

b F1CE_HE E7_H

b FF1E_H

8F_H

FFFF_H

Semiconductor Group

29

1998-05-01

C161RI

Name

Physical 8-Bit

Address Address

Description

Reset

Value

P0L

b FF00_H

80_H

81_H

82_H

83_H

E0_H

E2_H

E4_H

D1_H

D2_H

E6_H

60_H

61_H

62_H

63_H

64_H

65_H

66_H

67_H

88_H

Port 0 Low Register (Lower half of PORT0)

Port 0 High Register (Upper half of PORT0)

Port 1 Low Register (Lower half of PORT1)

Port 1 High Register (Upper half of PORT1)

Port 2 Register

00_H

P0H

b FF02_H

b FF04_H

b FF06_H

b FFC0_H

b FFC4_H

b FFC8_H

b FFA2_H

b FFA4_H

b FFCC_H

FEC0_H

P1L

00_H

P1H

00_H

P2

0000_H

00_H

P3

Port 3 Register

P4

Port 4 Register (7 bits)

P5

Port 5 Register (read only)

XXXX_H

0000_H

00_H

P5DIDIS

P6

Port 5 Digital Input Disable Register

Port 6 Register (8 bits)

PECC0

PECC1

PECC2

PECC3

PECC4

PECC5

PECC6

PECC7

PSW

RP0H

RTCH

RTCL

S0BG

PEC Channel 0 Control Register

PEC Channel 1 Control Register

PEC Channel 2 Control Register

PEC Channel 3 Control Register

PEC Channel 4 Control Register

PEC Channel 5 Control Register

PEC Channel 6 Control Register

PEC Channel 7 Control Register

CPU Program Status Word

0000_H

XX_H

FEC2_H

FEC4_H

FEC6_H

FEC8_H

FECA_H

FECC_H

FECE_H

b FF10_H

b F108_HE 84_H

F0D6_HE 6B_H

F0D4_HE 6A_H

System Startup Configuration Register (Rd. only)

RTC High Register

no

RTC Low Register

no

FEB4_H

5A_H

Serial Channel 0 Baud Rate Generator Reload

Register

0000_H

S0CON

S0EIC

b FFB0_H

b FF70_H

FEB2_H

D8_H

B8_H

59_H

Serial Channel 0 Control Register

0000_H

Serial Channel 0 Error Interrupt Control Register

S0RBUF

Serial Channel 0 Receive Buffer Register

(read only)

XXXX_H

S0RIC

b FF6E_H

B7_H

Serial Channel 0 Receive Interrupt Control

Register

0000_H

S0TBIC

S0TBUF

b F19C_HE CE_H

FEB0_H58_H

Serial Channel 0 Transmit Buffer Interrupt Control

Register

Serial Channel 0 Transmit Buffer Register

Semiconductor Group

30

1998-05-01

C161RI

Name

S0TIC

Physical 8-Bit

Address Address

Description

Reset

Value

b FF6C_H

B6_H

Serial Channel 0 Transmit Interrupt Control

Register

0000_H

SP

FE12_H

09_H

CPU System Stack Pointer Register

SSC Baudrate Register

FC00_H

0000_H

XXXX_H

0000_H

FA00_H

FC00_H

SSCBR

F0B4_HE 5A_H

SSCCON b FFB2_H

D9_H

BB_H

SSC Control Register

SSCEIC

SSCRB

SSCRIC

SSCTB

SSCTIC

STKOV

STKUN

b FF76_H

SSC Error Interrupt Control Register

SSC Receive Buffer (read only)

SSC Receive Interrupt Control Register

SSC Transmit Buffer (write only)

SSC Transmit Interrupt Control Register

CPU Stack Overflow Pointer Register

CPU Stack Underflow Pointer Register

CPU System Configuration Register

CPU System Configuration Register 2

CPU System Configuration Register 3

RTC Timer 14 Register

F0B2_HE 59_H

b FF74_H

BA_H

F0B0_HE 58_H

b FF72_H

B9_H

0A_H

0B_H

89_H

FE14_H

FE16_H

1)

SYSCON b FF12_H

0XX0_H

SYSCON2 b F1D0_HE E8_H

SYSCON3 b F1D4_HE EA_H

0000_H

no

T14

F0D2_HE 69_H

F0D0_HE 68_H

T14REL

T2

RTC Timer 14 Reload Register

GPT1 Timer 2 Register

no

FE40_H

b FF40_H

b FF60_H

FE42_H

20_H

A0_H

B0_H

21_H

A1_H

B1_H

22_H

A2_H

B2_H

23_H

A3_H

B3_H

24_H

A4_H

B4_H

D6_H

0000_H

T2CON

T2IC

T3

GPT1 Timer 2 Control Register

GPT1 Timer 2 Interrupt Control Register

GPT1 Timer 3 Register

T3CON

T3IC

T4

b FF42_H

b FF62_H

FE44_H

GPT1 Timer 3 Control Register

GPT1 Timer 3 Interrupt Control Register

GPT1 Timer 4 Register

T4CON

T4IC

T5

b FF44_H

b FF64_H

FE46_H

GPT1 Timer 4 Control Register

GPT1 Timer 4 Interrupt Control Register

GPT2 Timer 5 Register

T5CON

T5IC

T6

b FF46_H

b FF66_H

FE48_H

GPT2 Timer 5 Control Register

GPT2 Timer 5 Interrupt Control Register

GPT2 Timer 6 Register

T6CON

T6IC

TFR

b FF48_H

b FF68_H

b FFAC_H

GPT2 Timer 6 Control Register

GPT2 Timer 6 Interrupt Control Register

Trap Flag Register

Semiconductor Group

31

1998-05-01

C161RI

Name

WDT

Physical 8-Bit

Address Address

Description

Reset

Value

FEAE_H

57_H

Watchdog Timer Register (read only)

Watchdog Timer Control Register

I²C Data Interrupt Control Register

I²C Protocol Interrupt Control Register

X-Peripheral 2 Interrupt Control Register

RTC Interrupt Control Register

0000_H

2)

WDTCON b FFAE_H

D7_H

00XX_H

XP0IC

XP1IC

XP2IC

XP3IC

ZEROS

b F186_HE C3_H

b F18E_HE C7_H

b F196_HE CB_H

b F19E_HE CF_H

0000_H

b FF1C_H

8E_H

Constant Value 0’s Register (read only)

1)

The system configuration is selected during reset.

2)

The reset value depends on the indicated reset source.

Semiconductor Group

32

1998-05-01

C161RI

Absolute Maximum Ratings

Ambient temperature under bias (T_A):

SAB-C161RI ...................................................................................................................0 to + 70 °C

SAF-C161RI ..............................................................................................................– 40 to + 85 °C

Storage temperature (T_ST)........................................................................................– 65 to + 150 °C

Voltage on V_DDpins with respect to ground (V_SS) ..................................................... – 0.5 to + 6.5 V

Voltage on any pin with respect to ground (V_SS).................................................– 0.5 to V_DD+ 0.5 V

Input current on any pin during overload condition.................................................. – 10 to + 10 mA

Absolute sum of all input currents during overload condition ..............................................|100 mA|

Power dissipation..................................................................................................................... 1.5 W

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

During absolute maximum rating overload conditions (V_IN> V_DDor V_IN< V_SS) the voltage on

V_DDpins with respect to ground (V_SS) must not exceed the values defined by the absolute

maximum ratings.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161RI and partly

its demands on the system. To aid in interpreting the parameters right, when evaluating them for a

design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C161RI will provide signals with the respective timing characteristics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to the C161RI.

Semiconductor Group

33

1998-05-01

C161RI

DC Characteristics

_DD= 4.5 - 5.5 V;

T_A= 0 to + 70 °C

T_A= – 40 to + 85 °C for SAF-C161RI

V

V_SS= 0 V;

for SAB-C161RI

f_CPU= 20 MHz

Parameter

Symbol

Limit Values

max.

Unit Test Condition

min.

Input low voltage

(P3.0, P3.1, P6.5, P6.6, P6.7)

V_IL1

– 0.5

0.3 V_DD

V

–

SR

Input low voltage

(TTL)

V_IL

– 0.5

0.2 V_DD

– 0.1

SR

Input low voltage

V_ILS

2.0

(Special Threshold)

Input high voltage RSTIN

V_IH1

V_IH2

0.6 V_DD

0.7 V_DD

V

_DD+ 0.5

V

–

SR

Input high voltage XTAL1,

P3.0, P3.1, P6.5, P6.6, P6.7

V

Input high voltage

(TTL)

V_IH

0.2 V_DD

+ 0.9

V

–

_DD+ 0.5

V

–

SR

Input high voltage

(Special Threshold)

V_IHS

HYS

V_OL

0.8 V_DD

– 0.2

_DD+ 0.5

V

Input Hysteresis

(Special Threshold)

400

–

mV

V

Output low voltage

0.45

I_OL= 2.4 mA

CC

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE, CLKOUT, RSTOUT)

Output low voltage

(P3.0, P3.1, P6.5, P6.6, P6.7)

V_OL2

V_OL1

V_OH

–

0.4

0.45

–

V

I

_OL2= 3 mA

CC

Output low voltage

(all other outputs)

_OL1= 1.6 mA

Output high voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE, CLKOUT, RSTOUT)

0.9 V_DD

2.4

I

_OH= – 500 µA

_OH= – 2.4 mA

1)

Output high voltage

(all other outputs)

V_OH1

0.9 V_DD

2.4

–

V

I

_OH= – 250 µA

_OH= – 1.6 mA

CC

Input leakage current (Port 5)

Input leakage current (all other)

Overload current

I_OZ1

I_OZ2

I_OV

–

± 200

± 500

± 5

nA

mA

kΩ

µA

0.45 V < V_IN< V_DD

CC

SR

CC

–

0.45 V < V_IN< V_DD

5) 8)

–

RSTIN pullup resistor

R_RST

I_RWH

I_RWL

50

250

– 40

–

4)

2)

3)

Read/Write inactive current

–

V

_OUT= 2.4 V

4)

Read/Write active current

– 500

_OUT= V_OLmax

Semiconductor Group

34

1998-05-01

C161RI

Parameter

Symbol

Limit Values

Unit Test Condition

min.

–

max.

40

4)

2)

ALE inactive current

I_ALEL

µA

pF

V

_OUT= V_OLmax

4)

3)

ALE active current

I_ALEH

500

–

_OUT= 2.4 V

_OUT= V_OL1max

4)

2)

Port 6 inactive current

I_P6H

– 40

4)

3)

Port 6 active current

I_P6L

– 500

–

4)

2)

PORT0 configuration current

I_P0H

–

– 10

–

V_IN= V_IHmin

3)

I_P0L

– 100

V_IN= V_ILmax

XTAL1 input current

I_IL

–

± 20

10

0 V < V_IN< V_DD

CC

5)

Pin capacitance

C_IO

I_DD

I_IDX

I_IDO

f = 1 MHz

T_A= 25 °C

(digital inputs/outputs)

Power supply current (active)

with all peripherals active

–

7 +

3 × f_CPU

mA

µA

RSTIN = V_IL2

f

_CPUin [MHz] ⁶⁾

Idle mode supply current

with all peripherals active

3 +

1.1 × f_CPU

RSTIN = V_IH1

_CPUin [MHz] ⁶⁾

f

Idle mode supply current

with all peripherals deactivated,

PLL off, SDD factor = 32

500 +

50 × f_OSC

RSTIN = V_IH1

_OSCin [MHz] ⁶⁾

9)

f

Power-down mode supply current I_PDR

with RTC running

–

100 +

25 × f_OSC

µA

V

f

_DD= 5.5 V

9)

_OSCin [MHz] ⁷⁾

Power-down mode supply current I_PDO

50

V

_DD= 5.5 V ⁷⁾

with RTC disabled

Semiconductor Group

35

1998-05-01

C161RI

Notes

1)

This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

2)

3)

4)

5)

6)

The maximum current may be drawn while the respective signal line remains inactive.

The minimum current must be drawn in order to drive the respective signal line active.

This specification is only valid during Reset, or during Adapt-mode.

Not 100% tested, guaranteed by design characterization.

The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at V_DDmaxand 20 MHz CPU clock with all outputs disconnected and all inputs at

V_ILor V_IH.

The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. I_PDRmax

.

For lower oscillator frequencies the respective supply current can be reduced accordingly.

7)

8)

This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at V_DD– 0.1 V to V_DD, V_REF= 0 V, all outputs (including pins configured as outputs) disconnected.

Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input overload currents on

all port pins may not exceed 50 mA. The supply voltage (V_DDand V_SS) must remain within the specified limits.

9)

This parameter is determined mainly by the current consumed by the oscillator. This current, however, is

influenced by the external oscillator circuitry (crystal, capacitors). The values given for I_PDRrefer to a typical

circuitry and may change in case of a not optimized external oscillator circuitry.

A typical value for I_PDRat room temperature and f_CPU= 16 MHz is 300 µA.

Semiconductor Group

36

1998-05-01

C161RI

I_DDmax

70

40

I_DDtyp

I_IDXmax

I_IDXtyp

10

f_CPU[MHz]

5

10

15

20

Figure 8

Supply/Idle Current as a Function of Operating Frequency

1500

1250

1000

750

I_IDOmax

I_IDOtyp

I_PDRmax

500

250

I_PDOmax

f_OSC[MHz]

4

8

12

16

Figure 9

Power Down Supply Current as a Function of Oscillator Frequency

Semiconductor Group

37

1998-05-01

C161RI

AC Characteristics

Definition of Internal Timing

The internal operation of the C161RI is controlled by the internal CPU clock f_CPU. Both edges of the

CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between

two consecutive edges of the CPU clock, called “TCL” (see figure below).

Direct Clock Drive

f_XTAL

f_CPU

TCLTCL

Prescaler Operation

f_XTAL

f_CPU

TCL

Figure 10

Generation Mechanisms for the CPU Clock

The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their

variation (and also the derived external timing) depends on the used mechanism to generate f_CPU

.

This influence must be regarded when calculating the timings for the C161RI.

The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins

P0.15-13 (P0H.7-5).

Semiconductor Group

38

1998-05-01

C161RI

The table below associates the combinations of these three bits with the respective clock generation

mode.

C161RI Clock Generation Modes

P0.15-13

(P0H.7-5)

CPU Frequency f_CPU= Notes

_XTAL× F

f

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Reserved

Default configuration without pull-downs

f

_XTAL× 1

Reserved

_XTAL/ 2

Reserved

Direct drive ¹⁾

f

CPU clock via prescaler

¹⁾The maximum frequency depends on the duty cycle of the external clock signal.

Prescaler Operation

When pins P0.15-13 (P0H.7-5) equal ‘001’ during reset the CPU clock is derived from the internal

oscillator (input clock signal) by a 2:1 prescaler.

The frequency of f_CPUis half the frequency of f_XTALand the high and low time of f_CPU(i.e. the duration

of an individual TCL) is defined by the period of the input clock f_XTAL

.

The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the

period of f_XTALfor any TCL.

Direct Drive

When pins P0.15-13 (P0H.7-5) equal ‘011’ during reset the on-chip phase locked loop is disabled

and the CPU clock is directly driven from the internal oscillator with the input clock signal.

The frequency of f_CPUdirectly follows the frequency of f_XTALso the high and low time of f_CPU(i.e. the

duration of an individual TCL) is defined by the duty cycle of the input clock f_XTAL

.

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL

that is possible under the respective circumstances. This minimum value can be calculated via the

following formula:

TCL_min= 1/f_XTAL× DC_min

(DC = duty cycle)

For two consecutive TCLs the deviation caused by the duty cycle of f_XTALis compensated so the

duration of 2TCL is always 1/f_XTAL. The minimum value TCL_mintherefore has to be used only once

for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of

TCLs (2,4,...) may use the formula 2TCL = 1/f_XTAL

Note: The address float timings in Multiplexed bus mode (t₁₁and t₄₅) use the maximum duration of

TCL (TCL_max= 1/f_XTAL× DC_max) instead of TCL_min

.

Semiconductor Group

39

1998-05-01

C161RI

AC Characteristics

External Clock Drive XTAL1

V

_DD= 4.5 - 5.5 V;

V_SS= 0 V

T_A= 0 to + 70 °C

for SAB-C161RI

T_A= – 40 to + 85 °C for SAF-C161RI

Parameter

Symbol

Direct Drive 1:1

max.

Prescaler 2:1

Unit

min.

31

6

max.

4000

–

Oscillator period

High time

t_OSC

62

8000

ns

SR

t₁

25 ^{1) 2)}

–

SR

Low time

t₂

25 ^{1) 2)}

–

6

–

SR

Rise time

t₃

–

10 ¹⁾

–

6 ¹⁾

SR

Fall time

t₄

–

SR

1)

The clock input signal must reach the defined levels V_ILand V_IH2.

The specified minimum low and high times allow a duty cycle range of 40...60% at 16 MHz.

2)

t₁

t₃

t₄

V_IH2

V_IL

0.5 V_DD

t₂

t_OSC

MCT02534

Figure 11

External Clock Drive XTAL1

Semiconductor Group

40

1998-05-01

C161RI

A/D Converter Characteristics

V

_DD= 4.5 - 5.5 V;

V_SS= 0 V

T_A= 0 to + 70 °C

for SAB-C161RI

T_A= – 40 to + 85 °C for SAF-C161RI

4.0 V ≤ V_AREF≤ V_DD+ 0.1 V; V_SS- 0.1 V ≤ V_AGND≤ V_SS+ 0.2 V

Parameter

Symbol

Limit Values

Unit Test Condition

min.

max.

V_AREF

4

1)

2)

Analog input voltage range

Basic clock frequency

Sample time

V_AINSR V_AGND

V

f_BC

t_S

0.5

CC –

MHz

6 t_BC

t_BC= 1 / f_BC

3)

Conversion time

t_C

30 t_BC

+ 2 t_CPU

t_CPU= 1 / f_CPU

4)

Total unadjusted error

TUE CC –

± 2

LSB

t_BCin [ns] ^{5) 6)}

Internal resistance of reference

voltage source

R

_AREFSR –

t_BC/ 125 kΩ

- 0.25

t_Sin [ns] ^{6) 7)}

Internal resistance of analog

source

R

_ASRCSR –

t_S/ 750

- 0.25

kΩ

6)

ADC input capacitance

C_AINCC –

50

pF

The conversion time of the C161RI’s A/D Converter is programmable. The table below should be

used to calculate the above timings.

The limit values for f_BCmust not be exceeded when selecting ADCTC.

ADCON.15|14 A/D Converter Basic Clock

2)

(ADCTC)

f_BC

00

01

10

11

f

_CPU/ 2

_CPU/ 4

_CPU/ 8

_CPU/ 16

Converter Timing Example:

Assumptions:

f_CPU= 16 MHz (i.e. t_CPU= 62.5 ns), ADCTC = ‘01’.

f_BC= f_CPU/ 4 = 4 MHz, i.e. t_BC= 250 ns.

Basic clock

Sample time

t_S

= t_BC× 6 = 1500 ns.

Conversion time t_C

= 30 t_BC+ 2 t_CPU= (7500 + 125) ns = 7.625 µs.

Semiconductor Group

41

1998-05-01

C161RI

Notes

1)

V_AINmay exceed V_AGNDor V_AREFup to the absolute maximum ratings. However, the conversion result in these

cases will be X000 or X3FF , respectively.

H

2)

3)

The limit values for f_BCmust not be exceeded when selecting the CPU frequency and the ADCTC setting.

This parameter includes the sample time t_S, the time for determining the digital result and the time to load the

result register with the conversion result.

Values for the basic clock t_BCdepend on programming and can be taken from the table above.

This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.

4)

5)

TUE is tested at V_AREF= 5.0 V, V_AGND= 0 V, V_DD= 4.9 V. It is guaranteed by design for all other voltages within

the defined voltage range.

The specified TUE is guaranteed only if an overload condition (see I_OVspecification) occurs on maximum 2 not

selected analog input pins and the absolute sum of input overload currents on all analog input pins does not

exceed 10 mA.

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference voltage source must allow the capacitance to reach its respective voltage level

within each conversion step. The maximum internal resistance results from the programmed conversion

timing.

6)

7)

Not 100% tested, guaranteed by design.

During the sample time the input capacitance C_Ican be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach its final voltage level within t_S.

After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion result.

Values for the sample time t_Sdepend on programming and can be taken from the table above.

Semiconductor Group

42

1998-05-01

C161RI

Testing Waveforms

AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’.

Timing measurements are made at V_IHmin for a logic ‘1’ and V_ILmax for a logic ‘0’.

Figure 12

Input Output Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load

voltageoccurs,butbeginstofloatwhena100 mVchangefromtheloadedV_OH/V_OLl e ve l o c c ur s

(I_OH/I_OL= 20 mA).

Figure 13

Float Waveforms

Semiconductor Group

43

1998-05-01

C161RI

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and

represent the special characteristics of the programmed memory cycle. The following table

describes, how these variables are to be computed.

Description

Symbol

Values

ALE Extension

t_A

t_C

t_F

TCL × <ALECTL>

2TCL × (15 - <MCTC>)

2TCL × (1 - <MTTC>)

Memory Cycle Time Waitstates

Memory Tristate Time

AC Characteristics

Multiplexed Bus

V

_DD= 4.5 - 5.5 V;

V_SS= 0 V

for SAB-C161RI

T_A= 0 to + 70 °C

T_A= – 40 to + 85 °C for SAF-C161RI

C_L= 100 pF

ALE cycle time = 6 TCL + 2t_A+ t_C+ t_F(186 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

CC 21 + t_A

max.

min.

max.

ALE high time

t₅

t₆

t₇

–

TCL - 10 + t_A

TCL - 16 + t_A

TCL - 10 + t_A

–

ns

CC

Address setup to ALE

Address hold after ALE

15 + t_A

21 + t_A

t₈

ALE falling edge to RD,

WR (with RW-delay)

t₉

CC

ALE falling edge to RD,

WR (no RW-delay)

– 10 + t_A

–

– 10 + t_A

–

ns

t₁₀CC

t₁₁CC

Address float after RD,

WR (with RW-delay)

–

6

–

6

Address float after RD,

WR (no RW-delay)

37

–

TCL + 6

RD, WR low time

(with RW-delay)

t₁₂CC 53 + t_C

t₁₃CC 84 + t_C

2TCL - 10

+ t_C

–

RD, WR low time

(no RW-delay)

–

3TCL - 10

+ t_C

Semiconductor Group

44

1998-05-01

C161RI

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

RD to valid data in

(with RW-delay)

t₁₄SR

t₁₅SR

t₁₆SR

t₁₇SR

t₁₈SR

t₁₉SR

–

0

–

43 + t_C

–

0

–

2TCL - 20

+ t_C

ns

RD to valid data in

(no RW-delay)

74 + t_C

3TCL - 20

+ t_C

ALE low to valid data in

74

+ t_A+ t_C

3TCL - 20

+ t_A+ t_C

Address to valid data in

95

+ 2t_A+ t_C

4TCL - 30

+ 2t_A+ t_C

Data hold after RD

rising edge

–

Data float after RD

Data valid to WR

Data hold after WR

49 + t_F

2TCL - 14

+ t_F

t₂₂CC 43 + t_C

t₂₃CC 49 + t_F

–

2TCL - 20

+ t_C

–

2TCL - 14

+ t_F

–

ALE rising edge after RD, t₂₅CC 49 + t_F

WR

–

2TCL - 14

+ t_F

–

Address hold after RD,

WR

t₂₇CC 49 + t_F

t₃₈CC – 4 - t_A

–

2TCL - 14

+ t_F

–

ALE falling edge to CS

CS low to Valid Data In

10 - t_A

– 4 - t_A

10 - t_A

ns

t₃₉SR

–

74

–

3TCL - 20

+ t_C+ 2t_A

CS hold after RD, WR

t₄₀CC 80 + t_F

t₄₂CC 27 + t_A

t₄₃CC – 4 + t_A

–

3TCL - 14

+ t_F

–

ns

ALE fall. edge to RdCS,

WrCS (with RW delay)

–

TCL - 4

+ t_A

–

ALE fall. edge to RdCS,

WrCS (no RW delay)

–

-4

+ t_A

–

Address float after RdCS, t₄₄CC

WrCS (with RW delay)

–

0

–

0

Address float after RdCS, t₄₅CC

WrCS (no RW delay)

31

TCL

RdCS to Valid Data In

(with RW delay)

t₄₆SR

39 + t_C

2TCL - 24

+ t_C

Semiconductor Group

45

1998-05-01

C161RI

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

RdCS to Valid Data In

(no RW delay)

t₄₇SR

–

70 + t_C

–

3TCL - 24

+ t_C

ns

RdCS, WrCS Low Time

(with RW delay)

t₄₈CC 53 + t_C

t₄₉CC 84 + t_C

t₅₀CC 49 + t_C

–

2TCL - 10

+ t_C

–

RdCS, WrCS Low Time

(no RW delay)

3TCL - 10

+ t_C

Data valid to WrCS

2TCL - 14

+ t_C

Data hold after RdCS

Data float after RdCS

t₅₁SR

t₅₂SR

0

–

0

–

ns

43 + t_F

2TCL - 20

+ t_F

Address hold after

RdCS, WrCS

t₅₄CC 43 + t_F

t₅₆CC 43 + t_F

–

2TCL - 20

+ t_F

–

ns

Data hold after WrCS

2TCL - 20

+ t_F

Semiconductor Group

46

1998-05-01

C161RI

t₅

t₁₆

t₂₅

ALE

CSx

t₃₈

t₃₉

t₄₀

t₁₇

t₂₇

A23-A16

(A15-A8)

BHE

Address

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

t₈

Data In

t₁₀

t₁₄

t₁₂

t₄₆

t₄₈

RD

t₅₁

t₄₄

t₄₂

t₅₂

RdCSx

Write Cycle

t₂₃

BUS

Address

t₈

Data Out

t₅₆

t₁₀

t₂₂

WR,

WRL, WRH

t₁₂

t₄₄

t₄₂

t₅₀

WrCSx

t₄₈

Figure 14-1

External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE

Semiconductor Group

47

1998-05-01

C161RI

t₅

t₁₆

t₂₅

ALE

CSx

t₃₈

t₃₉

t₄₀

t₁₇

t₂₇

A23-A16

(A15-A8)

BHE

Address

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

t₈

Data In

t₁₀

t₁₄

t₁₂

t₄₆

t₄₈

RD

t₅₁

t₄₄

t₄₂

t₅₂

RdCSx

Write Cycle

t₂₃

BUS

Address

t₈

Data Out

t₅₆

t₁₀

t₂₂

WR,

WRL, WRH

t₁₂

t₄₄

t₄₂

t₅₀

WrCSx

t₄₈

Figure 14-2

External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE

Semiconductor Group

48

1998-05-01

C161RI

t₅

t₁₆

t₂₅

ALE

CSx

t₃₈

t₃₉

t₄₀

t₁₇

t₂₇

A23-A16

(A15-A8)

BHE

Address

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

t₉

Data In

t₁₁

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₄₃

t₄₅

t₅₂

RdCSx

Write Cycle

t₂₃

BUS

Address

t₉

Data Out

t₅₆

t₁₁

t₂₂

WR,

WRL, WRH

t₁₃

t₅₀

t₄₃

t₄₅

WrCSx

t₄₉

Figure 14-3

External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE

Semiconductor Group

49

1998-05-01

C161RI

t₅

t₁₆

t₂₅

ALE

CSx

t₃₈

t₃₉

t₄₀

t₁₇

t₂₇

A23-A16

(A15-A8)

BHE

Address

t₆

t₇

t₅₄

t₁₉

t₁₈

Read Cycle

BUS

Address

t₉

Data In

t₁₁

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₄₃

t₄₅

t₅₂

RdCSx

Write Cycle

t₂₃

BUS

Address

t₉

Data Out

t₅₆

t₁₁

t₂₂

WR,

WRL, WRH

t₁₃

t₄₃

t₄₅

t₅₀

WrCSx

t₄₉

Figure 14-4

External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE

Semiconductor Group

50

1998-05-01

C161RI

AC Characteristics

Demultiplexed Bus

V

_DD= 4.5 - 5.5 V;

V_SS= 0 V

T_A= 0 to + 70 °C

for SAB-C161RI

T_A= – 40 to + 85 °C for SAF-C161RI

C_L= 100 pF

ALE cycle time = 4 TCL + 2t_A+ t_C+ t_F(125 ns at 16 MHz CPU clock without waitstates)

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

CC 21 + t_A

max.

min.

max.

ALE high time

t₅

t₆

–

TCL - 10 + t_A

TCL - 16 + t_A

–

ns

CC

Address setup to ALE

15 + t_A

21 + t_A

t₈

ALE falling edge to RD,

WR (with RW-delay)

TCL - 10

+ t_A

t₉

CC

ALE falling edge to RD,

WR (no RW-delay)

– 10 + t_A

–

– 10

+ t_A

–

ns

RD, WR low time

(with RW-delay)

t₁₂CC 53 + t_C

t₁₃CC 84 + t_C

–

2TCL - 10

+ t_C

RD, WR low time

(no RW-delay)

–

3TCL - 10

+ t_C

RD to valid data in

(with RW-delay)

t₁₄SR

t₁₅SR

t₁₆SR

t₁₇SR

t₁₈SR

t₂₀SR

t₂₁SR

–

0

–

43 + t_C

74 + t_C

–

0

–

2TCL - 20

+ t_C

RD to valid data in

(no RW-delay)

3TCL - 20

+ t_C

ALE low to valid data in

74

+ t_A+ t_C

3TCL - 20

+ t_A+ t_C

Address to valid data in

95

+ 2t_A+ t_C

4TCL - 30

+ 2t_A+ t_C

Data hold after RD

rising edge

–

Data float after RD rising

edge (with RW-delay ¹⁾)

49 +

2t_A+ t_F

2TCL - 14

+ 2t_A+ t_F

1)

Data float after RD rising

edge (no RW-delay ¹⁾)

21 +

2t_A+ t_F

TCL - 10

+ 2t_A+ t_F

1)

Data valid to WR

t₂₂CC 43 + t_C

t₂₄CC 21 + t_F

–

2TCL - 20

+ t_C

–

ns

Data hold after WR

–

TCL - 10 + t_F

– 10 + t_F

–

ns

ALE rising edge after RD, t₂₆CC – 10 + t_F

WR

Semiconductor Group

51

1998-05-01

C161RI

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

–

min.

max.

–

2)

Address hold after WR

ALE falling edge to CS

CS low to Valid Data In

t₂₈CC 0 + t_F

t₃₈CC – 4 - t_A

0 + t_F

– 4 - t_A

–

ns

10 - t_A

t₃₉SR

–

74

3TCL - 20

+ t_C+ 2t_A

CS hold after RD, WR

t₄₁CC 17 + t_F

–

TCL - 14

+ t_F

–

ns

ALE falling edge to RdCS, t₄₂CC 27 + t_A

WrCS (with RW-delay)

–

TCL - 4

+ t_A

ALE falling edge to RdCS, t₄₃CC – 4 + t_A

WrCS (no RW-delay)

–

– 4

+ t_A

RdCS to Valid Data In

(with RW-delay)

t₄₆SR

t₄₇SR

–

39 + t_C

–

2TCL - 24

+ t_C

RdCS to Valid Data In

(no RW-delay)

70 + t_C

–

3TCL - 24

+ t_C

RdCS, WrCS Low Time

(with RW-delay)

t₄₈CC 53 + t_C

t₄₉CC 84 + t_C

t₅₀CC 49 + t_C

–

2TCL - 10

+ t_C

–

RdCS, WrCS Low Time

(no RW-delay)

3TCL - 10

+ t_C

Data valid to WrCS

2TCL - 14

+ t_C

Data hold after RdCS

t₅₁SR

t₅₃SR

0

–

0

–

ns

Data float after RdCS

(with RW-delay)

43 + t_F

2TCL - 20

+ t_F

Data float after RdCS

(no RW-delay)

t₆₈SR

–

11 + t_F

–

TCL - 20

+ t_F

ns

Address hold after

RdCS, WrCS

t₅₅CC – 10 + t_F

t₅₇CC 17 + t_F

–

– 10

+ t_F

–

Data hold after WrCS

TCL - 14

+ t_F

¹⁾RW-delay and t_Arefer to the next following bus cycle.

²⁾It is guaranteed by design that read data are latched before the address changes.

Semiconductor Group

52

1998-05-01

C161RI

t₅

t₁₆

t₂₆

ALE

CSx

t₃₈

t₃₉

t₄₁

t₁₇

t₂₈

A23-A16

A15-A0

BHE

Address

t₆

t₅₅

t₂₀

Read Cycle

BUS

(D15-D8)

D7-D0

t₁₈

Data In

t₈

t₁₄

RD

t₁₂

t₄₆

t₄₈

t₅₁

t₄₂

t₅₃

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

t₂₄

Data Out

t₅₇

t₈

t₂₂

WR,

WRL, WRH

t₁₂

t₄₂

t₅₀

WrCSx

t₄₈

Figure 15-1

External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE

Semiconductor Group

53

1998-05-01

C161RI

t₅

t₁₆

t₃₉

t₁₇

t₂₆

ALE

CSx

t₃₈

t₄₁

t₂₈

A23-A16

A15-A0

BHE

Address

t₆

t₅₅

t₂₀

t₁₈

Read Cycle

BUS

(D15-D8)

D7-D0

Data In

t₈

t₁₄

t₁₂

t₄₆

t₄₈

RD

t₅₁

t₄₂

t₅₃

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

t₂₄

Data Out

t₅₇

t₈

t₂₂

WR,

WRL, WRH

t₁₂

t₄₂

t₅₀

WrCSx

t₄₈

Figure 15-2

External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE

Semiconductor Group

54

1998-05-01

C161RI

t₅

t₁₆

t₂₆

ALE

CSx

t₃₈

t₃₉

t₄₁

t₁₇

t₂₈

A23-A16

A15-A0

BHE

Address

t₆

t₅₅

t₂₁

Read Cycle

BUS

(D15-D8)

D7-D0

t₁₈

Data In

t₉

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₄₃

t₆₈

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

t₂₄

Data Out

t₅₇

t₉

t₂₂

WR,

WRL, WRH

t₁₃

t₅₀

t₄₃

WrCSx

t₄₉

Figure 15-3

External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE

Semiconductor Group

55

1998-05-01

C161RI

t₅

t₁₆

t₃₉

t₁₇

t₂₆

ALE

CSx

t₃₈

t₄₁

t₂₈

A23-A16

A15-A0

BHE

Address

t₆

t₅₅

t₂₁

t₁₈

Read Cycle

BUS

(D15-D8)

D7-D0

Data In

t₉

t₁₅

t₁₃

t₄₇

t₄₉

RD

t₅₁

t₄₃

t₆₈

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

t₂₄

Data Out

t₅₇

t₉

t₂₂

WR,

WRL, WRH

t₁₃

t₄₃

t₅₀

WrCSx

t₄₉

Figure 15-4

External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE

Semiconductor Group

56

1998-05-01

C161RI

AC Characteristics

CLKOUT and READY

V

_DD= 4.5 - 5.5 V;

V_SS= 0 V

T_A= 0 to + 70 °C

for SAB-C161RI

T_A= – 40 to + 85 °C for SAF-C161RI

C_L= 100 pF

Parameter

Symbol

Max. CPU Clock

= 16 MHz

Variable CPU Clock

1/2TCL = 1 to 16 MHz

Unit

min.

max.

min.

max.

CLKOUT cycle time

CLKOUT high time

CLKOUT low time

CLKOUT rise time

CLKOUT fall time

t₂₉CC 62

62

2TCL

TCL – 6

TCL – 10

–

2TCL

ns

t₃₀CC

t₃₁CC

25

21

–

t₃₂CC

t₃₃CC

4

–

4

–

4

CLKOUT rising edge to

ALE falling edge

t₃₄CC 0 + t_A

10 + t_A

0 + t_A

10 + t_A

Synchronous READY

setup time to CLKOUT

t₃₅SR 14

–

14

–

ns

Synchronous READY

hold time after CLKOUT

t₃₆SR

4

–

Asynchronous READY

low time

t₃₇SR 76

2TCL + 14

–

t₅₈SR

t₅₉SR

t₆₀SR

Asynchronous READY

14

4

14

4

–

1)

setup time

Asynchronous READY

–

1)

hold time

Async. READY hold time

after RD, WR high

(Demultiplexed Bus) ²⁾

0

1

0

TCL - 30

+ 2t_A+ t_C

+ t_F

+ 2t_A+ t_C+ t_F

2)

Notes

1)

These timings are given for test purposes only, in order to assure recognition at a specific clock edge.

2)

Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This

adds even more time for deactivating READY.

The 2t and t_Crefer to the next following bus cycle, t_Frefers to the current bus cycle.

A

Semiconductor Group

57

1998-05-01

C161RI

READY

waitstate

Running cycle ¹⁾

MUX/Tristate ⁶⁾

t₃₂

t₃₃

CLKOUT

ALE

t₃₀

t₃₄

t₂₉

t₃₁

7)

Command

RD, WR

2)

t₃₅

t₃₆

t₃₅

t₃₆

Sync

READY

3)

4)

t₅₈

t₅₉

t₅₈

t₅₉

t₆₀

Async

READY

3)

t₃₇

5)

see ⁶⁾

Figure 16

CLKOUT and READY

Notes

1)

Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).

The leading edge of the respective command depends on RW-delay.

2)

3)

READY sampled HIGH at this sampling point generates a READY controlled waitstate,

READY sampled LOW at this sampling point terminates the currently running bus cycle.

4)

5)

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or

WR).

If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT

(eg. because CLKOUT is not enabled), it must fulfill t in order to be safely synchronized. This is guaranteed,

37

4)

if READY is removed in reponse to the command (see Note ).

6)

7)

Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may

be inserted here.

For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without

MTTC waitstate this delay is zero.

The next external bus cycle may start here.

Semiconductor Group

58

1998-05-01

C161RI

Package Outlines

Plastic Package, P-MQFP-100-2 (SMD)

(Plastic Metric Quad Flat Package)

Figure 17

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

Semiconductor Group

59

1998-05-01

C161RI

Package Outlines (cont’d)

Plastic Package, P-TQFP-100-1 (SMD)

(Plastic Thin Metric Quad Flat Package)

Figure 18

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

Semiconductor Group

60

1998-05-01


型号：	C161RI
厂家：	Infineon
描述：	16-Bit CMOS Single-Chip Microcontroller 16位CMOS单芯片微控制器微控制器
文件：	总60页 (文件大小：605K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C161RI [INFINEON]

相关型号：

C161RI_1

C161S

C161U

C161U-LF

C161U-LM

C161U_02

C161V

C161V_96

C163

C163-L

C1632C10012GAC

C1632C100K2GAC