C167CS-XC [INFINEON]
16-Bit Single-Chip Microcontroller Bare Die Delivery; 16位单芯片微控制器裸片供货
| 型号： | C167CS-XC |
| 厂家： | 
Infineon |
| 描述： | 16-Bit Single-Chip Microcontroller Bare Die Delivery |
| 文件： | 总24页 (文件大小：966K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V1.0, Aug. 2001
C167CS-xC, Step BA
16-Bit Single-Chip Microcontroller
Bare Die Delivery
Microcontrollers
N e v e r s t o p t h i n k i n g .
Edition 2001-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.0, Aug. 2001
C167CS-xC, Step BA
16-Bit Single-Chip Microcontroller
Bare Die Delivery
Microcontrollers
N e v e r s t o p t h i n k i n g .
C167CS-xC
(Bare Die Delivery)
Revision History:
2001-08
V1.0
Previous Version:
-
Page
Subjects (major changes since last revision)
Controller Area Network (CAN): License of Robert Bosch GmbH
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
16-Bit Single-Chip Microcontroller
C166 Family
C167CS-xC
C167CS-xC
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
– 400/303 ns Multiplication (16 × 16 bit), 800/606 ns Division (32/16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules
– 3 KBytes On-Chip Internal RAM (IRAM)
– 8 KBytes On-Chip Extension RAM (XRAM)
– 32 KBytes On-Chip Program Mask ROM
• On-Chip Peripheral Modules
– 24-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 µs
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 × 15 Message Objects
(Full CAN/Basic CAN), can work on one bus with 30 objects
– On-Chip Real Time Clock
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
Data Sheet
1
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
This document describes several derivatives of the C167 group. Table 1 enumerates
these derivatives and summarizes the differences. As this document refers to all of these
derivatives, some descriptions may not apply to a specific product.
Table 1
Type
C167CS-xC Bare Die Derivative Synopsis
Ordering
Code
Program
Memory
Operating
Temperature
Wafers
SAK-C167CS-4RC
SAK-C167CS-LC
SAL-C167CS-LC1)
Q67120-
D....
32 KByte ROM -40 to +125 °C Whole
Q67120-
C2200
---
---
---
-40 to +125 °C Sawn
-40 to +150 °C Sawn
-40 to +150 °C Sawn
Q67120-
C2274
SAL-C167CS-L33C1) Q67120-
C2275
1)
The designation SAL-… conforms to the valid ProElectron specification. These devices were named SAA-…
formerly.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
For simplicity all versions are referred to by the term C167CS-xC throughout this
document.
Data Sheet
2
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Introduction
The C167CS-xC derivatives are high performance derivatives of the Infineon
C166 Family of full featured single-chip CMOS microcontrollers. They combine high
CPU performance (up to 16.5 million instructions per second) with high peripheral
functionality and enhanced IO-capabilities. They also provide clock generation via PLL
and various on-chip memory modules such as program ROM, internal RAM, and
extension RAM.
VAREF VAGND VDD
VSS
Port 0
16 Bit
XTAL1
XTAL2
Port 1
16 Bit
RSTIN
RSTOUT
Port 2
16 Bit
NMI
Port 3
15 Bit
EA
C167CS-xC
Port 4
8 Bit
READY
ALE
Port 6
8 Bit
RD
WR/WRL
Port 7
8 Bit
Port 5
16 Bit
Port 8
8 Bit
MCL04411
Figure 1
Logic Symbol
Data Sheet
3
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Pad Configuration
(top view)
Pad 110
Pad 74
C167CS-xC
y
0.0
Pad 1
Pad 36
x
Position of
Logo and Marking
0.0
Figure 2
Several pins of Port 4 and Port 8 can have CAN interface lines assigned to them.
Table 2 on the following pages lists the possible assignments.
Data Sheet
4
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions
Symbol Pad In / Position [µm] Function
Num Out
x
305
460
615
y
9AREF
9AGND
P5.10
1
2
3
-
-
I
0 Reference voltage for the A/D converter.
0 Reference ground for the A/D converter.
0 Port 5 input, analog input AN10,
external up/down T6EUD.
P5.11
P5.12
P5.13
P5.14
P5.15
4
5
6
7
8
I
I
I
I
I
770
925
0 Port 5 input, analog input AN11,
external up/down T5EUD.
0 Port 5 input, analog input AN12,
timer input T6IN.
1081
1236
1391
0 Port 5 input, analog input AN13,
timer input T5IN.
0 Port 5 input, analog input AN14,
external up/down T4EUD.
0 Port 5 input, analog input AN15,
external up/down T2EUD.
9SS
9DD
P2.0
9
-
1563
1688
1960
0 Digital Ground.
10
11
-
0 Digital Supply Voltage.
I/O
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC0IO.
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
12
13
14
15
16
17
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2139
2318
2497
2676
2855
3034
3214
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC1IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC2IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC3IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC4IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC5IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC6IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC7IO.
Data Sheet
5
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
3393
3572
3751
y
9SS
9DD
P2.8
19
20
21
-
0 Digital Ground.
-
0 Digital Supply Voltage.
I/O
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC8IO,
Fast Interrupt EX0IN.
P2.9
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3930
4109
4288
4467
4646
4826
5005
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC9IO,
Fast Interrupt EX1IN.
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC10IO,
Fast Interrupt EX2IN.
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC11IO,
Fast Interrupt EX3IN.
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC12IO,
Fast Interrupt EX4IN.
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC13IO,
Fast Interrupt EX5IN.
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC14IO,
Fast Interrupt EX6IN.
0 Port 2 input/output (open drain, sp. threshold),
Capt. Input/Comp. Output CC15IO,
Fast Interrupt EX7IN, Timer T7 input T7IN.
P3.0
P3.1
P3.2
P3.3
29
30
31
32
I/O
I/O
I/O
I/O
5184
5363
5542
5721
0 Port 3 input/output (open drain, sp. threshold),
Timer T0 Input T0IN.
0 Port 3 input/output (open drain, sp. threshold),
Timer T6 Toggle Latch Output T6OUT.
0 Port 3 input/output (open drain, sp. threshold),
CAPREL Capture Input CAPIN.
0 Port 3 input/output (open drain, sp. threshold),
Timer T3 Toggle Latch Output T3OUT.
Data Sheet
6
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
y
P3.4
P3.5
33
I/O
5900
0 Port 3 input/output (open drain, sp. threshold),
Timer T3 ext.up/down T3EUD.
34
I/O
6079
0 Port 3 input/output (open drain, sp. threshold),
Timer T4 Input T4IN.
9SS
9DD
P3.6
35
36
37
-
6258
6437
6936
0 Digital Ground.
-
0 Digital Supply Voltage.
I/O
498 Port 3 input/output (open drain, sp. threshold),
Timer T3 Input T3IN.
P3.7
38
39
40
41
42
I/O
I/O
I/O
I/O
I/O
6936
6936
695 Port 3 input/output (open drain, sp. threshold),
Timer T2 Input T2IN.
P3.8
892 Port 3 input/output (open drain, sp. threshold),
SSC Master-Rec./Slave-Transmit I/O MRST.
P3.9
6936 1090 Port 3 input/output (open drain, sp. threshold),
SSC Master-Transmit/Slave-Rec. O/I MTSR.
P3.10
P3.11
P3.12
6936 1287 Port 3 input/output (open drain, sp. threshold),
ASC0 Clock/Data Output (Asyn./Syn.) TxD0.
6936 1484 Port 3 input/output (open drain, sp. threshold),
ASC0 Data Input (Asyn.) or I/O (Syn.) RxD0.
43
44
I/O
O
6936 1681 Port 3 input/output (open drain, sp. threshold).
6936 1878 High Byte Enable BHE,
High Byte Write Strobe WRH.
P3.13
P3.15
45
I/O
6936 2075 Port 3 input/output (open drain, sp. threshold),
SSC Master(Slave) Clock Output(Input) SCLK.
46
47
I/O
O
6936 2272 Port 3 input/output (open drain, sp. threshold).
6936 2469 System Clock Output (=CPU Clock) CLKOUT,
Programmable Frequency Output FOUT.
9DD
9SS
48
49
50
51
52
53
-
6936 2666 Digital Supply Voltage.
-
6936 2837 Digital Ground.
P4.0
P4.1
P4.2
P4.3
I/O
I/O
I/O
I/O
6936 2993 Port 4 input/output, Segment Address Line A16.
6936 3149 Port 4 input/output, Segment Address Line A17.
6936 3306 Port 4 input/output, Segment Address Line A18.
6936 3462 Port 4 input/output, Segment Address Line A19.
Data Sheet
7
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
y
P4.4
P4.5
P4.6
54
55
56
I/O
I/O
I/O
6936 3618 Port 4 input/output, Segment Address Line A20,
CAN2 Receive Data Input CAN2_RxD.
6936 3775 Port 4 input/output, Segment Address Line A21,
CAN1 Receive Data Input CAN1_RxD.
6936 3931 Port 4 input/output, Segment Address Line A22
CAN1 Transmit Data Output CAN1_TxD
CAN2 Transmit Data Output CAN2_TxD.
P4.7
57
I/O
6936 4087 Port 4 input/output, Segment Address Line A23,
CAN1 Receive Data Input CAN1_RxD
CAN2 Transmit Data Output CAN2_TxD,
CAN2 Receive Data Input CAN2_RxD.
9DD
9SS
58
59
60
61
-
6936 4244 Digital Supply Voltage.
-
6936 4400 Digital Ground.
RD
O
6936 4556 External Memory Read Strobe RD.
6936 4712 External Memory Write(Low) Strobe WR (WRL).
6936 4869 Ready Input.
WR(L)
O
READY 62
I
ALE
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
O
6936 5025 Address Latch Enable Output.
EA
I
6936 5181 External Access Enable pin.
P0L.0
P0L.1
P0L.2
P0L.3
P0L.4
P0L.5
P0L.6
P0L.7
P0H.0
9DD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
6936 5338 PORT0 input/output, Address/Data Line AD0.
6936 5494 PORT0 input/output, Address/Data Line AD1.
6936 5650 PORT0 input/output, Address/Data Line AD2.
6936 5807 PORT0 input/output, Address/Data Line AD3.
6936 5963 PORT0 input/output, Address/Data Line AD4.
6936 6119 PORT0 input/output, Address/Data Line AD5.
6936 6275 PORT0 input/output, Address/Data Line AD6.
6936 6432 PORT0 input/output, Address/Data Line AD7.
6936 6588 PORT0 input/output, Address/Data Line AD8.
6437 7086 Digital Supply Voltage.
9SS
-
6274 7086 Digital Ground.
P0H.1
P0H.2
I/O
I/O
6110 7086 PORT0 input/output, Address/Data Line AD9.
5947 7086 PORT0 input/output, Address/Data Line AD10.
Data Sheet
8
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
y
P0H.3
P0H.4
P0H.5
P0H.6
P0H.7
P1L.0
78
79
80
81
82
83
I/O
I/O
I/O
I/O
I/O
I/O
5783 7086 PORT0 input/output, Address/Data Line AD11.
5620 7086 PORT0 input/output, Address/Data Line AD12.
5456 7086 PORT0 input/output, Address/Data Line AD13.
5293 7086 PORT0 input/output, Address/Data Line AD14.
5129 7086 PORT0 input/output, Address/Data Line AD15.
4966 7086 PORT1 input/output, Address Line A0,
analog input AN16.
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
9DD
84
85
86
87
88
89
90
91
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4802 7086 PORT1 input/output, Address Line A1,
analog input AN17.
4639 7086 PORT1 input/output, Address Line A2,
analog input AN18.
4475 7086 PORT1 input/output, Address Line A3,
analog input AN19.
4312 7086 PORT1 input/output, Address Line A4,
analog input AN20.
4148 7086 PORT1 input/output, Address Line A5,
analog input AN21.
3985 7086 PORT1 input/output, Address Line A6,
analog input AN22.
3821 7086 PORT1 input/output, Address Line A7,
analog input AN23.
-
I
3658 7086 Digital Supply Voltage.
C167CS 92
MODE
3494 7086 Must be connected to 9DD.1)
Standard oscillator mode, single-chip reset with
PORT0-configuration.
9SS
93
94
95
96
97
98
-
3331 7086 Digital Ground.
P1H.0
P1H.1
P1H.2
P1H.3
P1H.4
I/O
I/O
I/O
I/O
I/O
3167 7086 PORT1 input/output, Address Line A8.
3004 7086 PORT1 input/output, Address Line A9.
2840 7086 PORT1 input/output, Address Line A10.
2677 7086 PORT1 input/output, Address Line A11.
2513 7086 PORT1 input/output, Addr. Line A12,
Capt. Input/Comp. Output CC24.
Data Sheet
9
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
y
P1H.5
P1H.6
P1H.7
9DD
99
I/O
2350 7086 PORT1 input/output, Addr. Line A13,
Capt. Input/Comp. Output CC25.
100 I/O
101 I/O
2186 7086 PORT1 input/output, Addr. Line A14,
Capt. Input/Comp. Output CC26.
2023 7086 PORT1 input/output, Addr. Line A15,
Capt. Input/Comp. Output CC27.
102
-
1859 7086 Digital Supply Voltage.
XTAL2 103
XTAL1 104
O
I
1708 7086 Output of the oscillator amplifier circuit.
1479 7086 Input to oscillator amplifier and internal clock
generator.
9SS
105
-
1316 7086 Digital Ground.
RSTIN 106 I/O
1152 7086 Reset Input with Schmitt-Trigger characteristics,
output in bidirectional reset mode.
RST
OUT
107
O
989 7086 Internal Reset Indication Output.
NMI
9SS
108
109
110
I
825 7086 Non-Maskable Interrupt Input.
662 7086 Digital Ground.
-
-
9DD
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
498 7086 Digital Supply Voltage.
111 I/O
112 I/O
113 I/O
114 I/O
115 I/O
116 I/O
0
0
0
0
0
0
6588 Port 6 input/output, Chip Select 0 Output CS0.
6404 Port 6 input/output, Chip Select 1 Output CS1.
6220 Port 6 input/output, Chip Select 2 Output CS2.
6036 Port 6 input/output, Chip Select 3 Output CS3.
5852 Port 6 input/output, Chip Select 4 Output CS4.
5668 Port 6 input/output,
External Hold Request Input HOLD.
P6.6
117 I/O
0
5485 Port 6 input/output,
External Hold Acknowledge Output HLDA.
P6.7
P8.0
118 I/O
119 I/O
0
0
5301 Port 6 input/output, Bus Request Output BREQ.
5117 Port 8 input/output,
Capt.-Input/Comp.-Output CC16IO,
CAN1 Receive Data Input CAN1_RxD,
CAN2 Receive Data Input CAN2_RxD.
Data Sheet
10
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
y
P8.1
P8.2
P8.3
120 I/O
121 I/O
122 I/O
0
4933 Port 8 input/output,
Capt.-Input/Comp.-Output CC17IO,
CAN1 Transmit Data Output CAN1_TxD,
CAN2 Transmit Data Output CAN2_TxD.
0
0
4749 Port 8 input/output,
Capt.-Input/Comp.-Output CC18IO,
CAN1 Receive Data Input CAN1_RxD,
CAN2 Receive Data Input CAN2_RxD.
4565 Port 8 input/output,
Capt.-Input/Comp.-Output CC19IO,
CAN1 Transmit Data Output CAN1_TxD,
CAN2 Transmit Data Output CAN2_TxD.
P8.4
P8.5
P8.6
P8.7
123 I/O
124 I/O
125 I/O
126 I/O
0
0
0
0
4381 Port 8 input/output,
Capt.-Input/Comp.-Output CC20IO.
4197 Port 8 input/output,
Capt.-Input/Comp.-Output CC21IO.
4013 Port 8 input/output,
Capt.-Input/Comp.-Output CC22IO.
3829 Port 8 input/output,
Capt.-Input/Comp.-Output CC23IO.
3646 Digital Supply Voltage.
3462 Digital Ground.
9DD
9SS
P7.0
127
128
-
-
0
0
0
129 I/O
130 I/O
131 I/O
132 I/O
133 I/O
134 I/O
3278 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT0.
P7.1
P7.2
P7.3
P7.4
P7.5
0
0
0
0
0
3094 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT1.
2910 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT2.
2726 Port 7 input/output, (open drain, sp. threshold),
PWM Channel Output POUT3.
2542 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC28IO.
2358 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC29IO.
Data Sheet
11
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 2
Pad Definitions and Functions (cont’d)
Symbol Pad In / Position [µm] Function
Num Out
x
y
P7.6
P7.7
135 I/O
0
2174 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC30IO.
136 I/O
0
1990 Port 7 input/output, (open drain, sp. threshold),
Capt.-Input/Comp.-Output CC31IO.
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
137
138
139
140
141
142
143
144
145
146
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
0
0
0
1701 Port 5 input, analog input AN0.
1546 Port 5 input, analog input AN1.
1391 Port 5 input, analog input AN2.
1236 Port 5 input, analog input AN3.
1081 Port 5 input, analog input AN4.
925 Port 5 input, analog input AN5.
770 Port 5 input, analog input AN6.
615 Port 5 input, analog input AN7.
460 Port 5 input, analog input AN8.
305 Port 5 input, analog input AN9.
P5.9
1)
Prepared to enable Enhanced Mode, i.e. low-power oscillator mode, single-chip reset with RD/ALE-
configuration.
Note: All 9SS pads and all 9DD pads must be connected to the system ground and the
power supply, respectively.
The pad definitions and locations in this table are only valid for the indicated device
and design step.
Data Sheet
12
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Handling Of Unconnected Pads
Signal input stages may generate undesired switching noise and cross-current when left
open. Respect the following precautions for unconnected (not bonded) pads:
Table 3
Precautions for Unconnected Pads
Pad Type
Recommended Action
Related Pads
Power Supply
Always connect!
9DD, 9SS, 9AREF, 9AGND
Standard IO pads
Switch to output
PORT0, PORT11), P2, P3,
P4, P6, P7, P8
Input port pads
Disable input stages via P5DIDIS P5
Double-bond ports Connect port pad (43, 46), if the
alternate output (44, 47) is used.2)
P3.12 (43/44), P3.15 (46/47)
Configuration lines Always connect!
EA, C167CSMODE, RD3)
XTAL1, RSTIN, NMI
Required
Always connect!
control lines
Optional
control lines
Can be left open
RD3), WR(L), READY, ALE,
RSTOUT
1)
The lower part of PORT1 (P1L) may be left open and its input stages can then be disabled via P1DIDIS.
Port pad is input in this case! If the port pad is used, the corresponding alternate output pad may be left open.
Pin RD can be used for configuration to disable the OWD. Otherwise it is held high by an internal pullup.
2)
3)
Data Sheet
13
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Functional Description
As the standard packaged devices are made from this silicon the C167CS-xC dies
provide exactly the same functionality and behaviour. Also the DC characteristics and
AC characteristics are compatible with those of the packaged devices.
For a description of the functionality and the DC and AC parameters please refer to the
following documents (or later versions thereof):
• C167CS-4R/-L Data Sheet, Version 2.2, 2001-08
• C167CS Derivatives User’s Manual, Version 2.0, 2000-07
C166-Core
ProgMem
IRAM
Internal
RAM
16
16
Data
Data
32
16
ROM
32 KByte
Instr. / Data
CPU
3 KByte
Osc / PLL
XTAL
XRAM
PEC
External Instr. / Data
6+2 KByte
16-Level
Priority
Interrupt Controller
RTC WDT
16
Interrupt Bus
CAN2
Rev 2.0B active
Peripheral Data Bus
16
CAN1
Rev 2.0B active
ADC ASC0 SSC
GPT PWM CCOM2CCOM1
10-Bit
(USART)
(SPI)
T2
T3
T4
T7
T0
16+8
EBC
Channels
T8
T1
8
8
XBUS Control
External Bus
Control
16
T5
T6
BRGen
BRGen
Port 0
Port 1
Port 5
Port 3
Port 7
8
Port 8
8
16
16
16
15
MCB04323_7CS
Figure 3
Block Diagram
Data Sheet
14
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Absolute Maximum Ratings
Table 4
Absolute Maximum Rating Parameters
Parameter
Symbol
Limit Values
min. max.
Unit Notes
Storage temperature
Junction temperature
7ST
7J
-65
-40
-0.5
150
150
6.5
°C
°C
under bias
Voltage on 9DD pins with 9DD
respect to ground (9SS)
V
Voltage on any pin with
respect to ground (9SS)
9IN
-0.5
-10
-
9
DD + 0.5 V
Input current on any pin
during overload condition
10
mA
mA
Absolute sum of all input
currents during overload
condition
|100|
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (9IN > 9DD or 9IN < 9SS) the
voltage on 9DD pins with respect to ground (9SS) must not exceed the values
defined by the absolute maximum ratings.
Storage Conditions
The C167CS-xC dies may be stored for a certain time under the conditions described
below.
Table 5
Bare Die Storage Conditions and Duration
Packing
Environment
Temperature
Rel. Humidity Storage Time
< 60 % < 4 Months
Vacuum pack
Air
15 … 30 °C
Data Sheet
15
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C167CS-xC. All parameters specified in the following sections refer to
these operating conditions, unless otherwise noticed.
Table 6
Operating Condition Parameters
Parameter
Symbol
Limit Values
min. max.
4.5 5.5
Unit Notes
Digital supply voltage
9DD
V
Active mode,
CPUmax = 33 MHz
I
2.5 1)
5.5
V
V
PowerDown mode
Digital ground voltage
Overload current
9SS
0
Reference voltage
,
-
-
5
mA Per pin 2) 3)
OV
3)
Absolute sum of overload Σ|,OV|
currents
50
mA
External Load
Capacitance
&
-
50
pF
Pin drivers in
L
fast edge mode 4)
Temperature of the
bottom side of the die
7D
-40
-40
150
125
°C
°C
SAL-C167CS-xC...
SAK-C167CS-xC...
1)
Output voltages and output currents will be reduced when 9DD leaves the range defined for active mode.
2)
Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. 9OV ! 9DD+0.5V or 9OV ꢀ 9SS-0.5V). The absolute sum of input overload
currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD, WR,
etc.
3)
4)
Not 100% tested, guaranteed by design and characterization.
The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in
dynamic current mode must be respected when designing the system.
Data Sheet
16
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Chip Outline
0.38
7.29
y
x
0,0
0.090
0.125
min
Typical
Dimensions in mm
Figure 4
Data Sheet
17
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Table 7
Item
Wafer Characteristics
Characteristic
Chips per wafer
262 (geometrically)
Metallization layers
2
Metallization material
Metallization thickness
Metallization barrier material
Metallization isolation
Metallization material on pads
Passivation
AlCu
Met1: 450 nm, Met2: 800 nm
Ti
SOG-CMP
AlSiCu (Al 98.5% - SI 1% - Cu 0.5%)
Oxide (300 nm) + nitride (500 nm)
None (silicon)
Backside metallization1)
Inkdot diameter
1.0 - 1.3 typical
1)
The backside of the chip can either be left unconnected or must be connected to VSS
.
The wafers are glued to a plastic tape which is fixed within a plastic ring (see Figure 5).
Wafers can be shipped in one piece or sawn into individual dies.
Note: Please refer also to the document "Bare Die Packing Information".
Data Sheet
18
V1.0, 2001-08
C167CS-xC Bare Die
Step BA
Wafer Outline
Plastic Frame
Plastic Tape
Wafer
152.4 (6“)
210
230
Dimensions in mm
Figure 5
Data Sheet
19
V1.0, 2001-08
Infineon goes for Business Excellence
“Business excellence means intelligent approaches and clearly
defined processes, which are both constantly under review and
ultimately lead to good operating results.
Better operating results and business excellence mean less
idleness and wastefulness for all of us, more professional
success, more accurate information, a better overview and,
thereby, less frustration and more satisfaction.”
Dr. Ulrich Schumacher
h t t p : / / w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
相关型号：
©2020 ICPDF网 联系我们和版权申明