C3225X5R1C106K [INFINEON]
500kHz, 40A, 2-phase Synchronous Buck Converter using iP2001; 为500kHz ， 40A ，两相同步降压转换器使用iP2001
| 型号： | C3225X5R1C106K |
| 厂家： | 
Infineon |
| 描述： | 500kHz, 40A, 2-phase Synchronous Buck Converter using iP2001 |
| 文件： | 总8页 (文件大小：651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRDCiP2001-A
R
EFERENCE
D
ESIGN
International Rectifier 233 Kansas Street, El Segundo, CA 90245 USA
•
IRDCiP2001-A, 500kHz, 40A, 2-phase Synchronous Buck
Converter using iP2001
Overview
In this document, table 1 and figure 1 are provided to enable engineers to
easily evaluate the iP2001 in a 2-phase configuration that is capable of
providing up to 40A in a lab environment without airflow. Figures 3, 4, 5 and
6 and the complete bill of materials in table 2 are provided as a reference
design to enable engineers to very quickly and easily design a 2-phase
converter. In order to optimize this design to your specific requirements
refer to the data sheet for the controller listed in the bill of materials. A variety
of other controllers may also be used, but the design will require layout and
control circuit modifications.
Demoboard Quick Start Guide
Initial Settings:
z The output is set to 1.7V, but can be adjusted from 1.1 to 1.85V by setting
S1 according to the VID codes provided in Table 1. Droop control is set to 50mV at 40A, but can be adjusted by
following the instructions in the data sheet for the PWM controller.
z The switching frequency per phase is set to 500kHz with the frequency set resistor R4. This creates an effective
output frequency of 1MHz. The graph in figure 1 shows the relationship between R4 and the switching frequency
per phase. This frequency may be adjusted by changing R4 according to this graph; however, extreme changes
from the 500kHz set point may require redesigning the control loop and adjusting the values of input and output
capacitors. Also, refer to the SOA graph in the iP2001 datasheet for maximum operating current at different
frequencies.
Procedure for Connecting and Powering Up Demoboard:
1. Apply input voltage (5-12V) across VIN (TP18) and PGND (TP15). Note that this input source must be applied first during
the power-up sequence.
2. Apply +5V logic power across +5V (TP19) and PGND (TP20).
3. Apply load across VOUT pads (TP11 & TP12) and PGND pads (TP15 & TP16)
4. Set ENABLE high.
5. Monitor switch node signals (optional) via TP7 & TP8.
6. Adjust load accordingly.
iP2001 Recommended Operating Conditions
(refer to the iP2001 datasheet for maximum operating conditions)
Input voltage:
5 - 12V
Output voltage:
Output current:
Switching Freq:
1.1 - 1.85V
20A per phase, 40A total for 2-phase demo board.
500kHz per phase, 1MHz effective output frequency.
07/19/02
IRDCiP2001-A
1000
100
10
1
100
1000
Output Frequency (kHz)
Figure 1 - R4 vs. Frequency (per Phase)
VID4 VID3 VID2 VID1 VID0 VDAC
VID4 VID3 VID2 VID1 VID0 VDAC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Off
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.100
1.250
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
Table 1 - PWM IC Voltage Identification Codes
2
www.irf.com
IRDCiP2001-A
92%
fSW= 500kHz
90%
88%
86%
84%
82%
80%
fSW= 1MHz
VIN = 12V
V
OUT = 1.6V
TA = 25°C
0
5
10
15
20
25
30
35
40
Output Current (A)
Figure 2 - Typical Efficiency vs. Current
Refer to the following application notes for detailed guidelines and suggestions when
implementing iPOWIR Technology products:
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s
iPOWIR Technology BGAPackages
This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA’s
on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and
reworking recommendations.
AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design
This paper describes how to optimize the PCB layout design for both thermal and electrical performance.
This includes placement, routing, and via interconnect suggestions.
AN-1030: Applying iPOWIR Products inYour Thermal Environment
This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the
operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.
www.irf.com
3
IRDCiP2001-A
P
C O M
6
7
F B
7
8
9
1 0
1 1
1 2
6
5
4
3
2
1
Fig. 3 - Reference Design Schematic
4
www.irf.com
IRDCiP2001-A
Fig. 4 - Component Placement Top Layer
Fig. 5 - Component Placement Bottom Layer
www.irf.com
5
IRDCiP2001-A
Designator
Value 1
0.022uF
10.0uF
100uF
22.0pF
0.010uF
4700pF
0.54uH
1K
Value 2
50V
16V
6.3V
50V
50V
50V
27A
1/8W
1/8W
1/8W
-
Type
X7R
Tolerance
10%
10%
10%
5%
Package
0805
Mfr.
TDK
Mfr. Part No.
C2012X7R1H223K
C3225X5R1C106K
C5750X5R0J107K
C2012COG1H220J
C2012X7R1H103K
C1608X7R1H472K
ETQP6F0R6BFA
MCR10EZHJ102
MCR10EZHJ000
MCR10EZHJ103
-
C1
C2, C6-C11, C27, C30, C31
X5R
1210
TDK
C19, C20, C22, C23
X5R
2220
TDK
C28
C33
COG
0805
TDK
X7R
10%
10%
20%
5%
0805
TDK
Cx
X7R
0603
TDK
L2 L3
Ferrite
Thick film
Thick film
Thick film
-
SMT
Panasonic
ROHM
ROHM
ROHM
-
R1, R2
R11, R12, R14
R6, R16, R17
R3, R19, D2, D3
R4
0805
0
<50m
5%
0805
10K
0805
-
-
-
51K
1/8W
1/8W
1/10W
6 position
-
Thick film
Thick film
Thick film
Switch
-
5%
0805
ROHM
ROHM
KOA
MCR10EZHJ513
MCR10EZHJ202
RM73B1J510J
SD06H0SK
R7, R8
Rx
2K
5%
0805
51
5%
0603
S1
SPST
4-40
-
-
SMT
C&K Components
Keystone
Intersil
IR
ST1 - ST4
U1
-
-
8412
-
PWM controller 0 - 70°C
SOIC20
11 x 11 x 3mm
HIP6311CB
U3, U4
-
-
DC-DC
-
IP2001
Table 2 - Reference Design Bill of Materials
Adjusting the Over-Current Limit
R7 & R8 are the resistors used to adjust the over-current trip point. The trip point is a function of the controller and
corresponds to 165% of the output current indicated on the x-axis of Fig. 6. For example, selecting a resistance of 1.5K
at each phase will set the trip point to 165% of 15A, or 24.75A. The trip point for each phase on the demoboard is currently
set to 165% of 20A, or 33A.
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
10
11
12
13
14
15
16
17
18
19
20
Output Current (A)
Fig. 6 - RISEN vs Current (per Phase)
6
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IRDCiP2001-A
Sequencing Tip
It’s important to have proper sequencing between the control IC and the iP2001 blocks. This assures the soft-start
routine of the IC will properly ramp-up the output voltage during a power-up or restart from shut down event. Figure
7 shows a simple and cost effective way to synchronize the iP2001 blocks with an HIP6311 control IC in a 2 Phase
configuration.
Placing Schottky diodes between the iP2001’s PRDY pin and the IC’s FS/DIS pin creates an interface analogous to an
AND operation. With this configuration, no single iP2001 can enable the IC independently. This configuration also
resolves any differences in timing and logic thresholds between iP2001 devices. The capacitors are used to filter
high frequency noise on the PRDY line. Additionally, the ENABLE pin of the iP2001 blocks can be used as the master
control switch for the system.
During power-up, the PRDY pin is held low until V reaches a typical voltage of 4.4V. Until then, the schottky diode is
forward biased and clamps the FS/DIS pin well beDloDw the disable voltage of the HIP6311 IC (typically 1V). Upon
reaching 4.4V, the PRDY pin transitions to a logic-level high state and releases the clamp on the FS/DIS pin. This
enables the IC and allows its soft start routine to begin (see figure 8), assuming the voltage at the IC’s VCC pin is
greater than its power-on reset threshold.
When the ENABLE pin is held to a logic-level low state (shut down mode), the PRDY pin clamps the FS/DIS pin of the
IC below the disable voltage. After the ENABLE pin transitions to a logic-level high state, the PRDY releases the
clamp on the FS/DIS pin, enabling the IC and allowing its soft start routine to begin (see figure 9).
During power-down, the PRDY pin transitions to a logic-level low state when the VDD reaches the under voltage lock
out threshold of the iP2001 blocks. The FS/DIS pin is then clamped below the disable voltage, disabling the control IC.
BAT54
PRDY1
ENABLE
COMP
FB
PWM1
PWM2
ISEN2
ISEN3
PWM3
0.22µF
iP2001
BAT54
PRDY2
FS/DIS
GND
ENABLE
0.22µF
iP2001
51k
Master
Control
VSEN
HIP6311
Fig. 7 - Sequencing Schematic
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7
IRDCiP2001-A
Ch 1: VDD
Ch 2: PRDY
Ch 3: VOUT
Fig. 8 - VDD Rise vs. Output Timing
Ch 1: ENABLE
Ch 2: PRDY
Ch 3: VOUT
Fig. 9 - Enable On vs. Output Timing
Use of this design for any application should be fully verified by the customer. International
Rectifier cannot guarantee suitability for your applications, and is not liable for any result of
usage for such applications including, without limitation, personal or property damage or
violation of third party intellectual property rights.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
www.irf.com
8
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