C504 [INFINEON]
8-Bit CMOS Microcontroller; 8位CMOS微控制器
| 型号： | C504 |
| 厂家： | 
Infineon |
| 描述： | 8-Bit CMOS Microcontroller |
| 文件： | 总49页 (文件大小：962K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microcomputer Components
8-Bit CMOS Microcontroller
C504
Data Sheet 05.96
C504
Revision History:
Current Version: 05.96
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Edition 05.96
This edition was realized using the software system FrameMaker .
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1996.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
1
2
Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
8-Bit CMOS Microcontroller
Advance Information
C504
• Fully compatible to standard 8051 microcontroller
• Up to 40 MHz operating frequency
• 16 K×8 ROM (C504-2R only, optional ROM protection)
• 256×8 RAM
• 256×8 XRAM
• Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)
• Three 16-bit timers/counters (timer 2 with up/down counter feature)
• Capture/compare unit for PWM signal generation and signal capturing
- 3-channel, 16-bit capture/compare unit
- 1-channel, 10-bit compare unit
• Compare unit
• USART
• 10-bit A/D Converter with 8 multiplexed inputs
• Twelve interrupt sources with two priority levels
• On-chip emulation support logic (Enhanced Hooks Technology TM
• Programmable 15-bit Watchdog Timer
• Oscillator Watchdog
)
• Fast Power On Reset
• Power Saving Modes
• M-QFP-44 package
• Temperature ranges: SAB-C504 TA : 0 to 70°C
SAF-C504
TA : – 40 to 85°C
SAH-C504 TA : – 40 to 110°C (max. operating frequency.: TBD)
SAK-C504 TA : – 40 to 125°C (max. operating frequency.: 12 MHz)
Semiconductor Group
3
05.96
C504
The C504 with its capture compare unit (CCU) especially provides a functionality, which allows to
use the microcontroller in motor control applications. Further, the C504 is functionally upward
compatible with the SAB 80C52/C501 microcontroller and can replace it in existing applications.
The C504-2R contains a non-volatile 16K×8 read-only program memory, a volatile on-chip 512×8
read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/
compare unit with compare timer, a 10-bit compare timer, a twelve source, two priority level interrupt
structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a
genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the
program memory on chip. Therefore, the term C504 refers to all versions within this data sheet
unless otherwise noted.
Ordering Information
Type
Ordering Code Package
Description
(8-Bit CMOS microcontroller)
SAB-C504-LM
Q67120-C1048 P-MQFP-44 for external memory (12 MHz)
Q67120-C1049 P-MQFP-44 for external memory (24 MHz)
Q67120-C1050 P-MQFP-44 for external memory (40 MHz)
Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (12 MHz)
SAB-C504-L24M
SAB-C504-L40M
SAB-C504-2RM
SAB-C504-2R24M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (24 MHz)
SAB-C504-2R40M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (40 MHz)
Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C504) and – 40 ˚C to
125 ˚C (SAK-C504) are available on request.
The ordering number of ROM types (DXXXX extensions) is defined after program release
(verification) of the customer.
Semiconductor Group
4
C504
Figure 1
Logic Symbol
Semiconductor Group
5
C504
Figure 2
Pin Configuration (top view)
Semiconductor Group
6
C504
Table 1
Pin Definitions and Functions
Symbol
Pin Number I/O
(P-MQFP-44) *)
Function
Port 1
P1.0-P1.7
40-44,
1-3
I/O
is an 8-bit bidirectional port. Port pins can be used for
digital input/output. P1.0 - P1.3 can also be used as analog
inputs of the A/D-converter. As secondary digital functions,
port 1 contains the timer 2 pins and the capture/compare
inputs/outputs. Port 1 pins are assigned to be used as
analog inputs via the register P1ANA.
The functions are assigned to the pins of port 1 as follows:
40
41
P1.0 / AN0 / T2
Analog input channel 0 /
input to counter 2
Analog input channel 1 /
capture/reload trigger of timer 2 /
up-down count
P1.1 / AN1 / T2EX
42
43
P1.2 / AN2 / CC0
Analog input channel 2 /
input/output of capture/compare
channel 0
P1.3 / AN3 / COUT0 Analog input channel 3 /
output of capture/compare
channel 0
44
1
P1.4 / CC1
Input/output of capture/compare
channel 1
Output of capture/compare
channel 1
Input/output of capture/compare
channel 2
P1.5 / COUT1
P1.6 / CC2
2
3
P1.7 / COUT2
Output of capture/compare
channel 2
RESET
4
I
RESET
A high level on this pin for one machine cycle while the
oscillator is running resets the device. An internal diffused
resistor to VSS permits power-on reset using only an
external capacitor to VCC.
*) I = Input
O = Output
Semiconductor Group
7
C504
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number I/O
(P-MQFP-44) *)
Function
P3.0-P3.7
5, 7-13
I/O
Port 3
is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D)
operate as defined for the C501. P3.2 to P3.7 contain the
external interrupt inputs, timer inputs, input and as an
additional optinal function four of the analog inputs of the
A/D-converter. Port 3 pins are assigned to be used as
analog inputs via the bits of SFR P3ANA.
P3.6/WR can be assigned as a third interrupt input. The
functions are assigned to the pins of port 3 as follows:
5
7
8
9
P3.0 / RxD
P3.1 / TxD
Receiver data input (asynch.) or data
input/output (synch.) of serial
interface
Transmitter data output (asynch.) or
clock output (synch.) of serial
interface
P3.2 / AN4 / INT0 Analog input channel 4 / external
interrupt 0 input / timer 0 gate control
input
P3.3 / AN5 / INT1 Analog input channel 5 / external
interrupt 1 input / timer 1 gate control
input
10
11
12
P3.4 / AN6 / T0
Analog input channel 6 / timer 0
counter input
Analog input channel 7 / timer 1
counter input
P3.5 / AN7 / T1
P3.6 / WR / INT2 WR control output; latches the data
byte from port 0 into the external data
memory /
external interrupt 2 input
13
6
P3.7 / RD
RD control output; enables the
external data memory
CTRAP
I
CCU Trap Input
With CTRAP = low the compare outputs of the CAPCOM
unit are switched to the logic level as defined in the COINI
register (if they are enabled by the bits in SFR TRCON).
CTRAP is an input pin with an internal pullup resistor. For
power saving reasons, the signal source which drives the
CTRAP input should be at high or floating level during
power-down mode.
*) I = Input
O = Output
Semiconductor Group
8
C504
Table 1
Pin Definitions and Functions (cont’d)
Symbol
XTAL2
XTAL1
Pin Number I/O
(P-MQFP-44) *)
Function
14
–
XTAL2
Output of the inverting oscillator amplifier.
15
–
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1
should be driven, while XTAL2 is left unconnected. There
are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
divided down by a divide-by-two flip-flop. Minimum and
maximum high and low times as well as rise/fall times
specified in the AC characteristics must be observed.
P2.0-P2.7
18-25
I/O
Port 2
is a bidirectional I/O port with internal pullup resistors. Port
2 pins that have 1s written to them are pulled high by the
internal pullup resistors, and in that state can be used as
inputs. As inputs, port 2 pins being externally pulled low
will source current (IIL, in the DC characteris-tics) because
of the internal pullup resistors. Port 2 emits the high-order
address byte during fetches from external program
memory and during accesses to external data memory that
use 16-bit addresses (MOVX @DPTR). In this application
it uses strong internal pullup resistors when issuing 1s.
During accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of the
P2 special function register.
PSEN
ALE
26
27
O
O
The Program Store Enable
output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every six oscillator periodes except during
external data memory accesses. Remains high during
internal program execution.
The Address Latch Enable
output is used for latching the low-byte of the address into
external memory during normal operation. It is activated
every six oscillator periodes except during an external data
memory access. When instructions are executed from
internal ROM (EA=1) the ALE generation can be disabled
by bit EALE in SFR SYSCON.
*) I = Input
O = Output
Semiconductor Group
9
C504
Table 1
Pin Definitions and Functions (cont’d)
Symbol
Pin Number I/O
(P-MQFP-44) *)
Function
COUT3
28
O
I
10-Bit compare channel output
This pin is used for the output signal of the 10-bit compare
timer 2 unit. COUT3 can be disabled and set to a high or
low state.
EA
29
External Access Enable
When held at high level, instructions are fetched from the
internal ROM (C504-2R only) when the PC is less than
4000 .When held at low level, the C504 fetches all
H
instructions from external program memory.
For the C504-L this pin must be tied low.
P0.0-P0.7
37-30
I/O
Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float, and in that state can be used
as high-impendance inputs.Port 0 is also the multiplexed
low-order address and data bus during accesses to
external program or data memory. In this application it
uses strong internal pullup resistors when issuing 1 s.
Port 0 also outputs the code bytes during program
verification in the C504-2R. External pullup resistors are
required during program (ROM) verification.
VAREF
VAGND
VSS
38
39
16
17
–
–
–
–
Reference voltage for the A/D converter.
Reference ground for the A/D converter.
Ground (0V)
VCC
Power Supply (+5V)
*) I = Input
O = Output
Semiconductor Group
10
C504
Functional Description
The C504 basic architecture is fully compatible to the standard 8051 microcontroller family. While
maintaining all architectural and operational characteristics of the SAB 80C52 / C501, the C504
incorporates some enhancements such as on-chip XRAM, A/D converter, fail save mechanisms,
and a versatile capture/compare unit.
Figure 3 shows a block diagram of the C504.
Figure 3
Block Diagram of the C504
Semiconductor Group
11
C504
CPU
The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % three-
byte instructions. With a 12 MHz crystal, 58 % of the instructions are executed in 1.0µs (24 MHz:
500 ns, 40 MHz : 300 ns).
Special Function Register PSW (Address D0 )
H
Reset Value : 00
H
Bit No. MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
P
H
H
H
H
H
H
H
H
D0
CY
AC
F0
RS1
RS0
OV
F1
PSW
H
Bit
Function
CY
Carry Flag
Used by arithmetic instruction.
AC
F0
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1
RS0
Function
Bank 0 selected, data address 00 -07
0
0
1
1
0
1
0
1
H
H
Bank 1 selected, data address 08 -0F
H
H
Bank 2 selected, data address 10 -17
H
H
Bank 3 selected, data address 18 -1F
H
H
OV
Overflow Flag
Used by arithmetic instruction.
General Purpose Flag
Parity Flag
F1
P
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group
12
C504
Memory Organization
The C504 CPU manipulates operands in the following four address spaces:
– up to 64 Kbyte of external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 256 bytes of internal XRAM data memory
– a 128 byte special function register area
Figure 4 illustrates the memory address spaces of the C504.
Figure 4
C504 Memory Map
The XRAM in the C504 is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX instructions) must be used for accessing
the XRAM. The XRAM can be enabled and disabled by the XMAP bit in the SYSCON register.
ROM Protection
The C504-2R ROM version allows to protect the content of the internal ROM against read out by
non authorized people. The type of ROM protection (protected or unprotected) is fixed with the
ROM mask. Therefore, the customer of a C504-2R ROM version has to define whether ROM
protection has to be selected or not.
Semiconductor Group
13
C504
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the
special function register area.
The 63 special function register (SFR) include pointers and registers that provide an interface
between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits
within the SFR area.
The SFRs of the C504 are listed in table 2 and table 3. In table 2 they are organized in groups
which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in
numeric order of their addresses.
Semiconductor Group
14
C504
Table 2
Special Function Registers - Functional Blocks
Block
Symbol Name
Address Contents after
Reset
1)
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
E0
F0
83
82
00
00
00
00
00
07
H
H
H
H
H
H
H
1)
H
H
H
1)
D0
H
81
B1
H
H
3)
SYSCON System Control Register
XX10XXX0
B
1)
3)
Interrupt
System
IEN0
IEN1
CCIE2)
IP0
IP1
ITCON
Interrupt Enable Register 0
Interrupt Enable Register 1
Capture/Compare Interrupt Enable Reg.
Interrupt Priority Register 0
Interrupt Priority Register 1
A8
0X000000
XX000000
H
B
B
3)
A9
H
D6
B8
B9
00
H
H
H
1)
3)
3)
XX000000
XX000000
00101010
B
B
B
H
H
Interrupt Trigger Condition Register
9A
1)
Ports
P0
P1
Port 0
Port 1
80
90
90
FF
FF
H
H
H
H
H
1)
1) 4)
1)
3)
P1ANA2) Port 1 Analog Input Selection Register
XXXX1111
FF
FF
H
XX1111XX
B
P2
P3
Port 2
Port 3
A0
B0
B0
H
H
H
H
1)
1) 4)
3)
P3ANA2) Port 3 Analog Input Selection Register
B
B
1
3)
A/D-
Converter
ADCON0 A/D Converter Control Register 0
ADCON1 A/D Converter Control Register 1
ADDATH A/D Converter Data Register High Byte
ADDATL A/D Converter Data Register Low Byte
P1ANA2) Port 1 Analog Input Selection Register
P3ANA2) Port 3 Analog Input Selection Register
D8
DC
D9
XX000000
01XXX000
H
B
3)
H
00
H
H
H
3)
DA
00XXXXXX
XXXX1111
B
B
B
4)
4)
3)
3)
90
B0
H
H
XX1111XX
Serial
Channels
PCON2) Power Control Register
87
99
98
000X0000
H
H
H
B
3)
SBUF
SCON
Serial Channel Buffer Register
Serial Channel Control Register
XX
00
H
H
1)
1)
Timer 0/
Timer 1
TCON
TH0
TH1
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
88
00
00
00
00
00
00
H
H
8C
8D
8A
H
H
H
H
H
H
H
H
H
TL0
TL1
Timer 1, Low Byte
8B
89
TMOD
Timer Mode Register
H
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
15
C504
Table 2
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol Name
Address Contents after
Reset
1)
Timer 2
T2CON Timer 2 Control Register
T2MOD Timer 2 Mode Register
C8
00
H
H
3)
C9
XXXXXXX0
H
B
RC2H
RC2L
TH2
Timer 2 Reload Capture Register, High Byte CB
Timer 2 Reload Capture Register, Low Byte CA
Timer 2 High Byte
Timer 2 Low Byte
00
H
H
H
H
H
00
H
CD
CC
00
H
TL2
00
H
Capture /
Compare
Unit
CT1CON Compare timer 1 control register
E1
DE
DF
00010000
B
H
H
CCPL
CCPH
Compare timer 1 period register, low byte
Compare timer 1 period register, high byte
00
H
00
H
H
H
H
H
H
H
CT1OFL Compare timer 1 offset register, low byte
CT1OFH Compare timer 1 offset register, high byte
CMSEL0 Capture/compare mode select register 0
CMSEL1 Capture/compare mode select register 1
E6
E7
E3
E4
E2
00
H
00
H
00
H
00
H
COINI
Compare output initialization register
FF
H
TRCON Trap enable control register
CF
C2
00
H
H
CCL0
CCH0
CCL1
CCH1
CCL2
CCH2
CCIR
CCIE2)
Capture/compare register 0, low byte
00
H
H
H
H
H
H
H
H
Capture/compare register 0, high byte
Capture/compare register 1, low byte
Capture/compare register 1, high byte
Capture/compare register 2, low byte
Capture/compare register 2, high byte
C3
C4
C5
C6
C7
00
H
00
H
00
H
00
H
00
H
Capture/compare interrupt request flag reg. E5
Capture/compare interrupt enable register D6
00
H
00
H
H
H
H
H
H
H
H
CT2CON Compare timer 2 control register
C1
D2
D3
00010000
B
CP2L
CP2H
CMP2L
Compare timer 2 period register, low byte
Compare timer 2 period register, high byte
Compare timer 2 compare register, low byte D4
00
H
3)
XXXXXX00
B
00
H
3))
CMP2H Compare timer 2 compare register, high byte D5
XXXXXX00
B
BCON
Block commutation control register
D7
00
H
1)
3)
Watchdog WDCON Watchdog Timer Control Register
WDTREL Watchdog Timer Reload Register
C0
XXXX0000
H
B
86
00
H
H
3)
Power
PCON2) Power Control Register
87
88
000X0000
0XXXXXXX
H
H
B
4)
3)
Save Mode PCON1 Power Control Register 1
B
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) X means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
16
C504
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses
Addr Register Content Bit 7
after
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1)
Reset
2)
80
81
82
83
86
P0
FF
07
.7
.7
.7
.7
.6
.6
.6
.6
.6
.5
.5
.5
.5
.5
.4
.4
.4
.4
.4
.3
.3
.3
.3
.3
.2
.2
.2
.2
.2
.1
.1
.1
.1
.1
.0
.0
.0
.0
.0
H
H
H
H
H
H
SP
H
H
H
H
DPL
DPH
00
00
WDTREL 00
WDT
PSEL
87
PCON
000X-
0000
SMOD PDS
IDLS
–
GF1
GF0
PDE
IDLE
H
B
2)
3)
88
88
TCON
00
TF1 TR1
TF0
–
TR0
–
IE1
–
IT1
–
IE0
–
IT0
–
H
H
H
PCON1 0XXX- EWPD –
XXXX
B
89
TMOD
TL0
00
00
00
00
00
GATE C/T
M1
.5
.5
.5
.5
.5
–
M0
.4
.4
.4
.4
.4
–
GATE C/T
M1
.1
M0
.0
H
H
H
H
H
H
8A
8B
.7
.7
.7
.7
.7
–
.6
.6
.6
.6
.6
–
.3
.3
.3
.3
.3
.2
.2
.2
.2
.2
H
TL1
.1
.0
H
8C
8D
90
TH0
TH1
P1
.1
.0
H
.1
.0
H
2)
FF
T2EX T2
H
H
90 2)3) P1ANA XXXX-
EAN3 EAN2 EAN1 EAN0
H
1111
B
2)
98
99
SCON
SBUF
ITCON
00
SM0
.7
SM1
.6
SM2
.5
REN
.4
TB8
.3
RB8
.2
TI
.1
RI
.0
H
H
XX
H
H
9A
0010-
1010
IT2
IE2
I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR
H
B
2)
A0
A8
P2
FF
.7
.6
–
.5
.4
.3
.2
.1
.0
H
H
H
2)
IEN0
0X00-
0000
EA
ET2
ES
ET1
EX1
ET0
EX0
B
A9
IEN1
XX00-
–
–
ECT1 ECCM ECT2 ECEM EX2
EADC
RxD
H
H
0000
B
2)
B0
P3
FF
H
RD
WR
T1 T0 INT1 INT0 TxD
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
17
C504
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
Addr Register Content Bit 7
after
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1)
Reset
B0 2)3) P3ANA XX11-
–
–
–
–
–
–
–
–
–
–
EAN7 EAN6 EAN5 EAN4
–
–
H
11XX
B
B1
B8
B9
SYSCON XX10-
XXX0
EALE RMAP –
PT2 PS PT1
–
–
XMAP
PX0
H
H
H
B
2)
IP0
XX00-
PX1
PT0
0000
B
IP1
XX00-
PCT1 PCCM PCT2 PCEM PX2
OWDS WDTS WDT
PADC
SWDT
0000
B
2)
WDCON
C0
XXXX-
–
–
H
0000
B
C1
CT2CON 0001-
0000
CT2P ECT2O STE2 CT2
RES
CT2R CLK2 CLK1 CLK0
H
B
C2
C3
C4
C5
C6
C7
C8
CCL0
CCH0
CCL1
CCH1
CCL2
CCH2
00
00
00
00
00
00
.7
.6
.6
.6
.6
.6
.6
.5
.5
.5
.5
.5
.5
.4
.4
.4
.4
.4
.4
.3
.3
.3
.3
.3
.3
.2
.2
.2
.2
.2
.2
.1
.0
.0
.0
.0
.0
.0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
.7
.1
.7
.1
.7
.1
.7
.1
.7
.1
2)
T2CON 00
TF2
EXF2 RCLK TCLK EXEN2 TR2
C/T2
CP/
RL2
C9
T2MOD XXXX-
XXX0
–
–
–
–
–
–
–
DCEN
H
B
CA
CB
RC2L
RC2H
TL2
00
00
00
00
.7
.7
.7
.7
.6
.6
.6
.6
.5
.5
.5
.5
.4
.4
.4
.4
.3
.3
.3
.3
.2
.2
.2
.2
.1
.1
.1
.1
.0
.0
.0
.0
H
H
H
H
H
H
H
H
H
CC
CD
CF
H
H
TH2
TRCON 00
TRPEN TRF
TREN5 TREN4 TREN3 TREN2 TREN1 TREN0
H
2)
D0
D2
PSW
CP2L
00
00
CY
.7
AC
.6
F0
.5
RS1
.4
RS0
.3
OV
.2
F1
.1
P
H
.0
H
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group
18
C504
Table 3
Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)
Addr Register Content Bit 7
after
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1)
Reset
D3
CP2H
XXXX.
XX00
–
–
–
–
–
–
.1
.0
H
B
D4
D5
CMP2L 00
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
.1
.1
.0
.0
H
H
H
CMP2H XXXX.
XX00
B
D6
D7
D8
D9
CCIE
00
ECTP ECTC CC2
FEN
CC2
REN
CC1
FEN
CC1
REN
CC0
FEN
CC0
REN
H
H
H
H
H
BCERR
BCON
00
BCMP PWM1 PWM0 EBCE
BCEM
BCEN BCM1 BCM0
H
2)
ADCON0 XX00-
–
–
IADC BSY
ADM
MX2
MX1
MX0
0000
B
ADDATH 00
H
.9
.1
.8
.0
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
DA
ADDATL 00XX-
XXXX
H
B
DC
ADCON1 01XX-
X000
ADCL1 ADCL0 –
–
–
MX2
MX1
MX0
H
B
DE
CCPL
CCPH
ACC
00
00
00
.7
.6
.6
.6
.5
.5
.5
.4
.4
.4
.3
.3
.3
.2
.2
.2
.1
.1
.1
.0
.0
.0
H
H
H
H
H
DF
E0
.7
2)
.7
H
E1
E2
E3
E4
CT1CON 0001-
0000
CTM
ETRP STE1 CT1
RES
CT1R CLK2 CLK1 CLK0
H
B
COINI
FF
COUT COUTX COUT CC2I
3I 2I
COUT CC1I
1I
COUT CC0I
0I
H
H
H
H
H
H
I
CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL
CMSEL0 00
CMSEL1 00
13
12
11
10
03
CMSEL CMSEL CMSEL CMSEL
23 22 21 20
CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R
02
01
00
0
0
0
0
E5
E6
E7
F0
CCIR
00
H
H
H
H
H
H
H
CT1OFL 00
CT1OFH 00
.7
.7
.7
.6
.6
.6
.5
.5
.5
.4
.4
.4
.3
.3
.3
.2
.2
.2
.1
.1
.1
.0
.0
.0
2)
B
00
H
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
Semiconductor Group
19
C504
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4.
Table 4
Timer/Counter 0 and 1 Operating Modes
Mode Description
TMOD
Gate C/T M1
Input Clock
internal external (max)
M0
0
8-bit timer/counter with a
X
X
0
0
fOSC 12 × 32
/
fOSC/24 × 32
divide-by-32 prescaler
1
2
16-bit timer/counter
X
X
X
X
1
0
1
0
fOSC 12
/
fOSC 24
/
8-bit timer/counter with
8-bit autoreload
fOSC 12
/
fOSC 24
/
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
X
X
1
1
fOSC 12
/
fOSC/24
Timer 1 stops
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/12.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 5 illustrates the
input clock logic.
Figure 5
Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group
20
C504
Timer 2
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as
an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown
in table 5.
Table 5
Timer/Counter 2 Operating Modes
T2CON
T2MOD T2CON
Input Clock
external
P1.1/
T2EX
R×CLK
Mode
Remarks
CP/
or
TR2
internal
RL2
(P1.0/T2)
DCEN
EXEN
T×CLK
16-bit
Auto-
reload
0
0
0
1
1
0
0
X
reload upon
overflow
reload trigger
(falling edge)
Down counting
Up counting
0
0
1
↓
max
OSC/24
f
f
OSC/12
f
f
f
0
0
0
0
1
1
1
1
X
X
0
1
16-bit
Cap-
ture
0
1
1
X
0
X
16 bit Timer/
Counter (only
up-counting)
capture TH2,
TL2 → RC2H,
RC2L
max
OSC/24
OSC/12
0
1
1
X
1
↓
Baud
Rate
Gene-
rator
1
1
X
X
1
1
X
X
0
1
X
no overflow
interrupt
request (TF2)
extra external
interrupt
max
OSC/24
f
OSC/2
↓
(“Timer 2”)
off
X
X
0
X
X
X
Timer 2 stops
–
–
Note: ↓ =
falling edge
Semiconductor Group
21
C504
Capture/Compare Unit
The Capture / Compare Unit (CCU) of the C504 is built up by a 16-bit 3-channel capture/compare
unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit
provides two output signals per channel, which can have inverted signal polarity and non-
overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is
further used to modulate the CAPCOM output signals. In capture mode, the value of the compare
timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx. Figure 6 shows
the block diagram of the CCU.
Figure 6
Block Diagram of the CCU
Semiconductor Group
22
C504
The compare timer 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers which
have each a count rate with a maximum of fOSC/2 up to fOSC/256. The compare timer operations with
its possible compare output signal waveforms are shown in figure 7.
Figure 7
Basic Operating Modes of the CAPCOM Unit
Compare timer 1 runs only in operating mode 1 with one output signal of selectable signal polarity
at the pin COUT3.
Semiconductor Group
23
C504
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the
formulas given in table 6.
Table 6
USART Operating Modes
SCON
Baudrate
Description
Mode
SM0
SM1
0
0
0
1
1
0
f
OSC/12
Serial data enters and exits through R×D.
T×D outputs the shift clock. 8-bit are
transmitted/received (LSB first)
1
2
3
1
0
1
Timer 1/2 overflow rate
8-bit UART
10 bits are transmitted (through T×D) or
received (R×D)
f
OSC/32 or fOSC/64
9-bit UART
11 bits are transmitted (T×D) or
received (R×D)
Timer 1/2 overflow rate
9-bit UART
Like mode 2 except the variable baud rate
Figure 8
Block Diagram of Baud Rate Generation for the Serial Interface
Semiconductor Group
24
C504
The possible baudrates can be calculated using the formulas given in table 7.
Table 7
Formulas for Calculating Baudrates
Baud Rate
Interface Mode
Baudrate
derived from
Oscillator
0
2
f
OSC/12
(2SMOD × fOSC) / 64
Timer 1 (16-bit timer)
(8-bit timer with
1,3
1,3
(2SMOD × timer 1 overflow rate) /32
(2SMOD × fOSC) / (32 × 12 × (256-TH1))
8-bit autoreload)
Timer 2
1,3
fOSC / (32 × (65536-(RC2H, RC2L))
Semiconductor Group
25
C504
10-Bit A/D Converter
The C504 has a high performance 10-bit A/D converter (figure 9) with 8 inputs included which uses
successive approximation technique for the conversion of analog input voltages.
Figure 9
A/D Converter Block Diagram
Semiconductor Group
26
C504
The A/D converter uses two clock signals for operation : the conversion clock f
(= 1/ t
) and
ADC
ADC
the input clock f (= 1/ t ). Both clock signals are derived from the C504 system clock f which
IN
IN
OSC
is applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the f
IN
clock signal. The table in figure 10 shows the prescaler ratios and the resulting A/D conversion
times which must be selected for typical system clock rates.
MCUSystemClock f
Prescaler
f
A/DConversion
IN
ADC
Rate (f
)
[MHz]
[MHz]
Time [µs]
OSC
Ratio
÷ 4
ADCL1 ADCL0
3.5 MHz
12 MHz
16 MHz
24 MHz
32 MHz
40 MHz
1.75
6
0
0
0
0
0
1
0
0
0
1
1
0
.438
1.5
2
48 x t = 27.4
IN
÷ 4
48 x t = 8
IN
8
÷ 4
48 x t = 6
IN
12
16
20
÷ 8
1.5
2
96 x t = 8
IN
÷ 8
96 x t = 6
IN
÷ 16
1.25
192 x t = 9.6
IN
Figure 10
A/D Converter Clock Selection
The analog inputs are located at port 1 and port 3 (4 lines on each port). The corresponding port 1
and port 3 pins have a port structure, which allows to use it either as digital I/Os or analog inputs.
The analog input function of these mixed digital/analog port lines is selected via the registers
P1ANA and P3ANA.
Semiconductor Group
27
C504
Interrupt System
The C504 provides 12 interrupt sources with two priority levels. Figure 11 and 12 give a general
overview of the interrupt sources and illustrate the interrupt request and control flags.
Figure 11
Interrupt Request Sources (Part 1)
Semiconductor Group
28
C504
Figure 12
Interrupt Request Sources (Part 2)
Semiconductor Group
29
C504
Table 8
Interrupt Vector Addresses
Request Flags
Interrupt Source
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
IADC
IE2
TRF, BCERR
CT2P
CC0F-CC2F, CC0R-CC2R
CT1FP, CT1FC
–
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
A/D converter interrupt
External interrupt 2
CAPCOM emergency interrupt
Compare timer 2 interrupt
Capture / compare match interrupt
Compare timer 1 interrupt
Power-down interrupt
0003
H
000B
H
0013
H
001B
H
0023
H
002B
H
0043
H
004B
H
0053
H
005B
H
0063
H
006B
H
007B
H
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-
priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is
serviced. If requests of the same priority are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority
structure determined by the polling sequence as shown in table 9.
Table 9
Interrupt Source Structure
Interrupt Source
Priority
High Priority
Low Priority
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Serial Channel
A/D Converter
External Interrupt 2
CCU Emergency Interrupt
Compare Timer 2 Interrupt
Capture / Compare Match Interrupt
Compare Timer 1 Interrupt
High h
Timer 2 Interrupt
Low
Semiconductor Group
30
C504
Fail Save Mechanisms
The C504 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure.
– 15-bit reloadable watchdog timer
– Oscillator Watchdog
Watchdog Timer
The watchdog timer in the C504 is a 15-bit timer, which is incremented by a count rate of either fSOC
/
12 or fCYCLE/32. From the 15-bit watchdog timer count value only the upper 7 bits can be
programmed. Figure 5 shows the block diagram of the programmable watchdog timer.
Figure 13
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be
stopped during active mode of the device. If the software fails to refresh the running watchdog timer
an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog)
can be examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer
is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction
sequence has been implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and power down
mode of the processor. Therefore, it is possible to use the idle mode in combination with the
watchdog timer function.
Semiconductor Group
31
C504
Oscillator Watchdog
The oscillator watchdog of the C504 serves for three functions :
– Monitoring of the on-chip oscillator's function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504
is put into reset state; if the failure condition again disappears, the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.
– Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.
– Control of external wake-up from software power-down mode
When the power-down mode is left by a low level at the INT0 pin, the oscillator watchdog unit
assures that the microcontroller resumes operation (execution of the power-down wake-up
interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-
chip oscillator are stopped. Both oscillators are started again when power-down mode is
released. When the on-chip oscillator has a higher frequency than the RC oscillator, the
microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip
oscillator to stabilize.
Figure 14
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group
32
C504
Power Saving Modes
Two power down modes are available, the idle mode and power down mode.
– In the idle mode the oscillator of the C504 continues to run, but the CPU is gated off from the
clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers
with the exception of the watchdog timer are further provided with the clock. The CPU status
is preserved in its entirety: the stack pointer, program counter, program status word,
accumulator, and all other registers maintain their data during idle mode.
– In the power down mode, the RC oscillator and the on-chip oscillator which operates with the
XTAL pins is stopped. Therefore all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are
controlled by their port latches, output the values that are held by their SFR's.
Table 10 gives a general overview of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering
Leaving by
Remarks
2-Instruction
Example
Idle mode
ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Hardware Reset
Power-Down
Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware Reset
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Wake-up from power
down
In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC
is restored to its normal operating level, before the power down mode is terminated.
The idle mode can be terminated by activating any enabled peripheral interrupt or by resetting the
C504. The power down mode can be terminated using an interrupt by a short low pulse at the pin
P3.2/AN4/INT0 or by resetting the C504. If a power saving mode is left through an interrupt, the
microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by
a reset operation, the microcontroller state is disturbed and replaced by the reset state of the C504.
Semiconductor Group
33
C504
Absolute Maximum Ratings
Ambient temperature under bias (TA) .............................................................. 0 ˚C to + 70 ˚C
Storage temperature (TST)................................................................................– 65 ˚C to + 150 ˚C
Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS)..............................................– 0.5 V to VCC + 0.5 V
Input current on any pin during overload condition..........................................– 10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..........................| 100 mA |
Power dissipation.............................................................................................TBD
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the
absolute maximum ratings.
Semiconductor Group
34
C504
DC Characteristics
CC = 5 V + 10%, – 15%; VSS = 0 V
V
TA = 0 to 70 °C
for the SAB-C504
for the SAF-C504
for the SAH-C504
for the SAK-C504
TA = – 40 to 85 °C
TA = – 40 to 110 °C
TA = – 40 to 125 °C
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input low voltage (except EA,
RESET, CTRAP)
VIL
– 0.5
0.2 VCC
0.1
–
–
+
V
V
V
V
–
–
–
–
Input low voltage (EA)
VIL1
VIL2
– 0.5
– 0.5
0.2 VCC
0.3
Input low voltage (RESET,
CTRAP)
0.2 VCC
0.1
Input high voltage (except XTAL1, VIH
0.2 VCC
+
V
CC + 0.5
RESET and CTRAP)
0.9
Input high voltage to XTAL1
VIH1
0.7 VCC
0.6 VCC
V
V
CC + 0.5
CC + 0.5
V
V
–
–
Input high voltage to RESET and VIH2
CTRAP
Output low voltage (ports 1, 2, 3, VOL
COUT3)
–
–
0.45
0.45
V
V
V
V
V
IOL = 1.6 mA 1)
IOL = 3.2 mA 1)
Output low voltage (port 0, ALE,
PSEN)
VOL1
Output high voltage (ports 1, 2, 3) VOH
2.4
0.9 VCC
–
–
I
I
OH = – 80 µA,
OH = – 10 µA
Output high voltage (ports 1,3 pins VOH1
in push-pull mode and COUT3)
0.9 VCC
–
IOH = – 800 µA
Output high voltage (port 0 in
VOH2
2.4
0.9 VCC
–
–
I
I
OH = – 800 µA 2),
OH = – 80 µA 2)
external bus mode, ALE, PSEN)
Logic 0 input current (ports 1, 2, 3) IIL
– 10
– 65
– 50
µA
µA
VIN = 0.45 V
VIN = 2 V
Logical 1-to-0 transition current
(ports 1, 2, 3)
ITL
– 650
Input leakage current (port 0, EA) ILI
–
–
± 1
µA
0.45 < VIN < VCC
Pin capacitance
CIO
10
pF
fc = 1 MHz,
TA = 25 °C
7) 8)
Overload current
IOV
–
± 5
mA
Semiconductor Group
35
C504
Parameter
Symbol
Limit Values
Unit Test Condition
typ. 9)
max.
Power supply current:
Active mode, 12 MHz 4)
ICC
ICC
ICC
ICC
ICC
ICC
IPD
16
8
TBD
TBD
TBD
TBD
TBD
TBD
50
mA
mA
mA
mA
mA
mA
µA
V
V
V
V
V
V
V
CC = 5 V, 4)
CC = 5 V, 5)
CC = 5 V, 4)
CC = 5 V, 5)
CC = 5 V, 4)
CC = 5 V, 5)
CC = 2…5.5 V 3)
Idle mode, 12 MHz 5)
Active mode, 24 MHz 4)
Idle mode, 24 MHz 5)
Active mode, 40 MHz 4)
Idle mode, 40 MHz 5)
Power-down mode
25
13
38
17
1
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the
0.9 VCC specification when the address lines are stabilizing.
3) IPD (power-down mode) is measured under following conditions:
EA = Port0 = VCC ; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND = VSS ; all other pins are disconnected.
4) ICC (active mode) is measured with:
XTAL1 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
EA = Port0 = Port1 = RESET = VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal
oscillator is used (appr. 1 mA).
5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.;
RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected.
6) ICC max at other frequencies is given by:
active mode:
idle mode:
TBD
TBD
where f
is the oscillator frequency in MHz. I
values are given in mA and measured at V
= 5 V.
CC
osc
CC
7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VCC and VSS
must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50
mA.
8) Not 100 % tested, guaranteed by design characterization.
9) The typical ICC values are periodically measured at TA = +25 ˚C but not 100% tested.
Semiconductor Group
36
C504
A/D Converter Characteristics
CC = 5 V + 10%, – 15%; VSS = 0 V
4V ≤ VAREF ≤ VCC + 0.1 V;
V
TA = 0 to 70 °C
for the SAB-C504
for the SAF-C504
for the SAH-C504
for the SAK-C504
TA = – 40 to 85 °C
TA = – 40 to 110 °C
TA = – 40 to 125 °C
VSS – 0.1 V ≤ VAGND ≤ VSS + 0.2 V;
Parameter
Symbol
Limit Values
Unit Test Condition
min.
VAGND
–
max.
1)
Analog input voltage
Sample time
VAIN
tS
VAREF
V
64 x tIN
32 x tIN
16 x tIN
8 x tIN
ns
Prescaler ÷ 32
Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4
2)
3)
Conversion cycle time
Total unadjusted error
tADCC
–
384 x tIN ns
192 x tIN
96 x tIN
Prescaler ÷ 32
Prescaler ÷ 16
Prescaler ÷ 8
Prescaler ÷ 4
48 x tIN
TUE
–
–
± 2
± 4
LSB VSS + 0.5V ≤ VIN ≤ VCC – 0.5V 4)
LSB VSS < VIN < VSS + 0.5V
4)
VCC – 0.5V < VIN < VCC
5) 6)
t
ADC in [ns]
Internal resistance of
reference voltage source
RAREF
RASRC
CAIN
–
–
–
tADC / 250 kΩ
– 0.25
2) 6)
tS in [ns]
Internal resistance of
analog source
tS / 500
kΩ
– 0.25
6)
ADC input capacitance
Notes see next page.
50
pF
Clock calculation table :
ClockPrescaler ADCL1, 0
Ratio
t
t
t
ADCC
ADC
S
÷ 32
÷ 16
÷ 8
1
1
0
0
1
0
1
0
32 x t
16 x t
8 x t
64 x t
32 x t
16 x t
8 x t
384 x t
192 x t
96 x t
IN
IN
IN
IN
IN
IN
IN
IN
IN
÷ 4
4 x t
48 x t
IN
IN
IN
Further timing conditions : t
t
min = 500 ns
ADC
IN
= 2 / f
= 2 t
OSC
CLCL
Semiconductor Group
37
C504
Notes:
1) V
may exceed V
AGND
or V
up to the absolute maximum ratings. However, the conversion result in
AREF
AIN
these cases will be X000 or X3FF , respectively.
H
H
2) During the sample time the input capacitance C
can be charged/discharged by the external source. The
AIN
internal resistance of the analog source must allow the capacitance to reach their final voltage level within t .
After the end of the sample time t , changes of the analog input voltage have no effect on the conversion
S
result.
S
3) This parameter includes the sample time t , the time for determining the digital result and the time for the
S
calibration. Values for the conversion clock t
the previous page.
depend on programming and can be taken from the table on
ADC
4) T
is tested at V
= 5.0 V, V = 0 V, V
AGND
= 4.9 V. It is guaranteed by design characterization for all
CC
UE
AREF
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100 % tested, but guaranteed by design characterization.
Semiconductor Group
38
C504
AC Characteristics for C504-L / C504-2R
CC = 5 V + 10%, – 15%; VSS = 0 V
V
TA = 0 to 70 °C
for the SAB-C504
for the SAF-C504
for the SAH-C504
for the SAK-C504
TA = – 40 to 85 °C
TA = – 40 to 110 °C
TA = – 40 to 125 °C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
12-MHz clock Variable Clock
Unit
1/tCLCL = 3.5 MHz to
12 MHz
min.
127
43
30
–
max. min.
max.
ALE pulse width
tLHLL
tAVLL
tLLAX
tLLIV
–
2tCLCL – 40
–
–
–
ns
ns
ns
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
–
t
t
CLCL – 40
CLCL – 23
–
233
–
–
4tCLCL – 100 ns
tLLPL
tPLPH
tPLIV
tPXIX
58
215
–
t
CLCL – 25
–
–
ns
ns
PSEN pulse width
–
3tCLCL – 35
PSEN to valid instr in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN
150
–
–
0
–
3tCLCL – 100 ns
0
–
ns
ns
ns
*)
tPXIZ
–
63
–
t
CLCL – 20
*)
tPXAV
75
–
t
CLCL – 8
–
tAVIV
tAZPL
302
–
–
0
5tCLCL – 115 ns
– ns
0
*)
Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
39
C504
AC Characteristics for C504-L / C504-2R (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
12-MHz clock Variable Clock
Unit
1/tCLCL = 3.5 MHz to
12 MHz
min.
400
400
114
–
max. min.
max.
6tCLCL – 100 –
6tCLCL – 100 –
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
RD pulse width
–
ns
ns
ns
WR pulse width
–
Address hold after ALE
RD to valid data in
–
2tCLCL – 53
–
252
–
–
0
–
–
–
5tCLCL – 165 ns
– ns
Data hold after RD
0
Data float after RD
–
97
517
585
300
–
2tCLCL – 70 ns
8tCLCL – 150 ns
9tCLCL – 165 ns
ALE to valid data in
Address to valid data in
ALE to WR or RD
–
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
–
200
203
43
33
433
33
–
3tCLCL – 50 3tCLCL + 50 ns
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
4tCLCL – 130 –
ns
ns
ns
ns
ns
ns
123
–
t
t
CLCL – 40
CLCL – 50
tCLCL + 40
–
–
7tCLCL – 150 –
–
t
CLCL – 50
–
0
0
–
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 12 MHz
min.
83.3
20
20
–
max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Oscillator period
High time
294
ns
ns
ns
ns
ns
t
t
CLCL – tCLCX
CLCL – tCHCX
Low time
Rise time
20
20
Fall time
–
Semiconductor Group
40
C504
AC Characteristics for C504-L24 / C504-2R24
CC = 5 V + 10 %, – 15 %; VSS = 0 V
V
TA = 0 to 70 °C
for the SAB-C504
for the SAF-C504
TA = – 40 to 85 °C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
24-MHz clock Variable Clock
Unit
1/tCLCL = 3.5 MHz to
24 MHz
min.
43
17
17
–
max. min.
max.
ALE pulse width
tLHLL
tAVLL
tLLAX
tLLIV
–
2tCLCL – 40
–
–
–
ns
ns
ns
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
–
t
t
CLCL – 25
CLCL – 25
–
80
–
–
4tCLCL – 87 ns
tLLPL
tPLPH
tPLIV
tPXIX
22
95
–
t
CLCL – 20
–
–
ns
ns
PSEN pulse width
–
3tCLCL – 30
PSEN to valid instr in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN
60
–
–
0
–
3tCLCL – 65 ns
0
–
ns
ns
ns
*)
tPXIZ
–
32
–
t
CLCL – 10
*)
tPXAV
37
–
t
CLCL – 5
–
tAVIV
tAZPL
148
–
–
0
5tCLCL – 60 ns
– ns
0
*)
Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
41
C504
AC Characteristics for C504-L24 / C504-2R24 (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
24-MHz clock Variable Clock
Unit
1/tCLCL = 3.5 MHz to
24 MHz
min.
180
180
56
–
max. min.
max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
RD pulse width
–
6tCLCL – 70
–
–
–
ns
ns
ns
WR pulse width
–
6tCLCL – 70
Address hold after ALE
RD to valid data in
–
2tCLCL – 27
118
–
0
–
–
–
5tCLCL – 90 ns
– ns
Data hold after RD
0
Data float after RD
–
63
200
220
175
–
2tCLCL – 20 ns
8tCLCL – 133 ns
9tCLCL – 155 ns
ALE to valid data in
Address to valid data in
ALE to WR or RD
–
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
–
75
67
17
5
3tCLCL – 50 3tCLCL + 50 ns
Address valid to WR
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
4tCLCL – 97
–
ns
ns
ns
ns
ns
ns
67
–
t
t
CLCL – 25
CLCL – 37
t
CLCL + 25
–
170
15
–
–
7tCLCL – 122 –
–
t
CLCL – 27
–
0
0
–
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 24 MHz
min.
41.7
12
12
–
max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Oscillator period
High time
294
ns
ns
ns
ns
ns
t
t
CLCL – tCLCX
CLCL – tCHCX
Low time
Rise time
12
12
Fall time
–
Semiconductor Group
42
C504
AC Characteristics for C504-L40 / C504-2R40
CC = 5 V + 10 %, – 15 %; VSS = 0 V
V
TA = 0 to 70 °C
for the SAB-C504
for the SAF-C504
TA = – 40 to 85 °C
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
Parameter
Symbol
Limit Values
40-MHz clock Variable Clock
Unit
1/tCLCL = 3.5 MHz to
40 MHz
min.
35
10
10
–
max. min.
max.
ALE pulse width
tLHLL
tAVLL
tLLAX
tLLIV
–
2tCLCL – 15
–
–
–
ns
ns
ns
Address setup to ALE
Address hold after ALE
ALE low to valid instr in
ALE to PSEN
–
t
t
CLCL – 15
CLCL – 15
–
55
–
–
4tCLCL – 45 ns
tLLPL
tPLPH
tPLIV
tPXIX
10
60
–
t
CLCL – 15
–
–
ns
ns
PSEN pulse width
–
3tCLCL – 15
PSEN to valid instr in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN
25
–
–
0
–
3tCLCL – 50 ns
0
–
ns
ns
ns
*)
tPXIZ
–
20
–
t
CLCL – 5
*)
tPXAV
20
–
t
CLCL – 5
–
tAVIV
tAZPL
65
–
–
5tCLCL – 60 ns
– ns
– 5
– 5
*)
Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group
43
C504
AC Characteristics for C504-L40 / C504-2R40 (cont’d)
External Data Memory Characteristics
Parameter
Symbol
Limit Values
40-MHz clock Variable Clock
Unit
1/tCLCL = 3.5 MHz to
40 MHz
min.
120
120
35
–
max. min.
max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
RD pulse width
–
6tCLCL – 30
–
–
–
ns
ns
ns
WR pulse width
–
6tCLCL – 30
Address hold after ALE
RD to valid data in
–
2tCLCL – 15
75
–
0
–
–
–
5tCLCL – 50 ns
– ns
Data hold after RD
0
Data float after RD
–
38
150
150
90
–
2tCLCL – 12 ns
8tCLCL – 50 ns
9tCLCL – 75 ns
ALE to valid data in
Address to valid data in
ALE to WR or RD
–
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
–
60
70
10
5
3tCLCL – 15 3tCLCL + 15 ns
Address valid to WR
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
4tCLCL – 30
–
ns
ns
ns
ns
ns
ns
40
–
t
t
CLCL – 15
CLCL – 20
t
CLCL + 15
–
–
–
0
125
5
–
7tCLCL – 50
tCLCL – 20
–
–
0
–
External Clock Drive
Parameter
Symbol
Limit Values
Unit
Variable Clock
Freq. = 3.5 MHz to 40 MHz
min.
25
10
10
–
max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Oscillator period
High time
294
ns
ns
ns
ns
ns
t
t
CLCL – tCLCX
CLCL – tCHCX
Low time
Rise time
10
10
Fall time
–
Semiconductor Group
44
C504
Figure 15
Program Memory Read Cycle
Figure 16
Data Memory Read Cycle
Semiconductor Group
45
C504
Figure 17
Data Memory Write Cycle
Figure 18
External Clock Cycle
Semiconductor Group
46
C504
ROM Verification Characteristics for C504-2R
ROM Verification Mode 1
Parameter
Symbol
Limit Values
max.
Unit
min.
tAVQV
tELQV
Address to valid data
ENABLE to valid data
Data float after ENABLE
Oscillator frequency
–
–
0
4
48tCLCL
48tCLCL
48tCLCL
6
ns
ns
tEHQZ
1/tCLCL
ns
MHz
Figure 19
ROM Verification Mode 1
Semiconductor Group
47
C504
ROM Verification Mode 2
Parameter
Symbol
Limit Values
Unit
min.
typ
2 tCLCL
12 tCLCL
–
max.
tAWD
tACY
tDVA
tDSA
tAS
ALE pulse width
–
–
ns
ALE period
–
–
ns
Data valid after ALE
Data stable after ALE
P3.5 setup to ALE low
Oscillator frequency
–
4 tCLCL
ns
8 tCLCL
–
–
–
6
ns
–
4
tCLCL
ns
1/tCLCL
–
MHz
Figure 20
ROM Verification Mode 2
Semiconductor Group
48
C504
AC Inputs during testing are driven at VCC – 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
Figure 21
AC Testing: Input, Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH ≥ ± 20 mA
Figure 22
AC Testing : Float Waveforms
Figure 23
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group
49
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