C515C-8EM_技术文档

Data Sheet, Feb. 2003

C515C

8-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

Edition 2003-02

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide

(www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

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be endangered.

Data Sheet, Feb. 2003

C515C

8-Bit Single-Chip Microcontroller

Microcontrollers

N e v e r s t o p t h i n k i n g .

C515C Data Sheet

Revision History:

2003-02

Previous Version:

2000-08

Page

Subjects (major changes since last revision)

Enhanced Hooks Technology™ is a trademark of Infineon Technologies.

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8-Bit Single-Chip Microcontroller

Features

C515C

• Full upward compatibility with SAB 80C515A

• On-chip program memory (with optional memory protection)

– C515C-8R 64 Kbytes on-chip ROM

– C515C-8E 64 Kbytes on-chip OTP

– alternatively up to 64 Kbytes external program memory

• 256 bytes on-chip RAM

• 2 Kbytes of on-chip XRAM

• Up to 64 Kbytes external data memory

• Superset of the 8051 architecture with 8 datapointers

• Up to 10 MHz external operating frequency (1 µs instruction cycle time at 6 MHz

external clock)

• On-chip emulation support logic (Enhanced Hooks Technology)

• Current optimized oscillator circuit and EMI optimized design

(further features are on next page)

SSC (SPI)

Interface

Full-CAN

Controller

XRAM

2k x 8

RAM

256 x 8

Port 0

Port 1

Port 2

Port 3

I/O

Oscillator

Watchdog

10 Bit ADC

(8 inputs)

T0

T1

Power

Save Modes

Idle/

Power down

Slow down

8 Bit

USART

CPU

8 Datapointer

Timer 2

Capture/Compare Unit

Program Memory

C515C-8R : 64k x 8 ROM

C515C-8E : 64k x 8 OTP

Port 7

I/O

Port 6

Port 5

I/O

Port 4

Analog/

Digital

Input

I/O

MCA03646

Figure 1

C515C Functional Units

Data Sheet

1

2003-02

C515C

• Eight ports: 48 + 1 digital I/O lines, 8 analog inputs

– Quasi-bidirectional port structure (8051 compatible)

– Port 5 selectable for bidirectional port structure (CMOS voltage levels)

• Full-CAN controller on-chip

– 256 register/data bytes are located in external data memory area

– max. 1 MBaud at 8 - 10 MHz operating frequency

• Three 16-bit timer/counters

– Timer 2 can be used for compare/capture functions

• 10-bit A/D converter with multiplexed inputs and built-in self calibration

• Full duplex serial interface with programmable baudrate generator (USART)

• SSC synchronous serial interface (SPI compatible)

– Master and slave capable

– Programmable clock polarity/clock-edge to data phase relation

– LSB/MSB first selectable

– 2.5 MHz transfer rate at 10 MHz operating frequency

• Seventeen interrupt vectors, at four priority levels selectable

• Extended watchdog facilities

– 15-bit programmable watchdog timer

– Oscillator watchdog

• Power saving modes

– Slow-down mode

– Idle mode (can be combined with slow-down mode)

– Software power-down mode with wake-up capability through INT0 or RXDC pin

– Hardware power-down mode

• CPU running condition output pin

• ALE can be switched off

• Multiple separate V_DD/V_SSpin pairs

• P-MQFP-80-1 package

• Temperature Ranges:

SAB-C515C versions: T_A= 0 to 70 °C

SAF-C515C versions: T_A= -40 to 85 °C

SAH-C515C versions: T_A= -40 to 110 °C

Note: Versions for extended temperature range -40 °C to 110 °C (SAH-C515C) are

available on request.

The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller

which additionally provides a full CAN interface, a SPI compatible synchronous serial

interface, extended power save provisions, additional on-chip RAM, 64K of on-chip

program memory, two new external interrupts and RFI related improvements. With a

maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1 µs

at 6 MHz).

Data Sheet

2

2003-02

C515C

The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The

C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory.

The C515C-8E is the OTP version in the C515C microcontroller with an on-chip

64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in

a P-MQFP-80-1 package.

If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally

provides two features:

• The wake-up from software power down mode can, additionally to the external pin

P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin

P4.7/RXDC.

• For power consumption reasons the on-chip CAN controller can be switched off.

Table 1

Device

Differences in Internal Program Memory of the C505 MCUs

Internal Program Memory

ROM

OTP

C515C-LM

C515C-8RM

C515C-8EM

–

64 Kbytes

–

64 Kbytes

Note: The term C515C refers to all versions described within this document unless

otherwise noted.

Ordering Information

The ordering code for Infineon Technologies’ microcontrollers provides an exact

reference to the required product. This ordering code identifies:

• The derivative itself, i.e. its function set

• The specified temperature rage

• The package and the type of delivery

For the available ordering codes for the C515C please refer to the “Product information

Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet

3

2003-02

C515C

V_AGND

V_AREF

Port 0

8 Bit Digital I/O

Port 1

8 Bit Digital I/O

XTAL1

XTAL2

Port 2

8 Bit Digital I/O

ALE

PSEN

EA

Port 3

8 Bit Digital I/O

RESET

PE/SWD

HWPD

CPUR

Port 4

8 Bit Digital I/O

C515C

Port 5

8 Bit Digital I/O

Port 6

8 Bit Analog/

Digital Inputs

V_SSE1

V_DDE1

V_SSE2

V_DDE2

Port 7

1 Bit Digital I/O

V_SS1

V_DD1

V_SSCLK

V_DDCLK

V_SSEXT

V_DDEXT

MCL02714

Figure 2

Logic Symbol

Data Sheet

4

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C515C

V

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P5.6

P5.5

P5.4

P5.3

P5.2

P5.1

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P2.2/A10

P2.1/A9

P2.0/A8

XTAL1

XTAL2

V_SSE1

V_SS1

V_DD1

V_DDE1

P5.0

V_DDE2

HWPD

V_SSE2

N.C.

P1.0/INT3/CC0

P1.1/INT4/CC1

P1.2/INT5/CC2

P1.3/INT6/CC3

P1.4/INT2

P1.5/T2EX

P1.6/CLKOUT

P1.7/T2

C515C

P4.0/ADST

P4.1/SCLK

P4.2/SRI

PE/SWD

P4.3/STO

P4.4/SLS

P4.5/INT8

P4.6/TXDC

P4.7/RXDC

P7.0/INT7

P3.7/RD

P3.6/WR

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

V

MCP02715

Figure 3

C515C Pin Configuration P-MQFP-80-1 (top view)

Data Sheet

5

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C515C

Table 2

Symbol

Pin Definitions and Functions

Pin Number I/O¹⁾Function

P-MQFP-80-1

RESET

1

I

RESET

A low level on this pin for the duration of two

machine cycles while the oscillator is running resets

the C515C. A small internal pullup resistor permits

power-on reset using only a capacitor connected to

V_SS.

V_AREF

V_AGND

3

4

–

I

Reference voltage for the A/D converter

Reference ground for the A/D converter

P6.0-P6.7 12-5

Port 6

is an 8-bit unidirectional input port to the

A/D converter. Port pins can be used for digital

input, if voltage levels simultaneously meet the

specifications high/low input voltages and for the

eight multiplexed analog inputs.

P7.0 / INT7 23

I/O Port 7

is an 1-bit quasi-bidirectional I/O port with internal

pull-up resistor. When a 1 is written to P7.0 it is

pulled high by an internal pull-up resistor, and in that

state can be used as input. As input, P7.0 being

externally pulled low will source current (I_IL, in the

DC characteristics) because of the internal pull-up

resistor. If P7.0 is used as interrupt input, its output

latch must be programmed to a one (1). The

secondary function is assigned to the port 7 pin as

follows:

P7.0 INT7, Interrupt 7 input

Data Sheet

6

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

P3.0-P3.7 15-22

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal

pullup resistors. Port 3 pins that have 1's written to

them are pulled high by the internal pullup resistors,

and in that state can be used as inputs. As inputs,

port 3 pins being externally pulled low will source

current (I_IL, in the DC characteristics) because of

the internal pullup resistors. Port 3 also contains the

interrupt, timer, serial port and external memory

strobe pins that are used by various options. The

output latch corresponding to a secondary function

must be programmed to a one (1) for that function to

operate. The secondary functions are assigned to

the pins of port 3, as follows:

15

16

P3.0 RXD

Receiver data input (asynch.) or

data input/output (synch.) of

serial interface

Transmitter data output (asynch.)

or clock output (synch.) of serial

interface

P3.1 TXD

17

18

P3.2 INT0

P3.3 INT1

External interrupt 0 input / timer 0

gate control input

External interrupt 1 input / timer 1

gate control input

19

20

21

P3.4 T0

P3.5 T1

P3.6 WR

Timer 0 counter input

Timer 1 counter input

WR control output; latches the

data byte from port 0 into the

external data memory

22

P3.7 RD

RD control output; enables the

external data memory

Data Sheet

7

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

P1.0 - P1.7 31-24

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal

pullup resistors. Port 1 pins that have 1's written to

them are pulled high by the internal pullup resistors,

and in that state can be used as inputs. As inputs,

port 1 pins being externally pulled low will source

current (I_IL, in the DC characteristics) because of

the internal pullup resistors. The port is used for the

low-order address byte during program verification.

Port 1 also contains the interrupt, timer, clock,

capture and compare pins that are used by various

options. The output latch corresponding to a

secondary function must be programmed to a one

(1) for that function to operate (except when used for

the compare functions). The secondary functions

are assigned to the port 1 pins as follows:

P1.0 INT3 CC0 Interrupt 3 input / compare 0

output / capture 0 input

31

30

29

28

P1.1 INT4 CC1 Interrupt 4 input / compare 1

output / capture 1 input

P1.2 INT5 CC2 Interrupt 5 input / compare 2

output / capture 2 input

P1.3 INT6 CC3 Interrupt 6 input / compare 3

output / capture 3 input

27

26

P1.4 INT2

P1.5 T2EX

Interrupt 2 input

Timer 2 external reload / trigger

input

25

24

P1.6 CLKOUT System clock output

P1.7 T2

Counter 2 input

XTAL2

36

I

XTAL2

Input to the inverting oscillator amplifier and input to

the internal clock generator circuits.

To drive the device from an external clock source,

XTAL2 should be driven, while XTAL1 is left

unconnected. Minimum and maximum high and low

times as well as rise/fall times specified in the AC

characteristics must be observed.

Data Sheet

8

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

XTAL1

37

O

XTAL1

Output of the inverting oscillator amplifier.

P2.0-P2.7 38-45

I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal

pullup resistors. Port 2 pins that have 1's written to

them are pulled high by the internal pullup resistors,

and in that state can be used as inputs. As inputs,

port 2 pins being externally pulled low will source

current (I_IL, in the DC characteristics) because of

the internal pullup resistors.

Port 2 emits the high-order address byte during

fetches from external program memory and during

accesses to external data memory that use 16-bit

addresses (MOVX @DPTR). In this application it

uses strong internal pullup resistors when issuing

1's. During accesses to external data memory that

use 8-bit addresses (MOVX @Ri), port 2 issues the

contents of the P2 special function register.

CPUR

46

O

CPU Running Condition

This output pin is at low level when the CPU is

running and program fetches or data accesses in

the external data memory area are executed. In idle

mode, hardware and software power down mode,

and with an active RESET signal CPUR is set to

high level.

CPUR can be typically used for switching external

memory devices into power saving modes.

PSEN

47

O

The Program Store Enable

output is a control signal that enables the external

program memory to the bus during external fetch

operations. It is activated every six oscillator

periods, except during external data memory

accesses. The signal remains high during internal

program execution.

Data Sheet

9

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

ALE

48

O

The Address Latch Enable

output is used for latching the address into external

memory during normal operation. It is activated

every six oscillator periods, except during an

external data memory access. ALE can be switched

off when the program is executed internally.

EA

49

I

External Access Enable

When held high, the C515C executes instructions

always from the internal ROM. When held low, the

C515C fetches all instructions from external

program memory.

Note: For the ROM protection version EA pin is

latched during reset.

P0.0-P0.7 52-59

I/O Port 0

is an 8-bit open-drain bidirectional I/O port.

Port 0 pins that have 1's written to them float, and in

that state can be used as high-impedance inputs.

Port 0 is also the multiplexed low-order address and

data bus during accesses to external program and

data memory. In this application it uses strong

internal pullup resistors when issuing 1's.

Port 0 also outputs the code bytes during program

verification in the C515C. External pullup resistors

are required during program verification.

P5.0-P5.7 67-60

I/O Port 5

is an 8-bit quasi-bidirectional I/O port with internal

pullup resistors. Port 5 pins that have 1's written to

them are pulled high by the internal pullup resistors,

and in that state can be used as inputs. As inputs,

port 5 pins being externally pulled low will source

current (I_IL, in the DC characteristics) because of

the internal pullup resistors.

Port 5 can also be switched into a bidirectional

mode, in which CMOS levels are provided. In this

bidirectional mode, each port 5 pin can be

programmed individually as input or output.

Data Sheet

10

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

HWPD

69

I

Hardware Power Down

A low level on this pin for the duration of one

machine cycle while the oscillator is running resets

the C515C.

A low level for a longer period will force the part to

power down mode with the pins floating.

P4.0-P4.7 72-74, 76-80 I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal

pull-up resistors. Port 4 pins that have 1’s written to

them are pulled high by the internal pull-up resistors,

and in that state can be used as inputs. As inputs,

port 4 pins being externally pulled low will source

current (I_IL, in the DC characteristics) because of

the internal pull-up resistors.

P4 also contains the external A/D converter control

pin, the SSC pins, the CAN controller input/output

lines, and the external interrupt 8 input. The output

latch corresponding to a secondary function must

be programmed to a one (1) for that function to

operate. The alternate functions are assigned to

port 4 as follows:

72

73

P4.0 ADST External A/D converter start pin

P4.1 SCLK SSC Master Clock Output /

SSC Slave Clock Input

74

76

77

78

79

P4.2 SRI

P4.3 STO

P4.4 SLS

P4.5 INT8

SSC Receive Input

SSC Transmit Output

Slave Select Input

External interrupt 8 input

P4.6 TXDC Transmitter output of the CAN

controller

80

P4.7 RXDC Receiver input of the CAN controller

Data Sheet

11

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

PE/SWD

75

I

Power saving mode enable / Start watchdog

timer

A low level on this pin allows the software to enter

the power down, idle and slow down mode. In case

the low level is also seen during reset, the watchdog

timer function is off on default.

Use of the software controlled power saving modes

is blocked, when this pin is held on high level. A high

level during reset performs an automatic start of the

watchdog timer immediately after reset. When left

unconnected this pin is pulled high by a weak

internal pull-up resistor.

V_SSCLK

13

14

–

Ground (0 V) for on-chip oscillator

This pin is used for ground connection of the on-chip

oscillator circuit.

V_DDCLK

Supply voltage for on-chip oscillator

This pin is used for power supply of the on-chip

oscillator circuit.

V_DDE1

V_DDE2

32

68

Supply voltage for I/O ports

These pins are used for power supply of the I/O

ports during normal, idle, and power down mode.

V_SSE1

V_SSE2

35

70

Ground (0 V) for I/O ports

These pins are used for ground connections of the

I/O ports during normal, idle, and power down

mode.

V_DD1

33

34

–

Supply voltage for internal logic

This pins is used for the power supply of the internal

logic circuits during normal, idle, and power down

mode.

V_SS1

Ground (0 V) for internal logic

This pin is used for the ground connection of the

internal logic circuits during normal, idle, and power

down mode.

Data Sheet

12

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C515C

Table 2

Symbol

Pin Definitions and Functions (cont’d)

Pin Number I/O¹⁾Function

P-MQFP-80-1

V_DDEXT

50

–

Supply voltage for external access pins

This pin is used for power supply of the I/O ports and

control signals which are used during external

accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR,

and P3.7/RD).

V_SSEXT

51

Ground (0 V) for external access pins

This pin is used for the ground connection of the I/O

ports and control signals which are used during

external accesses (for Port 0, Port 2, ALE, PSEN,

P3.6/WR, and P3.7/RD).

N.C.

2, 71

Not connected

These pins should not be connected.

1)

I = Input; O = Output

Data Sheet

13

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C515C

Multiple

Oscillator Watchdog

OSC & Timing

V

_DD/V_SS

XRAM

2k x 8

RAM

256 x 8

ROM/OTP

64k x 8

Lines

XTAL1

XTAL2

ALE

CPU

PSEN

EA

8 Datapointers

Emulation

Support

Logic

Programmable

CPUR

PE/SWD

HWPD

RESET

Watchdog Timer

Timer 0

Timer 1

Timer 2

Port 0

8 Bit Digital I/O

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 1

8 Bit Digital I/O

Port 2

8 Bit Digital I/O

Capture

Compare Unit

Port 3

8 Bit Digital I/O

USART

Baud Rate Generator

Port 4

8 Bit Digital I/O

SSC (SPI) Interface

Port 5

8 Bit Digital I/O

Full-CAN

Controller

Port 6

8 Bit Analog/

Digital Inputs

Interrupt Unit

V_AREF

V_AGND

Port 7

1 Bit Digital I/O

A/D Converter

10 Bit

S & H

MUX

C515C

MCB03647

Figure 4

Block Diagram of the C515C

Data Sheet

14

2003-02

C515C

CPU

The C515C is efficient both as a controller and as an arithmetic processor. It has

extensive facilities for binary and BCD arithmetic and excels in its bit-handling

capabilities. Efficient use of program memory results from an instruction set consisting

of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal,

58% of the instructions are executed in 1 µs (10 MHz: 600 ns).

PSW

Special Function Register

(D0 )

Reset Value: 00

H

Bit No. MSB

LSB

D7_H

CY

D6_H

AC

D5_H

F0

D4_H

RS1

D3_H

RS0

D2_H

OV

D1_H

F1

D0_H

P

D0_H

PSW

Bit

Function

CY

Carry Flag

Used by arithmetic instruction.

AC

Auxiliary Carry Flag

Used by instructions which execute BCD operations.

General Purpose Flag

F0

RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1

RS0

Function

Bank 0 selected, data address 00 -07

0

1

0

1

0

1

H

Bank 1 selected, data address 08 -0F

H

Bank 2 selected, data address 10 -17

H

Bank 3 selected, data address 18 -1F

H

OV

Overflow Flag

Used by arithmetic instruction.

General Purpose Flag

Parity Flag

F1

P

Set/cleared by hardware after each instruction to indicate an

odd/even number of “one” bits in the accumulator, i.e. even parity.

Data Sheet

15

2003-02

C515C

Memory Organization

The C515C CPU manipulates data and operands in the following five address spaces:

• up to 64 Kbytes of internal/external program memory

• up to 64 Kbytes of external data memory

• 256 bytes of internal data memory

• 256 bytes CAN controller registers / data memory

• 2 Kbytes of internal XRAM data memory

• a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515C.

Alternatively

FFFF

H

Internal

XRAM

(2 KByte)

External

Data

F800

F7FF

H

Memory

Internal

(EA = 1)

Int. CAN

Controller

(256 Byte)

F700

H

Indirect

Address

Direct

Address

F6FF

H

FF

80

FF

80

H

External

(EA = 0)

Special

Function

Register

Internal

RAM

External

7F

H

Internal

RAM

0000

00

H

"Code Space"

"Data Space"

"Internal Data Space"

MCD02717

Figure 5

C515C Memory Map

Data Sheet

16

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C515C

Control of XRAM/CAN Controller Access

The XRAM in the C515C is a memory area that is logically located at the upper end of

the external memory space, but is integrated on the chip. Because the XRAM and the

CAN controller is used in the same way as external data memory the same instruction

types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON,

XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller.

SYSCON

Special Function Register

(B1 ) C515C-8R Reset Value: X010XX01

H

B

C515C-8E Reset Value: X010X001

Bit No. MSB

LSB

7

6

5

4

3

–

2

1

0

–

PMOD

EALE RMAP

B1

CSWO XMAP1 XMAP0

SYSCON

H

The function of the shaded bits is not described in this section.

Bit

XMAP1

Function

XRAM/CAN controller visible access control

Control bit for RD/WR signals during XRAM/CAN Controller

accesses. If addresses are outside the XRAM/CAN controller

address range or if XRAM is disabled, this bit has no effect.

XMAP1 = 0: The signals RD and WR are not activated during

accesses to the XRAM/CAN Controller

XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated

during accesses to XRAM/CAN Controller. In this

mode, address and data information during

XRAM/CAN Controller accesses are visible externally.

XMAP0

Global XRAM/CAN controller access enable/disable control

XMAP0 = 0: The access to XRAM and CAN controller is enabled.

XMAP0 = 1: The access to XRAM and CAN controller is disabled

(default after reset). All MOVX accesses are

performed via the external bus. Further, this bit is

hardware protected.

Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access

enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit

again.

Data Sheet

17

2003-02

C515C

The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR,

MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the

XRAM or CAN controller, the effective address stored in DPTR must be in the range of

F700 to FFFF .

H

The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX

@Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1).

Therefore, a special page register XPAGE which provides the upper address information

(A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX

access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the

state of pin EA. Table 3 lists the various operating conditions.

Data Sheet

18

2003-02

C515C

Table 3

Behaviour of P0/P2 and RD/WR During MOVX Accesses

XMAP1, XMAP0

00

10

X1

EA = 0 MOVX

DPTR

<

XRAM/CAN

address range is used

a) P0/P2→Bus

b) RD/WR active

c) ext.memory

a) P0/P2→Bus

b) RD/WR active

c) ext.memory

is used

a) P0/P2→Bus

b) RD/WR active

c) ext.memory

is used

@DPTR

DPTR

≥

a) P0/P2→Bus

(RD/WR-Data)

b) RD/WR inactive

a) P0/P2→Bus

(RD/WR-Data)

b) RD/WR active

c) XRAM is used

a) P0/P2→Bus

XRAMCAN

address range c) XRAM is used

b) RD/WR active

c) ext.memory

is used

MOVX

@ Ri

XPAGE

<

a) P0→Bus

P2→I/O

a) P0→Bus

P2→I/O

a) P0→Bus

P2→I/O

XRAMCAN

addr. page

range

b) RD/WR active

c) ext.memory

is used

b) RD/WR active

c) ext.memory

is used

b) RD/WR active

c) ext.memory

is used

XPAGE

≥

XRAMCAN

addr. page

range

a) P0→Bus

(RD/WR-Data)

P2→I/O

b) RD/WR inactive

c) XRAM is used

a) P0→Bus

(RD/WR-Data only) P2→I/O

P2→I/O

b) RD/WR active

c) XRAM is used

a) P0→Bus

b) RD/WR active

c) ext.memory

is used

EA = 1 MOVX

DPTR

<

XRAM/CAN

address range is used

a) P0/P2→Bus

b) RD/WR active

c) ext.memory

a) P0/P2→Bus

b) RD/WR active

c) ext.memory

is used

a) P0/P2→Bus

b) RD/WR active

c) ext.memory

is used

@DPTR

DPTR

≥

a) P0/P2→Ι/0

a) P0/P2→Bus

(RD/WR-Data)

b) RD/WR active

c) XRAM is used

a) P0/P2→Bus

XRAMCAN

address range c) XRAM is used

b) RD/WR inactive

b) RD/WR active

c) ext.memory

is used

MOVX

@ Ri

XPAGE

<

a) P0→Bus

P2→I/O

a) P0→Bus

P2→I/O

a) P0→Bus

P2→I/O

XRAMCAN

addr. page

range

b) RD/WR active

c) ext.memory

is used

b) RD/WR active

c) ext.memory is

used

b) RD/WR active

c) ext.memory

is used

XPAGE

≥

XRAMCAN

addr. page

range

a) P2→I/O

P0/P2→I/O

a) P0→Bus

(RD/WR-Data)

P2→I/O

b) RD/WR active

c) XRAM is used

a) P0→Bus

P2→I/O

b) RD/WR inactive

c) XRAM is used

b) RD/WR active

c) ext.memory

is used

modes compatible to 8051/C501 family

19

Data Sheet

2003-02

C515C

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized

internally, the RESET pin must be held low for at least two machine cycles (12 oscillator

periods) while the oscillator is running. A pullup resistor is internally connected to V_DDto

allow a power-up reset with an external capacitor only. An automatic reset can be

obtained when V_DDis applied by connecting the RESET pin to V_SSvia a capacitor.

Figure 6 shows the possible reset circuitries.

a)

b)

&

+

RESET

C515C

c)

+

RESET

C515C

MCS02721

Figure 6

Reset Circuitries

Figure 7 shows the recommended oscillator circiutries for crystal and external clock

operation.

Data Sheet

20

2003-02

C515C

Crystal/Resonator Oscillator Mode

Driving from External Source

C

N.C.

XTAL1

XTAL2

XTAL1

XTAL2

2 - 10 MHz

External Oscillator

Signal

C

Crystal Mode

: C = 20 pF ± 10 pF (incl. stray capacitance)

Resonator Mode : C = depends on selected ceramic resonator

MCT02765

Figure 7

Recommended Oscillator Circuitries

Multiple Datapointers

As a functional enhancement to the standard 8051 architecture, the C515C contains

eight 16-bit datapointers instead of only one datapointer. The instruction set uses just

one of these datapointers at a time. The selection of the actual datapointer is done in the

special function register DPSEL. Figure 8 illustrates the datapointer addressing

mechanism.

- - - - - .2 .1 .0

DPSEL(92

)

H

DPTR7

DPTR0

DPSEL

Selected

Data-

pointer

.2

.1

.0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DPTR 0

DPTR 1

DPTR 2

DPTR 3

DPTR 4

DPTR 5

DPTR 6

DPTR 7

DPH(83

)

DPL(82 )

H

External Data Memory

MCD00779

Figure 8

External Data Memory Addressing using Multiple Datapointers

Data Sheet

21

2003-02

C515C

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new,

innovative way to control the execution of C500 MCUs and to gain extensive information

on the internal operation of the controllers. Emulation of on-chip ROM based programs

is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation

Concept. Therefore, no costly bond-out chips are necessary for emulation. This also

ensure that emulation and production chips are identical.

The Enhanced Hooks Technology, which requires embedded logic in the C500 allows

the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the

design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a

compatible C500 are able to emulate all operating modes of the different versions of the

C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and

ROMless modes of operation. It is also able to operate in single step mode and to read

the SFRs after a break.

ICE-System Interface

to Emulation Hardware

RESET

SYSCON

PCON

RSYSCON

RPCON

EA

ALE

EH-IC

TCON

RTCON

PSEN

C500

MCU

Enhanced Hooks

Interface Circuit

Port 0

Port 2

Optional

I/O Ports

Port 3 Port 1

RPort 2 RPort 0

TEA TALE TPSEN

MCS03280

Target System Interface

Figure 9

Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by

Enhanced Hooks Emulation Concept to control the operation of the device during

emulation and to transfer informations about the program execution and data transfer

between the external emulation hardware (ICE-system) and the C500 MCU.

Data Sheet

22

2003-02

C515C

Special Function Registers

The registers, except the program counter and the four general purpose register banks,

reside in the special function register area. The special function register area consists of

two portions: the standard special function register area and the mapped special function

register area. Two special function registers of the C515C (PCON1 and DIR5) are

located in the mapped special function register area. For accessing the mapped special

function register area, bit RMAP in special function register SYSCON must be set. All

other special function registers are located in the standard special function register area

which is accessed when RMAP is cleared (“0”). As long as bit RMAP is set, mapped

special function register area can be accessed. This bit is not cleared by hardware

automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit

RMAP must be cleared/set by software, respectively each.

SYSCON

Special Function Register

(B1 ) C515C-8R Reset Value: X010XX01

H

B

C515C-8E Reset Value: X010X001

Bit No. MSB

LSB

7

6

5

4

3

–

2

1

0

–

PMOD

EALE RMAP

B1

CSWO XMAP1 XMAP0

SYSCON

H

The function of the shaded bits is not described in this section.

Bit

RMAP

Function

Special function register map bit

RMAP = 0: The access to the non-mapped (standard) special

function register area is enabled (reset value).

RMAP = 1: The access to the mapped special function register

area is enabled.

The 59 special function registers (SFRs) in the standard and mapped SFR area include

pointers and registers that provide an interface between the CPU and the other on-chip

peripherals. The SFRs of the C515C are listed in Table 4 and Table 5. In Table 4 they

are organized in groups which refer to the functional blocks of the C515C. The CAN-

SFRs are also included in Table 4. Table 5 illustrates the contents of the SFRs in

numeric order of their addresses. Table 6 list the CAN-SFRs in numeric order of their

addresses.

Data Sheet

23

2003-02

C515C

Table 4

Block

Special Function Registers - Functional Block

Symbol

Name

Addr

Contents after

Reset

2)

CPU

ACC

B

Accumulator

B-Register

E0_H₂₎

00_H

XXXXX000_B

00_H

07_H

F0_H

83_H

DPH

DPL

DPSEL

PSW

SP

Data Pointer, High Byte

Data Pointer, Low Byte

Data Pointer Select Register

Program Status Word Register

Stack Pointer

82_H

3)

92_{H 2)}

D0_H

81_H

SYSCON¹⁾System Control Register

C515C-8R B1_H

C515C-8E B1_H

X010XX01_B₃₎

3)

X010X001_B

A/D-

ADCON0¹⁾A/D Converter Control Register 0

D8_H

00_H

2)

3)

Converter

ADCON1

ADDATH

ADDATL

A/D Converter Control Register 1

A/D Converter Data Register High Byte

A/D Converter Data Register Low Byte

DC_H

D9_H

DA_H

0XXXX000_B

00_H

3)

00XXXXXX_B

2)

Interrupt

System

IEN0¹⁾

IEN1¹⁾

IEN2

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Enable Register 2

Interrupt Priority Register 0

Interrupt Priority Register 1

Timer Control Register

Timer 2 Control Register

Serial Channel Control Register

Interrupt Request Control Register

A8_H₂₎

B8_H

9A_H

00_H

XX00X00X_B

00_H

0X000000_B

00_H

3)

IP0¹⁾

A9_H

3)

IP1

B9_H₂₎

88_H₂₎

C8_H

TCON¹⁾

T2CON¹⁾

SCON¹⁾

IRCON

2)

98_H₂₎

C0_H

XRAM

Ports

XPAGE

Page Address Register for Extended

on-chip XRAM and CAN Controller

91_H

00_H

SYSCON¹⁾System Control Register

C515C-8R B1_H

C515C-8E B1_H

X010XX01_B₃₎

3)

X010X001_B

2)

P0

P1

P2

P3

P4

P5

DIR5

P6

P7

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

80_H₂₎

90_H₂₎

A0_H₂₎

B0_H₂₎

E8_H₂₎

FF_H

F8_H₂₎₄₎FF_H

Port 5 Direction Register

Port 6, Analog/Digital Input

Port 7

F8_H

DB_H

FF_H

–

XXXXXXX1_B

3)

FA_H

SYSCON¹⁾System Control Register

C515C-8R B1_H

C515C-8E

X010XX01_B₃₎

3)

X010X001_B

Watchdog

WDTREL

Watchdog Timer Reload Register

86_{H 2)}

A8_H₂₎

B8_H

00_H

IEN0¹⁾

IEN1¹⁾

IP0¹⁾

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Priority Register 0

A9_H

Data Sheet

24

2003-02

C515C

Table 4

Block

Special Function Registers - Functional Block (cont’d)

Symbol

Name

Addr

Contents after

Reset

2)

Serial

Channel

ADCON0¹⁾A/D Converter Control Register 0

D8_H

87_H

00_H

PCON¹⁾

SBUF

Power Control Register

00_{H 3)}

XX_H

00_H

D9_H

XXXXXX11_B

Serial Channel Buffer Register

Serial Channel Control Register

99_H2)

SCON

SRELL

SRELH

98_H

Serial Channel Reload Register, low byte AA_H

Serial Channel Reload Register, high byte BA_H

3)

CAN

Controller

CR

SR

IR

Control Register

Status Register

Interrupt Register

F700_H

101_H

6)

F701_H

F702_H

F704_H

F705_H

F706_H

F707_H

F708_H

F709_H

F70A_H

F70B_H

XX_H6)

XX_H₆₎

BTR0

BTR1

GMS0

GMS1

UGML0

UGML1

LGML0

LGML1

UMLM0

Bit Timing Register Low

Bit Timing Register High

Global Mask Short Register Low

Global Mask Short Register High

Upper Global Mask Long Register Low

Upper Global Mask Long Register High

Lower Global Mask Long Register Low

Lower Global Mask Long Register High

Upper Mask of Last Message Register

Low

Upper Mask of Last Message Register

High

Lower Mask of Last Message Register

Low

Lower Mask of Last Message Register

High

UU_H

6)

0UUUUUUU_B

6)

UU_H

6)

UUU11111_B

6)

UU_H6)

UU_H

6)

UUUUU000_B

6)

F70C_HUU_H

6)

UMLM1

LMLM0

LMLM1

F70D_HUU_H

F70E_H

F70F_H

UU_H

6)

UUUUU000_B

Message Object Registers:

Message Control Register Low

Message Control Register High

Upper Arbitration Register Low

Upper Arbitration Register High

Lower Arbitration Register Low

Lower Arbitration Register High

Message Configuration Register

Message Data Byte 0

Message Data Byte 1

Message Data Byte 2

Message Data Byte 3

Message Data Byte 4

5)

6)

MCR0

MCR1

UAR0

UAR1

LAR0

LAR1

MCFG

DB0n

DB1n

DB2n

DB3n

DB4n

DB5n

DB6n

DB7n

F7n0_H5)UU_H6)

F7n1_H5)UU_H6)

F7n2_H5)UU_H6)

F7n3_H5)UU_H6)

F7n4_H5)UU_H

6)

F7n5_H5)UUUUU000_{B 6)}

F7n6_H5)UUUUUU00_B

6)

F7n7_H5)XX_H6)

F7n8_H5)XX_H6)

F7n9_H₅₎XX_H6)

F7nA_H5)XX_H6)

F7nB_H5)XX_H6)

F7nC_H5)XX_H6)

F7nD_H5)XX_H6)

Message Data Byte 5

Message Data Byte 6

Message Data Byte 7

F7nE_H

XX_H

Data Sheet

25

2003-02

C515C

Table 4

Block

Special Function Registers - Functional Block (cont’d)

Symbol

Name

Addr

Contents after

Reset

2)

SSC

Interface

SSCCON SSC Control Register

93_H

94_H

07_{H 3)}

XX_H3)

XX_H

STB

SSC Transmit Buffer

SRB

SCF

SSC Receive Register

SSC Flag Register

95_{H 2)}

AB_H

AC_H

96_H

3)

XXXXXX00_B3)

SCIEN

SSC Interrupt Enable Register

XXXXXX00_B

00_H

SSCMOD SSC Mode Test Register

2)

Timer 0/

Timer 1

TCON

TH0

TH1

TL0

TL1

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88_H

00_H

8C_H

8D_H

8A_H

8B_H

89_H

TMOD

Compare/

CaptureUnit/ CCH1

Timer 2

CCEN

Comp./Capture Enable Reg.

Comp./Capture Reg. 1, High Byte

Comp./Capture Reg. 2, High Byte

Comp./Capture Reg. 3, High Byte

Comp./Capture Reg. 1, Low Byte

Comp./Capture Reg. 2, Low Byte

Comp./Capture Reg. 3, Low Byte

Com./Rel./Capt. Reg. High Byte

Com./Rel./Capt. Reg. Low Byte

Timer 2, High Byte

C1_H

C3_H

C5_H

C7_H

C2_H

C4_H

C6_H

CB_H

CA_H

CD_H

CC_H

00_H

CCH2

CCH3

CCL1

CCL2

CCL3

CRCH

CRCL

TH2

TL2

T2CON

Timer 2, Low Byte

Timer 2 Control Register

2)

C8_H

Power Save PCON¹⁾

Power Control Register

Power Control Register 1

87_H7)

00_H

3)

Modes

PCON1

C515C-8R 88_H7)

C515C-8E 88_H

0XXXXXXX_B₃₎

0XX0XXXX_B

1)

This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

Bit-addressable special function registers

2)

3)

4)

5)

6)

“X” means that the value is undefined and the location is reserved.

This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.

The notation “n” in the message object address definition defines the number of the related message object.

“X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by

a reset operation. “U” values are undefined (as “X”) after a power-on reset operation.

7)

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Data Sheet

26

2003-02

C515C

Table 5

Contents of the SFRs, SFRs in Numeric Order

of their Addresses

Addr. Register

Content Bit 7

after

Reset

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1)

2)

80

81

82

83

86

P0

FF

.7

.6

.5

.4

.3

.2

.1

.0

H

SP

07

00

DPL

DPH

WDTREL

WDT

PSEL

87

88

PCON

TCON

00

SMOD PDS

IDLS

TF0

–

SD

TR0

–

GF1

IE1

–

GF0

IT1

–

PDE

IE0

–

IDLE

IT0

–

H

2)

3)

TF1

TR1

–

H

4)

PCON1

0XXX-

XXXX

EWPD

B

3)

5)

88

PCON1

0XX0-

XXXX

EWPD

–

WS

–

H

B

89

TMOD

TL0

00

GATE

.7

C/T

.6

M1

.5

M0

.4

GATE C/T

M1

.1

M0

.0

H

8A

8B

.3

.2

H

TL1

.7

.6

.5

.4

.3

.2

.1

.0

H

8C

8D

TH0

TH1

P1

.7

.6

.5

.4

.3

.2

.1

.0

H

.7

.6

.5

.4

.3

.2

.1

.0

2)

90

FF

T2

CLK-

OUT

T2EX INT2

INT6

INT5

INT4

INT3

H

91

92

XPAGE

DPSEL

00

.7

–

.6

–

.5

–

.4

–

.3

–

.2

.1

.0

H

XXXX-

X000

B

93

94

95

96

98

99

SSCCON

STB

07

SCEN

.7

TEN

.6

MSTR CPOL CPHA BRS2 BRS1

BRS0

H

XX

.5

.4

.3

0

.2

.1

0

.0

H

SRB

.7

.6

.5

.4

.2

.0

SSCMOD 00

LOOPB TRIO

0

LSBSM

H

2)

SCON

SBUF

IEN2

00

SM0

.7

SM1

.6

SM2

.5

REN

.4

TB8

.3

–

RB8

.2

TI

.1

RI

.0

–

H

XX

H

9A

X00X-

X00X

–

EX8

EX7

ESSC ECAN

H

B

2)

A0

A8

A9

P2

FF

.7

.6

.5

.4

.3

.2

.1

.0

H

IEN0

IP0

00

EAL

WDT

ET2

ES

.4

ET1

.3

EX1

.2

ET0

.1

EX0

.0

OWDS WDTS .5

Data Sheet

27

2003-02

C515C

Table 5

Contents of the SFRs, SFRs in Numeric Order

of their Addresses (cont’d)

Addr. Register

Content Bit 7

after

Reset

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1)

AA

AB

SRELL

SCF

D9

.7

–

.6

–

.5

–

.4

–

.3

–

.2

–

.1

.0

H

XXXX-

XX00

WCOL TC

H

B

AC

SCIEN

XXXX-

XX00

–

WCEN TCEN

H

B

2)

B0

B1

P3

FF

RD

–

WR

T1

T0

INT1

INT0

–

TxD

RxD

H

4)

5)

SYSCON

X010-

XX01

PMOD EALE RMAP –

XMAP1 XMAP0

H

B

B1

SYSCON

X010-

X001

–

PMOD EALE RMAP –

CSWO XMAP1 XMAP0

H

B

2)

B8

B9

IEN1

IP1

00

EXEN2 SWDT EX6

EX5

.4

EX4

.3

EX3

.2

EX2

.1

EADC

.0

H

0X00-

0000

PDIR

–

.5

B

BA

SRELH

XXXX-

XX11

–

.1

.0

H

B

2)

C0

C1

IRCON

CCEN

00

EXF2

TF2

IEX6

IEX5

IEX4

IEX3

IEX2

IADC

H

COCA COCA COCA COCA COCA COCA COCA COCA

H

H3

L3

H2

L2

.4

H1

.3

L1

.2

H0

.1

L0

C2

C3

C4

C5

C6

C7

C8

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

T2CON

CRCL

CRCH

TL2

00

.7

.6

.5

.0

H

.7

.6

.5

.0

.7

.6

.5

.0

.7

.6

.5

.0

.7

.6

.5

.0

.7

.6

.5

.0

2)

T2PS

.7

I3FR

.6

I2FR

.5

T2R1 T2R0 T2CM T2I1

T2I0

.0

CA

CB

.4

.3

.2

.1

H

.7

.6

.5

.0

H

CC

CD

.7

.6

.5

.0

H

TH2

.7

.6

.5

.0

Data Sheet

28

2003-02

C515C

Table 5

Contents of the SFRs, SFRs in Numeric Order

of their Addresses (cont’d)

Addr. Register

Content Bit 7

after

Reset

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1)

2)

D0

D8

D9

PSW

00

CY

BD

.9

AC

CLK

.8

F0

RS1

RS0

ADM

.5

OV

MX2

.4

F1

MX1

.3

P

H

2)

ADCON0

ADDATH

ADDATL

ADEX BSY

MX0

.2

.7

–

.6

–

DA

00XX-

.1

.0

–

H

XXXX

B

DB

P6

–

.7

.6

–

.5

–

.4

–

.3

0

.2

.1

.0

H

DC

ADCON1

0XXX-

X000

ADCL

MX2

MX1

MX0

H

B

2)

E0

E8

ACC

P4

B

00

.7

.6

.5

.4

.3

.2

.1

.0

H

2)

FF

RXDC

TXDC INT8

SLS

.4

STO

.3

SRI

.2

SCLK

.1

ADST

.0

H

2)

F0

F8

00

.7

–

.6

–

.5

–

H

P5

FF

.4

.3

.2

.1

.0

H

6)

DIR5

.4

.3

.2

.1

.0

FA

P7

XXXX-

XXX1

–

INT7

H

B

7)8)

FC

FD

VR0

C5

1

0

1

0

1

0

1

0

1

0

H

7)8)

VR1

95

H

7)8)

9)

FE

VR2

02

H

1)

“X” means that the value is undefined and the location is reserved.

Bit-addressable special function registers

2)

3)

4)

5)

6)

7)

8)

9)

SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

This SFR is available in the C515C-8R and C515C-L.

This SFR is available in the C515C-8E.

This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.

This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

These SFRs are read-only registers (C515C-8E only).

The content of this SFR varies with the actual step of the C515C-8E (e.g. 01 for the first step).

H

Data Sheet

29

2003-02

C515C

Table 6

Contents of the CAN Registers in Numeric Order

of their Addresses

Addr.

n = 1 to F

Regis- Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1)

ter

after

H

2)

Reset

F700

F701

F702

F704

F705

CR

01

TEST CCE

0

EIE

SIE

IE

INIT

H

SR

XX

BOFF EWRN –

RXOK TXOK LEC2 LEC1 LEC0

H

IR

INTID

BRP

H

BTR0

BTR1

UU

H

SJW

0UUU.

UUUU

0

TSEG2

TSEG1

B

F706

F707

GMS0

GMS1

UU

ID28-21

H

UUU1.

1111

ID20-18

1

0

1

0

1

0

B

F708

F709

UGML0 UU

UGML1 UU

LGML0 UU

ID28-21

ID20-13

ID12-5

H

F70A

F70B

H

LGML1 UUUU.

U000

ID4-0

B

F70C

F70D

UMLM0 UU

ID28-21

ID12-5

H

UMLM1 UU

LMLM0 UU

ID20-18

ID17-13

0

F70E

F70F

LMLM1 UUUU.

U000

B

F7n0

F7n1

MCR0

MCR1

UU

MSGVAL

RMTPND

TXIE

RXIE

INTPND

H

TXRQ

MSGLST

CPUUPD

NEWDAT

F7n2

F7n3

F7n4

F7n5

UAR0

UAR1

LAR0

LAR1

UU

ID28-21

H

ID20-18

ID17-13

ID12-5

UUUU.

U000

ID4-0

DLC

.5

0

B

F7n6

MCFG UUUU.

UU00

DIR

XTD

H

B

F7n7

F7n8

F7n9

DB0n

DB1n

DB2n

DB3n

DB4n

XX

.7

.6

.4

.3

.2

.1

.0

H

.5

F7nA

F7nB

H

Data Sheet

30

2003-02

C515C

Table 6

Contents of the CAN Registers in Numeric Order

of their Addresses (cont’d)

Addr.

n = 1 to F

Regis- Content Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1)

ter

after

H

2)

Reset

F7nC

F7nD

DB5n

DB6n

DB7n

XX

.7

.6

.5

.4

.3

.2

.1

.0

H

F7nE

1)

The notation “n” in the address definition defines the number of the related message object.

2)

“X” means that the value is undefined and the location is reserved. “U” means that the value is

unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation.

Data Sheet

31

2003-02

C515C

Digital I/O Ports

The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and

one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read

and write accesses to the I/O ports P0 through P7 are performed via their corresponding

special function registers P0 to P7. The port structure of port 5 of the C515C is especially

designed to operate either as a quasi-bidirectional port structure, compatible to the

standard 8051-Family, or as a genuine bidirectional port structure. This port operating

mode can be selected by software (setting or clearing the bit PMOD in the SFR

SYSCON).

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for

accessing external memory. In this application, port 0 outputs the low byte of the external

memory address, time-multiplexed with the byte being written or read. Port 2 outputs the

high byte of the external memory address when the address is 16 bits wide. Otherwise,

the port 2 pins continue emitting the P2 SFR contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital

inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines.

When used for analog inputs the desired analog channel is selected by a three-bit field

in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to

these input-only ports by writing to the SFR P6. This will have no effect.

If a digital value is to be read, the voltage levels are to be held within the input voltage

specifications (V_IL/V_IH). Since P6 is not bit-addressable, all input lines of P6 are read at

the same time by byte instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input.

However, care must be taken that all bits of P6 that have an undetermined value caused

by their analog function are masked.

Data Sheet

32

2003-02

C515C

Port Structure Selection of Port 5

After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port

structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit

PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as

an input or an output, additionally, after the selection of the bidirectional mode the

direction register DIR5 of port 5 must be written. This direction register is mapped to the

port 5 register. This means, the port register address is equal to its direction register

address. Figure 10 illustrates the port and direction register configuration.

Internal

Write to Port

Bus

Enable

Int. Bus, Bit 7

Write to IP 1

D

R

Q

Port Register

PDIR

Delay:

2.5 Machine Cycles

Enable

Direction Register

Read Port

Instruction sequence for the programming of the direction registers:

ORL IP1, #80H ; Set bit PDIR

MOV DIRx, #OYYH ; Write port x direction register with value YYH

MCS02649

Figure 10

Port Register, Direction Register

Data Sheet

33

2003-02

C515C

Timer / Counter 0 and 1

Timer / Counter 0 and 1 can be used in four operating modes as listed in Table 7:

Table 7

Timer/Counter 0 and 1 Operating Modes

TMOD Timer/Counter Input Clock

M1 M0 internal external (max)

Mode Description

0

8-bit timer/counter with a

0

f

_OSC/6 × 32

f

_OSC/12 × 32

divide-by-32 prescaler

1

2

16-bit timer/counter

0

1

0

f

_OSC/6

f

_OSC/12

8-bit timer/counter with 8-bit 1

autoreload

3

Timer/counter 0 used as

one 8-bit timer/counter and

one 8-bit timer / Timer 1

stops

1

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle.

Therefore the count rate is f_OSC/6.

In the “counter” function the register is incremented in response to a 1-to-0 transition at

its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine

cycles to detect a falling edge the max. count rate is f_OSC/12. External inputs INT0 and

INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width

measurements. Figure 11 illustrates the input clock logic.

÷

6

f_OSC/6

OSC

C/T = 0

C/T = 1

Timer 0/1

Input Clock

P3.4/T0

P3.5/T1

Control

TR0

TR1

&

=1

Gate

(TMOD)

_

<

1

P3.2/INT0

P3.3/INT1

MCS03117

Figure 11

Timer/Counter 0 and 1 Input Clock Logic

Data Sheet

34

2003-02

C515C

Timer / Counter 2 with Compare/Capture/Reload

The timer 2 of the C515C provides additional compare/capture/reload features, which

allow the selection of the following operating modes:

• Compare: up to 4 PWM signals with 16-bit/600 ns resolution

• Capture: up to 4 high speed capture inputs with 600 ns resolution

• Reload: modulation of timer 2 cycle time

The block diagram in Figure 12 shows the general configuration of timer 2 with the

additional compare/capture/reload registers. The I/O pins which can used for timer 2

control are located as multifunctional port functions at port 1.

P1.5/

T2EX

_

<

1

Sync.

÷6

EXF2

Interrupt

Request

T2I0

T2I1

EXEN2

Reload

P1.7/

T2

&

Reload

f _OSC

OSC

÷12

Timer 2

TL2 TH2

T2PS

TF2

Compare

P1.0/

INT3/

CC0

P1.1/

INT4/

CC1

16 Bit

Comparator

16 Bit

Comparator

16 Bit

Comparator

16 Bit

Comparator

Input/

Output

Control

P1.2/

INT5/

CC2

Capture

P1.2/

INT6/

CC3

CCL3/CCH3

CCL2/CCH2

CCL1/CCH1

CRCL/CRCH

MCB02730

Figure 12

Timer 2 Block Diagram

Data Sheet

35

2003-02

C515C

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated

timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer

overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register

T2CON are used to control the timer 2 operation.

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A

prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator

frequency.

Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as

a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer.

T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The

external gate signal is sampled once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in

response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this

function, the external input is sampled every machine cycle. Since it takes two machine

cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is

1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external

input signal, but to ensure that a given level is sampled at least once before it changes,

it must be held for at least one full machine cycle.

Reload of Timer 2: Two reload modes are selectable:

In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also

causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which

is preset by software.

In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the

corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2

in SFR IEN1 has been set.

Data Sheet

36

2003-02

C515C

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows: the 16-bit

value stored in a compare or compare/capture register is compared with the contents of

the timer register; if the count value in the timer register matches the stored value, an

appropriate output signal is generated at a corresponding port pin and an interrupt can

be generated.

Compare Mode 0

In compare mode 0, upon matching the timer and compare register contents, the output

signal changes from low to high. lt goes back to a low level on timer overflow. As long as

compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit

only and writing to the port will have no effect. Figure 13 shows a functional diagram of

a port circuit when used in compare mode 0. The port latch is directly controlled by the

timer overflow and compare match signals. The input line from the internal bus and the

write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.

Port Circuit

Read Latch

V_DD

Compare Register

Circuit

Compare Reg.

S

Q

Port

Internal

Bus

16 Bit

Comparator

D

Port

Latch

Write to

Latch

Compare

Match

CLK

16 Bit

Timer Register

Timer Circuit

R

Timer

Overflow

Read Pin

MCS02661

Figure 13

Port Latch in Compare Mode 0

Data Sheet

37

2003-02

C515C

Compare Mode 1

If compare mode 1 is enabled and the software writes to the appropriate output latch at

the port, the new value will not appear at the output pin until the next compare match

occurs. Thus, it can be choosen whether the output signal has to make a new transition

(1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the

time when the timer value matches the stored compare value.

In compare mode 1 (see Figure 14) the port circuit consists of two separate latches. One

latch (which acts as a “shadow latch”) can be written under software control, but its value

will only be transferred to the port latch (and thus to the port pin) when a compare match

occurs.

Port Circuit

Read Latch

V_DD

Compare Register

Circuit

Compare Reg.

Internal

Bus

D

Q

D

Q

Port

16 Bit

Comparator

Shadow

Latch

Port

Latch

Compare

Match

Write to

Latch

CLK

16 Bit

Timer Register

Timer Circuit

Read Pin

MCS02662

Figure 14

Compare Function in Compare Mode 1

Data Sheet

38

2003-02

C515C

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode,

three asynchronous modes) as illustrated in Table 8.

Table 8

Mode

0

USART Operating Modes

SCON

SM1

Description

SM0

0

1

0

1

Shift register mode, fixed baud rate

Serial data enters and exits through R×D; T×D outputs

the shift clock; 8-bit are transmitted/received (LSB first)

1

2

3

0

1

8-bit UART, variable baud rate

10 bits are transmitted (through T×D) or received (at

R×D)

9-bit UART, fixed baud rate

11 bits are transmitted (through T×D) or received (at

R×D)

9-bit UART, variable baud rate

Like mode 2

For clarification some terms regarding the difference between “baud rate clock” and

“baud rate” should be mentioned. In the asynchronous modes the serial interfaces

require a clock rate which is 16 times the baud rate for internal synchronization.

Therefore, the baud rate generators/timers have to provide a “baud rate clock” (output

signal in Figure 15 to the serial interface which - there divided by 16 - results in the

actual “baud rate”. Further, the abbreviation f_OSCrefers to the oscillator frequency

(crystal or external clock operation).

The variable baud rates for modes 1 and 3 of the serial interface can be derived either

from timer 1 or from a dedicated baud rate generator (see Figure 15).

Data Sheet

39

2003-02

C515C

Timer 1

Overflow

SCON.7

SCON.6

(SM0/

ADCON0.7

(BD)

PCON.7

(SMOD)

Baud

Rate

Generator

Mode 1

Mode 3

SM1)

0

1

÷2

0

f _OSC

Baud

Rate

Clock

1

(SRELH

SRELL)

Mode 2

Mode 0

Only one mode

can be selected

÷6

Note: The switch configuration shows the reset state.

MCS02733

Figure 15

Block Diagram of Baud Rate Generation for the Serial Interface

Table 9 below lists the values/formulas for the baud rate calculation of the serial

interface with its dependencies of the control bits BD and SMOD.

Table 9

Serial Interface - Baud Rate Dependencies

Serial Interface

Operating Modes

Active Control Baud Rate Calculation

Bits

BD

SMOD

Mode 0 (Shift

Register)

–

f_OSC/ 6

Mode 1 (8-bit UART) 0

Mode 3 (9-bit UART)

X

Controlled by timer 1 overflow:

(2^SMOD× timer 1 overflow rate) / 32

1

Controlled by baud rate generator

(2^SMOD× f_OSC) /

(32 × baud rate generator overflow rate)

Mode 2 (9-bit UART) –

0

1

f

_OSC/ 32

_OSC/ 16

Data Sheet

40

2003-02

C515C

SSC Interface

The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This

interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block

diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input

and the output of this shift register are each connected via a control logic to the pin P4.2

/ SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out). This shift register can

be written to (SFR STB) and can be read through the Receive Buffer Register SRB.

P4.1/SCLK

f _OSC

P4.2/SRI

P4.3/STO

P4.4/SLS

Clock Divider

Control

Logic

STB

Shift Register

SRB

Clock Selection

Receive Buffer Register

Interrupt

SCIEN

Int. Enable Reg.

Control Logic

SSCCON

Control Register

SCF

Status Register

Internal Bus

MCB02735

Figure 16

SSC Block Diagram

The SSC has implemented a clock control circuit, which can generate the clock via a

baud rate generator in the master mode, or receive the transfer clock in the slave mode.

The clock signal is fully programmable for clock polarity and phase. The pin used for the

clock signal is P4.1 / SCLK. When operating in slave mode, a slave select input is

provided which enables the SSC interface and also will control the transmitter output.

The pin used for this is P4.4 / SLS.

The SSC control block is responsible for controlling the different modes and operation of

the SSC, checking the status, and generating the respective status and interrupt signals.

Data Sheet

41

2003-02

C515C

CAN Controller

The on-chip CAN controller is the functional heart which provides all resources that are

required to run the standard CAN protocol (11-bit identifiers) as well as the extended

CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the

CPU of as much overhead as possible when controlling many different message objects

(up to 15). This includes bus arbitration, resending of garbled messages, error handling,

interrupt generation, etc. In order to implement the physical layer, external components

have to be connected to the C515C.

The internal bus interface connects the on-chip CAN controller to the internal bus of the

microcontroller. The registers and data locations of the CAN interface are mapped to a

specific 256 bytes wide address range of the external data memory area (F700 to

H

F7FF ) and can be accessed using MOVX instructions. Figure 17 shows a block

H

diagram of the on-chip CAN controller.

Data Sheet

42

2003-02

C515C

TXDC

RXDC

Bit

Timing

Logic

BTL-Configuration

CRC

Gen./Check

Timing

Generator

TX/RX Shift Register

Messages

Clocks

(to all)

Control

Messages

Handlers

Intelligent

Memory

Interrupt

Register

Status +

Control

Bit

Stream

Processor

Error

Management

Logic

Status

Register

to internal Bus

MCB02736

Figure 17

CAN Controller Block Diagram

The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the

parallel access to the whole data or remote frame for the acceptance match test and the

parallel transfer of the frame to and from the Intelligent Memory.

The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream

between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also

controls the EML and the parallel data stream between the TX/RX Shift Register and the

Intelligent Memory such that the processes of reception, arbitration, transmission, and

error signalling are performed according to the CAN protocol. Note that the automatic

retransmission of messages which have been corrupted by noise or other external error

conditions on the bus line is handled by the BSP.

Data Sheet

43

2003-02

C515C

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy

Check code to be transmitted after the data bytes and checks the CRC code of incoming

messages. This is done by dividing the data stream by the code generator polynomial.

The Error Management Logic (EML) is responsible for the fault confinement of the

CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are

incremented and decremented by commands from the Bit Stream Processor. According

to the values of the error counters, the CAN controller is set into the states error active,

error passive and busoff.

The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline

related bit timing according to the CAN protocol. The BTL synchronizes on a recessive

to dominant busline transition at Start of Frame (hard synchronization) and on any further

recessive to dominant busline transition, if the CAN controller itself does not transmit a

dominant bit (resynchronization). The BTL also provides programmable time segments

to compensate for the propagation delay time and for phase shifts and to define the

position of the Sample Point in the bit time. The programming of the BTL depends on the

baudrate and on external physical delay times.

The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message

objects of maximum 8 data bytes length. Each of these objects has a unique identifier

and its own set of control and status bits. After the initial configuration, the Intelligent

Memory can handle the reception and transmission of data without further CPU actions.

Switch-off Capability of the CAN Controller (C515C-8E only)

For power consumption reasons, the on-chip CAN controller in the C515C-8E can be

switched off by setting bit CSWO (bit 2) in SFR SYSCON. When the CAN controller is

switched off its clock signal is turned off and the operation of the CAN controller is

stopped. This switch-off state of the CAN controller is equal to its state in software power

down mode. After clearing bit CSWO again the CAN controller has to be reconfigured.

Data Sheet

44

2003-02

C515C

10-Bit A/D Converter

The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with

8 analog input channels. It operates with a successive approximation technique and

uses self calibration mechanisms for reduction and compensation of offset and linearity

errors. The A/D converter provides the following features:

• 8 multiplexed input channels (port 6), which can also be used as digital inputs

• 10-bit resolution

• Single or continuous conversion mode

• Internal or external start-of-conversion trigger capability

• Interrupt request generation after each conversion

• Using successive approximation conversion technique via a capacitor array

• Built-in hidden calibration of offset and linearity errors

The main functional blocks of the A/D converter are shown in Figure 19.

The A/D converter uses basically two clock signals for operation: the input clock f_IN

(= 1/t_IN) and the conversion clock f_ADC(= 1/t_ADC). These clock signals are derived from

the C515C system clock f_OSCwhich is applied at the XTAL pins. The input clock f_INis

equal to f_OSC. The conversion clock is limited to a maximum frequency of 2 MHz and

therefore must be adapted to f_OSCby programming the conversion clock prescaler. The

table in Figure 18 shows the prescaler ratios and the resulting A/D conversion times

which must be selected for typical system clock rates.

Data Sheet

45

2003-02

C515C

ADCL

MUX

f _OSC

÷4

÷8

Conversion Clock f _ADC

A/D

Converter

Clock Prescaler

Input Clock f _IN

1

CLP

_

<

Conditions:

f _{ADC max}2 MHz

f _IN= f _OSC=

MCS02748

MCU System

Clock Rate

ADCL

Conversion

Clock

(f_OSC

)

f_ADC[MHz]

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz

0

1

.5

1

1.5

2

1.25

Figure 18

A/D Converter Clock Selection

Data Sheet

46

2003-02

C515C

Internal

Bus

IEN1 (B8

)

H

EXEN2 SWDT EX6

IRCON (C0

EX5

IEX5

P6.4

-

EX4

IEX4

P6.3

-

EX3

IEX3

P6.2

MX2

EX2 EADC

)

H

EXF2

TF2

IEX6

P6.5

-

IEX2

P6.1

MX1

IADC

P6.0

MX0

P6 (DB

P6.7

)

H

P6.6

ADCON1 (DC

)

H

ADCL

-

ADCON0 (D8

)

H

BD

CLK

ADEX BSY

ADM

ADDATH ADDATL

(D9

)

(DA )

H

Single/

Continuous

Mode

.2

-

.3

.4

.5

.6

.7

.8

Port 6

MUX

S & H

A/D

LSB

.1

Converter

MSB

Conversion

Clock

Prescaler

Conversion

f _OSC

Clock f_ADC

Input

Clock f_IN

V_AREF

V_AGND

P4.0/ADST

Start of

Write to

ADDATL

Conversion

Internal

Bus

Shaded bit locations are not used in ADC-functions.

MCB02747

Figure 19

A/D Converter Block Diagram

Data Sheet

47

2003-02

C515C

Interrupt System

The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can

be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface,

A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered

externally (P1.5/T2EX, P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,

P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The wake-up from power-down mode

interrupt has a special functionality which allows to exit from the software power-down

mode by a short low pulse at pin P3.2/INT0.

In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt

sources. Each interrupt group can be programmed to one of the four interrupt priority

levels. Figure 20 to Figure 22 give a general overview of the interrupt sources and

illustrate the interrupt request and control flags.

Data Sheet

48

2003-02

C515C

Highest

Priority Level

P3.2/

INT0

IE0

0003

0043

EX0

IEN0.0

H

TCON.1

IT0

TCON.0

Lowest

Priority Level

A/D Converter

IADC

EADC

IRCON.0

IEN1.0

IP1.0

IP0.0

Timer 0

Overflow

TF0

000B

008B

ET0

IEN0.1

H

TCON.5

Status

Error

_

SIE

CR.2

<

1

IE

CR.1

ECAN

IEN2.1

EIE

CR.3

Message

Transmit

see Note

_

TXIE

<

1

INTPND

MCR0.3/2

Message

Receive

MCR0.0/1

RXIE

MCR0.5/4

P1.4/

INT2

IEX2

004B

EX2

IEN1.1

H

IRCON.1

I2FR

T2CON.5

EAL

IEN0.7

IP1.1

IP0.1

Bit addressable

MCS02752

Request Flag is

cleared by hardware

Note: Each of the 15 CAN controller message objects provides the bits/flags in the shaded area.

Figure 20

Interrupt Request Sources (Part 1)

Data Sheet

49

2003-02

C515C

Highest

Priority Level

P3.3/

INT1

IE1

0013

0093

0053

H

TCON.3

IT1

TCON.2

EX1

IEN0.2

Lowest

Priority Level

WCOL

SCF.1

_

<

1

WCEN

SCIEN.1

SSC

Inerface

ESSC

IEN2.2

TC

TCEN

SCIEN.0

SCF.0

P1.0/

INT3/

CC0

IEX3

IRCON.2

I3FR

EX3

T2CON.6

IEN1.2

IP1.2

IP0.2

Timer 1

Overflow

TF1

001B

005B

H

TCON.7

ET1

IEN0.3

P1.1/

INT4/

CC1

IEX4

IRCON.3

EX4

IEN1.3

EAL

IP1.3

IP0.3

IEN0.7

Bit addressable

Request Flag is

cleared by hardware

MCS02753

Figure 21

Interrupt Request Sources (Part 2)

Data Sheet

50

2003-02

C515C

Highest

Priority Level

RI

_

<

1

SCON.0

USART

0023

00A3

0063

H

TI

ES

IEN0.4

Lowest

Priority Level

SCON.1

P7.0/

INT7

EX7

IEN2.4

P1.2/

INT5/

CC2

IEX5

IRCON.4

EX5

IEN1.4

IP1.4

IP0.4

Timer 2

Overflow

TF2

_

<

1

IRCON.6

002B

P1.5/

T2EX

H

EXF2

ET2

IEN0.5

IRCON.7

EXEN2

IEN1.7

P4.5/

INT8

00AB

006B

H

EX8

IEN2.5

P1.3/

INT6/

CC3

IEX6

IRCON.5

EX6

IEN1.5

EAL

IP1.5

IP0.5

IEN0.7

Bit addressable

Request Flag is

MCS02754

cleared by hardware

Figure 22

Interrupt Request Sources (Part 3)

Data Sheet

51

2003-02

C515C

Table 10

Interrupt Source and Vectors

Interrupt Source

Interrupt Vector

Address

Interrupt Request Flags

External Interrupt 0

Timer 0 Overflow

External Interrupt 1

Timer 1 Overflow

Serial Channel

0003

IE0

H

000B

TF0

H

0013

IE1

H

001B

TF1

H

0023

RI / TI

TF2 / EXF2

IADC

IEX2

IEX3

IEX4

IEX5

IEX6

–

H

Timer 2 Overflow / Ext. Reload 002B

H

A/D Converter

0043

H

External Interrupt 2

External Interrupt 3

External Interrupt 4

External Interrupt 5

External Interrupt 6

004B

H

0053

H

005B

H

0063

H

006B

007B

H

Wake-up from power-down

mode

H

CAN controller

008B

00A3

–

H

External Interrupt 7

External Interrupt 8

SSC interface

–

H

00AB

–

H

0093

TC / WCOL

H

Data Sheet

52

2003-02

C515C

Fail Save Mechanisms

The C515C offers two on-chip peripherals which monitor the program flow and ensure

an automatic “fail-safe” reaction for cases where the controller’s hardware fails or the

software hangs up:

• A programmable watchdog timer (WDT) with variable time-out period from

512 microseconds up to approx. 1.1 seconds at 6 MHz.

• An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the

clock for a fast internal reset after power-on.

Programmable Watchdog Timer

The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate

of f_OSC/12 up to f_OSC/192. For programming of the watchdog timer overflow rate, the

upper 7 bit of the watchdog timer can be written. Figure 23 shows the block diagram of

the watchdog timer unit.

0

7

f _OSC/6

÷2

÷16

WDTL

14

8

WDT Reset Request

WDTH

IP0 (A9

-

)

H

-

WDTS

-

External HW Reset

WDTPSEL

External HW Power-Down

PE/SWD

Control Logic

7

6

0

-

WDT

-

IEN0 (A8

)

H

WDTREL (86

)

H

SWDT

IEN1 (B8

MCB02755

Figure 23

Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin

PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails

to refresh the running watchdog timer an internal reset will be initiated on watchdog timer

overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is

transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of

Data Sheet

53

2003-02

C515C

two consecutive instructions which set the bits WDT and SWDT each. The reset cause

(external reset or reset caused by the watchdog) can be examined by software (flag

WDTS). It must be noted, however, that the watchdog timer is halted during the idle

mode and power down mode of the processor.

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

• Monitoring of the on-chip oscillator’s function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the

frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is

supplied by the RC oscillator and the device is brought into reset; if the failure

condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC

oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the

oscillator to stabilize; then the oscillator watchdog reset is released and the part starts

program execution again.

• Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip

oscillator has started. The oscillator watchdog unit also works identically to the

monitoring function.

• Restart from the hardware power down mode

If the hardware power down mode is terminated the oscillator watchdog has to control

the correct start-up of the on-chip oscillator and to restart the program. The oscillator

watchdog function is only part of the complete hardware power down sequence;

however, the watchdog works identically to the monitoring function.

• Control of external wake-up from software power-down mode

When the software power-down mode is left by a low level at the P3.2/INT0 pin, the

oscillator watchdog unit assures that the microcontroller resumes operation

(execution of the power-down wake-up interrupt) with the nominal clock rate. In the

power-down mode the RC oscillator and the on-chip oscillator are stopped. Both

oscillators are started again when power-down mode is released. When the on-chip

oscillator has a higher frequency than the RC oscillator, the microcontroller starts

operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to

stabilize.

Data Sheet

54

2003-02

C515C

EWPD

(PCON1.7)

Power-Down

Mode Activated

Power-Down Mode

Wake-Up Interrupt

Control

Logic

Control

Logic

P3.2/

INT0

Internal

Reset

Start/

Stop

RC

Oscillator

f _RC

f ₁

÷2

÷5

3 MHz

f ₂< f ₁

Frequency

Comparator

_

<

1

Delay

f ₂

Start/

Stop

XTAL1

XTAL2

On-Chip

Oscillator

IP0 (A9

)

H

OWDS

Internal

Clock

MCB02757

Figure 24

Block Diagram of the Oscillator Watchdog

Data Sheet

55

2003-02

C515C

Power Saving Modes

The C515C provides two basic power saving modes, the idle mode and the power down

mode. Additionally, a slow down mode is available. This power saving mode reduces the

internal clock rate in normal operating mode and it can be also used for further power

reduction in idle mode.

• Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock

and are able to work. Idle mode is entered by software and can be left by an interrupt

or reset.

• Power down mode

The operation of the C515C is completely stopped and the oscillator is turned off. This

mode is used to save the contents of the internal RAM with a very low standby current.

Software power down mode: Software power down mode is entered by software

and can be left by reset or by a short low pulse at pin P3.2/INT0 (or P4.7/RXDC,

C515C-8E only).

Hardware power down mode: Hardware power down mode is entered when the pin

HWPD is put to low level.

• Slow-down mode

The controller keeps up the full operating functionality, but its normal clock frequency

is internally divided by 32. This slows down all parts of the controller, the CPU and all

peripherals, to 1/32^thof their normal operating frequency. Slowing down the frequency

significantly reduces power consumption. The slow down mode can be combined with

the idle mode.

Table 11 gives a general overview of the entry and exit conditions of the power saving

modes.

In the power down mode of operation, V_DDcan be reduced to minimize power

consumption. It must be ensured, however, that V_DDis not reduced before the power

down mode is invoked, and that V_DDis restored to its normal operating level, before the

power down mode is terminated.

If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports,

peripherals) remains preserved. If a power saving mode is left by a hardware reset, the

microcontroller state is disturbed and replaced by the reset state of the C515C.

If WS (bit 4) is SFR PCON1 is set (C515C-8E only), pin P4.7/RXDC is alternatively

selected as wake-up pin for the software power down mode. If WS (bit 4) is SFR PCON1

is cleared (C515C-8E only), pin P3.2/INT0 is selected as wake-up pin for the software

power down mode.

For the C515C-8R, P3.2/INT0 is always selected as wake-up pin.

Data Sheet

56

2003-02

C515C

Table 11

Mode

Power Saving Modes Overview

Entering

Leaving by

Remarks

(2-Instruction

Example)

Idle mode

ORL PCON, #01_HOccurrence of an

ORL PCON, #20_Hinterrupt from a

peripheral unit

CPU clock is stopped;

CPU maintains their data;

peripheral units are active (if

enabled) and provided with

clock

Hardware Reset

Software

ORL PCON, #02_HHardware Reset

Oscillator is stopped;

Power-Down ORL PCON, #40_H

Mode

contents of on-chip RAM

and SFR’s are maintained;

Short low pulse at

pin P3.2/INT0

(or P4.7/RXDC,

C515C-8E only)

Hardware

Power-Down

Mode

HWPD = low

HWPD = high

C515C is put into its reset

state and the oscillator is

stopped;

ports become floating

outputs

Slow Down

Mode

ORL PCON, #10_HANL PCON, #0EF_HOscillator frequency is

or

reduced to 1/32 of its

nominal frequency

Hardware Reset

Data Sheet

57

2003-02

C515C

OTP Memory Operation (C515C-8E only)

The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory.

With the C515C-8E fast programming cycles are achieved (1 byte in 100 µs). Also

several levels of OTP memory protection can be selected.

For programming of the device, the C515C-8E must be put into the programming mode.

This typically is done not in-system but in a special programming hardware. In the

programming mode the C515C-8E operates as a slave device similar as an EPROM

standalone memory device and must be controlled with address/data information,

control lines, and an external 11.5 V programming voltage. Figure 25 shows the pins of

the C515C-8E which are required for controlling of the OTP programming mode.

V_DD

V_SS

A0-7

A8-A15

Port 2

Port 0

P0-7

EA/V_PP

PROG

PRD

PALE

PMSEL0

PMSEL1

C515C-8E

RESET

PSEN

PSEL

XTAL1

XTAL2

MCP03651

Figure 25

Programming Mode Configuration of the C515C-8E

Data Sheet

58

2003-02

C515C

C515C-8E Pin Configuration in Programming Mode

V

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

N.C.

A2/A10

A1/A9

A0/A8

XTAL1

XTAL2

V_SS

V_DD

N.C.

V_DD

N.C.

V_SS

N.C.

C515C-8E

N.C.

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20

V

MCP03652

Figure 26

P-MQFP-80-1 Pin Configuration of the C515C-8E in Programming

Mode (top view)

Data Sheet

59

2003-02

C515C

The following Table 12 contains the functional description of all C515C-8E pins which

are required for OTP memory programming.

Table 12

Pin Definitions and Functions in Programming Mode

Symbol Pin Number I/O¹⁾Function

RESET

1

I

Reset

This input must be at static “0” (active) level during the

whole programming mode.

PMSEL0 15

PMSEL1 16

I

Programming mode selection pins

These pins are used to select the different access

modes in programming mode. PMSEL1,0 must satisfy

a setup time to the rising edge of PALE. When the logic

level of PMSEL1,0 is changed, PALE must be at low

level.

PMSEL1 PMSEL0 Access Mode

0

1

0

1

0

1

Reserved

Read version bytes

Program/read lock bits

Program/read OTP memory

byte

PSEL

PRD

17

18

I

Basic programming mode select

This input is used for the basic programming mode

selection and must be switched according Figure 27.

Programming mode read strobe

This input is used for read access control for OTP

memory read, version byte read, and lock bit read

operations.

PALE

19

I

Programming address latch enable

PALE is used to latch the high address lines. The high

address lines must satisfy a setup and hold time to/from

the falling edge of PALE. PALE must be at low level

whenever the logic level of PMSEL1,0 is changed.

XTAL2

XTAL1

36

37

I

XTAL2

Input to the oscillator amplifier.

O

XTAL1

Output of the inverting oscillator amplifier.

Data Sheet

60

2003-02

C515C

Table 12

Pin Definitions and Functions in Programming Mode (cont’d)

Symbol Pin Number I/O¹⁾Function

A0/A8 - 38 - 45

A7/A15

I

Address lines

P2.0-7 are used as multiplexed address input lines

A0-A7 and A8-A15. A8-A15 must be latched with PALE.

PSEN

PROG

47

48

Program store enable

This input must be at static “0” level during the whole

programming mode.

Programming mode write strobe

This input is used in programming mode as a write

strobe for OTP memory program and lock bit write

operations. During basic programming mode selection

a low level must be applied to PROG.

EA/V_PP49

I

External Access / Programming voltage

This pin must be at 11.5 V (V_PP) voltage level during

programming of an OTP memory byte or lock bit. During

an OTP memory read operation this pin must be at high

level (V_IH). This pin is also used for basic programming

mode selection. At basic programming mode selection

a low level must be applied to EA/V_PP.

D0 - 7

52 - 58

I/O Data lines 0-7

During programming mode, data bytes are read or

written from or to the C515C-8E via the bidirectional

D0-7 which are located at port 0.

V_SS

V_DD

N.C.

13, 34, 35,

51, 70

–

Circuit ground potential

must be applied to these pins in programming mode.

14, 32, 33,

50, 69

Power supply terminal

must be applied to these pins in programming mode.

2-12, 20-31, –

46, 60-67,

69, 71-80

Not Connected

These pins should not be connected in programming

mode.

1)

I = Input; O = Output

Data Sheet

61

2003-02

C515C

C515C-8E Basic Programming Mode Selection

The basic programming mode selection scheme is shown in Figure 27.

5 V

V_DD

Clock

(XTAL1/XTAL2)

Stable

"0"

RESET

PSEN

0.1

PMSEL1, 0

PROG

PRD

"0"

"1"

PSEL

"0"

PALE

V_PP

V_IH

0 V

EA/V_PP

Ready for access

mode selection

During this period signals

are not actively driven

MCT03653

Figure 27

C515C-8E Basic Programming Mode Selection

Data Sheet

62

2003-02

C515C

Table 13

Access Modes Selection

EA/ PROG PRD

Access Mode

PMSEL Address

Data

V_PP

(Port 2)

(Port 0)

1

0

Program OTP memory

byte

V_PP

H

A0-7

A8-15

D0-7

Read OTP memory byte V_IH

H

Program OTP lock bits

Read OTP lock bits

V_PP

V_IH

H

L

–

D1, D0

see

Table 14

H

Read OTP version byte V_IH

H

Byte addr. D0-7

of version

byte

C515C-8E Lock Bits Programming / Read

The C515C-8E has two programmable lock bits which, when programmed according

Table 14, provide four levels of protection for the on-chip OTP code memory. The state

of the lock bits can also be read.

Data Sheet

63

2003-02

C515C

Table 14

Lock Bit Protection Types

Lock Bits at

D1, D0

Protection Protection Type

Level

D1

D0

1

Level 0

Level 1

The OTP lock feature is disabled. During normal

operation of the C515C-8E, the state of the EA pin is

not latched on reset.

1

0

During normal operation of the C515C-8E, MOVC

instructions executed from external program memory

are disabled from fetching code bytes from internal

memory. EA is sampled and latched on reset. An OTP

memory read operation is only possible according to

ROM verification mode 2, as it is defined for a

protected ROM version of the C515C-8R. Further

programming of the OTP memory is disabled

(reprogramming security).

0

1

0

Level 2

Level 3

Same as level 1, but also OTP memory read operation

using ROM verification mode 2 is disabled.

Same as level 2; but additionally external code

execution by setting EA = low during normal operation

of the C515C-8E is no more possible.

External code execution, which is initiated by an

internal program (e.g. by an internal jump instruction

above the ROM boundary), is still possible.

Data Sheet

64

2003-02

C515C

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

max.

Unit Notes

min.

-65

Storage temperature

T_ST

150

°C

–

Voltage on V_DDpins with

respect to ground (V_SS)

V_DD

-0.5

6.5

V

Voltage on any pin with respect V_IN

to ground (V_SS)

-0.5

-10

–

V

_DD+ 0.5 V

–

Input current on any pin during –

overload condition

10

mA

Absolute sum of all input

currents during overload

condition

–

|100 mA|

Power dissipation

P_DISS

–

1

W

–

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage of the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for longer periods may

affect device reliability. During absolute maximum rating overload

conditions (V_IN> V_DDor V_IN< V_SS) the voltage on V_DDpins with respect to

ground (V_SS) must not exceed the values defined by the absolute maximum

ratings.

Data Sheet

65

2003-02

C515C

Operating Conditions

Parameter

Symbol

Limit Values

max.

Unit Notes

min.

Supply voltage

V_DD

4.25

5.5

V

Active mode,

f

_OSCmax= 10 MHz

2

5.5

0

Power Down

mode

Ground voltage

Ambient temperature:

SAB-C515C

V_SS

V

Reference voltage

–

°C

T_A

0

70

SAF-C505

-40

4

85

SAH-C505

110

Analog reference voltage V_AREF

V_DD+ 0.1 V

–

Analog ground voltage

Analog input voltage

XTAL clock

V_AGND

V_AIN

V

_SS- 0.1

V_SS+ 0.2 V

V_AGND

V_AREF

10

V

f_OSC

2

MHz –

Data Sheet

66

2003-02

C515C

DC Characteristics (Operating Conditions apply)

Parameter

Sym-

bol

Limit Values

max.

Unit Test

Condition

min.

Input low voltages all except

EA, RESET, HWPD

EA pin

RESET and HWPD pins

Port 5 in CMOS mode

V

–

V_IL

-0.5

0.2 V_DD- 0.1

V_IL1-0.5

V_IL2-0.5

V_ILC-0.5

0.2 V_DD- 0.3

0.2 V_DD+ 0.1

0.3 V_DD

Input high voltages

all except XTAL2, RESET,

and HWPD)

V

–

V_IH

0.2 V_DD+ 0.9 V_DD+ 0.5

XTAL2 pin

RESET and HWPD pins

Port 5 in CMOS mode

V_IH10.7 V_DD

V_IH20.6 V_DD

V_IHC0.7 V_DD

V

_DD+ 0.5

Output low voltages

Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) V_OL

Port 0, ALE, PSEN, CPUR

P4.1, P4.3 in push-pull mode

V

–

0.45

I

_OL= 1.6 mA¹⁾

V_OL1

V_OL3

_OL= 3.2 mA¹⁾

_OL= 3.75 mA¹⁾

Output high voltages

Ports 1, 2, 3, 4, 5, 7

V_OH2.4

0.9 V_DD

V_OH22.4

0.9 V_DD

V_OHC0.9 V_DD

V_OH30.9 V_DD

–

I

_OH= -80 µA

_OH= -10 µA

_OH= -800 µA

_OH= -80 µA²⁾

_OH= -800 µA

_OH= -833 µA

Port 0 in external bus mode,

ALE, PSEN, CPUR

Port 5 in CMOS mode

P4.1, P4.3 in push-pull mode

Logic 0 input current

Ports 1, 2, 3, 4, 5, 7

I_IL

I_TL

I_LI

-10

-65

–

-70

-650

±1

µA

V_IN= 0.45 V

Logical 0-to-1 transition current

Ports 1, 2, 3, 4, 5, 7

µA V_IN= 2 V

Input leakage current

µA 0.45 < V_IN< V_DD

Port 0, EA, P6, HWPD, AIN0-7

Input low current

To RESET for reset

XTAL2

µA

I_LI2

I_LI3

I_LI4

–

-100

-15

-20

V_IN= 0.45 V

PE/SWD

Pin capacitance

C_IO

–

10

pF

f_c= 1 MHz,

T_A= 25 °C

3)4)

Overload current

I_OV

–

±5

mA

V

Programming voltage

V_PP10.9

12.1

11.5 V ± 5%

Data Sheet

67

2003-02

C515C

1)

Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLof ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these

pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise

pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger,

or use an address latch with a Schmitt-trigger strobe input.

2)

3)

Capacitive loading on ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall below the

0.9 V_DDspecification when the address lines are stabilizing.

Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified

operating range (i.e. V_OV> V_DD+ 0.5 V or V_OV< V_SS- 0.5 V). The absolute sum of input overload currents on

all port pins may not exceed 50 mA. The supply voltage (V_DDand V_SS) must remain within the specified limits.

4)

Not 100% tested, guaranteed by design characterization.

Data Sheet

68

2003-02

C515C

Power Supply Current

Parameter

Sym- Limit Values Unit Test Condition

typ.¹⁾max.²⁾

bol

3)

Active mode

C515C-8R/ 6 MHz I_DD

C515C-LM 10 MHz

11.97 13.74 mA

18.81 21.10

C515C-8E 6 MHz I_DD

11.3

17.66 20.10

6.9 7.87

10.46 11.87

12.94 mA

10 MHz

4)

5)

6)

Idle mode

C515C-8R/ 6 MHz I_DD

C515C-LM 10 MHz

mA

µA

C515C-8E 6 MHz I_DD

3.95

4.71

4.70

5.50

10 MHz

Active mode

C515C-8R/ 6 MHz I_DD

withslow-down C515C-LM 10 MHz

4.06

4.62

5.03

5.75

enabled

C515C-8E 6 MHz I_DD

4.01

4.65

4.77

5.53

10 MHz

Idle mode with C515C-8R/ 6 MHz I_DD

3.54

3.86

4.46

4.90

slow-down

enabled

C515C-LM 10 MHz

C515C-8E 6 MHz I_DD

3.62

4.14

4.21

4.77

10 MHz

Power-down

mode

C515C-8R/

C515C-LM

I_PD

26

42.9

V_DD= 2 … 5.5 V

7)

C515C-8E

I_PD

11.14 30

30

µA

At EA/V_PPin

programming

mode

I_DDP

–

mA –

1)

The typical I_DDvalues are periodically measured at T_A= +25 °C and V_DD= 5 V but not 100% tested.

The maximum I_DDvalues are measured under worst case conditions (T_A= 0 °C or -40 °C and V_DD= 5.5 V)

2)

3)

I_DD(active mode) is measured with:

XTAL2 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_DD- 0.5 V; XTAL1 = N.C.;

EA = PE/SWD = Port 0 = Port 6 = V_DD; HWPD = V_DD; RESET = V_SS; all other pins are disconnected.

4)

5)

I_DD(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL2 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_DD- 0.5 V; XTAL1 = N.C.;

RESET = V_DD; EA = V_SS; Port0 = V_DD; all other pins are disconnected;

I_DD(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL2 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_DD- 0.5 V; XTAL1 = N.C.;

RESET = V_DD; all other pins are disconnected; the microcontroller is put into slow-down mode by software.

Data Sheet

69

2003-02

C515C

6)

7)

I_DD(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

disabled;

XTAL2 driven with t_CLCH, t_CHCL= 5 ns, V_IL= V_SS+ 0.5 V, V_IH= V_DD- 0.5 V; XTAL1 = N.C.;

RESET = V_DD; EA = V_SS; Port0 = V_DD; all other pins are disconnected; the microcontroller is put into idle mode

with slow-down enabled by software.

I_PD(power-down mode) is measured under following conditions:

EA = RESET = Port 0 = Port 6 = V_DD; XTAL1 = N.C.; XTAL2 = V_SS; PE/SWD = V_SS; HWPD = V_DD

V_AGND= V_SS; V_AREF= V_DD; all other pins are disconnected.

;

I_PD(hardware power-down mode) is independent of any particular pin connection.

Data Sheet

70

2003-02

C515C

Power Supply Current Calculation Formulas

Parameter

Symbol

Formula

Active mode

C515C-8R/

C515C-LM

I_{DD typ}

I_{DD max}

1.71 × f_OSC+ 1.71

1.84 × f_OSC+ 2.7

C515C-8E

I_{DD typ}

I_{DD max}

1.59 × f_OSC+ 1.76

1.79 × f_OSC+ 2.2

Idle mode

C515C-8R/

C515C-LM

I_{DD typ}

I_{DD max}

0.89 × f_OSC+ 1.56

1.00 × f_OSC+ 1.87

C515C-8E

I_{DD typ}

I_{DD max}

0.19 × f_OSC+ 2.81

0.20 × f_OSC+ 3.5

Active mode with

slow-down enabled

C515C-8R/

C515C-LM

I_{DD typ}

I_{DD max}

0.14 × f_OSC+ 3.22

0.18 × f_OSC+ 3.95

C515C-8E

I_{DD typ}

I_{DD max}

0.16 × f_OSC+ 3.05

0.19 × f_OSC+ 3.63

Idle mode with slow-down C515C-8R/

I_{DD typ}

I_{DD max}

0.08 × f_OSC+ 3.06

0.11 × f_OSC+ 3.8

enabled

C515C-LM

C515C-8E

I_{DD typ}

I_{DD max}

0.13 × f_OSC+ 2.84

0.14 × f_OSC+ 3.37

Note: f_OSCis the oscillator frequency in MHz. I_DDvalues are given in mA.

Data Sheet

71

2003-02

C515C

[mA]

25

C515C-8E

C515C-LM

20

15

10

5

I_{DD max}

I_{DD typ}

e

d

o

M

e

l

d

I

e

d

o

M

n

w

o

d

-

w

o

l

S

n

w

o

-d

w

lo

S

+

le

Id

f_OSC

[MHz]

2

4

6

8

10

Figure 28

I

_DDDiagrams of C515C-8R/C515C-LM

Data Sheet

72

2003-02

C515C

C515C-8E

[mA]

25

20

15

10

5

I_{DD max}

I_{DD typ}

f_OSC

[MHz]

2

4

6

8

10

Figure 29

I_DDDiagrams of C515C-8E

Data Sheet

73

2003-02

C515C

A/D Converter Characteristics (Operating Conditions apply)

Parameter

Symbol

Limit Values

max.

Unit Test Condition

min.

1)

Analog input voltage

Sample time

V_AIN

t_S

V_AGND

V_AREF

V

–

16 × t_IN

8 × t_IN

ns

Prescaler ÷ 8

Prescaler ÷ 4²⁾

Conversion cycle time

Total unadjusted error

t_ADCC

–

96 × t_IN

48 × t_IN

ns

Prescaler ÷ 8

Prescaler ÷ 4³⁾

4)

T_UE

–

±2

LSB

5)6)

Internal resistance of

R_AREF

t_ADC/ 250 kΩ t_ADCin [ns]

reference voltage source

- 0.25

2)6)

Internal resistance of

analog source

R_ASRC

–

t_S/ 500

- 0.25

kΩ

t_Sin [ns]

6)

ADC input capacitance C_AIN

–

50

pF

1)

V_AINmay exceed V_AGNDor V_AREFup to the absolute maximum ratings. However, the conversion result in

these cases will be X000 or X3FF , respectively.

H

2)

3)

4)

During the sample time the input capacitance C_AINcan be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t_S.

After the end of the sample time t_S, changes of the analog input voltage have no effect on the conversion result.

This parameter includes the sample time t_S, the time for determining the digital result and the time for the

calibration. Values for the conversion clock t_ADCdepend on programming and can be taken from the table on

the previous page.

T

is tested at V_AREF= 5.0 V, V_AGND= 0 V, V_DD= 4.9 V. It is guaranteed by design characterization for all

UE

other voltages within the defined voltage range.

If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input

overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB

is permissible.

5)

6)

During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The maximum internal resistance results from the programmed conversion timing.

Not 100% tested, but guaranteed by design characterization.

Data Sheet

74

2003-02

C515C

Clock Calculation Table

Clock Prescaler Ratio

ADCL

t_ADC

t_S

t_ADCC

÷8

÷4

1

0

8 × t_IN

4 × t_IN

16 × t_IN

8 × t_IN

96 × t_IN

48 × t_IN

Further timing conditions:

t_{ADC min}= 500 ns

t_IN= 1 / f_OSC= t_CLP

Data Sheet

75

2003-02

C515C

AC Characteristics (Operating Conditions apply)

(C_Lfor port 0, ALE and PSEN outputs = 100 pF; C_Lfor all other outputs = 80 pF)

Program Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

Unit

10-MHz Clock

Duty Cycle

0.4 to 0.6

1/CLP = 2 MHz

to 10 MHz

min.

60

15

–

max. min.

max.

ALE pulse width

t_LHLL

–

CLP - 40

–

TCL_Hmin- 25 –

ns

Address setup to ALE t_AVLL

Address hold after ALE t_LLAX

–

ALE to valid instruction t_LLIV

113

–

2 CLP - 87

in

ALE to PSEN

t_LLPL

20

–

TCL_Lmin- 20 –

ns

PSEN pulse width

t_PLPH

115

CLP +

–

TCL_Hmin- 30

PSEN to valid

instruction in

t_PLIV

t_PXIX

–

75

–

CLP +

TCL_Hmin- 65

ns

Input instruction hold

after PSEN

0

–

1)

Input instruction float

after PSEN

t_PXIZ

t_PXAV

t_AVIV

–

30

–

TCL_Lmin- 10 ns

1)

Address valid after

PSEN

35

–

TCL_Lmin- 5

–

ns

Address to valid

instruction in

180

–

2 CLP +

TCL_Hmin- 60

Address float to PSEN t_AZPL

0

–

1)

Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not

cause any damage to port 0 drivers.

Data Sheet

76

2003-02

C515C

Unit

External Data Memory Characteristics

Parameter

Symbol

Limit Values

Variable Clock

10-MHz Clock

Duty Cycle

0.4 to 0.6

1/CLP= 2 MHz to 10 MHz

min.

max. min. max.

RD pulse width

WR pulse width

t_RLRH

230

–

3 CLP - 70

CLP - 15

–

ns

t_WLWH230

Address hold after

ALE

t_LLAX2

48

RD to valid data in

t_RLDV

–

150

–

2 CLP +

ns

TCL_Hmin- 90

Data hold after RD

Data float after RD

t_RHDX

t_RHDZ

0

–

0

–

ns

80

CLP - 20

4 CLP - 133

4 CLP +

ALE to valid data in t_LLDV

267

285

Address to valid data t_AVDV

in

TCL_Hmin- 155

ALE to WR or RD

t_LLWL

90

190

CLP +

ns

TCL_Lmin- 50 TCL_Lmin+ 50

Address valid to WR t_AVWL

103

15

–

2 CLP - 97

–

WR or RD high to

ALE high

t_WHLH

t_QVWX

65

TCL_Hmin- 25 TCL_Hmin+ 25 ns

Data valid to WR

transition

5

–

TCL_Lmin- 35

–

ns

Data setup before

WR

t_QVWH218

3 CLP +

TCL_Lmin- 122

Data hold after WR

t_WHQX13

t_RLAZ

–

0

TCL_Hmin- 27 –

ns

Address float after

RD

–

0

Data Sheet

77

2003-02

C515C

SSC Interface Characteristics

Parameter

Symbol

Limit Values

max.

Unit

min.

Clock Cycle Time:

Master Mode

Slave Mode

t_SCLK

0.4

1.0

–

µs

Clock high time

Clock low time

Data output delay

Data output hold

Data input setup

Data input hold

TC bit set delay

t_SCH

t_SCL

t_D

360

–

ns

–

100

t_HO

t_S

0

–

100

–

t_HI

–

t_DTC

8 CLP

External Clock Drive at XTAL2

Parameter

Symbol CPU Clock = 10 MHz

Duty cycle 0.4 to 0.6

Variable CPU Clock

1/CLP = 2 to 10 MHz

Unit

min.

100

40

–

max.

100

–

min.

max.

Oscillator period CLP

100

500

ns

High time

Low time

Rise time

Fall time

TCL_H

TCL_L

t_R

40

CLP - TCL_L

–

40

CLP - TCL_Hns

12

–

12

ns

–

t_F

–

12

–

12

Oscillator duty

cycle

DC

0.4

0.6

40 / CLP

1 - 40 / CLP

Clock cycle

TCL

40

60

CLP × DC_minCLP × DC_maxns

Note: The 10 MHz values in the tables are given as an example for a typical duty cycle

variation of the oscillator clock from 0.4 to 0.6.

Data Sheet

78

2003-02

C515C

t _LHLL

ALE

t_AVLL

t _PLPH

t _LLPL

t _LLIV

t _PLIV

PSEN

t _AZPL

t _LLAX

t _PXAV

t _PXIZ

t _PXIX

Port 0

A0 - A7

Instr.IN

A0 - A7

t _AVIV

Port 2

A8 - A15

MCT00096

Figure 30

Program Memory Read Cycle

Data Sheet

79

2003-02

C515C

t_WHLH

ALE

PSEN

RD

t _LLDV

t _LLWL

t _RLRH

t _RLDV

t _AVLL

t_RHDZ

t _LLAX2

t _RLAZ

t_RHDX

A0 - A7 from

Ri or DPL

A0 - A7

from PCL

Instr.

IN

Port 0

Data IN

t_AVWL

t _AVDV

Port 2

P2.0 - P2.7 or A8 - A15 from DPH

A8 - A15 from PCH

MCT00097

Figure 31

Data Memory Read Cycle

Data Sheet

80

2003-02

C515C

t_WHLH

ALE

PSEN

WR

t _LLWL

t _WLWH

t_QVWX

t _AVLL

t_WHQX

t _LLAX2

t_QVWH

A0 - A7 from

Ri or DPL

A0 - A7

from PCL

Instr.IN

Port 0

Port 2

Data OUT

t_AVWL

P2.0 - P2.7 or A8 - A15 from DPH

A8 - A15 from PCH

MCT00098

Figure 32

Data Memory Write Cycle

t _R

t _F

TCLH

V_IH2

XTAL2

V_IL

TCLL

CLP

MCT02704

Figure 33

External Clock Drive at XTAL2

Data Sheet

81

2003-02

C515C

t_SCLK

t_SCL

t_SCH

SCLK

STO

SRI

t_D

t_HD

MSB

LSB

t_S

t_HI

MSB

LSB

t_DTC

TC

MCT02417

Figure 34

Notes:

SSC Timing

1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is

valid for the other cases accordingly.

2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the

falling edge of SLS (if transmitter is enabled).

3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data

has been written into the shift register, i.e. at least one half SCLK clock cycle before

the first clock transition.

Data Sheet

82

2003-02

C515C

OTP Memory Programming Mode Characteristics

_DD= 5 V ± 10%; V_PP= 11.5 V ± 5%; T_A= 25 °C ± 10 °C

V

Parameter

Symbol

Limit Values

Unit

min.

max.

ALE pulse width

t_PAW

t_PMS

t_PAS

35

10

–

ns

PMSEL setup to ALE rising edge

Address setup to ALE, PROG, or PRD

falling edge

Address hold after ALE, PROG, or PRD

falling edge

t_PAH

10

–

ns

Address, data setup to PROG or PRD

Address, data hold after PROG or PRD

PMSEL setup to PROG or PRD

PMSEL hold after PROG or PRD

PROG pulse width

t_PCS

t_PCH

t_PMS

t_PMH

t_PWW

t_PRW

t_PAD

t_PRD

t_PDH

t_PDF

t_PWH1

100

0

–

ns

µs

ns

µs

–

10

100

–

PRD pulse width

–

Address to valid data out

PRD to valid data out

75

20

–

Data hold after PRD

0

Data float after PRD

–

20

–

PROG high between two consecutive

PROG low pulses

1

PRD high between two consecutive PRD t_PWH2

low pulses

100

2

–

ns

XTAL clock period

t_CLKP

10

MHz

Data Sheet

83

2003-02

C515C

t

PAW

PMS

PALE

t

H, H

PMSEL1,0

t

PAH

PAS

A8-15

A0-7

D0-7

Port 2

Port 0

PROG

t

PWH

t

PCH

PCS

PWW

Notes: PRD must be high during a programming write cycle.

MCT03690

Figure 35

Programming Code Byte - Write Cycle Timing

Data Sheet

84

2003-02

C515C

t

PAW

PMS

PALE

t

H, H

PMSEL1,0

t

PAH

PAS

A8-15

A0-7

Port 2

Port 0

PRD

t

PDH

PAD

D0-7

t

PRD

PDF

PCH

t

PWH

t

PCS

PRW

Notes: PROG must be high during a programming read cycle.

MCT03689

Figure 36

Verify Code Byte - Read Cycle Timing

Data Sheet

85

2003-02

C515C

H, L

PMSEL1,0

Port 0

D0, D1

t

PCH

PCS

t

PMS

PMH

PROG

t

PDH

t

PRD

t

PMS

PWW

PDF

t

PMH

t

PRW

PRD

Note: PALE should be low during a lock bit read / write cycle.

MCT03393

Figure 37

Lock Bit Access Timing

Data Sheet

86

2003-02

C515C

L, H

PMSEL1,0

Port 2

e. g. FD

H

t

PCH

D0-7

Port 0

PRD

t

PCS

PDH

t

PRD

PDF

t

PMS

PMH

t

PRW

Note: PROG must be high during a programming read cycle.

MCT03394

Figure 38

Version Byte - Read Timing

Data Sheet

87

2003-02

C515C

ROM/OTP Verification Characteristics for C515C-8R / C515C-8E

ROM Verification Mode 1 (C515C-8R)

Parameter

Symbol

Limit Values

Unit

min.

max.

Address to valid data

t_AVQV

–

5 CLP

ns

P1.0 - P1.7

P2.0 - P2.7

Address

New Address

t _AVQV

Port 0

Data:

Data Out

New Data Out

P0.0 - P0.7 = D0 - D7

Inputs: PSEN = V_SS

ALE, EA = V_IH

Addresses: P1.0 - P1.7 = A0 - A7

P2.0 - P2.7 = A8 - A15

RESET = V_IL2

MCT02764

Figure 39

ROM Verification Mode 1

Data Sheet

88

2003-02

C515C

Unit

ROM/OTP Verification Mode 2

Parameter

Symbol

Limit Values

min.

typ.

CLP

6 CLP

–

max.

ALE pulse width

t_AWD

t_ACY

t_DVA

t_DSA

t_AS

–

ns

ALE period

–

ns

Data valid after ALE

Data stable after ALE

P3.5 setup to ALE low

Oscillator frequency

–

2 CLP

ns

4 CLP

–

6

ns

–

4

t_CL

–

ns

1 / CLP

MHz

t _ACY

t _AWD

ALE

t _DSA

t _DVA

Port 0

P3.5

Data Valid

t _AS

MCT02613

Figure 40

ROM/OTP Verification Mode 2

Data Sheet

89

2003-02

C515C

V_DD- 0.5 V

0.2 V_DD+ 0.9

Test Points

0.2 V_DD- 0.1

0.45 V

MCT00039

AC Inputs during testing are driven at V_DD- 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’.

Timing measurements are made at V_IHminfor a logic ‘1’ and V_ILmaxfor a logic ‘0’.

Figure 41

AC Testing: Input, Output Waveforms

-0.1 V

V_OH

V

_Load+0.1 V

Timing Reference

Points

V_Load

-0.1 V

V_Load

V_OL+0.1 V

MCT00038

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs.

I_OL/I_OH≥ ± 20 mA

Figure 42

AC Testing: Float Waveforms

Crystal/Resonator Oscillator Mode

Driving from External Source

C

N.C.

XTAL1

XTAL2

XTAL1

XTAL2

2 - 10 MHz

External Oscillator

Signal

C

Crystal Mode

: C = 20 pF ± 10 pF (incl. stray capacitance)

Resonator Mode : C = depends on selected ceramic resonator

MCT02765

Figure 43

Recommended Oscillator Circuits for Crystal Oscillator

Data Sheet

90

2003-02

C515C

Package Outlines

P-MQFP-80-1

(Plastic Metric Quad Flat Package)

H

0.65

±0.08

0.88

80x

0.3

C

0.1

12.35

17.2

14 ¹⁾

M

0.12

A-B D C

0.2 A-B D 80x

0.2 A-B D 4x

H

D

B

A

80

1

Index Marking

0.6x45˚

1) Does not include plastic or metal protrusions of 0.25 max per side

GPM05249

You can find all of our packages, sorts of packing and others in our

Infineon Internet Page “Products”: http://www.infineon.com/products.

Dimensions in mm

2003-02

SMD = Surface Mounted Device

Data Sheet

91

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	C515C-8EM
厂家：	Infineon
描述：	8-Bit Single-Chip Microcontroller 8位单芯片微控制器微控制器
文件：	总96页 (文件大小：1236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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