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CHL8328-00CRTY [INFINEON]

Digital Multi-Phase Buck Controller 6-phase 8-phase dual output PWM Controller; 数字多相降压控制器的6 - 8相相双输出PWM控制器
CHL8328-00CRTY
型号： CHL8328-00CRTY
厂家： Infineon    Infineon
描述：

Digital Multi-Phase Buck Controller 6-phase 8-phase dual output PWM Controller
数字多相降压控制器的6 - 8相相双输出PWM控制器

多相元件 控制器
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IR3536/38  
CHL8326/28  
Digital Multi-Phase Buck Controller  
FEATURES  
DESCRIPTION  
6-phase & 8-phase dual output PWM Controller  
The IR3536/CHL8326 and IR3538/CHL8328 are dual-loop  
digital multi-phase buck controllers. The IR3536/CHL8326  
drive up to 6 phases and the IR3538/CHL8328 drives up to  
8 phases. The IR3536/CHL8326 and IR3538/CHL8328 are  
fully Intel® VR12 and AMD® SVI/PVI compliant on both  
loops and provide a Vtt tracking function for DDR memory.  
Phases are flexibly assigned between Loops 1 & 2  
Intel® VR12, AMD® 3.4MHz SVI/PVI & Memory  
modes  
Overclocking & Gaming Mode with Vmax setting  
Switching frequency from 200kHz to 1.2MHz per  
phase  
The IR3536/CHL8326 and IR3538/CHL8328 include the  
IR Efficiency Shaping Technology to deliver exceptional  
efficiency at minimum cost across the entire load range.  
IR Variable Gate Drive optimizes the MOSFET gate drive  
voltage based on real-time load current. IR Dynamic Phase  
Control adds/drops phases based upon load current.  
The IR3536/CHL8326 and IR3538/CHL8328 can be  
configured to enter 1-phase operation and active diode  
emulation mode automatically or by command.  
IR Efficiency Shaping Features including Variable  
Gate Drive and Dynamic Phase Control  
Programmable 1-phase or 2-phase for Light Loads  
and Active Diode Emulation for Very Light Loads  
IR Adaptive Transient Algorithm (ATA) on both loops  
minimizes output bulk capacitors and system cost  
Auto-Phase Detection with auto-compensation  
IR’s unique Adaptive Transient Algorithm (ATA), based on  
proprietary non-linear digital PWM algorithms, minimizes  
output bulk capacitors.  
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP  
I2C/SMBus/PMBus system interface for telemetry  
of Temperature, Voltage, Current & Power for  
both loops  
The I2C/PMBus interface can communicate with up to 16  
IR3536/CHL8326 and IR3538/CHL8328 based VR loops.  
Device configuration and fault parameters are easily  
defined using the IR Intuitive Power Designer (DPDC) GUI  
and stored in on-chip NVM.  
Non-Volatile Memory (NVM) for custom  
configuration  
Compatible with IR ATL and 3.3V Tri-state Drivers  
+3.3V supply voltage; -20ºC to 85ºC ambient  
operation  
The IR3536/CHL8326 and IR3538/CHL8328 provides  
extensive OVP, UVP, OCP and OTP fault protection and  
includes thermistor based temperature sensing with  
VR_HOT signal.  
Pb-Free, RoHS, 7x7 48-pin & 8x8 56-pin QFN, MSL2  
package  
APPLICATIONS  
NVM storage saves pins and enables a small package size.  
The IR3536/CHL8326 and IR3538/CHL8328 also include  
numerous features like register diagnostics for fast design  
cycles and platform differentiation, truly simplifying  
VRD design and enabling fastest time-to-market with its  
“set-and-forget” methodology.  
Intel ® VR12 & AMD® SVI & PVI based systems  
DDR Memory with Vtt tracking  
Overclocked & Gaming platforms  
PIN DIAGRAM  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
1
2
42 ISEN7  
ISEN8  
RCSP  
RCSM  
VCC  
1
36 RCSP_L2  
35 RCSM_L2  
34 VCC  
RCSP  
RCSM  
VCC  
41  
40  
39  
38  
37  
RCSP_L2  
RCSM_L2  
VCC  
2
3
3
4
CFP1  
/
CFP1  
/
5
4
33 VSEN_L2  
32 VRTN_L2  
31 PWM6  
30 PWM5  
29 PWM4  
28 PWM3  
27 PWM2  
26 PWM1  
VSEN_L2  
VRTN_L2  
VFIXEN_PSI2  
VFIXEN_PSI2  
6
VSEN  
5
VSEN  
CHL8328  
56 Pin 8x8 QFN  
Top View  
CHL8326  
48 Pin 7x7 QFN  
Top View  
7
36 PWM8  
VRTN  
RRES  
TSEN  
V18A  
6
VRTN  
RRES  
TSEN  
V18A  
8
35  
34  
33  
32  
31  
30  
29  
PWM7  
PWM6  
PWM5  
PWM4  
PWM3  
PWM2  
PWM1  
7
9
8
10  
11  
12  
13  
14  
9
VR_READY1  
/
PWRGD2  
VR_READY1  
/
10  
11  
PWRGD2  
VR_READY_L21  
/
PWROK2  
GPO_B  
VR_READY_L21  
/
PWROK2  
49 GND  
57 GND  
VINSEN 12  
25  
VAR_GATE  
VINSEN  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
1Intel/MPoL mode  
2AMD mode  
Figure 2: IR3538/CHL8328 Package Top View  
Figure 1: IR3536/CHL8326 Package Top View  
1
June 21, 2013 | FINAL | V1.09  
IR3536/38  
CHL8326/28  
Digital Multi-Phase Buck Controller  
ORDERING INFORMATION  
Packing  
Package  
Part Number  
IR3536MTRPBF  
Programming  
Default  
Qty  
IR353M           
TR=3000  
TY=2600  
QFN  
IR3536MTYPBF  
P/PBF – Lead Free  
TR=3000  
TY=2600  
IR3538MTRPBF  
IR3538MTYPBF  
IR3536MxxyyTRP1  
QFN  
QFN  
Default  
TR – Tape & Reel / TY - Tray  
yy – Configuration File ID  
xx – Customer ID  
TR=3000  
TR=3000  
Customer Configuration  
Customer Configuration  
QFN  
IR3538MxxyyTRP1  
Notes:  
Package Type (QFN)  
1. Customer Specific Configuration File, where  
xx = Customer ID and yy = Configuration File  
(Codes assigned by IR Marketing).  
Part –  
6: IR3536  
8: IR3538  
Package  
QFN  
Packing Qty  
T=3000  
TY=2600  
Part Number  
CHL8326-00CRT  
CHL8326-00CRTY  
CHL8326-xxCRT1  
CHL832―       
QFN  
T=3000  
T – Tape & Reel / TY - Tray  
R – Package Type (QFN)  
T=3000  
TY=2600  
CHL8328-00CRT  
CHL8328-00CRTY  
CHL8328-xxCRT1  
QFN  
QFN  
T=3000  
C – Operating Temperature,  
Commercial  
Notes:  
1. “xx” indicates a customer specific configuration file.  
xx – Configuration File  
Part –  
6: CHL8326  
8: CHL8328  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
1
2
42  
41  
40  
39  
38  
37  
ISEN7  
ISEN8  
RCSP  
RCSM  
VCC  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
RCSP_L2  
RCSM_L2  
VCC  
RCSP_L2  
RCSM_L2  
VCC  
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
RCSP  
RCSM  
VCC  
3
4
CFP1  
/
3
5
VSEN_L2  
VRTN_L2  
VFIXEN_PSI2  
CFP1  
/
VSEN_L2  
VRTN_L2  
PWM6  
4
VFIXEN_PSI2  
6
VSEN  
CHL8328  
56 Pin 8x8 QFN  
Top View  
5
7
36 PWM8  
VSEN  
VRTN  
RRES  
TSEN  
V18A  
CHL8326  
8
35  
PWM7  
6
VRTN  
RRES  
TSEN  
V18A  
48 Pin 7x7 QFN  
Top View  
9
34  
33  
32  
31  
30  
29  
PWM6  
PWM5  
PWM4  
PWM3  
PWM2  
PWM1  
PWM5  
7
10  
11  
12  
13  
14  
PWM4  
8
VR_READY1  
/
PWRGD2  
PWM3  
9
VR_READY_L21  
/ PWROK2  
VR_READY1  
/
PWM2  
10  
11  
12  
PWRGD2  
GPO_B  
VINSEN  
VR_READY_L21  
57 GND  
PWM1  
/ PWROK2  
49 GND  
VAR_GATE  
VINSEN  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
1Intel/MPoL mode  
2AMD mode  
Figure 4: IR3538/CHL8328 Package Top View, Enlarged  
Figure 3: IR3536/CHL8326 Package Top View, Enlarged  
2
June 21, 2013 | FINAL | V1.09  
IR3536/38  
CHL8326/28  
Digital Multi-Phase Buck Controller  
FUNCTIONAL BLOCK DIAGRAM  
V18A  
VCC  
LDO  
RCSP_L2  
VID_2  
RSCM_L2  
AFE_2  
1.8V  
VSEN_L2  
VRTN_L2  
ITOT_2  
Vout1_Error  
Voltage  
ADC  
PWM1  
PWM2  
PWM3  
PWM4  
RCSP  
RSCM  
AFE_1  
VSEN  
Vout2_Error  
VID_1  
VRTN  
ISEN1  
Mode Control  
PWM Generator  
IP1  
IRTN1  
.
.
.
.
.
.
PWM5  
PWM6  
.
.
.
Phase_  
Period_1  
Control  
and  
Monitoring  
ISENx  
IRTNx  
IPx  
Phase_  
Period_2  
ITOT_1  
Σ
PWM7  
IR3536/  
CHL8326 CHL8328  
IR3538/  
Only for  
IR3538/CHL8328  
x
y
z
3
4
6
4
5
8
PWM8  
Iout  
Vin  
ISENy  
VAR_GATE  
IPy  
IRTNy  
.
.
.
.
.
.
.
.
.
ITOT_2  
Vout  
ISENz  
IRTNz  
Temp  
IPz  
Current ADC  
Σ
Fault Bus  
System Clock  
IP1  
.
.
.
IP6  
System Clock  
ADC Clocks  
MUX Clocks  
IP7  
.
.
.
Only for  
IR3538/CHL8328  
1Intel/MPoL mode  
2AMD mode  
IP8  
Phase_Period_1  
TSEN2  
Phase_Period_2  
VID_1  
TSEN  
VID_2  
Monitor ADC  
Iout  
Vin  
VINSEN  
Reference,  
Oscillator,  
State Control,  
Interfaces,  
Registers and  
NVM  
V3_3  
EN  
Temp  
SV_CLK1/SVC_VID[3]2  
Fault Bus  
SV_DIO1/SVD_VID[2]2  
SV_ALERT#1/VID[4]2  
VR_HOT#1/  
VRHOT_ICRIT#2  
SMB_DIO  
SMB_CLK  
VR_READY1/PWRGD2  
VR_READY_L21/  
PWROK2  
SMB_ALERT  
PSI1/VID[5]2  
GPO_A  
Only for  
C
IR3538/CHL8328  
SV_ADDR1/VID[1]2  
PM_ADDR1/  
GPO_B  
PM_ADDR_VID[0]2  
CFP1/VFIXEN_PSI2  
RRES  
Figure 5: IR3536/CHL8326 and CHL8328 Functional Block Diagram  
3
June 21, 2013 | FINAL | V1.09  

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