CY14B116K-ZS25XIT [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14B116K-ZS25XIT |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 |
| 文件： | 总44页 (文件大小：1142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY14B116K/CY14B116M
16-Mbit (2048 K × 8/1024 K × 16) nvSRAM
with Real Time Clock
CY14B116K/CY14B116M, 16-Mbit (2048
K × 8/1024 K × 16) nvSRAM with Real Time Clock
Features
Functional Description
■ 16-Mbit nonvolatile static random access memory (nvSRAM)
❐ 25-ns and 45-ns access times
❐ Internally organized as 2048 K × 8 (CY14B116K),
1024 K × 16 (CY14B116M)
❐ Hands-off automatic STORE on power-down with only a
small capacitor
❐ STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
❐ RECALL to SRAM initiated by software or power-up
The Cypress CY14B116K/CY14B116M combines a 16-Mbit
nvSRAM with a full-featured RTC in a monolithic integrated
circuit. The nvSRAM is a fast SRAM with a nonvolatile element
in each memory cell. The memory is organized as 2048 K bytes
of 8 bits each or 1024 K words of 16 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data residing in the nonvolatile elements do not
change when data is written to the SRAM. Data transfers from
the SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the nonvol-
atile memory. Both the STORE and RECALL operations are also
available under software control.
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ Sleep mode operation
The RTC function provides an accurate clock with leap year
tracking and a programmable, high-accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer.
■ Full-featured real time clock (RTC)
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Backup power fail indication
❐ Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
❐ Capacitor or battery backup for RTC
❐ Backup current of 0.45 µA (typical)
For a complete list of related documentation, click here.
■ Low power consumption
❐ Active current of 75 mA at 45 ns
❐ Standby mode current of 750 µA
❐ Sleep mode current of 10 µA
■ Operating voltage: VCC = 2.7 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ Packages
❐ 44-pin thin small-outline package (TSOP II)
❐ 54-pin thin small-outline package (TSOP II)
❐ 165-ball fine-pitch ball grid array (FBGA) package
■ Restriction of hazardous substances (RoHS) compliant
Cypress Semiconductor Corporation
Document #: 001-67786 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 24, 2019
CY14B116K/CY14B116M
Logic Block Diagram[1, 2, 3]
V
V
V
V
CAP
CC
RTCbat
RTCcap
POWER CONTROL
SLEEP MODE
CONTROL
ZZ
QUANTUMTRAP
4096 X 4096
STORE / RECALL
CONTROL
HSB
STORE
RECALL
STATIC RAM
ARRAY
4096 X 4096
SOFTWARE
DETECT
A
-A
11
0
A
-A
2
14
OE
CE
[4]
WE
BLE
BHE
ZZ
COLUMN IO
DQ -DQ
15
0
X
X
INT
out
in
RTC
COLUMN DECODER
MUX
A -A
0
20
A
-A
20
12
Notes
1. Address A –A for ×8 configuration and address A –A for ×16 configuration.
0
20
0
19
2. Data DQ –DQ for ×8 configuration and data DQ –DQ for ×16 configuration.
0
7
0
15
3. BLE, BHE are applicable for x16 configuration.
4. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.
1
2
1
2
Document #: 001-67786 Rev. *K
Page 2 of 43
CY14B116K/CY14B116M
Contents
Pinouts ..............................................................................4
Device Operation ..............................................................6
SRAM Read .......................................................................6
SRAM Write .......................................................................6
AutoStore Operation (Power-Down) ...............................6
Hardware STORE (HSB) Operation .................................7
Hardware RECALL (Power-Up) .......................................7
Software STORE ...............................................................7
Software RECALL .............................................................7
Sleep Mode ........................................................................8
Preventing AutoStore .....................................................10
Data Protection ...............................................................10
Real Time Clock Operation ............................................10
nvTime Operation ......................................................10
Clock Operations .......................................................10
Reading the Clock .....................................................10
Setting the Clock .......................................................10
Backup Power ...........................................................11
Stopping and Starting the Oscillator ..........................11
Calibrating the Clock .................................................11
Alarm .........................................................................12
Watchdog Timer ........................................................12
Programmable Square Wave Generator ...................12
Power Monitor ...........................................................13
Backup Power Monitor ..............................................13
Interrupts ...................................................................13
Flags Register ...........................................................14
RTC External Components .......................................15
PCB Design Considerations for RTC ............................15
Layout Requirements ................................................15
Maximum Ratings ...........................................................22
Operating Range .............................................................22
DC Electrical Characteristics ........................................22
Data Retention and Endurance .....................................23
Capacitance ....................................................................23
Thermal Resistance ........................................................24
AC Test Conditions ........................................................24
RTC Characteristics .......................................................25
AC Switching Characteristics .......................................26
AutoStore/Power-Up RECALL Characteristics ............30
Sleep Mode Characteristics ...........................................31
Software Controlled STORE and RECALL
Characteristics ................................................................32
Hardware STORE Characteristics .................................33
Truth Table For SRAM Operations ................................34
For ×8 Configuration .................................................34
For ×16 Configuration ...............................................34
For ×16 Configuration ...............................................35
Ordering Information ......................................................36
Ordering Code Definitions .........................................36
Package Diagrams ..........................................................37
Acronyms ........................................................................40
Document Conventions .................................................40
Units of Measure .......................................................40
Document History Page .................................................41
Sales, Solutions, and Legal Information ......................43
Worldwide Sales and Design Support .......................43
Products ....................................................................43
PSoC® Solutions ......................................................43
Cypress Developer Community .................................43
Technical Support .....................................................43
Document #: 001-67786 Rev. *K
Page 3 of 43
CY14B116K/CY14B116M
Pinouts
Figure 1. Pin Diagram: 44-Pin TSOP II (×8)
Figure 2. Pin Diagram: 54-Pin TSOP II (×16)
INT
A
19
1
2
54
53
HSB
INT
1
2
3
4
44
43
42
41
HSB
NC
A
[5]
18
A
20
A
0
A
3
4
5
52
51
50
49
48
17
A
0
A
19
A
A
1
16
A
1
A
18
A
2
A
15
A
2
A
5
6
40
39
A
3
6
17
OE
A
3
A
4
BHE
BLE
DQ
7
A
16
CE
DQ
0
8
9
47
46
45
44
43
42
41
A
4
38
37
7
8
A
15
15
CE
DQ
0
OE
DQ
DQ
10
11
12
13
14
15
16
DQ
1
14
44 - TSOP II
(x8)
9
10
36
35
7
54 - TSOP II
(x16)
DQ
DQ
V
DQ
13
12
2
3
DQ
1
DQ
V
DQ
V
6
V
11
12
13
14
34
33
32
31
CC
CC
SS
SS
Top View
(not to scale)
V
SS
V
V
CC
Top View
(not to scale)
V
SS
CC
DQ
DQ
40
39
38
37
36
35
34
33
32
31
DQ
11
4
DQ
2
5
DQ
DQ
DQ
DQ
3
5
10
DQ
4
DQ
DQ
17
18
19
20
21
9
6
7
WE
A
5
15
16
17
18
19
20
21
22
30
29
V
CAP
DQ
8
A
14
WE
A
5
V
CAP
A
6
28
27
26
25
24
23
A
13
12
A
14
A
7
A
A
A
6
A
13
A
12
A
8
A
9
22
23
24
25
26
27
A
7
A
8
11
A
11
A
10
A
10
A
9
Xout
Xin
V
V
RTCcap
30
29
28
NC
Xout
Xin
NC
VRTCcap
VRTCbat
RTCbat
Figure 3. Pin Diagram: 165-Ball FBGA (×16)
1
2
3
4
5
6
CE1
CE2
A7
7
8
9
10
A3
11
NC
A
B
C
D
E
F
NC
NC
ZZ
A6
DQ0
NC
A8
DQ1
NC
NC
NC
NC
NC
VCC
NC
DQ4
NC
NC
DQ7
NC
A15
WE
A4
BLE
BHE
A0
NC
OE
A2
A5
NC
NC
Xin
NC
NC
NC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
A13
NC
A1
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
A12
DQ15
NC
DQ14
NC
NC
NC
NC
HSB
NC
NC
NC
NC
NC
INT
NC
NC
DQ2
VCAP
DQ3
NC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VSS
A11
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VSS
A9
VSS
Xout
NC
NC
VCC
NC
NC
NC
NC
NC
NC
A14
DQ13
NC
NC
VSS
DQ12
NC
G
H
J
VSS
NC
NC
VSS
NC
NC
NC
VSS
DQ8
NC
NC
K
L
NC
VSS
NC
DQ5
NC
VSS
NC
DQ9
NC
M
N
P
R
VSS
DQ10
NC
DQ6
NC
A10
NC
A19
A17
VRTCbat
VRTCcap
A18
A16
DQ11
NC
NC
NC
NC[5]
NC
Note
5. Address expansion for the 32-Mbit. NC pin not connected to die.
Document #: 001-67786 Rev. *K
Page 4 of 43
CY14B116K/CY14B116M
Table 1. Pin Definitions
Pin Name
A0–A20
I/O Type
Description
Address inputs. Used to select one of the 2,097,152 bytes of the nvSRAM for the ×8 configuration.
Address inputs. Used to select one of the 1,048,576 words of the nvSRAM for the ×16 configuration.
Input
A0–A19
Bidirectional data I/O lines for the ×8 configuration. Used as input or output lines depending on
operation.
DQ0–DQ7
DQ0–DQ15
WE
Input/Output
Input
Bidirectional data I/O lines for the ×16 configuration. Used as input or output lines depending on
operation.
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Chip Enable input in TSOP II package, Active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
CE
CE1, CE2
OE
Input
Chip Enable input in FBGA package. The device is selected and a memory access begins on the
falling edge of CE1 (while CE2 is HIGH) or the rising edge of CE2 (while CE1 is LOW).
Output Enable, Active LOW. The Active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Input
Input
Input
Byte Enable, Active LOW. When selected LOW, enables DQ7–DQ0.
Byte Enable, Active LOW. When selected LOW, enables DQ15–DQ8.
BLE
BHE
Sleep Mode Enable. When the ZZ pin is pulled LOW, the device enters a low-power Sleep mode and
consumes the lowest power. Since this input is logically AND’ed with CE, ZZ must be HIGH for normal
operation.
ZZ[6]
Input
[7]
Xout
Output
Input
Crystal connection. Drives crystal on start-up.
Crystal connection. For 32.768-KHz crystal.
[7]
Xin
[7]
VRTCcap
Power Supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.
Power Supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used.
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the watchdog
[7]
VRTCbat
timer, and the power monitor. In addition, programmable to be either Active HIGH (push or pull) or LOW
(open drain). In the Calibration mode, a 512-Hz square wave is driven out. In the Square Wave mode,
INT[7]
Output
you can select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as a continuous output.
VCC
VSS
Power Supply Power supply inputs to the device.
Power Supply Ground for the device. Must be connected to ground of the system.
Hardware STORE Busy (HSB).When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
HSB
Input/Output
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
VCAP
NC
Power Supply
NC
No Connect. Die pads are not connected to the package pin.
Notes
6. Sleep mode feature is offered only in the 165-ball FBGA package.
7. Left unconnected if RTC feature is not used.
Document #: 001-67786 Rev. *K
Page 5 of 43
CY14B116K/CY14B116M
Device Operation
AutoStore Operation (Power-Down)
The CY14B116K/CY14B116M stores data to the nonvolatile
QuantumTrap cells using one of the three storage operations.
These three operations are: Hardware STORE, activated by the
HSB; Software STORE, activated by an address sequence;
AutoStore, on device power-down. The AutoStore operation is a
unique feature of nvSRAM and is enabled by default on the
CY14B116K/CY14B116M.
The CY14B116K/CY14B116M nvSRAM is made up of two
functional components paired in the same physical cell. These
are an SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation) automatically at power-down, or from the
nonvolatile cell to the SRAM (the RECALL operation) on
power-up. Both the STORE and RECALL operations are also
available under software control. Using this unique architecture,
all cells are stored and recalled in parallel. During the STORE
and RECALL operations, SRAM read and write operations are
inhibited. The CY14B116K/CY14B116M supports infinite reads
and writes to the SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. See the Truth Table For SRAM Operations on page
34 for a complete description of read and write modes.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a STORE operation during
power-down. If the voltage on the VCC pin drops below VSWITCH
,
the part automatically disconnects the VCAP pin from VCC and a
STORE operation is initiated with power provided by the VCAP
capacitor.
Note If the capacitor is not connected to the VCAP pin, AutoStore
must be disabled using the soft sequence specified in the section
Preventing AutoStore on page 10. If AutoStore is enabled without
a capacitor on the VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the STORE. This
corrupts the data stored in the nvSRAM.
SRAM Read
The CY14B116K/CY14B116M performs a read cycle whenever
CE and OE are LOW, and WE, ZZ, and HSB are HIGH. The
address specified on pins A0–A20 or A0–A19 determines which
of the 2,097,152 data bytes or 1,048,576 words of 16 bits each
are accessed. Byte enables (BHE, BLE) determine which bytes
are enabled to the output, in the case of 16-bit words. When the
read is initiated by an address transition, the outputs are valid
after a delay of tAA (read cycle 1). If the read is initiated by CE or
OE, the outputs are valid at tACE or at tDOE, whichever is later
(read cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for transi-
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
Figure 4. AutoStore Mode
V
CC
0.1 uF
V
CC
WE
V
SRAM Write
CAP
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins
DQ0–DQ15 is written into the memory if it is valid tSD before the
end of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on the
common I/O lines. If OE is left LOW, the internal circuitry turns
off the output buffers tHZWE after WE goes LOW.
V
CAP
V
SS
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for the automatic STORE operation. Refer to DC
Electrical Characteristics on page 22 for the size of the VCAP. The
voltage on the VCAP pin is driven to VVCAP by a regulator on the
chip. A pull-up resistor should be placed on WE to hold it inactive
during power-up. This pull-up resistor is only effective if the WE
signal is in tristate during power-up. When the nvSRAM comes
out of power-up-RECALL, the host microcontroller must be
active or the WE held inactive until the host microcontroller
comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place (which sets a write latch) since
the most recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether a write
operation has taken place.
Document #: 001-67786 Rev. *K
Page 6 of 43
CY14B116K/CY14B116M
To initiate the Software STORE cycle, the following read
sequence must be performed:
Hardware STORE (HSB) Operation
The CY14B116K/CY14B116M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a Hardware STORE cycle. When the HSB pin is driven
LOW, the device conditionally initiates a STORE operation after
1. Read address 0x4E38 Valid Read
2. Read address 0xB1C7 Valid Read
3. Read address 0x83E0 Valid Read
4. Read address 0x7C1F Valid Read
5. Read address 0x703F Valid Read
6. Read address 0x8FC0 Initiate STORE cycle
t
DELAY. A STORE cycle begins only if a write to the SRAM has
taken place since the last STORE or RECALL cycle. The HSB
pin also acts as an open drain driver (an internal 100-k weak
pull-up resistor) that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
The software sequence may be clocked with CE-controlled
reads or OE-controlled reads, with WE kept HIGH for all the six
read sequences. After the sixth address in the sequence is
entered, the STORE cycle commences and the chip is disabled.
HSB is driven LOW. After the tSTORE cycle time is fulfilled, the
SRAM is activated again for the read and write operations.
Note After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100-k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. If the write latch is not set, HSB is not driven LOW
by the device. However, any of the SRAM read and write cycles
are inhibited until HSB is returned HIGH by the host microcon-
troller or another external source.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations:
During any STORE operation, regardless of how it is initiated,
the device continues to drive the HSB pin LOW, releasing it only
when the STORE is complete. Upon completion of the STORE
operation, the nvSRAM memory access is inhibited for tLZHSB
time after the HSB pin returns HIGH. Leave the HSB uncon-
nected if it is not used.
1. Read address 0x4E38 Valid Read
2. Read address 0xB1C7 Valid Read
3. Read address 0x83E0 Valid Read
4. Read address 0x7C1F Valid Read
5. Read address 0x703F Valid Read
6. Read address 0x4C63 Initiate RECALL cycle
Hardware RECALL (Power-Up)
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared; then, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation does not alter the data in the nonvolatile elements.
During power-up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power-up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. A Software STORE cycle is
initiated by executing sequential CE or OE controlled read cycles
from six specific address locations in exact order. During the
STORE cycle, the previous nonvolatile data is first erased,
followed by a store into the nonvolatile elements. After a STORE
cycle is initiated, further reads and writes are disabled until the
cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence. Otherwise, the sequence is
aborted and no STORE or RECALL takes place.
Document #: 001-67786 Rev. *K
Page 7 of 43
CY14B116K/CY14B116M
Sleep Mode
In Sleep mode, the device consumes the lowest power supply current (IZZ). The device enters a low-power sleep mode after asserting
the ZZ pin LOW. After the Sleep mode is registered, the nvSRAM does a STORE operation to secure the data to the nonvolatile
memory and then enters the low-power mode. The device starts consuming IZZ current after tSLEEP time from the instance when the
Sleep mode is initiated. When the ZZ pin is LOW, all input pins are ignored except the ZZ pin. The nvSRAM is not accessible for
normal operations while it is in Sleep mode.
When the device enters Sleep mode, the RTC circuit power supply switches to backup power (VRTCcap or VRTCbat) and the crystal
oscillator circuit runs into the low-power mode, which is similar to the power-off condition. Whenever the device comes out of Sleep
mode, the RTC circuit power switches back to VCC power and will be driven by the main supply (VCC) source.
When the ZZ pin is de-asserted (HIGH), there is a delay tWAKE before the user can access the device. If Sleep mode is not used, the
ZZ pin should be tied to VCC
.
Note When nvSRAM enters Sleep mode, it initiates a nonvolatile STORE cycle, which results in losing one endurance cycle for every
Sleep mode entry unless data was not written to the nvSRAM since the last nonvolatile STORE/RECALL operation.
Note If the ZZ pin is LOW during power-up, the device will not be in Sleep mode. However, the I/Os are in tristate until the ZZ pin is
de-asserted (HIGH).
Figure 5. Sleep Mode (ZZ) Flow Diagram
Power Applied
After tHRECALL
After tWAKE
Device Ready
CE = LOW
ZZ = HIGH
CE = HIGH
ZZ = HIGH
CE = LOW; ZZ = HIGH
CE = HIGH; ZZ = HIGH
Active Mode
(ICC
Standby Mode
(ISB
)
)
CE = Don’t Care
ZZ = HIGH
ZZ = LOW
ZZ = LOW
Sleep Routine
After tSLEEP
Sleep Mode
(IZZ
)
Document #: 001-67786 Rev. *K
Page 8 of 43
CY14B116K/CY14B116M
Table 2. Mode Selection
[10]
CE[8]
H
WE
X
OE
X
BHE, BLE[9]
A15 - A0
Mode
I/O
Power
Standby
Active
X
X
X
X
Not selected Output High Z
L
L
L
H
L
L
X
L
L
L
X
Read SRAM
Write SRAM
Output Data
Input Data
Active
Active[11]
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Disable
L
L
L
H
H
H
L
L
L
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[11]
Enable
[11]
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data Active ICC2
Output Data
Output Data
Output Data
Output Data
Output High Z
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[11]
Notes
8. TSOP II package is offered in single CE and the BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted
1
2
1
2
on any of the chip enable pins (CE for the single chip enable device; CE and CE for the dual chip enable device).
1
2
9. BLE, BHE are applicable for the x16 configuration only.
10. While there are 21 address lines on the CY14B116K (20 address lines on the CY14B116M), only 13 address lines (A –A ) are used to control software modes. The
14
2
remaining address lines are don’t care.
11. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile operation.
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Page 9 of 43
CY14B116K/CY14B116M
Preventing AutoStore
Real Time Clock Operation
nvTime Operation
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
The CY14B116K/CY14B116M offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
RTC registers use the last 16 address locations of the SRAM.
Internal double buffering of the clock and timer information
registers prevents accessing transitional internal clock data
during a read or write operation. Double buffering also circum-
vents disrupting normal timing counts or the clock accuracy of
the internal clock when accessing clock data. Clock and alarm
registers store data in BCD format.
1. Read address 0x4E38 Valid Read
2. Read address 0xB1C7 Valid Read
3. Read address 0x83E0 Valid Read
4. Read address 0x7C1F Valid Read
5. Read address 0x703F Valid Read
6. Read address 0x8B45 AutoStore Disable
RTC functionality is described with respect to CY14B116K in the
following sections. The same description applies to
CY14B116M, except for the RTC register addresses. The RTC
register addresses for CY14B116K range from 0x1FFFF0 to
0x1FFFFF, and for CY14B116M,they range from 0xFFFF0 to
0xFFFFF. Refer to Table 6 on page 17 and Table 7 on page 18
for a detailed Register Map description.
AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
Clock Operations
1. Read address 0x4E38 Valid Read
2. Read address 0xB1C7 Valid Read
3. Read address 0x83E0 Valid Read
4. Read address 0x7C1F Valid Read
5. Read address 0x703F Valid Read
6. Read address 0x4B46 AutoStore Enable
The clock registers maintain time up to 9,999 years in
one-second increments. The time can be set to any calendar
time and the clock automatically keeps track of days of the week
and month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in the BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
If the AutoStore function is disabled or re-enabled, a manual
software STORE operation must be performed to save the
AutoStore state through subsequent power-down cycles. The
part comes from the factory with AutoStore enabled and 0x00
written in all cells.
Reading the Clock
The double-buffered RTC register structure reduces the chance
of reading incorrect data from the clock. Internal updates to the
CY14B116K time-keeping registers are stopped when the read
bit ‘R’ (in the Flags register at 0x1FFFF0) is set to ‘1’ before
reading clock data to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
Data Protection
The CY14B116K/CY14B116M protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC is less than VSWITCH. If the CY14B116K/
CY14B116M is in a Write mode at power-up (both CE and WE
are LOW), after a RECALL or STORE, the write is inhibited until
the SRAM is enabled after tLZHSB (HSB to output active). This
protects against inadvertent writes during power-up or brown out
conditions.
When a read sequence of the RTC device is initiated, the update
of the user time-keeping registers stops and does not restart until
a ‘0’ is written to the read bit ‘R’ (in the Flags register at
0x1FFFF0). After the end of a read sequence, all the RTC
registers are simultaneously updated within 20 ms.
Setting the Clock
A write access to the RTC device stops updates to the time
keeping registers and enables the time to be set when the write
bit ‘W’ (in the Flags register at 0x1FFFF0) is set to ‘1’. The correct
day, date, and time is then written into the registers and must be
in the 24-hour BCD format. The time written is referred to as the
“Base Time”. This value is stored in nonvolatile registers and
used in the calculation of the current time. When the write bit ‘W’
is cleared by writing ‘0’ to it, the values of timekeeping registers
are transferred to the actual clock counters after which the clock
resumes normal operation.
If the time written to the time-keeping registers is not in the
correct BCD format, each invalid nibble of the RTC registers
continues counting to 0xF before rolling over to 0x0, after which
RTC resumes normal operation.
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CY14B116K/CY14B116M
Note After the ‘W’ bit is set to ‘0’, values written into the
time-keeping, alarm, calibration, and interrupt registers are
transferred to the RTC time keeping counters in tRTCp time.
These counter values must be saved to nonvolatile memory
either by initiating a Software/Hardware STORE or AutoStore
operation. While working in the AutoStore Disabled mode,
perform a STORE operation after tRTCp after writing into the RTC
registers for the modifications to be correctly recorded.
the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to ‘1’. The system must check
for this condition and then write ‘0’ to clear the flag.
Note that in addition to setting the OSCF flag bit, the time
registers are reset to the ‘Base Time’, which is the value last
written to the timekeeping registers. The control or calibration
registers and the OSCEN bit are not affected by the ‘oscillator
failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit,
which may have been set when the system was first powered on.
Backup Power
The RTC in the CY14B116K is intended for a permanently
powered operation. The VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When the primary power, VCC, fails and drops below
VSWITCH the device switches to the backup power supply.
To reset OSCF, set the write bit ‘W’ (in the Flags register at
0x1FFFF0) to a ‘1’ to enable writes to the Flags register. Write a
‘0’ to the OSCF bit and then reset the write bit to ‘0’ to disable
writes.
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
Calibrating the Clock
The RTC is driven by a quartz-controlled crystal with a nominal
frequency of 32.768 kHz. The clock accuracy depends on the
quality of the crystal and calibration. The crystals available in the
market typically have an error of +20 ppm to +35 ppm. However,
CY14B116K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at any given temperature. This implies an
error of +2.5 seconds to –5 seconds per month.
During the backup operation, the CY14B116K consumes
0.45 A (Typical) at room temperature. Choose the capacitor or
battery values according to your application.
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in the Calibration register at 0x1FFFF8.
The calibration bits occupy the five lower order bits in the
Calibration register. These bits are set to represent any value
between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a
‘1’ indicates positive calibration and a ‘0’ indicates negative
calibration. Adding counts speeds the clock up and subtracting
counts slows the clock down. If a binary ‘1’ is loaded into the
register, it corresponds to an adjustment of 4.068 or –2.034-ppm
offset in oscillator error, depending on the sign.
Table 3. RTC Backup Time
Capacitor Value
Backup Time (CY14B116K)
0.1F
0.47F
1.0F
2.5 days
12 days
25 days
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3-V lithium battery is recommended and the
CY14B116K sources current only from the battery when the
primary power is removed. However, the battery is not recharged
at any time by the CY14B116K. The battery capacity must be
chosen for total anticipated cumulative down time required over
the life of the system.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once every minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment for every calibration step in the Calibration register.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFFF8 controls
enabling and disabling of the oscillator. This bit is nonvolatile and
is shipped to customers in the “enabled” (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
To determine the required calibration, the CAL bit in the Flags
register (0x1FFFF0) must be set to ‘1’. This causes the INT pin
to toggle at a nominal frequency of 512 Hz. Any deviation
measured from 512 Hz indicates the degree and direction of the
required correction. For example, a reading of 512.01024 Hz
indicates a +20-ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
While the system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum levels,
the oscillator may fail. The CY14B116K can detect oscillator
failure when system power is restored. This is recorded in the
Oscillator Fail Flag (OSCF) of the Flags register at the address
0x1FFFF0. When the device is powered on (VCC goes above
VSWITCH), the OSCEN bit is checked for the ‘enabled’ status. If
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit ‘W’ (in the flags register at
0x1FFFF0) to ‘1’ to enable writes to the flags register. Write a
value to CAL, and then reset the write bit to ‘0’ to disable writes.
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CY14B116K/CY14B116M
New timeout values are written by setting the Watchdog Write
(WDW) bit to ‘0’. When the WDW is ‘0’, new writes to the
watchdog timeout value bits D5–D0 are enabled to modify the
timeout value. When WDW is ‘1’, writes to bits D5–D0 are
ignored. The WDW function enables you to set the WDS bit,
without concern that the watchdog timer value is modified. A
logical diagram of the watchdog timer is shown in Figure 6. Note
that setting the watchdog timeout value to ‘0’ disables the
watchdog function.
Alarm
The alarm function compares user-programmed values of alarm
time and date (stored in the registers 0x1FFFF2-0x1FFFF5) with
the corresponding time of day and date values. When a match
occurs, the alarm interrupt flag (AF) is set and an interrupt is
generated on the INT pin if the Alarm Interrupt Enable (AIE) bit
is set.
There are four alarm match fields – date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, the alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the Watchdog Interrupt
Enable (WIE) bit in the Interrupt register is set, a hardware
interrupt on the INT pin is also generated on watchdog timeout.
The flag and the hardware interrupt are both cleared when you
read the Flags register.
Figure 6. Watchdog Timer Block Diagram
Clock
1 Hz
Oscillator
32768 Hz
Divider
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x1FFFF0 indicates that a date or time match has occurred. The
AF bit is set to ‘1’ when a match occurs. Reading the flags
register clears the alarm flag bit (and all of the register bits). A
hardware interrupt pin may also be used to detect an alarm
event.
32 Hz
Zero
Compare
WDF
Counter
To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register
– 0x1FFFF0) to ‘1’ to enable writes to Alarm Registers. After
writing the alarm value, clear the ‘W’ bit back to ‘0’ for the
changes to take effect.
Load
WDS
Register
Q
D
Note CY14B116K requires the alarm match bit for seconds (bit
‘D7’ in Alarm-Seconds register 0x1FFFF2) to be set to ‘0’ for
proper operation of Alarm Flag and Interrupt.
WDW
Q
Watchdog
Register
Watchdog Timer
Write to
Watchdog
Register
The Watchdog Timer is a free-running down counter that uses
the 32 Hz (31.25 ms period) clock derived from the crystal oscil-
lator. The oscillator must be running for the watchdog to function.
It begins counting down from the value loaded in the Watchdog
Timer register 0x1FFFF7.
Programmable Square Wave Generator
The square wave generator block uses the crystal output to
generate a desired frequency on the INT pin of the device. The
output frequency can be programmed to be one of the following:
Note Since the Watchdog Timer uses a free-running 32-Hz
(31.25 ms period) clock, the start of countdown has a delay
between 0 ms and 31.25 ms.
1. 1 Hz
2. 512 Hz
3. 4096 Hz
4. 32768 Hz
The timer consists of a loadable register and a free-running
counter. On power-up, the watchdog timeout value in register
0x1FFFF7 is loaded in the Counter Load register, which is shown
in Figure 6. Counting begins on power-up and restarts from the
loadable value any time the Watchdog Strobe (WDS) bit is set to
‘1’. The counter is compared to the terminal value of ‘0’. If the
counter reaches this value, it causes an internal flag and an
optional interrupt output. You can prevent the timeout interrupt
by setting the WDS bit to ‘1’ prior to the counter reaching ‘0’. This
causes the counter to reload with the watchdog timeout value
and to be restarted. If you set the WDS bit prior to the counter
reaching the terminal value, the interrupt does not occur and the
watchdog timer flag is not set.
The square wave output is not generated while the device is
running on backup power.
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CY14B116K/CY14B116M
Interrupt Register
Power Monitor
Watchdog Interrupt Enable (WIE). When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog timeout occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in Flags register.
The CY14B116K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to back up power for the clock and protects the memory from low
VCC access. The power monitor is based on an internal bandgap
reference circuit that compares the VCC voltage to VSWITCH
threshold.
Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF flag in the Flags register.
When VSWITCH is reached, as VCC decays from power loss, a
data store operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
switched from VCC to the backup supply (battery or capacitor) to
operate the RTC oscillator.
Power Fail Interrupt Enable (PFE). When set to ‘1’, the power
fail monitor drives the INT pin and an internal flag. When PFE is
set to ‘0’, the power fail monitor only affects the PF flag in the
Flags register.
When operating from the backup source, read and write opera-
tions to nvSRAM are inhibited and the RTC functions are not
available to the user. The RTC clock continues to operate in the
background. The updated RTC time keeping registers are
available to the user after VCC is restored to the device (see
“AutoStore/Power-Up RECALL Characteristics” on page 30).
Square Wave Enable (SQWE). When set to ‘1’, a square wave
of programmable frequency is generated on the INT pin. The
frequency is decided by the SQ1 and SQ0 bits of the interrupts
register. This bit is nonvolatile and survives the power cycle. The
SQWE bit overrides all other interrupts. However, the CAL bit will
take precedence over the square wave generator. This bit
defaults to ‘0’ from the factory.
Backup Power Monitor
High/Low (H/L). When set to ‘1’, the INT pin is active HIGH and
The CY14B116K provides a backup power monitoring system
that detects the backup power (either battery or capacitor
backup) failure. The backup power fail flag (BPF) is issued on
the next power-up if the backup power fails. The BPF flag is set
in the event of backup voltage falling lower than VBAKFAIL. The
backup power is monitored even while the RTC is running in the
backup mode. Low voltage detected during the backup mode is
flagged through the BPF flag. BPF can hold the data only until a
defined low level of the back up voltage (VDR).
the driver mode is push pull. The INT pin drives HIGH only when
VCC is greater than VSWITCH. When set to ‘0’, the INT pin is active
LOW and the Drive mode is open drain. The INT pin must be
pulled up to VCC by a 10-k resistor while using the interrupt in
active LOW mode.
Pulse/Level (P/L). When set to ‘1’ and an interrupt occurs, the
INT pin is driven active (determined by H/L) for approximately
200 ms. When P/L is set to ‘0’, the INT pin is driven HIGH or LOW
(determined by H/L) until the Flags or Control register is read.
Interrupts
SQ1 and SQ0. These bits are used together to fix the frequency
of the square wave on the INT pin output when the SQWE bit is
set to ‘1’. These bits are nonvolatile and survive the power cycle.
The output frequency is decided as illustrated in the following
table.
The CY14B116K has a Flags register, Interrupt register, and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x1FFFF6). In addition, each has an associated flag bit
in the Flags register (0x1FFFF0) that the host processor uses to
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
Table 4. Square Wave Output Selection
SQ1
SQ0
Frequency
1 Hz
Comment
1 Hz signal
512 Hz clock output
0
0
1
1
0
1
0
1
An Interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in the Inter-
rupts register is enabled (set to ‘1’). After an interrupt source is
active, two programmable bits, H/L and P/L, determine the
behavior of the output pin driver on the INT pin. These two bits
are located in the Interrupt register and can be used to drive
Level or Pulse mode output from the INT pin. In the Pulse mode,
the pulse width is internally fixed at approximately 200 ms. This
mode is intended to reset a host microcontroller. In the Level
mode, the pin goes to its active polarity until you read the Flags
register. This mode is used as an interrupt to a host microcon-
troller. The control bits are summarized in the following section.
512 Hz
4096 Hz 4 KHz clock output
32768 Hz Oscillator output frequency
While using more than one of the interrupt sources and an
interrupt source activates the INT pin, the external host must
read the Flags Register to determine the cause of the interrupt.
Remember that all the flags are cleared when the Flags register
is read. If the INT pin is programmed for the Level mode, then
reading the flag clears the flag and the INT pin returns to its
inactive state. If the pin is programmed for the Pulse mode, then
reading the flag clears the flag and the pin. The pulse does not
complete its specified duration if the Flags register is read. If the
INT pin is used as a host reset, then the Flags or Control register
is not read during a reset.
Interrupts are only generated while working on normal power and
are not triggered when the system runs in the backup power
mode.
Note CY14B116K generates valid interrupts only after the
Powerup RECALL sequence is completed. All events on the INT
pin must be ignored for tHRECALL duration after power-up.
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CY14B116K/CY14B116M
Setting the calibration bit CAL = ‘1’ or SQWE = ‘1’ enables square
wave output on the INT pin. In this situation, the CAL bit setting
gets priority over the SQWE bit and enables the 512-Hz digital
clock output on the INT pin for calibration. The CAL bit does not
survive the power cycle and resets to zero during the next
power-up cycle. The setting of SQWE, SQ0 and SQ1, requires
AutoStore or software STORE to keep the setting of these bits
nonvolatile and enable them to survive the power cycle. When
multiple sources are set to drive the interrupt pin (INT), then the
following priority will be followed to resolve ambiguity as to which
cause drives the INT pin.
Flags Register
The Flags register has three flag bits: WDF, AF, and PF, which
can be used to generate an interrupt. They are set by the
watchdog timeout, alarm match, or power fail monitor respec-
tively. The processor can either poll this register or enable inter-
rupts when a flag is set. These flags are automatically reset when
the register is read. The flags register is automatically loaded
with the value 0x00 on power-up (except for the OSCF bit. See
Stopping and Starting the Oscillator on page 11).
Following is a summary table that shows the state of the INT pin,
Table 5. State of the INT pin
CAL
SQWE
WIE/AIE/PFE
INT Pin Output
512 Hz
1
0
0
0
X
1
0
0
X
X
1
0
Square wave output
Alarm
HI-Z
Figure 7. Interrupt Block Diagram
WIE
Watchdog
Timer
WDF
PFE
VCC
P/L
Power
Monitor
PF
512 Hz
Clock
Pin
INT
Driver
AIE
Mux
Clock
Alarm
Square
Wave
AF
HI-Z
Control
H/L
VSS
SEL Line
SQWE
CAL
Priority
Encoder
WIE/PIE/
AIE
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CY14B116K/CY14B116M
RTC External Components
The RTC requires connecting an external 32.768-kHz crystal and C1, C2 load capacitance as shown in the Figure 8. The figure shows
the recommended RTC external component values. The load capacitances, C1 and C2, are inclusive of parasitic of the printed circuit
board (PCB). The PCB parasitic includes the capacitance due to land pattern of crystal pads/pins, Xin/Xout pads, and copper traces
connecting the crystal and device pins.
Figure 8. RTC Recommended Component Configuration[12]
Recommended Values
Y1 = 32.768 kHz (12.5 pF)
C1 = 12 pF
C2 = 69 pF
Note The recommended values for C1 and C2 include
board trace capacitance.
C1
C2
X
out
Y1
X
in
Note
12. For nonvolatile static random access memory (nvSRAM) real time clock (RTC) design guidelines and best practices, see application note AN61546.
Document #: 001-67786 Rev. *K
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CY14B116K/CY14B116M
■ Shield the Xin and Xout signals by providing a guard ring around
the crystal circuitry. This guard ring prevents noise coupling
from neighboring signals.
PCB Design Considerations for RTC
The RTC crystal oscillator is a low-current circuit with
high-impedance nodes on their crystal pins. Due to the low
operating current of the RTC circuit, the crystal connections are
very sensitive to noise on the board. Hence, it is necessary to
isolate the RTC circuit from other signals on the board.
■ Take care while routing any other high-speed signal in the
vicinity of RTC traces. The more the crystal is isolated from
other signals on the board, the less likely it is that noise is
coupled into the crystal. Maintain a minimum of 200 mil
separation between the Xinand Xout traces, and any other high
speed signal on the board.
It is also critical to minimize the stray capacitance on the PCB.
Stray capacitances add to the overall crystal load capacitance
and, therefore, cause oscillation frequency errors. Proper
bypassing and careful layout are required to achieve the
optimum RTC performance.
■ No signals should run underneath crystal components on the
same PCB layer.
■ Create an isolated solid copper ground plane on the adjacent
PCB layer and underneath the crystal circuitry to prevent
unwanted noise coupled from traces routed on the other signal
layers of the PCB. The local ground plane should be separated
by at least 40 mils from the neighboring plane on the same PCB
layer. The solid ground plane should only be in the vicinity of
RTC components and its perimeter should be kept equal to the
guard ring perimeter. The isolated ground plane should be
connected to system ground. Figure 9 shows the recom-
mended layout for the RTC circuit.
Layout Requirements
The board layout must adhere to (but not limited to) the following
guidelines during routing RTC circuitry because they help you
achieve optimum performance from the RTC design.
■ Place the crystal as close as possible to the Xin and Xout pins.
Keep the trace lengths between the crystal and RTC equal in
length and as short as possible to reduce the probability of
noise coupling.
■ Keep Xin and Xout trace width below 8 mils. A wider trace width
leads to larger trace capacitance. The larger these bond pads
and traces are, the more likely it is that noise can couple from
adjacent signals.
Figure 9. Recommended Layout for RTC
Top component layer: L1
Ground plane layer: L2
System ground
C1
Y1
C2
Isolated ground plane on
layer 2: L2
Guard ring - Top (Component)
layer: L1
Via: Via connects to isolated
ground plane on L2
Via: Via connects to system ground
plane on L2
Document #: 001-67786 Rev. *K
Page 16 of 43
CY14B116K/CY14B116M
Table 6. RTC Register Map[13]
Register
BCD Format Data[14]
Function/Range
CY14B116K CY14B116M
D7
D6
D5
10s years
0
D4
D3
D2
Years
Months
Day of month
D1
D0
0x1FFFFF
0x1FFFFE
0x1FFFFD
0xFFFFF
0xFFFFE
0xFFFFD
Years: 00–99
0
0
0
0
10s months
Months: 01–12
10s day of month
Day of month:
01–31
0x1FFFFC
0xFFFFC
0
0
0
0
0
0
Day of week
Day of week:
01–07
0x1FFFFB
0x1FFFFA
0x1FFFF9
0x1FFFF8
0xFFFFB
0xFFFFA
0xFFFF9
0xFFFF8
0
0
0
10s hours
Hours
Minutes
Seconds
Hours: 00–23
Minutes: 00–59
Seconds: 00–59
10s minutes
10s seconds
OSCEN
(0)
0
Calsign
(0)
Calibration (00000)
Calibration
values[15]
0x1FFFF7
0x1FFFF6
0x1FFFF5
0x1FFFF4
0x1FFFF3
0x1FFFF2
0xFFFF7
0xFFFF6
0xFFFF5
0xFFFF4
0xFFFF3
0xFFFF2
WDS
(0)
WDW
(0)
WDT (000000)
Watchdog timer15]
WIE
(0)
AIE
(0)
PFE
(0)
SQWE
(0)
H/L
(1)
P/L
(0)
SQ1 SQ0
Interrupts[15]
(0)
(0)
M (1)
M (1)
M (1)
M (1)
0
10s alarm day of month
Alarm, day of month
Alarm, hours
Alarm, day of
month: 01–31
0
10s alarm hours
Alarm, hours:
00–23
10s alarm minutes
10s alarm seconds
Alarm, minutes
Alarm, seconds
Centuries
Alarm, minutes:
00–59
Alarm, seconds:
00–59
0x1FFFF1
0x1FFFF0
0xFFFF1
0xFFFF0
10s centuries
AF PF
Centuries: 00–99
Flags[15]
WDF
OSCF[16]
BPF[16]
CAL
(0)
W
(0)
R
(0)
Notes
13. Upper Byte D -D (CY14B116M) of RTC registers are reserved for future use.
15
8
14. ( ) designates values shipped from the factory.
15. This is a binary value, not a BCD value.
16. When you reset OSCF and BPF flag bits, the flags register will be updated after t
time.
RTCp
Document #: 001-67786 Rev. *K
Page 17 of 43
CY14B116K/CY14B116M
Table 7. Register Map Detail
Register
Description
CY14B116K
CY14B116M
Time Keeping - Years
D4 D3
0x1FFFFF
0xFFFFF
D7
D6
D5
D2
D1
D0
10s years
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years;
upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The
range for the register is 0–99.
Time Keeping - Months
0x1FFFFE
0xFFFFE
D7
D6
D5
D4
D3
D2
D1
Months
D0
0
0
0
10s
month
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range
for the register is 1–12.
Time Keeping - Day of month
0x1FFFFD
0x1FFFFC
0x1FFFFB
0x1FFFFA
0x1FFFF9
0x1FFFF8
0xFFFFD
0xFFFFC
0xFFFFB
0xFFFFA
0xFFFF9
0xFFFF8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s day of month
Day of month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit
and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.
The range for the register is 1–31. Leap years are automatically adjusted for.
Time Keeping - Day of week
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of week
Lower nibble (three bits) contains a value that correlates to the of the week. Day of the week is a
ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day
value, because the day is not integrated with the date.
Time Keeping - Hours
D7
D6
D5
10s hours
D4
D3
D2
D1
D0
0
0
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower
digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from
0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
D6
D5
D4
D3
D2
D1
Minutes
D0
0
10s minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.
The range for the register is 0–59.
Time Keeping - Seconds
D7
D6
D5
D4
D3
D2
D1
Seconds
D0
0
10s seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range
for the register is 0–59.
Calibration/Control
D7
D6
D5
D4
D3
D2
D1
D0
Document #: 001-67786 Rev. *K
Page 18 of 43
CY14B116K/CY14B116M
Table 7. Register Map Detail (continued)
Register
Description
CY14B116K
CY14B116M
OSCEN
0
Calibration
sign
Calibration
OSCEN
Oscillator enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs.
Disabling the oscillator saves battery or capacitor power during storage.
Calibration
Sign
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0)
from the time-base.
Calibration
These five bits control the calibration of the clock.
Watchdog Timer
0x1FFFF7
0xFFFF7
D7
D6
D5
D4
D3
WDT
D2
D1
D0
WDS
WDW
WDS
Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to
‘0’ has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit
is write only. Reading it always returns a 0.
WDW
Watchdog write enable. Setting this bit to ‘1’ disables any write to the watchdog timeout value
(D5–D0). This allows you to set the watchdog strobe bit without disturbing the timeout value.
Setting this bit to ‘0’ allows bits D5–D0 to be written to the watchdog register when the next write
cycle is complete. This function is explained in more detail in Watchdog Timer on page 12.
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32-Hz count (31.25 ms). The range of timeout value is
31.25 ms (a setting of 01h) to 2 seconds (setting of 3Fh). Setting the watchdog timer register to
0 disables the timer. These bits can be written only if the WDW bit was set to ‘0’ on a previous cycle.
Note Since the Watchdog Timer uses a free-running 32-Hz (31.25 ms period) clock, the set time
interval has an additional time between 0 ms and 31.25 ms.
Interrupt Status/Control
0x1FFFF6
0xFFFF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
SQWE
H/L
P/L
SQ1
SQ0
WIE
Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer
drives the INT pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF
flag.
AIE
PFE
Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When
set to ‘0’, the alarm match only affects the AF flag.
Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When
set to ‘0’, the power fail monitor affects only the PF flag.
SQWE
Square wave enable. When set to ‘1’, a square wave is driven on the INT pin with frequency
programmed using SQ1 and SQ0 bits. The square wave output takes precedence over interrupt
logic. If the SQWE bit is set to ‘1’. when an enabled interrupt source becomes active, only the
corresponding flag is raised and the INT pin continues to drive the square wave.
H/L
P/L
HIGH/LOW. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open
drain, active LOW.
Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L)
until the flags register is read.
SQ1, SQ0
SQ1, SQ0. These bits are used to decide the frequency of the square wave on the INT pin output
when SQWE bit is set to ‘1’. The following is the frequency output for each combination of SQ1,
SQ0:
(0, 0) - 1 Hz
(0, 1) - 512 Hz
(1, 0) - 4096 Hz
(1, 1) - 32768 Hz
Document #: 001-67786 Rev. *K
Page 19 of 43
CY14B116K/CY14B116M
Table 7. Register Map Detail (continued)
Register
Description
CY14B116K
CY14B116M
Alarm - Day of month
D4 D3
10s alarm day of month
0x1FFFF5
0xFFFF5
D7
D6
D5
D2
D1
D0
M
0
Alarm day of month
Contains the alarm value for the date of the month and the match bit to select or deselect the date
value.
M
M
M
Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the date value.
Alarm - Hours
0x1FFFF4
0x1FFFF3
0x1FFFF2
0xFFFF4
0xFFFF3
0xFFFF2
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s alarm hours
Alarm hours
Contains the alarm value for the hours and the match bit to select or deselect the hours value.
Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’
causes the match circuit to ignore the hours value.
Alarm - Minutes
D7
D6
D5
D4
D3
D2
D1
D0
M
10s alarm minutes
Alarm minutes
Contains the alarm value for the minutes and the match bit to select or deselect the minutes value.
Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to
‘1’ causes the match circuit to ignore the minutes value.
Alarm - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
M
10s alarm seconds
Alarm seconds
Contains the alarm value for the seconds and the match bit to select or deselect the second’s
value.
M
Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to
‘1’ causes the match circuit to ignore the seconds value.
Time Keeping - Centuries
0x1FFFF1
0xFFFF1
D7
D6
D5
D4
D3
D2
D1
D0
10s centuries
Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0
to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is
0-99 centuries.
Document #: 001-67786 Rev. *K
Page 20 of 43
CY14B116K/CY14B116M
Table 7. Register Map Detail (continued)
Register
Description
CY14B116K
CY14B116M
Flags
D7
0x1FFFF0
0xFFFF0
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
BPF
CAL
W
R
WDF
Watchdog timer flag. This read-only bit is set to ‘1’ when the watchdog timer is allowed to reach
0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power-up
AF
PF
Alarm flag. This read-only bit is set to ‘1’ when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power-up.
Power fail flag. This read-only bit is set to ‘1’ when power falls below the power fail threshold
VSWITCH. It is cleared when the Flags register is read.
OSCF
Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first
5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.
This bit survives the power cycle and is never cleared internally by the chip. The user must check
for this condition and write 0 to clear this flag. When user resets OSCF flag bit, the bit will be
updated after tRTCp time.
BPF
Backup power fail flag. Set to ‘1’ on power-up if the backup power (battery or capacitor) failed.
The backup power fail condition is determined by the voltage falling below their respective
minimum specified voltage. BPF can hold the data only till a defined low level of the back up
voltage (VDR). User must reset this bit to clear this flag. When user resets BPF flag bit, the bit will
be updated after tRTCp time.
CAL
W
Calibration mode. When set to ‘1’, a 512-Hz square wave is output on the INT pin. When set to
‘0’, the INT pin resumes normal operation. This bit takes priority over SQ0/SQ1 and other
functions. This bit defaults to 0 (disabled) on power-up.
Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. You can then write to
RTC registers, alarm registers, calibration register, interrupt register and flags register. Setting the
‘W’ bit to ‘0’ causes the contents of the RTC registers to be transferred to the time keeping counters
if the time has changed. This transfer process takes tRTCp time to complete. This bit defaults to 0
on power-up.
R
Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates
are not seen during the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding
register. Setting this bit does not require ‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up.
Document #: 001-67786 Rev. *K
Page 21 of 43
CY14B116K/CY14B116M
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. .1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount lead soldering
temperature (3 seconds) .......................................... +260 C
DC output current (1 output at a time, 1s duration) ..... 20 mA
At 150 C ambient temperature.................................. 1000 h
At 85 C ambient temperature................................. 20 Years
Maximum junction temperature .................................. 150 C
Supply voltage on VCC relative to VSS .........–0.5 V to +4.1 V
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current .................................................... > 140 mA
Operating Range
Voltage applied to outputs
in high-Z state......................................–0.5 V to VCC + 0.5 V
Ambient
Temperature (TA)
Product
Range
VCC
Input voltage.........................................–0.5 V to Vcc + 0.5 V
CY14B116K/
CY14B116M
Transient voltage (<20 ns) on
any pin to ground potential ..................–2.0 V to VCC + 2.0 V
Industrial
–40 C to +85 C 2.7 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Power supply
Test Conditions
Min
2.7
–
Typ[17]
Max
3.6
95
Unit
V
–
3.0
–
ICC1
Average VCC current Values obtained without output loads
(IOUT = 0 mA)
tRC = 25 ns
tRC = 45 ns
mA
mA
mA
–
–
75
ICC2
ICC3
Average VCC current All inputs don’t care, VCC = VCC(Max).
during STORE
–
–
10
Average current for duration tSTORE
Average VCC current All inputs cycling at CMOS Levels.
at tRC = 200 ns,
VCC(Typ), 25 °C
–
–
50
–
–
6
mA
mA
Values obtained without output loads (IOUT = 0 mA).
[18]
ICC4
Average VCAP current All inputs don’t care. Average current for duration tSTORE
during AutoStore cycle
ISB
VCC standby current CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC tRC = 25 ns
–
–
–
–
750
600
µA
µA
– 0.2 V). ‘W’ and ‘R’ bit set to ‘0’.
tRC = 45 ns
Standbycurrentlevelafternonvolatilecycle
is complete. Inputs are static. f = 0 MHz.
IZZ
Sleep mode current
All inputs are static at CMOS Level; RTC running on
backup power supply.
–
–
–
10
+1
µA
µA
[19]
IIX
Input leakage current VCC = VCC(Max), VSS < VIN < VCC
(except HSB)
–1
Input leakage current VCC = VCC(Max), VSS < VIN < VCC
(for HSB)
–100
–
+1
µA
Notes
17. Typical values are at 25 °C, V = V (Typ). Not 100% tested.
CC
CC
18. This parameter is only guaranteed by design and is not tested.
19. The HSB pin has I = -2 µA for V of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
OH
OH
OL
parameter is characterized but not tested.
20. Min V value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor
CAP
CAP
on V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore,
CAP
it is always recommended to use a capacitor within the specified min and max limits.
21. Maximum voltage on V pin (V ) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
CAP
VCAP
CAP
temperature range should be higher than the V
voltage.
VCAP
22. These parameters are only guaranteed by design and are not tested.
Document #: 001-67786 Rev. *K
Page 22 of 43
CY14B116K/CY14B116M
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
IOZ
Description
Test Conditions
VCC = VCC(Max), VSS < VOUT < VCC, CE or OE > VIH or
BLE/BHE > VIH or WE < VIL
–
Min
Typ[17]
Max
Unit
Off state output
leakage current
–1
–
+1
µA
VIH
Input HIGH voltage
2.0
–
VCC
0.5
+
V
VIL
Input LOW voltage
–
VSS – 0.5
–
–
0.8
–
V
V
VOH
VOL
VCAP
Output HIGH voltage IOUT = –2 mA
Output LOW voltage IOUT = 4 mA
2.4
–
–
0.4
82.0
5.0
V
[20]
Storage capacitor
Between VCAP pin and VSS
VCC = VCC (max)
19.8
–
22.0
–
µF
V
[21, 22]
VVCAP
Maximum voltage
driven on VCAP pin by
the device
Notes
17. Typical values are at 25 °C, V = V (Typ). Not 100% tested.
CC
CC
18. This parameter is only guaranteed by design and is not tested.
19. The HSB pin has I = -2 µA for V of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
OH
OH
OL
parameter is characterized but not tested.
20. Min V value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor
CAP
CAP
on V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore,
CAP
it is always recommended to use a capacitor within the specified min and max limits.
21. Maximum voltage on V pin (V ) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
CAP
VCAP
CAP
temperature range should be higher than the V
voltage.
VCAP
22. These parameters are only guaranteed by design and are not tested.
Data Retention and Endurance
Over the Operating Range
Parameter
DATAR
Description
Min
20
Unit
Years
Cycles
Data retention
Nonvolatile STORE operations
NVC
1,000,000
Capacitance
In the following table, the capacitance parameters are listed. [23]
Max
Max
Parameter
CIN
Description
Input capacitance
Test Conditions
(All packages
(165-FBGA
package)
Unit
except 165-FBGA)
TA = 25 C, f = 1 MHz,
CC = VCC (Typ)
8
8
8
10
10
10
pF
pF
pF
V
CIO
Input/Output capacitance
Output capacitance
COUT
Notes
23. These parameters are only guaranteed by design and are not tested.
Document #: 001-67786 Rev. *K
Page 23 of 43
CY14B116K/CY14B116M
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[24]
Parameter
Description
Test Conditions
44-TSOP II 54-TSOP II 165-FBGA Unit
JA
Thermal resistance
(Junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
44.6
41.1
15.6
C/W
JC
Thermal resistance
(Junction to case)
2.4
4.6
2.9
C/W
Notes
24. These parameters are only guaranteed by design and are not tested.
Figure 10. AC Test Loads and Waveforms
For Tristate specs
577
577
3.0 V
OUTPUT
3.0 V
R1
R1
OUTPUT
R2
R2
CL
CL
789
789
30 pF
5 pF
AC Test Conditions
Input pulse levels....................................................0 V to 3 V
Input rise and fall times (10% - 90%)........................... < 3 ns
Input and output timing reference levels........................ 1.5V
Document #: 001-67786 Rev. *K
Page 24 of 43
CY14B116K/CY14B116M
RTC Characteristics
Over the Operating Range
Parameters
Description
Min
1.8
–
Typ[25]
Max
3.6
0.45
–
Unit
V
VRTCbat
RTC battery pin voltage
3.0
–
[26]
IBAK
RTC backup current
TA = –40 C
TA = 25 °C
TA = 85 °C
TA = –40 C
TA = 25 °C
TA = 85 °C
µA
µA
µA
V
–
0.45
–
–
0.60
3.6
3.6
3.6
2.2
-
[27]
VRTCcap
RTC capacitor pin voltage
1.6
1.5
1.4
1.8
1.6
–
–
3.0
–
V
V
VBAKFAIL
VDR
Backup failure threshold
BPF flag retention voltage
–
V
–
V
tOCS
tRTCp
RTC oscillator time to start
1
2
sec
ms
RTC processing time from end of ‘W’ bit set to ‘0’
–
–
1
RBKCHG
RTC backup capacitor charge current-limiting resistor
350
–
850
Notes
25. Typical values are at 25 °C, V = V (Typ). Not 100% tested.
CC
CC
26. From either V
or V
.
RTCbat
RTCcap
27. If V
> 0.5 V or if no capacitor is connected to V
pin, the oscillator starts in tOCS time. If a backup capacitor is connected and V < 0.5 V, the capacitor
RTCcap
RTCcap
RTCcap
must be allowed to charge to 0.5 V for oscillator to start.
Document #: 001-67786 Rev. *K
Page 25 of 43
CY14B116K/CY14B116M
AC Switching Characteristics
Over the Operating Range[28]
Parameters
25 ns
45 ns
Description
Unit
Cypress
Alt Parameter
Parameter
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
tRC
tAA
Chip enable access time
–
25
–
25
–
–
45
–
45
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[29]
tRC
Read cycle time
[30]
tAA
tDOE
Address access time
25
12
–
45
20
–
tOE
tOH
tLZ
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
–
–
[30]
tOHA
3
3
[31]
tLZCE
tHZCE
tLZOE
tHZOE
3
–
3
–
[ 31, 32]
[31]
tHZ
–
10
–
–
15
–
tOLZ
tOHZ
tPA
0
0
[31, 32]
–
10
–
–
15
–
[31]
tPU
0
0
[31]
tPD
tPS
–
25
12
–
–
45
20
–
tDBE
–
–
[31]
tLZBE
Byte enable to output active
Byte disable to output inactive
0
0
[31, 32]
tHZBE
–
10
–
15
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write cycle time
25
20
20
10
0
–
–
45
30
30
15
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
–
–
–
–
tHD
–
–
tAW
tSA
20
0
–
30
0
–
–
–
tHA
tWR
tWZ
tOW
0
–
0
–
[31, 32, 33]
tHZWE
–
10
–
–
15
–
[31]
tLZWE
3
3
tBW
20
–
30
–
Notes
28. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of V /2, input pulse levels of 0 to V (Typ), and output loading of the specified
CC
CC
I
/I and 30 pF load capacitance as shown in Figure 10 on page 24.
OL OH
29. WE must be HIGH during SRAM read cycles.
30. Device is continuously selected with CE, OE and BLE, BHE LOW.
31. These parameters are only guaranteed by design and are not tested.
32. t
, t
, t
and t
are specified with a load capacitance of 5 pF. Transition is measured ±200 mV from the steady state output voltage.
HZCE HZOE HZBE
HZWE
33. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
Document #: 001-67786 Rev. *K
Page 26 of 43
CY14B116K/CY14B116M
Figure 11. SRAM Read Cycle 1: Address Controlled[34, 35, 36]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Figure 12. SRAM Read Cycle 2: CE and OE Controlled[34, 36, 37]
Address
[38]
Address Valid
tRC
tHZCE
tACE
tAA
CE
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Standby
Data Output
Output Data Valid
tPU
tPD
ICC
Active
Notes
34. WE must be HIGH during SRAM read cycles.
35. Device is continuously selected with CE, OE and BLE, BHE LOW.
36. HSB must remain HIGH during Read and Write cycles.
37. BLE, BHE are applicable for x16 configuration only.
38. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted
1
2
1
2
on any of the chip enable pins (CE for the single chip enable device; CE and CE for the dual chip enable device).
1
2
Document #: 001-67786 Rev. *K
Page 27 of 43
CY14B116K/CY14B116M
Figure 13. SRAM Write Cycle 1: WE Controlled[39, 40, 41, 42]
tWC
Address
Address Valid
tSCE
tHA
[43]
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Data Output
Previous Data
Figure 14. RAM Write Cycle 2: CE Controlled[39, 40, 41, 42]
tWC
Address Valid
Address
tSA
tSCE
tHA
[43]
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Data Input
Input Data Valid
High Impedance
Data Output
Notes
39. BLE, BHE are applicable for x16 configuration only.
40. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
41. HSB must remain HIGH during Read and Write cycles.
42. CE or WE must be >V during address transitions.
IH
43. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted
1
2
1
2
on any of the chip enable pins (CE for the single chip enable device; CE and CE for the dual chip enable device).
1
2
Document #: 001-67786 Rev. *K
Page 28 of 43
CY14B116K/CY14B116M
Figure 15. SRAM Write Cycle 2: CE Controlled[44, 45, 46, 47]
tWC
Address Valid
tSCE
Address
tSA
tHA
[48]
CE
tBW
tPWE
tSD
BHE, BLE
WE
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Figure 16. SRAM Write Cycle 3: BHE, BLE Controlled[44, 45, 46, 47, 49]
(Not applicable for RTC register writes)
tWC
Address
[48]
Address Valid
tSCE
CE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Input Data Valid
High Impedance
Data Input
Data Output
Notes
44. BLE, BHE are applicable for x16 configuration only.
45. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
46. HSB must remain HIGH during Read and Write cycles.
47. CE or WE must be >V during address transitions.
IH
48. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted
1
2
1
2
on any of the chip enable pins (CE for the single chip enable device; CE and CE for the dual chip enable device).
1
2
49. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
Document #: 001-67786 Rev. *K
Page 29 of 43
CY14B116K/CY14B116M
AutoStore/Power-Up RECALL Characteristics
Over the Operating Range
CY14B116K/CY14B116M
Unit
Parameter
Description
Power-Up RECALL duration
Min
–
Max
30
8
[50]
tHRECALL
ms
ms
ns
V
[51]
tSTORE
STORE cycle duration
–
[52, 53]
tDELAY
Time allowed to complete SRAM write cycle
Low voltage trigger level
VCC rise time
–
25
2.65
–
VSWITCH
–
[53]
tVCCRISE
150
–
µs
V
[53]
VHDIS
HSB output disable voltage
HSB to output active time
HSB HIGH active time
1.9
5
[53]
tLZHSB
–
µs
ns
[53]
tHHHD
–
500
Figure 17. AutoStore or Power-Up RECALL[54]
VCC
VSWITCH
VHDIS
[51]
Note
[51]
tVCCRISE
tSTORE
tSTORE
Note
tHHHD
tHHHD
[55]
Note
[55]
Note
HSB out
tDELAY
tLZHSB
tLZHSB
AutoStore
tDELAY
Power-Up
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
Power-Up
RECALL
BROWN
OUT
AutoStore
Power-down
AutoStore
Power-Up
RECALL
Notes
50. t
starts from the time V rises above V
CC SWITCH.
HRECALL
51. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
52. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
53. These parameters are only guaranteed by design and are not tested.
.
DELAY
54. Read and Write cycles are ignored during STORE, RECALL, and while V is below V
CC
SWITCH.
55. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-67786 Rev. *K
Page 30 of 43
CY14B116K/CY14B116M
Sleep Mode Characteristics
Over the Operating Range
CY14B116K/CY14B116M
Unit
Parameter
Description
Min
–
Max
30
8
tWAKE
tSLEEP
tZZL
Sleep mode exit time (ZZ HIGH to first access after wakeup)
Sleep mode enter time (ZZ LOW to CE don’t care)
ZZ active LOW time
ms
ms
ns
–
50
0
–
tWEZZ
tZZH
Last write to Sleep mode entry time
ZZ active to DQ Hi-Z time
–
µs
ns
–
70
Figure 18. Sleep Mode[56]
V
V
SWITCH
SWITCH
V
CC
ZZ
t
t
t
HRECALL
SLEEP
WAKE
t
WEZZ
t
WE
DQ
ZZH
Data
Read & Write
Inhibited
(RWI)
Power-Up
RECALL
Sleep
Entry
Sleep
Exit
Power-down
AutoStore
Read & Write
Sleep
Read & Write
Note
56. Device initiates sleep routine and enters into Sleep mode after t
duration.
SLEEP
Document #: 001-67786 Rev. *K
Page 31 of 43
CY14B116K/CY14B116M
Software Controlled STORE and RECALL Characteristics
Over the Operating Range[57, 58]
25 ns
45 ns
Unit
Parameter
Description
Min
25
0
Max
–
Min
45
0
Max
–
tRC
tSA
tCW
tHA
STORE/RECALL initiation cycle time
Address setup time
ns
ns
ns
ns
µs
µs
–
–
Clock pulse width
20
0
–
30
0
–
Address hold time
–
–
tRECALL
RECALL duration
–
600
500
–
600
500
[59, 60]
tSS
Soft sequence processing time
–
–
Figure 19. CE and OE Controlled Software STORE and RECALL Cycle[58]
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
[61]
CE
tHA
tHA
tHA
tSA
tHA
OE
tHHHD
tHZCE
[62]
Note
HSB (STORE only)
DQ (DATA)
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 20. AutoStore Enable and Disable Cycle
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
[61]
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
[62]
tLZCE
tDELAY
Note
DQ (DATA)
RWI
Notes
57. The software sequence is clocked with CE controlled or OE controlled reads.
58. The six consecutive addresses must be read in the order listed in Table 2. WE must be HIGH during all six consecutive cycles.
59. This is the amount of time it takes to take action on a soft sequence command. V power must remain high to effectively register command.
CC
60. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
61. TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted
1
2
1
2
on any of the chip enable pins (CE for the single chip enable device; CE and CE for the dual chip enable device).
1
2
62. DQ output data at the sixth read may be invalid since the output is disabled at t
time.
DELAY
Document #: 001-67786 Rev. *K
Page 32 of 43
CY14B116K/CY14B116M
Hardware STORE Characteristics
Over the Operating Range
CY14B116K/CY14B116M
Unit
Parameter
Description
Min
–
Max
25
–
tDHSB
tPHSB
HSB to output active time when write latch not set
Hardware STORE pulse width
ns
ns
15
Figure 21. Hardware STORE Cycle[63]
Write Latch set
t
PHSB
HSB (IN)
t
STORE
t
t
HHHD
DELAY
HSB (OUT)
RWI
t
LZHSB
Write Latch not set
t
PHSB
HSB (IN)
HSB pin is driven HIGH to V
only by internal
CC
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
HSB (OUT)
RWI
t
DELAY
Figure 22. Soft Sequence Processing[64, 65]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
[66]
CE
VCC
Notes
63. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
64. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain high to effectively register a command.
65. Commands such as STORE and RECALL lock out I/O until the operation is complete, which further increases this time. See the specific command.
66. The TSOP II package is offered in single CE and BGA package is offered in dual CE options. In this datasheet, for a dual CE device, CE refers to the internal logical
combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted
1
2
1
2
on any of the chip enable pins (CE for the single chip enable device; CE and CE for the dual chip enable device).
1
2
Document #: 001-67786 Rev. *K
Page 33 of 43
CY14B116K/CY14B116M
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For ×8 Configuration
Single chip enable option (44-pin TSOP II package)
CE
H
L
WE
X
OE
X
Inputs and Outputs
Mode
Power
High-Z
Deselect/Power-down
Read
Standby
Active
Active
Active
H
L
Data out (DQ0–DQ7);
High-Z
L
H
H
Output disabled
Write
L
L
X
Data in (DQ0–DQ7);
For ×16 Configuration
Single chip enable option (54-pin TSOP II package)
CE
H
L
WE
X
OE
X
BLE
X
BHE
X
Inputs and Outputs
High-Z
Mode
Deselect/Power-down
Output disabled
Read
Power
Standby
Active
Active
Active
X
X
H
H
High-Z
L
H
L
L
L
Data out (DQ0–DQ15)
L
H
L
L
H
Data out (DQ0–DQ7);
DQ8–DQ15 in High-Z
Read
L
H
L
H
L
Data out (DQ8–DQ15);
DQ0–DQ7 in High-Z
Read
Active
L
L
L
H
L
L
H
X
X
X
L
L
X
L
High-Z
Output disabled
Write
Active
Active
Active
Data in (DQ0–DQ15
)
H
Data in (DQ0–DQ7);
DQ8–DQ15 in High-Z
Write
L
L
X
H
L
Data in (DQ8–DQ15);
DQ0–DQ7 in High-Z
Write
Active
Document #: 001-67786 Rev. *K
Page 34 of 43
CY14B116K/CY14B116M
For ×16 Configuration
Dual chip enable option (165-ball FBGA package)
CE1
H
CE2
X
WE
X
OE
X
BLE
X
BHE
X
Inputs and Outputs
High-Z
Mode
Deselect/Power-down
Deselect/Power-down
Output disabled
Read
Power
Standby
X
L
X
X
X
X
High-Z
Standby
Active
Active
Active
L
H
X
X
H
H
High-Z
L
H
H
L
L
L
Data out (DQ0–DQ15)
L
H
H
L
L
H
Data out (DQ0–DQ7);
DQ8–DQ15 in High-Z
Read
L
H
H
L
H
L
Data out (DQ8–DQ15);
DQ0–DQ7 in High-Z
Read
Active
L
L
L
H
H
H
H
L
L
H
X
X
X
L
L
X
L
High-Z
Output disabled
Write
Active
Active
Active
Data in (DQ0–DQ15
)
H
Data in (DQ0–DQ7);
DQ8–DQ15 in High-Z
Write
L
H
L
X
H
L
Data in (DQ8–DQ15);
DQ0–DQ7 in High-Z
Write
Active
Document #: 001-67786 Rev. *K
Page 35 of 43
CY14B116K/CY14B116M
Ordering Information
Speed (ns)
Ordering Code
Package Diagram
51-85087
Package Type
44-pin TSOP II
44-pin TSOP II
54-pin TSOP II
54-pin TSOP II
165-ball FBGA
165-ball FBGA
Operating Range
25
CY14B116K-ZS25XI
Industrial
CY14B116K-ZS25XIT
CY14B116M-ZSP25XI
CY14B116M-ZSP25XIT
CY14B116M-BZ45XI
CY14B116M-BZ45XIT
51-85087
51-85160
51-85160
45
51-85195
51-85195
All parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 B 116 K
-
ZS 25
X
I
T
Option: T = Tape and Reel; Blank = Std.
o
Temperature Grade: I = Industrial ( 40 oC to + 85 C)
Pb-free
Speed: 25 = 25 ns; 45 = 45 ns
Package Type: ZS = 44 -TSOP II; ZSP = 54-TSOP II; BZ = 165-FBGA
Data Bus: K = x8 + RTC; M = x16 + RTC
Density: 116 = 16-Mbit
Voltage: B = 3.0 V
14 = nvSRAM
Company ID: CY = Cypress
Document #: 001-67786 Rev. *K
Page 36 of 43
CY14B116K/CY14B116M
Package Diagrams
Figure 23. 44-Pin TSOP II Package Outline (51-85087)
51-85087 *E
Document #: 001-67786 Rev. *K
Page 37 of 43
CY14B116K/CY14B116M
Package Diagrams (continued)
Figure 24. 54-Pin TSOP II Package Outline (51-85160)
51-85160 *E
Document #: 001-67786 Rev. *K
Page 38 of 43
CY14B116K/CY14B116M
Package Diagrams (continued)
Figure 25. 165-ball FBGA (15 mm × 17 mm × 1.40 mm) Package Outline (51-85195)
51-85195 *D
Document #: 001-67786 Rev. *K
Page 39 of 43
CY14B116K/CY14B116M
Acronyms
Document Conventions
Table 8. Acronyms Used in this Document
Units of Measure
Acronym
BCD
Description
Binary coded decimal
Table 9. Units of Measure
Symbol
Unit of Measure
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
°C
degree Celsius
hertz
Hz
Kbit
kHz
k
µA
mA
µF
Mbit
MHz
µs
FBGA
I/O
kilobit
kilohertz
kilohm
JESD
nvSRAM
RoHS
RTC
JEDEC Standards
nonvolatile Static Random Access Memory
Restriction of Hazardous Substances
Real time clock
microampere
milliampere
microfarad
megabit
RWI
Read and Write Inhibited
TSOP II
Thin Small Outline Package
megahertz
microsecond
millisecond
nanosecond
ohm
ms
ns
pF
picofarad
volt
V
W
watt
All errata for this product are fixed, effective date code 1431 (YY=14, WW=31). For more information, refer to datasheet 001-67786
Rev. *G or contact Cypress Technical Support at http://www.cypress.com/support.
Document #: 001-67786 Rev. *K
Page 40 of 43
CY14B116K/CY14B116M
Document History Page
Document Title: CY14B116K/CY14B116M, 16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with Real Time Clock
Document Number: 001-67786
Submission
Rev.
ECN No.
Description of Change
Date
**
3188189
3457528
03/04/2011
12/13/2011
New datasheet
*A
Datasheet status changed from “Advance” to “Preliminary”
Pin Diagrams: Updated Figure 3 and Figure 3
Table 1: Updated ZZ pin description
Added footnote 7 and 13
I
CC1 parameter spec value changed from 70 mA to 95 mA and 50 mA to 75 mA for 25 ns and 45 ns
access speed respectively.
I
I
I
CC3 parameter spec value changed from 35 mA to 50 mA
CC4 parameter spec value changed from 10 mA to 6 mA
SB parameter spec value changed from 500 uA to 750 uA
Added VCAP value for CY14C116X
Changed VCAP typ value from 27 uF to 22 uF
Added Thermal Resistance values
Added footnote 20 and 32
RTC Characteristics: Updated IBAK and VRTCcap parameter spec values
Changed tHRECALL parameter spec value from 40 ms to 60 ms for CY14C116X and from 20 ms to 30
ms for CY14B116X/CY14E116X.
Changed tWAKE parameter spec value from 40 ms to 60 ms for CY14C116X and from 20 ms to 30 ms
for CY14B116X/CY14E116X.
t
t
RECALL spec value changed from 300 us to 600 us
SS spec value changed from 200 us to 500 us
Updated Ordering Information
Package Diagrams: Updated 165-FBGA package diagram
*B
*C
3514357
3944873
02/07/2012
03/26/2013
No technical updates.
Removed 2.5 V and 5 V operating range voltage support
Removed ×32 configuration support
Added 54 - pin TSOP II package
Added Figure 5 (Sleep Mode (ZZ) Flow Diagram)
Updated Real Time Clock Operation description
Updated Maximum Ratings (Changed “Ambient temperature with power applied” to “Maximum junction
temperature”).
Changed CIN and COUT value from 7 pF to 8 pF
Changed VIH max spec value from VCC + 0.3 V to VCC + 0.5 V
Added VVCAP parameter spec
Added footnote 21
Changed VBAKFAIL spec max value from 2.0 V to 2.2 V
Changed TRTCp max value from 350 µs to 1 ms.
Updated tZZL parameter spec value from 15 ns to 50 ns
Added Figure 18
Added footnote 56
*D
4260504
01/24/2014
Modified Logic Block Diagram for more clarity.
Updated AutoStore Operation (Power-Down):
Removed sentence “The HSB signal is monitored by the system to detect if an AutoStore cycle is in
progress.”
Modified Figure 5 for more clarity.
Added note in Watchdog Timer and Table 7 (Watchdog Timer section) to clarify additional delay at the
start of countdown.
Added PCB Design Considerations for RTC
Added ISB max spec value for 45 ns access speed
Changed VCAP min spec value from 20 F to 19.8 F
Added thermal resistance values for 54-TSOP II package
Added footnote 32
Updated Figure 18 for more clarity
Changed tZZH max spec value from 20 ns to 70 ns.
*E
4366689
05/01/2014
Updated Sleep Mode:
Updated description.
Updated Thermal Resistance values
Added Note 17 and 32.
Added .
Updated in new template.
Document #: 001-67786 Rev. *K
Page 41 of 43
CY14B116K/CY14B116M
Document History Page (continued)
Document Title: CY14B116K/CY14B116M, 16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with Real Time Clock
Document Number: 001-67786
Submission
Rev.
ECN No.
Description of Change
Date
*F
4417851
06/24/2014
DC Electrical Characteristics:
Added R bit set to ‘0’ to ISB test condition
Added footnote 18
Updated maximum value of VVCAP parameter from 4.5 V to 5.0 V
Capacitance:
Updated CIN and COUTvalue from 8 pF to 10 pF for 165-FBGA package
Added CIO parameter.
*G
*H
4432183
4456803
07/07/2014
07/31/2014
DC Electrical Characteristics: Updated maximum value of VCAP parameter from 120.0 F to 82.0 F
Removed Errata section.
Added a note at the end of the document mentioning when the errata items were fixed.
*I
4562106
11/05/2014
Added related documentation hyperlink in page 1.
Updated package diagram 51-85160 to current revision
*J
4616093
6681289
01/07/2015
09/24/2019
Changed datasheet status from Preliminary to Final.
*K
Updated Sales page and Copyright information.
Updated Figure 25 (51-85095 Rev C to D) in Package Diagrams.
Updated Ordering Information:
Removed CY14B116K-ZS45XI and CY14B116K-ZS45XIT part numbers.
Added CY14B116M-BZ45XIT and CY14B116M-ZSP25XIT part numbers.
Document #: 001-67786 Rev. *K
Page 42 of 43
CY14B116K/CY14B116M
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© Cypress Semiconductor Corporation, 2011-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
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the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
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solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
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"Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
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data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document #: 001-67786 Rev. *K
Revised September 24, 2019
Page 43 of 43
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