CY14U256LA-BA35XI [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14U256LA-BA35XI |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 |
| 文件： | 总23页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
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The fact that Infineon offers the following product as part of the Infineon product
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY14U256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32
K × 8) nvSRAM
Features
Functional Description
■ 35 ns access time
The Cypress CY14U256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 K bytes of 8 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
■ Internally organized as 32 K × 8
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power down
■ RECALL to SRAM initiated by software or power up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
For a complete list of related documentation, click here.
■ Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram
V
V
CC
CCQ V
CAP
Quantum Trap
512 X 512
POWER
CONTROL
A5
STORE
A6
A7
A8
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
512 X 512
HSB
A9
A11
A12
A13
A14
SOFTWARE
DETECT
A14
-
A2
DQ0
COLUMN I/O
DQ1
DQ2
DQ3
COLUMN DEC
DQ4
DQ5
DQ6
DQ7
A0
A4
A10
A1
A3
A2
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-86200 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2014
CY14U256LA
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Device Operation ..............................................................4
SRAM Read ................................................................4
SRAM Write .................................................................4
AutoStore Operation ....................................................4
Hardware STORE Operation .......................................4
Hardware RECALL (Power-Up) ..................................5
Software STORE .........................................................5
Software RECALL .......................................................5
Preventing AutoStore ..................................................6
Data Protection ............................................................6
Maximum Ratings .............................................................7
Operating Range ...............................................................7
DC Electrical Characteristics ..........................................7
Data Retention and Endurance .......................................8
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Loads ..................................................................9
AC Test Conditions ..........................................................9
AC Switching Characteristics .......................................10
SRAM Read Cycle ....................................................10
SRAM Write Cycle .....................................................10
Switching Waveforms ....................................................11
AutoStore/Power-up RECALL .......................................13
Switching Waveforms ....................................................14
Software Controlled STORE/RECALL Cycle ................15
Switching Waveforms ....................................................15
Hardware STORE Cycle .................................................16
Switching Waveforms ....................................................16
Truth Table for SRAM Operations .................................17
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Package Diagrams ..........................................................19
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC Solutions .........................................................22
Document Number: 001-86200 Rev. *B
Page 2 of 22
CY14U256LA
Pinout
Figure 1. 48-ball FBGA (6 × 10 × 1.2 mm) pinout
(× 8)
Top View
(not to scale)
1
4
2
3
5
6
A
A
A
2
VCC
OE
NC
NC
NC
0
1
A
B
C
A
A
CE NC
3
4
VCC
A
A
6
DQ0
V
NC DQ4
5
A
V
DQ5
NC
D
E
F
SS DQ1
7
CCQ
V
SS
V
V
SS
VCAP
DQ6
CCQ DQ2
A
V
SS
NC
DQ3
NC DQ7
WE NC
14
A
A
G
H
HSB
NC
NC
13
12
A
A
9
A
A
8
NC
11
10
Pin Definitions
Pin Name
I/O Type
Input
Description
A0–A14
Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ0–DQ7 Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.
WE
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Input
Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
VSS
VCC
Ground
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the core of the device.
VCCQ
Power supply Power supply inputs for the inputs and outputs of the device.
Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each hardware
and software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
HSB
VCAP
NC
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No connect No connect. This pin is not connected to the die.
Document Number: 001-86200 Rev. *B
Page 3 of 22
CY14U256LA
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power up. This pull-up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
Device Operation
The CY14U256LA nvSRAM is made up of two functional
components paired in the same physical cell. They are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14U256LA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the nonvolatile cells and up to 1 million STORE operations.
Refer to the Truth Table for SRAM Operations on page 17 for a
complete description of read and write modes.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
Figure 2. AutoStore Mode
The CY14U256LA performs a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0–14 determines which of the 32,768 data bytes each are
accessed. When the read is initiated by an address transition,
the outputs are valid after a delay of tAA (read cycle 1). If the read
VCCQ
VCC
is initiated by CE or OE, the outputs are valid at tACE or at tDOE
,
0.1 uF
whichever is later (read cycle 2). The data output repeatedly
responds to address changes within the tAA access time without
the need for transitions on any control input pins. This remains
valid until another address change or until CE or OE is brought
HIGH, or WE or HSB is brought LOW.
0.1 uF
VCCQ
VCC
SRAM Write
WE
VCAP
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–7 are
written into the memory if the data is valid tSD before the end of
a WE-controlled write or before the end of a CE-controlled write.
Keep OE HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
VCAP
VSS
Hardware STORE Operation
AutoStore Operation
The CY14U256LA provides the HSB pin to control and
acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14U256LA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
The CY14U256LA stores data to the nvSRAM using one of the
following three storage operations: Hardware STORE activated
by HSB; Software STORE activated by an address sequence;
AutoStore on device power down. The AutoStore operation is a
unique feature of QuantumTrap technology and is enabled by
default on the CY14U256LA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled using the soft sequence specified in Preventing
AutoStore on page 6. If AutoStore is enabled without a capacitor
on VCAP pin, the device attempts an AutoStore operation without
sufficient charge to complete the Store. This corrupts the data
stored in nvSRAM.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14U256LA. But any SRAM read and write cycles
Document Number: 001-86200 Rev. *B
Page 4 of 22
CY14U256LA
are inhibited until HSB is returned HIGH by MPU or other
external source.
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
During any STORE operation, regardless of how it is initiated,
the CY14U256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
6. Read Address 0x0FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-Up)
During power up or after any low-power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14U256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read Address 0x0E38 Valid READ
2. Read Address 0x31C7 Valid READ
3. Read Address 0x03E0 Valid READ
4. Read Address 0x3C1F Valid READ
5. Read Address 0x303F Valid READ
6. Read Address 0x0C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
To initiate the Software STORE cycle, the following read
sequence must be performed:
Table 1. Mode Selection
[1]
A14–A0
Mode
I/O
Power
Standby
Active
CE
WE
OE
H
X
X
X
X
X
Not selected
Read SRAM
Write SRAM
Output High Z
Output data
Input data
L
L
L
H
L
L
X
L
Active
Active [2]
H
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Disable
Notes
1. While there are 15 address lines on the CY14U256LA, only the 13 address lines (A –A ) are used to control software modes. Rest of the address lines are don’t care.
14
2
2. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-86200 Rev. *B
Page 5 of 22
CY14U256LA
Table 1. Mode Selection (continued)
[1]
A14–A0
Mode
I/O
Power
CE
WE
OE
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output data
Output data
Output data
Output data
Output data
Output data
Active[3]
Enable
[3]
L
L
H
H
L
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output data
Output data
Output data
Output data
Output data
Output High Z
Active ICC2
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[3]
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled
and written 0x00 in all cells.
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
Data Protection
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B45 AutoStore Disable
The CY14U256LA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low-voltage condition is detected when
VCC < VSWITCH. If the CY14U256LA is in a write mode (both CE
and WE are LOW) at power up, after a RECALL or STORE, the
write is inhibited until the SRAM is enabled after tLZHSB (HSB to
output active). When VCCQ < VIODIS, I/Os are disabled (no
STORE takes place). This protects against inadvertent writes
during brown out conditions on VCCQ supply.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0B46 AutoStore Enable
Note
3. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-86200 Rev. *B
Page 6 of 22
CY14U256LA
Transient voltage (< 20 ns) on
any pin to ground potential ...............–2.0 V to VCCQ + 2.0 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time:
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current
(1 output at a time, 1s duration) .................................. 15 mA
At 150 C ambient temperature ..................... 1000 h
At 85 C ambient temperature .................... 20 Years
Maximum junction temperature ................................. 150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Supply voltage on VCCQ relative to VSS ......–0.5 V to 2.45 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch up current .................................................... > 140 mA
Operating Range
Voltage applied to outputs
in High Z State ..................................–0.5 V to VCCQ + 0.5 V
Ambient
Range
VCC
VCCQ
Input voltage .....................................–0.5 V to VCCQ + 0.5 V
Temperature
Industrial –40 C to +85 C 2.7 V to 3.6 V 1.65 V to 1.95 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
VCCQ
ICC1
Description
Test Conditions
Min
2.7
1.65
–
Typ [4]
3.0
1.8
–
Max
3.6
1.95
60
Unit
V
Power supply voltage
V
Average VCC current
Average VCCQ current
tRC = 35 ns
Values obtained without output
loads (IOUT = 0 mA)
mA
mA
ICCQ1
–
–
20
ICC2
ICC3
ICCQ3
ICC4
ISB
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
–
–
–
–
35
5
10
–
mA
mA
mA
mA
mA
Average VCC current at
All inputs cycling at CMOS levels.
Values obtained without output
loads (IOUT = 0 mA)
t
RC = 200 ns, VCC(Typ), 25 °C
Average VCCQ current at
RC = 200 ns, VCCQ(Typ), 25 °C
–
t
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average
current for duration tSTORE
–
8
VCC standby current
CE > (VCCQ – 0.2 V).
–
8
VIN < 0.2 V or > (VCCQ – 0.2 V).
Standby current level after
nonvolatile cycle is complete. Inputs
are static. f = 0 MHz
[5]
IIX
Input leakage current
(except HSB)
VCCQ = Max, VSS < VIN < VCCQ
–1
–
–
+1
+1
µA
µA
Input leakage current (for HSB) VCCQ = Max, VSS < VIN < VCCQ
–100
Notes
4. Typical values are at 25 °C, V = V
and V
= V
. Not 100% tested.
CCQ(Typ)
CC
CC(Typ)
CCQ
5. The HSB pin has I
= –4 µA for V of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
Document Number: 001-86200 Rev. *B
Page 7 of 22
CY14U256LA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
IOZ
Description
Test Conditions
Min
Typ [4]
Max
Unit
Off-state output leakage current VCCQ = Max, VSS < VOUT < VCCQ
,
–1
–
+1
µA
CE or OE > VIH or WE < VIL
VIH
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
Storage capacitor
–
0.7 × VCCQ
–
–
VCCQ + 0.3
0.3 × VCCQ
–
V
V
VIL
–
– 0.3
VOH
VOL
VCAP
IOUT = –1 mA
VCCQ – 0.45
–
V
IOUT = 2 mA
–
120
–
–
0.45
V
[6]
[7, 8]
Between VCAP pin and VSS
150
–
180
µF
V
VVCAP
Maximum voltage driven on VCAP VCC = Max
pin by the device
VCC
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data retention
Nonvolatile STORE operations
1,000
Capacitance
Parameter [8]
Description
Test Conditions
Max
Unit
pF
CIN
Input capacitance (except HSB) TA = 25 C, f = 1 MHz, VCC = VCC(Typ), VCCQ = VCCQ(Typ)
Input capacitance (for HSB)
7
8
7
8
pF
COUT
Output capacitance (except HSB)
pF
Output capacitance (for HSB)
pF
Thermal Resistance
Parameter [8]
Description
Test Conditions
48-ball FBGA Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
48.19
C/W
JC
Thermal resistance
(junction to case)
6.5
C/W
Notes
6. Min V
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor on
CAP
CAP
V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
CAP
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V
options.
CAP
7. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-86200 Rev. *B
Page 8 of 22
CY14U256LA
AC Test Loads
Figure 3. AC Test Loads
450
for tri-state specs
450
1.8 V
1.8 V
R1
R1
OUTPUT
OUTPUT
R2
450
R2
450
5 pF
30 pF
AC Test Conditions
Input pulse levels ................................................0 V to 1.8 V
Input rise and fall times (10% to 90%) ..................... < 1.8 ns
Input and output timing reference levels ....................... 0.9V
Document Number: 001-86200 Rev. *B
Page 9 of 22
CY14U256LA
AC Switching Characteristics
Over the Operating Range
Parameters [9]
35 ns
Description
Unit
Cypress
Parameters
Alt
Min
Max
Parameters
SRAM Read Cycle
tACE tACS
Chip enable access time
Read cycle time
–
35
–
ns
ns
[10]
tRC
tAA
tOE
tOH
tLZ
35
tRC
[11]
Address access time
–
–
3
3
–
0
–
0
–
35
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Output enable to data valid
tDOE
[11]
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
tOHA
[12, 13]
–
tLZCE
tHZCE
tLZOE
[12, 13]
[12, 13]
[12, 13]
tHZ
tOLZ
tOHZ
tPA
13
–
13
–
tHZOE
[12]
tPU
[12]
tPS
35
tPD
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tWC
tWP
tCW
tDW
tDH
tAW
tAS
Write cycle time
35
25
25
12
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
–
–
tHD
–
tAW
tSA
25
0
–
–
tHA
tWR
0
–
[12, 13, 14]
tWZ
–
13
tHZWE
[12, 13]
tOW
Output active after end of write
3
–
ns
tLZWE
Notes
9. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the specified
CC Q(typ)
CCQ
I
/I and load capacitance shown in Figure 3 on page 9.
OL OH
10. WE must be HIGH during SRAM read cycles.
11. Device is continuously selected with CE and OE LOW.
12. These parameters are guaranteed by design and are not tested.
13. Measured ±200 mV from steady state output voltage.
14. If WE is low when CE goes low, the outputs remain in the high-impedance state.
Document Number: 001-86200 Rev. *B
Page 10 of 22
CY14U256LA
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [15, 16, 17]
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [15, 17]
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tLZOE
High Impedance
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Standby
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE and OE LOW.
17. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-86200 Rev. *B
Page 11 of 22
CY14U256LA
Switching Waveforms (continued)
Figure 6. SRAM Write Cycle #1 (WE Controlled) [18, 19, 20]
tWC
Address
CE
Address Valid
tSCE
tHA
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Figure 7. SRAM Write Cycle #2 (CE Controlled) [18, 19, 20]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Notes
18. HSB must remain HIGH during READ and WRITE cycles.
19. If WE is low when CE goes low, the outputs remain in the high impedance state.
20. CE or WE must be > V during address transitions.
IH
Document Number: 001-86200 Rev. *B
Page 12 of 22
CY14U256LA
AutoStore/Power-up RECALL
Over the Operating Range
CY14U256LA
Parameter
Description
Unit
Min
Max
[21]
Power-up RECALL duration
STORE cycle duration
–
20
ms
ms
ns
tHRECALL
[22]
–
–
8
tSTORE
[23]
Time allowed to complete SRAM write cycle
25
tDELAY
VSWITCH
Low voltage trigger level for VCC
I/O disable voltage on VCCQ
VCC rise time
–
–
2.65
1.50
–
V
V
[24]
VIODIS
[25]
150
µs
tVCCRISE
[25]
[25]
HSB output disable voltage on VCC
HSB to output active time
HSB high active time
–
–
–
1.9
5
V
VHDIS
µs
ns
tLZHSB
[25]
500
tHHHD
Notes
21. t
starts from the time V rises above V
.
HRECALL
CC
SWITCH
22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
23. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
.
DELAY
24. HSB is not defined below V
voltage.
IODIS
25. These parameters are guaranteed by design and are not tested.
Document Number: 001-86200 Rev. *B
Page 13 of 22
CY14U256LA
Switching Waveforms
Figure 8. AutoStore or Power-up RECALL [26]
VCC
VSWITCH
VHDIS
VCCQ
V
IODIS
22
Note
22
tVCCRISE
tSTORE
Note
tSTORE
27
tHHHD
tHHHD
Note
27
HSB OUT
VCCQ
Note
tDELAY
tLZHSB
tLZHSB
AutoStore
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(
RWI)
Read & Write
Read
&
Write
POWER-UP
RECALL
POWER
DOWN
POWER-UP
RECALL
Read
&
VCC
Write AutoStore
VCCQ
BROWN
OUT
AutoStore
BROWN
OUT
I/O Disable
Notes
26. Read and write cycles are ignored during STORE, RECALL, and while V is below V
.
SWITCH
CC
27. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-86200 Rev. *B
Page 14 of 22
CY14U256LA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
35 ns
Unit
Parameter [28, 29]
Description
Min
Max
tRC
STORE/RECALL initiation cycle time
Address setup time
35
–
–
ns
ns
ns
ns
µs
tSA
0
20
0
tCW
Clock pulse width
–
tHA
Address hold time
–
tRECALL
RECALL duration
–
200
Switching Waveforms
Figure 9. CE and OE Controlled Software STORE/RECALL Cycle [29]
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
30
Note
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 10. AutoStore Enable / Disable Cycle [29]
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
30
Note
tLZCE
tDELAY
DQ (DATA)
RWI
Notes
28. The software sequence is clocked with CE controlled or OE controlled reads.
29. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
30. DQ output data at the sixth read may be invalid since the output is disabled at t
time.
DELAY
Document Number: 001-86200 Rev. *B
Page 15 of 22
CY14U256LA
Hardware STORE Cycle
Over the Operating Range
CY14U256LA
Parameters
Description
Unit
Min
–
Max
25
tDHSB
tPHSB
HSB to output active time when write latch not set
Hardware STORE pulse width
ns
ns
s
15
–
–
[31, 32]
tSS
Soft sequence processing time
100
Switching Waveforms
Figure 11. Hardware STORE Cycle [33]
Write Latch set
t
PHSB
HSB (IN)
t
STORE
t
t
HHHD
DELAY
HSB (OUT)
SO
t
LZHSB
RWI
Write Latch not set
t
PHSB
HSB (IN)
HSB pin is driven high to V
only by Internal
CCQ
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
HSB (OUT)
RWI
t
t
t
DELAY
DHSB
DHSB
Figure 12. Soft Sequence Processing [31, 32]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
31. This is the amount of time it takes to take action on a soft sequence command. V and V
power must remain HIGH to effectively register command.
CCQ
CC
32. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
33. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-86200 Rev. *B
Page 16 of 22
CY14U256LA
Truth Table for SRAM Operations
HSB must remain HIGH for SRAM operations.
CE
H
L
WE
X
OE
X
Inputs/Outputs
Mode
Deselect / Power-down
Read
Power
High Z
Standby
Active
Active
Active
H
L
Data out (DQ0–DQ7)
High Z
L
H
H
Output disabled
Write
L
L
X
Data in (DQ0–DQ7)
Document Number: 001-86200 Rev. *B
Page 17 of 22
CY14U256LA
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
35
CY14U256LA-BA35XIT
CY14U256LA-BA35XI
51-85128 48-ball FBGA
Industrial
All parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 U 256 L A - BA 35 X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
Speed:
35 - 35 ns
Package:
BA - 48-ball FBGA
Die revision:
Blank - No Rev
A - 1st Rev
Data Bus:
L - × 8
Density:
256 - 256 Kb
Voltage:
U - 3.0 V VCC, 1.8 V VCCQ
14 - nvSRAM
Cypress
Document Number: 001-86200 Rev. *B
Page 18 of 22
CY14U256LA
Package Diagrams
Figure 13. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B Package Outline, 51-85128
51-85128 *F
Document Number: 001-86200 Rev. *B
Page 19 of 22
CY14U256LA
Acronyms
Document Conventions
Units of Measure
Acronym
Description
Chip Enable
CE
Symbol
°C
Unit of Measure
CMOS
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Hardware Store Busy
degree Celsius
kilohm
EIA
k
MHz
A
F
s
FBGA
megahertz
microampere
microfarad
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
HSB
I/O
Input/Output
nvSRAM
Nonvolatile Static Random Access Memory
Output Enable
OE
SRAM
mA
mm
ms
ns
Static Random Access Memory
Restriction of Hazardous Substances
Read and Write Inhibited
Write Enable
RoHS
RWI
WE
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-86200 Rev. *B
Page 20 of 22
CY14U256LA
Document History Page
Document Title: CY14U256LA, 256-Kbit (32 K × 8) nvSRAM
Document Number: 001-86200
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
3918324
4024815
GVCH
GVCH
03/01/2013 New data sheet.
*A
06/10/2013 Changed status from “Summary” to “Final”.
Updated Maximum Ratings:
Removed “Ambient temperature with power applied” and added “Maximum
junction temperature”.
*B
4568158
GVCH
11/13/2014 Added related documentation hyperlink in page 1.
Document Number: 001-86200 Rev. *B
Page 21 of 22
CY14U256LA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-86200 Rev. *B
Revised November 13, 2014
Page 22 of 22
All products and company names mentioned in this document may be the trademarks of their respective holders.
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