CY14V104LA-BA25XI [INFINEON]
nvSRAM (non-volatile SRAM);
| 型号： | CY14V104LA-BA25XI |
| 厂家： | 
Infineon |
| 描述： | nvSRAM (non-volatile SRAM) 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY14V104LA
CY14V104NA
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
4-Mbit (512
K × 8 / 256 K × 16) nvSRAM
Features
Functional Description
■ 25 ns and 45 ns access times
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
■ Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16
(CY14V104NA)
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1-million STORE cycles to QuantumTrap
■ 20 year data retention
For a complete list of related documentation, click here.
■ Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram [1, 2, 3]
VCAP
VCC
V
CCQ
Quatrum Trap
2048 X 2048
A0
A1
A2
A3
A4
A5
A6
POWER
R
O
W
CONTROL
STORE
RECALL
STORE/RECALL
CONTROL
D
E
C
O
D
E
R
HSB
STATIC RAM
ARRAY
2048 X 2048
A7
A8
A17
SOFTWARE
DETECT
A14 - A2
A18
DQ0
DQ1
DQ2
DQ3
I
DQ4
DQ5
DQ6
N
P
U
T
B
U
F
F
E
R
S
DQ7
COLUMN I/O
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A9 A10 A11 A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.
0
18
0
17
2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document Number: 001-53954 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 5, 2014
CY14V104LA
CY14V104NA
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
Device Operation ..............................................................4
SRAM Read ................................................................4
SRAM Write .................................................................4
AutoStore Operation ....................................................4
Hardware STORE Operation .......................................4
Hardware RECALL (Power-Up) ..................................5
Software STORE .........................................................5
Software RECALL .......................................................5
Preventing AutoStore ..................................................6
Data Protection ............................................................6
Maximum Ratings .............................................................7
Operating Range ...............................................................7
DC Electrical Characteristics ..........................................7
Data Retention and Endurance .......................................8
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Loads ..................................................................9
AC Test Conditions ..........................................................9
AC Switching Characteristics .......................................10
Switching Waveforms ....................................................11
AutoStore/Power-Up RECALL .......................................14
Switching Waveforms ....................................................14
Software Controlled STORE/RECALL Cycle ................15
Switching Waveforms ....................................................15
Hardware STORE Cycle .................................................16
Switching Waveforms ....................................................16
Truth Table For SRAM Operations ................................17
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Package Diagrams ..........................................................19
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................23
Worldwide Sales and Design Support .......................23
Products ....................................................................23
PSoC® Solutions ......................................................23
Cypress Developer Community .................................23
Technical Support .....................................................23
Document Number: 001-53954 Rev. *H
Page 2 of 23
CY14V104LA
CY14V104NA
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
(× 8)
Top View
(not to scale)
(× 16)
Top View
(not to scale)
1
2
4
3
5
6
1
2
OE
NC
NC
4
3
5
6
A
A
A
2
OE
VCC
BLE
DQ8
A
A
A
0
1
A
B
C
VCC
NC
NC
0
1
2
A
B
C
A
A
4
BHE
DQ10
DQ11
CE DQ0
DQ1 DQ2
V
A
A
3
CE NC
NC DQ4
3
4
A
A
6
DQ9
A
A
6
DQ0
V
5
5
A
V
A17
A
DQ3
DQ4
DQ5
CCQ
D
E
F
SS
7
A17
DQ5 VCCQ
D
E
F
SS DQ1
7
A
V
SS
V
A
VCAP
V
V
SS
CCQ DQ12
16
VCAP
DQ6
NC
CCQ DQ2
16
A
A
15
DQ13
HSB
DQ14
DQ15
DQ6
A
A
15
NC
DQ3
NC
A18
DQ7
14
14
A
A
13
G
H
A
A
WE DQ7
A
G
H
HSB
WE NC
[4]
12
13
12
[4]
A
A
9
A
A
8
A
9
A
NC
A
8
10
NC
11
10
11
NC
Pin Definitions
Pin Name
A0–A18 Input
A0–A17
I/O Type
Description
Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for × 8 Configuration.
Address Inputs Used to Select One of the 262,144 words of the nvSRAM for × 16 Configuration.
DQ0–DQ7 Input/output Bidirectional Data I/O Lines for × 8 Configuration. Used as input or output lines depending on operation.
DQ0–DQ15
WE
Bidirectional Data I/O Lines for × 16 Configuration. Used as input or output lines depending on operation.
Input
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BHE
Input
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
BLE
VSS
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power supply Power Supply Inputs to the Core of the Device.
VCCQ
Power supply Power Supply Inputs for the Inputs and Outputs of the Device.
Input/output Hardware Store Busy (HSB).
HSB
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
NC
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
No Connect No Connect. This pin is not connected to the die.
Note
4. Address expansion for 8-Mbit. NC pin not connected to die.
Document Number: 001-53954 Rev. *H
Page 3 of 23
CY14V104LA
CY14V104NA
on VCAP pin, the device attempts an AutoStore operation without
sufficient charge to complete the Store. This may corrupt the data
stored in nvSRAM.
Device Operation
The CY14V104LA/CY14V104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a non-volatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14V104LA/CY14V104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 17
for a complete description of read and write modes.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place.
SRAM Read
The CY14V104LA/CY14V104NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–18 or A0–17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
Figure 2. AutoStore Mode
VCCQ
VCC
0.1 uF
0.1 uF
VCCQ
VCC
WE
VCAP
VCAP
VSS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. It is recommended that
OE be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
Hardware STORE Operation
The CY14V104LA/CY14V104NA provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14V104LA/CY14V104NA conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
AutoStore Operation
The CY14V104LA/CY14V104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
Store activated by HSB; Software Store activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14V104LA/CY14V104NA.
Note After each Hardware and Software STORE operation
HSB is driven HIGH for a short time (tHHHD) with standard output
high current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14V104LA/CY14V104NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If a capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. If AutoStore is enabled without a capacitor
During any STORE operation, regardless of how it is initiated,
the CY14V104LA/CY14V104NA continues to drive the HSB pin
Document Number: 001-53954 Rev. *H
Page 4 of 23
CY14V104LA
CY14V104NA
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14V104LA/CY14V104NA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software RECALL
Software STORE
Data is transferred from non-volatile memory to the SRAM by a
software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
Data is transferred from SRAM to the non-volatile memory by a
software address sequence. The CY14V104LA/CY14V104NA
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
Table 1. Mode Selection
[6]
A15–A0
Mode
I/O
Power
Standby
Active
CE
WE
OE
BHE, BLE[5]
H
X
X
X
X
X
X
Not Selected Output High Z
L
L
L
H
L
L
X
L
L
L
X
Read SRAM
Write SRAM
Output Data
Input Data
Active
Active[7]
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Disable
Notes
5. BHE and BLE are applicable for × 16 configuration only.
6. While there are 19 address lines on the CY14V104LA (18 address lines on the CY14V104NA), only the 13 address lines (A –A ) are used to control software
14
2
modes. Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document Number: 001-53954 Rev. *H
Page 5 of 23
CY14V104LA
CY14V104NA
Table 1. Mode Selection (continued)
[6]
BHE, BLE[5]
A15–A0
Mode
I/O
Power
CE
WE
OE
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[8]
Active ICC2
Active[8]
Enable
[8]
L
L
H
H
L
L
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Non-volatile Output High Z
Store
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile Output High Z
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled and
0x00 written in all cells.
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
Data Protection
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The CY14V104LA/CY14V104NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC
<
VSWITCH
.
If
the
CY14V104LA/CY14V104NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). When VCCQ < VIODIS, I/Os are disabled (no STORE
takes place). This protects against inadvertent writes during
brown out conditions on VCCQ supply.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Note
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document Number: 001-53954 Rev. *H
Page 6 of 23
CY14V104LA
CY14V104NA
Transient voltage (< 20 ns) on
any pin to ground potential ...............–2.0 V to VCCQ + 2.0 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature ..................... 20 Years
Maximum junction temperature ................................. 150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Supply voltage on VCCQ relative to VSS ......–0.5 V to 2.45 V
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch up current..................................................... > 140 mA
Operating Range
Voltage applied to outputs
Range Ambient Temperature
VCC
VCCQ
in High Z state ..................................–0.5 V to VCCQ + 0.5 V
Industrial
–40 C to +85 C
3.0 V – 3.6 V 1.65 V – 1.95 V
Input voltage .....................................–0.5 V to VCCQ + 0.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Test Conditions
Min
3.0
1.65
–
Typ [9]
Max
3.6
1.95
70
Unit
V
Power supply voltage
–
3.3
1.8
–
VCCQ
V
ICC1
Average VCC current
Average VCCQ current
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
mA
mA
mA
mA
mA
–
–
52
ICCQ1
–
–
–
–
15
–
10
ICC2
ICC3
ICCQ3
ICC4
ISB
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
10
Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
–
–
–
–
35
5
–
–
8
8
mA
mA
mA
mA
Average VCCQ current at
RC= 200 ns, VCCQ(Typ), 25 °C
t
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current for
duration tSTORE
–
VCC standby current
CE > (VCC – 0.2 V).
–
VIN < 0.2 V or > (VCC – 0.2 V). Standby
current level after non-volatile cycle is
complete. Inputs are static. f = 0 MHz.
[10]
IIX
Input leakage current
(except HSB)
VCCQ = Max, VSS < VIN < VCCQ
–1
–
+1
A
Input leakage current (for HSB) VCCQ = Max, VSS < VIN < VCCQ
VCCQ = Max, VSS < VOUT < VCCQ
Off-state output leakage current CE or OE > VIH or BHE/BLE > VIH or WE
–100
–1
–
–
+1
+1
A
A
IOZ
,
< VIL
[11]
VCAP
Storage capacitor
Between VCAP pin and VSS
61
–
68
–
180
VCC
F
V
[9, 12]
VVCAP
Maximum voltage driven on VCAP VCC = Max
pin by the device
Notes
9. Typical values are at 25 °C, V = V
and V
= V
. Not 100% tested.
CC
CC(Typ)
CCQ
CCQ(Typ)
10. The HSB pin has I
= -4 µA for V of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
11. Min V value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor
CAP
CAP
on V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore
CAP
it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V
options.
CAP
12. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
Document Number: 001-53954 Rev. *H
Page 7 of 23
CY14V104LA
CY14V104NA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
VIH
Description
Input HIGH voltage
Test Conditions
Min
0.7 × VCCQ
– 0.3
Typ [9]
Max
VCCQ + 0.3
0.3 × VCCQ
–
Unit
V
–
–
–
–
–
VIL
Input LOW voltage
V
VOH
Output HIGH voltage
IOUT = –1 mA
VCCQ
0.45
–
V
VOL
Output LOW voltage
IOUT = 2 mA
–
0.45
V
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data retention
Non-volatile STORE operation
1,000
Capacitance
Parameter[13]
Description
Test Conditions
Max
Unit
CIN
Input capacitance (except BLE, TA = 25 C, f = 1 MHz, VCC = VCC (Typ), VCCQ = VCCQ (Typ)
BHE and HSB)
7
pF
Input capacitance (for BLE, BHE
and HSB)
8
pF
COUT
Output capacitance (except HSB)
Output capacitance (for HSB)
7
8
pF
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter[13]
Description
Thermal resistance
(junction to ambient)
Test Conditions
48-ball FBGA Unit
JA
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, in accordance
with EIA/JESD51.
46.09
C/W
JC
Thermal resistance
(junction to case)
7.84
C/W
Note
13. These parameters are guaranteed by design but not tested.
Document Number: 001-53954 Rev. *H
Page 8 of 23
CY14V104LA
CY14V104NA
AC Test Loads
Figure 3. AC Test Loads
450
for tri-state specs
450
1.8 V
1.8 V
R1
R1
Output
Output
R2
450
R2
450
5 pF
30 pF
AC Test Conditions
Input pulse levels ................................................0 V to 1.8 V
Input rise and fall times (10%–90%) ......................... <1.8 ns
Input and output timing reference levels ....................... 0.9 V
Document Number: 001-53954 Rev. *H
Page 9 of 23
CY14V104LA
CY14V104NA
AC Switching Characteristics
Over the Operating Range
Parameters [14]
25 ns
45 ns
Description
Unit
Max
Cypress
Alt Parameter
Parameter
Min
Max
Min
SRAM Read Cycle
tACE
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
–
Chip enable access time
–
25
–
25
–
–
45
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[15]
tRC
Read cycle time
[16]
tAA
Address access time
25
12
–
45
20
–
tDOE
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
–
–
[16]
tOHA
3
3
[17, 18]
tLZCE
tHZCE
tLZOE
3
–
3
–
[17, 18]
[17, 18]
[17, 18]
–
10
–
–
15
–
0
0
tHZOE
–
10
–
–
15
–
[17]
tPU
0
0
[17]
tPD
–
25
12
–
–
45
20
–
tDBE
–
–
[17]
tLZBE
–
Byte enable to output active
Byte disable to output inactive
0
0
[17]
tHZBE
–
–
10
–
15
SRAM Write Cycle
tWC
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
–
Write cycle time
25
20
20
10
0
–
–
45
30
30
15
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWE
tSCE
tSD
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
–
–
–
–
tHD
–
–
tAW
20
0
–
30
0
–
tSA
–
–
tHA
0
–
0
–
[17, 18, 19]
tHZWE
–
10
–
–
15
–
[17, 18]
tLZWE
tBW
3
3
20
–
30
–
Notes
14. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the specified
CC Q(typ)
CCQ
I
/I and load capacitance shown in Figure 3 on page 9.
OL OH
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE, OE and BHE / BLE LOW.
17. These parameters are guaranteed by design but not tested.
18. Measured ±200 mV from steady state output voltage.
19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
20. HSB must remain HIGH during read and write cycles.
Document Number: 001-53954 Rev. *H
Page 10 of 23
CY14V104LA
CY14V104NA
Switching Waveforms
Address
Figure 4. SRAM Read Cycle #1 (Address Controlled) [21, 22, 23]
tRC
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [21, 23, 24]
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Data Output
Output Data Valid
tPU
tPD
Active
ICC
Standby
‘
Notes
21. WE must be HIGH during SRAM read cycles.
22. Device is continuously selected with CE, OE and BHE / BLE LOW.
23. HSB must remain HIGH during read and write cycles.
24. Typical values are at 25 °C, V = V
and V
= V
. Not 100% tested.
CC
CC(Typ)
CCQ
CCQ(Typ)
Document Number: 001-53954 Rev. *H
Page 11 of 23
CY14V104LA
CY14V104NA
Switching Waveforms (continued)
Figure 6. SRAM Write Cycle #1 (WE Controlled) [25, 26, 27, 28]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Figure 7. SRAM Write Cycle #2 (CE Controlled) [25, 26, 27, 28]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Notes
25. HSB must remain HIGH during read and write cycles.
26. BHE and BLE are applicable for x16 configuration only.
27. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
28. CE or WE must be >V during address transitions.
IH
Document Number: 001-53954 Rev. *H
Page 12 of 23
CY14V104LA
CY14V104NA
Switching Waveforms (continued)
Figure 8. SRAM Write Cycle #3 (BHE and BLE Controlled) [29, 30, 31, 32]
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Notes
29. HSB must remain HIGH during read and write cycles.
30. BHE and BLE are applicable for × 16 configuration only.
31. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
32. CE or WE must be >V during address transitions.
IH
Document Number: 001-53954 Rev. *H
Page 13 of 23
CY14V104LA
CY14V104NA
AutoStore/Power-Up RECALL
Over the Operating Range
CY14V104LA/CY14V104NA
Parameter
Description
Unit
Min
–
Max
20
[33]
tHRECALL
Power-Up RECALL duration
STORE cycle duration
ms
ms
ns
V
[34]
tSTORE
–
8
[35]
tDELAY
VSWITCH
Time allowed to complete SRAM write cycle
Low voltage trigger level for VCC
I/O disable voltage on VCCQ
VCC rise time
–
25
–
2.90
1.50
–
[36]
VIODIS
–
V
[39]
tVCCRISE
150
–
s
V
[39]
VHDIS
HSB output disable voltage on VCC
HSB to output active time
1.9
5
[39]
tLZHSB
–
s
ns
[39]
tHHHD
HSB high active time
–
500
Switching Waveforms
Figure 9. AutoStore or Power-Up RECALL [37]
VCC
VSWITCH
VHDIS
VCCQ
V
IODIS
35
35
tVCCRISE
tSTORE
Note
tSTORE
38
Note
tHHHD
tHHHD
Note
38
HSB OUT
VCCQ
Note
tDELAY
tLZHSB
tLZHSB
AutoStore
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(
RWI)
Read & Write
Read
&
Write
POWER-UP
RECALL
POWER
DOWN
POWER-UP
RECALL
Read
&
VCC
Write AutoStore
VCCQ
BROWN
OUT
AutoStore
BROWN
OUT
I/O Disable
Notes
33. t
starts from the time V rises above V .
SWITCH
HRECALL
CC
34. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware Store takes place.
35. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time t
.
DELAY
36. HSB will not be defined below V
voltage.
IODIS
37. Read and write cycles are ignored during STORE, RECALL, and while V is below V
.
SWITCH
CC
38. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
39. These parameters are guaranteed by design but not tested.
Document Number: 001-53954 Rev. *H
Page 14 of 23
CY14V104LA
CY14V104NA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
25 ns
45 ns
Unit
Parameters [40, 41]
Description
Min
25
0
Max
–
Min
45
0
Max
tRC
STORE/RECALL initiation cycle time
Address setup time
–
–
ns
ns
ns
ns
s
tSA
–
tCW
Clock pulse width
20
0
–
30
0
–
tHA
Address hold time
–
–
tRECALL
RECALL duration
–
200
–
200
Switching Waveforms
Figure 10. CE and OE Controlled Software STORE/RECALL Cycle [41]
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
42
Note
tDELAY
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 11. AutoStore Enable/Disable Cycle
tRC
Address #1
tCW
tRC
Address
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
42
Note
tLZCE
tDELAY
DQ (DATA)
Notes
40. The software sequence is clocked with CE controlled or OE controlled reads.
41. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
42. DQ output data at the sixth read may be invalid since the output is disabled at t
time.
DELAY
Document Number: 001-53954 Rev. *H
Page 15 of 23
CY14V104LA
CY14V104NA
Hardware STORE Cycle
Over the Operating Range
CY14V104LA/CY14V104NA
Parameters
Description
Unit
Min
–
Max
25
tDHSB
tPHSB
HSB to output active time when write latch not set
Hardware STORE pulse width
ns
ns
s
15
–
–
[43, 44]
tSS
Soft sequence processing time
100
Switching Waveforms
Figure 12. Hardware STORE Cycle [45]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
CC only by Internal
HSB pin is driven HIGH to V
100 kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 13. Soft Sequence Processing [43, 44]
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
43. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
44. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
45. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware Store takes place.
Document Number: 001-53954 Rev. *H
Page 16 of 23
CY14V104LA
CY14V104NA
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 2. Truth Table for × 8 Configuration
CE
H
L
WE
X
OE
X
Inputs/Outputs[46]
Mode
Deselect/Power-down
Read
Power
High Z
Standby
H
L
Data out (DQ0–DQ7)
High Z
Active
Active
Active
L
H
H
Output disabled
Write
L
L
X
Data in (DQ0–DQ7)
Table 3. Truth Table for × 16 Configuration
CE
H
L
WE
X
OE
X
BHE[47] BLE[47]
Inputs/Outputs[46]
High Z
Mode
Power
X
H
L
X
H
L
Deselect/Power-down
Output disabled
Read
Standby
Active
Active
Active
X
X
High Z
L
H
L
Data out (DQ0–DQ15)
L
H
L
H
L
Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
L
H
L
L
H
Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active
Active
Active
Active
Active
L
Data in (DQ0–DQ15)
L
H
Data in (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
L
L
X
L
H
Data in (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Notes
46. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.
0
7
0
15
47. BHE and BLE are applicable for × 16 configuration only.
Document Number: 001-53954 Rev. *H
Page 17 of 23
CY14V104LA
CY14V104NA
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
Package Type
Operating Range
25
CY14V104LA-BA25XIT
CY14V104LA-BA25XI
CY14V104NA-BA25XIT
CY14V104NA-BA25XI
CY14V104LA-BA45XIT
CY14V104LA-BA45XI
CY14V104NA-BA45XIT
CY14V104NA-BA45XI
51-85128 48-ball FBGA
Industrial
45
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 V 104 L A - BA 25 X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Speed:
25 - 25 ns
X - Pb-free
45 - 45 ns
Package:
BA - 48-ball FBGA
Die Revision:
Blank - No Rev
A - 1st Rev
Data Bus:
L - × 8
N - × 16
Density:
104 - 4 Mb
Voltage:
V - 3.3 V VCC, 1.8 V VCCQ
14 - NVSRAM
Cypress
Document Number: 001-53954 Rev. *H
Page 18 of 23
CY14V104LA
CY14V104NA
Package Diagrams
Figure 14. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B, 51-85128
51-85128 *F
Document Number: 001-53954 Rev. *H
Page 19 of 23
CY14V104LA
CY14V104NA
Acronyms
Document Conventions
Units of Measure
Acronym
Description
Byte High Enable
BHE
BLE
Symbol
°C
Unit of Measure
Byte Low Enable
Chip Enable
degree Celsius
kilo ohms
CE
k
MHz
A
mA
F
s
ms
ns
CMOS
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Hardware Store Busy
Mega Hertz
micro Amperes
milli Amperes
micro Farads
micro seconds
milli seconds
nano seconds
ohms
EIA
FBGA
HSB
I/O
Input/Output
nvSRAM
non-volatile Static Random Access Memory
Output Enable
OE
RoHS
Restriction of Hazardous Substances
Static Random Access Memory
Write Enable
SRAM
WE
%
percent
pF
V
pico Farads
Volts
W
Watts
Document Number: 001-53954 Rev. *H
Page 20 of 23
CY14V104LA
CY14V104NA
Document History Page
Document Title: CY14V104LA/CY14V104NA, 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Document Number: 001-53954
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
2729117
GVCH /
AESA
07/02/2009 New data sheet.
*A
2826127
GVCH /
AESA
12/11/2009 Removed commercial temperature related specs
Changed part number from CY14A104L/CY14A104N to
CY14V104LA/CY14V104NA
Removed 20 ns Access speed specs
Removed 44/54 TSOP II package related information
Updated STORE cycles to QuantumTrap from 200K to 1 million
Figure 3: Updated Autostore Mode
Page 4: Updated Hardware STORE (HSB) Operation description
Page 5: Updated Software STORE Operation description
Maximum Ratings: Supply Voltage on VCCQ Relative to GND from –0.5V to
2.5V to –0.5V to 2.45V
Added ICCQ1 and ICCQ3 for VCCQ operation
Updated ICC4 test condition
Updated footnote 8
Updated VIH/VIL as 70%/30% of VCCQ
Updated VOH test condition.
Updated Input Rise and Fall Times (10% - 90%) from 3ns to 1.8 ns
Updated footnote 19, 22 and added footnote 20, 25
Updated VIODIS parameter value from 1.6V to 1.5V
Updated Figure 10, 11 and 12
*B
*C
2858300
2951754
GVCH
01/19/2010 Changed latch up current from 200 mA to 140 mA.
Changed status from Advance to Preliminary.
Added Contents.
GVCH /
AESA
06/14/2010 Pin Definitions: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Table 1: Added more clarity on status of BHE/BLE pin operation
Updated HSB pin operation in Figure 9
Updated footnote 22
*D
3115647
GVCH
12/20/2010 Change datasheet status from “Preliminary” to “Final”
48 FBGA package: 16 Mb address expansion is not supported
Changed ISB and ICC4 value from 5 mA to 8 mA
Changed ICCQ1 value from 25 mA to 15 mA for 25 ns access speed and
15 mA to 10 mA for 45 ns access speed.
Added Acronyms and Units of Measure table
*E
*F
3150253
3303659
GVCH
GVCH
01/21/11
Updated input capacitance for BHE and BLE pin
07/06/2011 Updated DC Electrical Characteristics (Added Note 11 and referred the same
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 14 and referred the same
note in Parameters).
Updated Thermal Resistance (Values of JA for 48-ball FBGA package).
Updated Package Diagrams.
Document Number: 001-53954 Rev. *H
Page 21 of 23
CY14V104LA
CY14V104NA
Document History Page (continued)
Document Title: CY14V104LA/CY14V104NA, 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Document Number: 001-53954
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*G
4075544
GVCH
07/24/2013 Updated Pin Definitions:
Updated description of HSB pin (Added more clarity).
Updated Device Operation:
Updated AutoStore Operation (Removed sentence “The HSB signal is
monitored by the system to detect if an AutoStore cycle is in progress.”).
Removed Best Practices.
Updated Maximum Ratings:
Removed “Ambient temperature with power applied” and included “Maximum
junction temperature”.
Updated DC Electrical Characteristics:
Added VVCAP parameter and its details.
Referred Note 9 in VVCAP parameter, added Note 12 and referred the same
note in VVCAP parameter.
Updated in new template.
Completing Sunset Review.
*H
4557366
GVCH
11/05/2014 Added related documentation hyperlink in page 1
Document Number: 001-53954 Rev. *H
Page 22 of 23
CY14V104LA
CY14V104NA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
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psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
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Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
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PSoC
Touch Sensing
USB Controllers
Wireless/RF
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cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53954 Rev. *H
Revised November 5, 2014
Page 23 of 23
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