CY15B102QM-50SWXI [INFINEON]
2Mb 3.3V Industrial 50MHz SPI EXCELON™ F-RAM in 8-pin SOIC with WEL enabled;
| 型号： | CY15B102QM-50SWXI |
| 厂家： | 
Infineon |
| 描述： | 2Mb 3.3V Industrial 50MHz SPI EXCELON™ F-RAM in 8-pin SOIC with WEL enabled |
| 文件： | 总35页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY15B102QM
2Mb EXCELON™ LP Ferroelectric RAM
(F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Features
• 2-Mbit ferroelectric random access memory (F-RAM) logically organized as 256K × 8
- Virtually unlimited endurance of 1000 trillion (1015) read/write cycles
- 151-year data retention (see “Data retention and endurance” on page 23)
- Infineon instant non-volatile write technology
- Advanced high-reliability ferroelectric process
• Fast SPI (FSPI)
- Up to 50 MHz frequency
- Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
• Sophisticated write protection scheme
- Hardware protection using the Write Protect (WP) pin
- Software block protection for 1/4, 1/2, or entire array
• Device ID and serial number
- Device ID contains manufacturer ID and product ID
- Unique ID
- Serial number
• Dedicated 256-byte special sector F-RAM
- Dedicated special sector write and read
- Stored content can survive up to three standard reflow soldering cycles
• Low-power consumption
- 2.4 mA (typ) active current at 40 MHz
- 2.3 µA (typ) standby current
- 0.70 µA (typ) deep power down mode current
- 0.1 µA (typ) hibernate mode current
• Low-voltage operation
- CY15B102QM: VDD = 1.8 V to 3.6 V
• Industrial operating temperature: –40°C to +85°C
• Package
- 8-pin small outline integrated circuit (SOIC) package
• Restriction of hazardous substances (RoHS) compliant
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
Functional description
The EXCELON™ LP CY15B102QM is a low power, 2-Mbit nonvolatile memory employing an advanced ferroelectric
process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes similar to
a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and
system-level reliability problems caused by serial flash, EEPROM, and other nonvolatile memories.
Unlike serial flash and EEPROM, the CY15B102QM performs write operations at bus speed. No write delays are
incurred. Data is written to the memory array immediately after each byte is successfully transferred to the
device. The next bus cycle can commence without the need for data polling. In addition, the product offers
substantial write endurance compared to other nonvolatile memories. The CY15B102QM is capable of supporting
1015 read/write cycles, or 1000 million times more write cycles than EEPROM.
These capabilities make the CY15B102QM ideal for nonvolatile memory applications, requiring frequent or rapid
writes. Examples range from data collection, where the number of write cycles may be critical, to demanding
industrial controls where the long write time of serial flash or EEPROM can cause data loss.
The CY15B102QM provides substantial benefits to users of serial EEPROM or flash as a hardware drop-in
replacement. The CY15B102QM uses the high-speed SPI bus, which enhances the high-speed write capability of
F-RAM technology. The device incorporates a read-only Device ID and Unique ID features, which allow the host
to determine the manufacturer, product density, product revision, and unique ID for each part. The device also
provides a writable, 8-byte serial number registers, which can be used to identify a specific board or a system.
Logic block diagram
WP
256-Byte
Special Sector
F-RAM
CS
Instruction Decoder
F-RAM Control
Control Logic
Write Protect
SCK
SI
256K 8
F-RAM Array
Data I/O Register
SO
Nonvolatile
Status Register
Device ID and Serial
Number Registers
Datasheet
2
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Table of contents
Table of contents
Features ...........................................................................................................................................1
Functional description.......................................................................................................................2
Logic block diagram ..........................................................................................................................2
Table of contents...............................................................................................................................3
1 Pinout............................................................................................................................................4
2 Pin definitions ................................................................................................................................5
3 Functional overview .......................................................................................................................6
3.1 Memory architecture ..............................................................................................................................................6
3.2 SPI bus.....................................................................................................................................................................6
3.2.1 SPI overview.........................................................................................................................................................6
3.3 Terms used in SPI protocol ....................................................................................................................................7
3.3.1 SPI master ............................................................................................................................................................7
3.3.2 SPI slave ...............................................................................................................................................................7
3.3.3 Chip select (CS) ....................................................................................................................................................7
3.3.4 Serial clock (SCK) .................................................................................................................................................7
3.3.5 Data transmission (SI/SO) ...................................................................................................................................7
3.3.6 Most significant bit (MSb) ....................................................................................................................................8
3.3.7 Serial Opcode.......................................................................................................................................................8
3.3.8 Invalid Opcode .....................................................................................................................................................8
3.3.9 Status Register .....................................................................................................................................................8
3.4 SPI modes................................................................................................................................................................9
3.5 Power-up to first access .........................................................................................................................................9
4 Functional description ..................................................................................................................10
4.1 Command structure..............................................................................................................................................10
4.1.1 Register access commands ...............................................................................................................................12
4.1.2 Memory operation .............................................................................................................................................12
4.1.3 Memory write operation commands ................................................................................................................13
4.1.4 Memory read operation commands .................................................................................................................14
4.1.5 Special sector memory access commands.......................................................................................................15
4.1.6 Identification and serial number commands...................................................................................................16
4.1.7 Low power mode commands............................................................................................................................18
5 Maximum ratings..........................................................................................................................20
6 Operating range ...........................................................................................................................21
7 DC electrical characteristics...........................................................................................................22
8 Data retention and endurance .......................................................................................................23
9 Capacitance .................................................................................................................................24
10 Thermal resistance......................................................................................................................25
11 AC test conditions .......................................................................................................................26
12 AC switching characteristics ........................................................................................................27
13 Power cycle timing......................................................................................................................29
14 Ordering information ..................................................................................................................30
15 Package diagram ........................................................................................................................31
16 Acronyms ...................................................................................................................................32
17 Document conventions................................................................................................................33
17.1 Units of measure .................................................................................................................................................33
Revision history ..............................................................................................................................34
Datasheet
3
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Pinout
1
Pinout
1
2
3
4
8
7
6
5
VDD
CS
SO
DNU
SCK
SI
WP
VSS
TOP View
(Not to Scale)
Figure 1
8-pin SOIC pinout
Datasheet
4
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Pin definitions
2
Pin definitions
Table 1
Pin definitions
I/O type
Pin name
Description
ChipSelect.ThisactiveLOWinputactivatesthedevice.WhenHIGH,thedeviceenters
low-power standby mode, ignores other inputs, and the output is tristated. When
LOW, the device internally activates the SCK signal. A falling edge on CS must occur
before every opcode.
CS
Input
Input
Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched
on the rising edge and outputs occur on the falling edge of the serial clock. The clock
frequency may be any value between 0 MHz and 50 MHz and may be interrupted at
any time due to its synchronous behavior.
SCK
Serial Input. All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet the power (IDD) specifications.
SI[1]
Input
Serial Output. This is the data output pin. It is driven during a read and remains
tristated at all other times. Data transitions are driven on the falling edge of the
serial clock SCK.
SO[1]
Output
Write Protect. This Active LOW pin prevents write operation to the Status Register
when WPEN bit in the Status Register is set to ‘1’. This is critical because other write
WP
Input
protection features are controlled through the Status Register. A complete
explanation of write protection is provided in Table 3 and Table 6. This pin must
be tied to VDD if not used.
DNU
VSS
Do Not Use Do Not Use. Either leave this pin floating (not connected on the board) or tie to VDD
.
Power
Ground for the device. Must be connected to the ground of the system.
supply
Power
VDD
Power supply input to the device.
supply
Note
1. SI may be connected to SO for a single pin data interface.
Datasheet
5
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional overview
3
Functional overview
The CY15B102QM is a serial F-RAM memory. The memory array is logically organized as 262,144 × 8 bits and is
accessed using an industry-standard SPI bus. The functional operation of the F-RAM is similar to serial flash and
serial EEPROMs. The major difference between the CY15B102QM and a serial flash or EEPROM with the same
pinout is the F-RAM’s superior write performance, high endurance, and low power consumption.
3.1
Memory architecture
When accessing the CY15B102QM, the user addresses 256K locations of eight data bits each. These eight data bits
are shifted in or out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an opcode, and a three-byte address. The upper five bits of the address range
are ‘don’t care’ values. The complete address of 18 bits specifies each byte address uniquely.
Most functions of the CY15B102QM are either controlled by the SPI interface or handled by on-board circuitry.
The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not
necessary to poll the device for a ready condition because writes occur at bus speed. By the time a new bus
transaction can be shifted into the device, a write operation is complete. This is explained in more detail in the
interface section.
3.2
SPI bus
The CY15B102QM is an SPI slave device and operates at speeds of up to 50 MHz. This high-speed serial bus
provides high-performance serial communication to an SPI master. Many common microcontrollers have
hardware SPI ports allowing a direct interface. It is simple to emulate the port using ordinary port pins for
microcontrollers that do not have this feature. The CY15B102QM operates in SPI Modes 0 and 3.
3.2.1
SPI overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK)
pins.
The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports
multiple devices on the data bus. A device on the SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes
0 and 3. In both of these modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first
rising edge after CS goes active.
The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave
device. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode,
any addresses and data are then transferred. The CS must go inactive after an operation is complete and before
a new opcode can be issued.
Datasheet
6
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional overview
3.3
Terms used in SPI protocol
The commonly used terms in the SPI protocol are as follows:
3.3.1
SPI master
The SPI master device controls the operations on the SPI bus. An SPI bus may have only one master with one or
more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices
using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS
pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are
synchronized with this clock.
3.3.2
SPI slave
The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an
input from the SPI master and all the communication is synchronized with this clock. An SPI slave never initiates
a communication on the SPI bus and acts only on the instruction from the master.
The CY15B102QM operates as an SPI slave and may share the SPI bus with other SPI slave devices.
3.3.3
Chip select (CS)
To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued
to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored
and the serial output pin (SO) remains in a high-impedance state.
Note: A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each
active Chip Select cycle.
3.3.4
Serial clock (SCK)
The serial clock is generated by the SPI master and the communication is synchronized with this clock after CS
goes LOW.
The CY15B102QM supports SPI modes 0 and 3 for data communication. In both of these modes, the inputs are
latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the
first rising edge of SCK signifies the arrival of the first Most Significant Bit (MSb) of an SPI instruction on the SI pin.
Further, all data inputs and outputs are synchronized with SCK.
3.3.5
Data transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as Master
Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave
through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO
lines as described earlier.
The CY15B102QM has two separate pins for SI and SO, which can be connected with the master as shown in
Figure 2. For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce
hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off
(HIGH) the WP pin. Figure 3 shows such a configuration, which uses only three pins.
Datasheet
7
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional overview
SCK
MOSI
MISO
SCK
SI
SO
SCK
SI
SO
SPI Hostcontroller
or
SPI Master
CY15B102QM
CY15B102QM
CS
WP
CS
WP
CS1
WP1
CS2
WP2
Figure 2
System configuration with SPI port
P1.0
P1.1
SCK
SI
SO
SPI Hostcontroller
or
CY15B102QM
SPI Master
CS
WP
P1.2
Figure 3
System configuration without SPI port
3.3.6
Most significant bit (MSb)
The SPI protocol requires that the first bit to be transmitted is the MSb. This is valid for both address and data
transmission.
The 2-Mbit serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only
18 bits, the first six bits, which are fed in are ignored by the device. Although these six bits are ‘don’t care’, Infineon
recommends that these bits be set to 0s to enable seamless transition to higher memory densities.
3.3.7
Serial Opcode
After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the
intended operation. CY15B102QM uses the standard opcodes for memory accesses.
3.3.8
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI
pin until the next falling edge of CS, and the SO pin remains tristated.
3.3.9
Status Register
CY15B102QM has an 8-bit Status Register. The bits in the Status Register are used to configure the device. These
bits are described in Table 4.
Datasheet
8
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional overview
3.4
SPI modes
CY15B102QM may be driven by a microcontroller with its SPI peripheral running in either of the following two
modes:
• SPI Mode 0 (CPOL = 0, CPHA = 0)
• SPI Mode 3 (CPOL = 1, CPHA = 1)
For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after
CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is
considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 4 and
Figure 5. The status of the clock when the bus master is not transferring data is:
• SCK remains at 0 for Mode 0
• SCK remains at 1 for Mode 3
The device detects the SPI mode from the status of the SCK pin when the device is selected by bringing the CS
pin LOW. If the SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if the SCK pin is HIGH, it
works in SPI Mode 3.
CS
0
1
2
3
4
5
6
7
SCK
SI
7
6
5
4
3
2
1
0
Figure 4
SPI mode 0
CS
0
1
2
3
4
5
6
7
SCK
7
6
5
4
3
2
1
0
SI
Figure 5
SPI mode 3
3.5
Power-up to first access
The CY15B102QM is not accessible for a tPU time after power-up. Users must comply with the timing parameter,
tPU, which is the minimum time from VDD (min) to the first CS LOW. Refer to “Power cycle timing” on page 29 for
details.
Datasheet
9
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
4
Functional description
4.1
Command structure
There are 13 commands, called opcodes, that can be issued by the bus master to the CY15B102QM (see Table 2).
These opcodes control the functions performed by the memory.
Table 2
Name
Opcode commands
Opcode
Max. Frequency
(MHz)
Description
Hex
Binary
Register Access
RDSR
WRSR
Read Status Register
Write Status Register
05h
01h
0000 0101b
0000 0001b
50
50
Memory Write
WRITE
Write memory data
02h
0000 0010b
50
Memory Read
READ
FSTRD
Read memory data
Fast read memory data
03h
0Bh
0000 0011b
0000 1011b
40
50
Special Sector Memory Access
SSWR
SSRD
Special Sector Write
Special Sector Read
42h
4Bh
0100 0010b
0100 1011b
50
40
Identification and Serial Number
RDID
RUID
WRSN
RDSN
Read device ID
Read Unique ID
Write Serial Number
Read Serial Number
9Fh
4Ch
C2h
C3h
1001 1111b
0100 1100b
1100 0010b
11000 011b
50
50
50
50
Low Power Mode Commands
DPD
Enter Deep
BAh
B9h
1011 1010b
1011 1001b
50
50
Power-Down
HBN
Enter Hibernate Mode
Reserved
Reserved
Reserved
Unused opcodes are reserved for future
use.
–
Datasheet
10
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
Status register and write protection
The write protection features of the CY15B102QM are multi-tiered and are enabled through the status register.
The Status Register is organized as follows. (The default value shipped from the factory for BP0, BP1, bits 4–5,
and WPEN is ‘0’ and WEL, bit 6 is ‘1’).
Table 3
Bit 7
WPEN (0)
Status register
Bit 6
Bit 5
X (0)
Bit 4
X (0)
Bit 3
BP1 (0)
Bit 2
BP0 (0)
Bit 1
WEL (1)
Bit 0
X (0)
X (1)
Table 4
Status register bit definition
Definition
Bit
Description
Bit 0
Don’t care
This bit is non-writable and always returns ‘0’ upon read.
WEL indicates if the device is write enabled. This bit defaults to ‘1’ (enabled)
on power-up.
Write Enable
(Don’t Care)
WEL = 1 = Write enabled
Bit 1 (WEL)
This bit is non-writable and always returns ‘1’ upon read.
WEL is not reset after executing write (WRSR, WRITE, WRSN, SSWR)
commands.
Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 5.
Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 5.
Bit 4–5
Bit 6
Don’t care
Don’t care
These bits are non-writable and always return ‘0’ upon read.
This bit is non-writable and always returns ‘1’ upon read.
WriteProtect
Enablebit
Used to enable the function of Write Protect Pin (WP). For details, see
Table 6.
Bit 7 (WPEN)
Bits 0 and 4–5 are fixed at ‘0’ and WEL, bit 6 is fixed at ‘1’; none of these bits can be modified. Note that bit 0
(“Ready or Write in progress” bit in serial flash and EEPROM) is unnecessary, as the F-RAM writes in real-time and
is never busy, so it reads out as a ‘0’. An exception to this is when the device is waking up either from “Deep
power-down mode (DPD, BAh)” on page 18 or “Hibernate mode (HBN, B9h)” on page 19. The BP1 and BP0
control the software write-protection features and are nonvolatile bits. The WEL flag indicates the state of the
Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its state. This
bit is internally set permanently on power-up and does not clear to ‘0’ on the rising edge of CS following any write
(WRSR, WRITE, WRSN, SSWR) commands.
BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected
as shown in Table 5.
Table 5
Block memory write protection
BP0
BP1
Protected address range
0
0
1
1
0
1
0
1
None
30000h to 3FFFFh (upper 1/4)
20000h to 3FFFFh (upper 1/2)
00000h to 3FFFFh (all)
The BP1 and BP0 bits are the only mechanismsthatprotectthememoryfromwrites.Theremaining write
protectionfeaturesprotectinadvertentchangestotheblock protect bits.
The write protect enable bit (WPEN) in the Status Register controls the effect of the hardware write protect (WP)
pin. Refer to Figure 21 for the WP pin timing diagram. When the WPEN bit is set to ‘0’, the status of the WP pin is
ignored. When the WPEN bit is set to ‘1’, a LOW on the WP pin inhibits a write to the Status Register. Thus the Status
Register is write-protected only when WPEN = ‘1’ and WP = ‘0’. Table 6 summarizes the write protection
conditions.
Datasheet
11
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
Table 6
WEL
Write protection
WPEN
WP
X
0
Protected blocks
Protected
Unprotected blocks
Unprotected
Status register
Unprotected
Protected
1
1
1
0
1
1
Protected
Protected
Unprotected
Unprotected
1
Unprotected
4.1.1
Register access commands
Read Status Register (RDSR, 05h)
The RDSR command allows the bus master to verify the contents of the Status Register. Reading the Status
Register provides information about the current state of the write-protection features. Following the RDSR
opcode, the CY15B102QM will return one byte with the contents of the Status Register.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
0
0
0
0
0
1
0
1
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Opcode (05h)
Read Data
Figure 6
RDSR bus configuration
Write Status Register (WRSR, 01h)
The WRSR command allows the SPI bus master to write into the Status Register and change the write protect
configuration by setting the WPEN, BP0, and BP1 bits as required. Before issuing a WRSR command, the WP pin
must be HIGH or inactive. Note that on the CY15B102QM, WP only prevents writing to the Status Register, not the
memory array.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Hi-Z
SO
Opcode (01h)
Write Data
Figure 7
WRSR bus configuration
4.1.2
Memory operation
The SPI interface, which is capable of a high clock frequency, highlights the fast write capability of the F-RAM
technology. Unlike serial flash and EEPROMs, the CY15B102QM can perform sequential writes at bus speed. No
page register is needed and any number of sequential writes may be performed.
Datasheet
12
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
4.1.3
Memory write operation commands
Write operation (WRITE, 02h)
All writes to the memory begin with a WRITE opcode with CS being asserted. The WRITE opcode is followed by a
three-byte address containing the 18-bit address (A17–A0) of the first data byte to be written into the memory.
The upper six bits of the three-byte address are ignored. Subsequent bytes are data bytes, which are written
sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and keeps
CS LOW. If the last address of 3FFFFh is reached, the internal address counter will roll over to 00000h. Every data
byte to be written is transmitted on SI in 8-clock cycles with MSb first and the LSb last. The rising edge of CS
terminates a write operation. The CY15B102QM write operation is shown in Figure 8.
Notes
• When a burst write reaches a protected block address, the automatic address increment stops and all the
subsequent data bytes received for write will be ignored by the device. EEPROMs use page buffers to increase
their write throughput. This compensates for the technology’s inherently slow write operations. F-RAM
memories do not have page buffers because each byte is written to the F-RAM array immediately after it is
clocked in (after the eighth clock). This allows any number of bytes to be written without page buffer delays.
• If power is lost in the middle of the write operation, only the last completed byte will be written.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
A23 A22 A21 A20
A3
A2
A1 A0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
MSb
0
LSb
Hi-Z
Hi-Z
SO
Opcode (02h)
Address
Write Data
Figure 8
Memory write operation
Datasheet
13
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
4.1.4
Memory read operation commands
Read operation (READ, 03h)
After the falling edge of CS, the bus master can issue a READ opcode. Following the READ command is a three-byte
address containing the 18-bit address (A17–A0) of the first byte of the read operation. The upper six bits of the
address are ignored. After the opcode and address are issued, the device drives out the read data on the next
eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out
sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and CS is
LOW. If the last address of 3FFFFh is reached, the internal address counter will roll over to 00000h. The device also
provides a writable, 8-byte serial number registers, which can be used to identify a specific board or a system.
The rising edge of CS terminates a read operation and tristates the SO pin. The CY15B102QM read operation is
shown in Figure 9.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
A23 A22 A21 A20
A3
A2
A1 A0
0
0
0
0
0
0
1
1
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Opcode (03h)
Address
Read Data
Figure 9
Memory read operation
Fast read operation (FAST_READ, 0Bh)
The CY15B102QM supports a FAST READ opcode (0Bh) that is provided for opcode compatibility with serial flash
devices. The FAST READ opcode is followed by a three-byte address containing the 18-bit address (A17–A0) of the
first byte of the read operation and then a dummy byte. The dummy byte inserts a read latency of 8-clock cycle.
The fast read operation is otherwise the same as an ordinary read operation except that it requires an additional
dummy byte. After receiving the opcode, address, and a dummy byte, the CY15B102QM starts driving its SO line
with data bytes, with MSb first, and continues transmitting as long as the device is selected and the clock is
available. In case of bulk read, the internal address counter is incremented automatically, and after the last
address 3FFFFh is reached, the internal address counter rolls over to 00000h. When the device is driving data on
its SO line, any transition on its SI line is ignored. The rising edge of CS terminates a fast read operation and
tristates the SO pin. The CY15B102QM Fast Read operation is shown in Figure 10.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
A23 A22 A21 A20
MSb
A3
A2
A1 A0
0
0
0
0
1
0
1
x
x
x
x
x
x
x
x
1
LSb
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb
LSb
Opcode (0Bh)
Address
Dummy Byte
Read Data
Figure 10
Fast read operation
Datasheet
14
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
4.1.5
Special sector memory access commands
Special sector write (SSWR, 42h)
All writes to the 256-byte special begin with a SSWR opcode with CS being asserted. The SSWR opcode is followed
by a three-byte address containing the 8-bit sector address (A7–A0) of the first data byte to be written into the
special sector memory. The upper 16 bits of the three-byte address are ignored. Subsequent bytes are data bytes,
which are written sequentially. Addresses are incremented internally as long as the bus master continues to issue
clocks and keeps CS LOW. Once the internal address counter auto increments to XXX7Fh, CS should toggle HIGH
to terminate the ongoing SSWR operation. Every data byte to be written is transmitted on SI in 8-clock cycles with
MSb first and the LSb last. The rising edge of CS terminates a write operation. The CY15B102QM special sector
write operation is shown in Figure 11.
Notes
• If power is lost in the middle of the write operation, only the last completed byte will be written.
• The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow
soldering.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
A23 A22 A21 A20
A3
A2
A1 A0
0
1
0
0
0
0
1
D7 D6
MSb
D5
D4 D3
D2
D1
D0
0
LSb
Hi-Z
Hi-Z
SO
Opcode (42h)
Address
Write Data
Figure 11
Special sector write operation
Special sector read (SSRD, 4Bh)
After the falling edge of CS, the bus master can issue an SSRD opcode. Following the SSRD command is a
three-byte address containing the 8-bit address (A7–A0) of the first byte of the special sector read operation. The
upper 16 bits of the address are ignored. After the opcode and address are issued, the device drives out the read
data on the next eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes,
which are read out sequentially. Addresses are incremented internally as long as the bus master continues to
issue clocks and CS is LOW. Once the internal address counter auto increments to XXX7Fh, CS should toggle HIGH
to terminate the ongoing SSRD operation. Every read data byte on SO is driven in 8-clock cycles with MSb first
and the LSb last. The rising edge of CS terminates a special sector read operation and tristates the SO pin. The
CY15B102QM special sector read operation is shown in Figure 12.
Note The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow
soldering.
CS
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23
0
1
2
3
4
5
6
7
SCK
SI
Hi-Z
A23 A22 A21 A20
A3
A2
A1 A0
0
1
0
0
1
0
1
1
Hi-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Opcode (4Bh)
Address
Read Data
Figure 12
Special sector write read operation
Datasheet
15
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
4.1.6
Identification and serial number commands
Read device ID (RDID, 9Fh)
The CY15B102QM device can be interrogated for its manufacturer, product identification, and die revision. The
RDID opcode 9Fh allows the user to read the 9-byte manufacturer ID and product ID, both of which are read-only
bytes. The JEDEC-assigned manufacturer ID places the Cypress (Ramtron) identifier in bank 7; therefore, there
are six bytes of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID,
which includes a family code, a density code, a sub code, and the product revision code. Table 6 shows 9-Byte
Device ID field description. Refer to “Ordering information” on page 30 for 9-Byte device ID of an individual part.
The CY15B102QM read device ID operation is shown in Figure 13.
Note The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 8) shifts out
last.
Table 7
9-byte device ID
Device ID field description
Manufacturer ID
[71:16]
Family
[15:13]
Density
Inrush
[8]
Sub type Revision Voltage Frequency
[12:9]
[7:5]
[4:3]
[2]
[1:0]
56-bit
3-bit
4-bit
1-bit
3-bit
2-bit
1-bit
2-bit
CS
0
1
2
3
4
5
6
7
0
1
2
3
60 61 62 63 64 65 66 67 68 69 70 71
SCK
SI
Hi-Z
1
0
0
1
1
1
1
1
MSb
D7
LSb
Hi-Z
D6
D5
D4
D3
D2
D1 D0
SO
D7 D6
D5
D4
D3
D2
D1
D0
Byte 0
Byte 8
Opcode (9Fh)
9-Byte Device ID
Figure 13
Read device ID
Read unique ID (RUID, 4Ch)
The CY15B102QM device can be interrogated for unique ID which is a factory programmed, 64-bit number unique
to each device. The RUID opcode, 4Ch allows to read the 8-byte, read only unique ID. The CY15B102QM read
unique ID operation is shown in Figure 14.
Notes
• The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out last.
• The unique ID registers are guaranteed to retain data integrity of up to three cycles of the standard reflow
soldering.
CS
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63
SCK
SI
Hi-Z
0
1
0
0
1
1
0
0
MSb
D7
LSb
Hi-Z
D6
D5
D4
D3
D2
D1 D0
SO
D7 D6
D5
D4
D3
D2
D1
D0
Byte 0
Byte 7
Opcode (4Ch)
8-Byte Unique ID
Figure 14
Read unique ID
Datasheet
16
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
Write serial number (WRSN, C2h)
The serial number is an 8-byte one-time programmable memory space provided to the user to uniquely identify
a PC board or a system. A serial number typically consists of a two-byte Customer ID, followed by five bytes of a
unique serial number and one byte of CRC check. However, the end application can define its own format for the
8-byte serial number. All writes to the Serial Number Register begin with a WRSN opcode with CS being asserted.
The WRSN instruction can be used in burst mode to write all the 8 bytes of serial number. After the last byte of
the serial number is shifted in, CS must be driven high to complete the WRSN operation. The CY15B102QM write
serial number operation is shown in Figure 15.
Note The CRC checksum is not calculated by the device. The system firmware must calculate the CRC checksum
on the 7-byte content and append the checksum to the 7-byte user-defined serial number before programming
the 8-byte serial number into the serial number register. The factory default value for the 8-byte Serial Number
is ‘0000000000000000h’.
Table 8
16-bit customer identifier
SN[63:56] SN[55:48]
8-byte serial number
40-bit unique number
SN[39:32] SN[31:24] SN[23:16]
8-bit CRC
SN[7:0]
SN[47:40]
SN[15:8]
CS
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63
SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
LSb
MSb
Hi-Z
Hi-Z
SO
Opcode (C2h)
Write 8-Byte Serial Number
Figure 15
Write serial number operation
Read serial number (RDSN, C3h)
The CY15B102QM device incorporates an 8-byte serial space provided to the user to uniquely identify the device.
The serial number is read using the RDSN instruction. A serial number read may be performed in burst mode to
read all the eight bytes at once. After the last byte of the serial number is read, the device loops back to the first
byte of the serial number. An RDSN instruction can be issued by shifting the opcode for RDSN after CS goes LOW.
The CY15B102QM read serial number operation is shown in Figure 16.
Note The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out
last.
CS
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63
SCK
SI
Hi-Z
1
1
0
0
0
0
1
1
MSb
D7
LSb
Hi-Z
D6
D5
D4
D3
D2
D1 D0
SO
D7 D6
D5
D4
D3
D2
D1
D0
Byte 0
Byte 7
Opcode (C3h)
8-Byte Serial Number
Figure 16
Read serial number operation
Datasheet
17
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
4.1.7
Low power mode commands
Deep power-down mode (DPD, BAh)
A power-saving Deep Power-Down mode is implemented on the CY15B102QM device. The device enters the Deep
Power-Down mode after tENTDPD time after the DPD opcode BAh is clocked in and a rising edge of CS is applied.
When in Deep Power-Down mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues
to monitor the CS pin.
A CS pulse-width of tCSDPD exits the DPD mode after tEXTDPD time. The CS pulse-width can be generated either by
sending a dummy command cycle or toggling CS alone while SCK and I/Os are don’t care. The I/Os remain in hi-Z
state during the wakeup from deep power-down. Refer to Figure 17 for DPD entry and Figure 18 for DPD exit
timing.
Enters DPD
tENTDPD
CS
0
1
2
3
4
5
6
7
SCK
SI
1
0
1
1
1
0
1
0
hi-Z
SO
Opcode (BAh)
Figure 17
DPD entry timing
tEXTDPD
tCSDPD
CS
0
1
2
SCK
tSU
X
I/Os
Figure 18
DPD exit timing
Datasheet
18
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Functional description
Hibernate mode (HBN, B9h)
A lowest power Hibernate mode is implemented on the CY15B102QM device. The device enters Hibernate mode
after tENTHIB time after the HBN opcode B9h is clocked in and a rising edge of CS is applied. When in Hibernate
mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues to monitor the CS pin. On the
next falling edge of CS, the device will return to normal operation within tEXTHIB time. The SO pin remains in a Hi-Z
state during the wakeup from hibernate period. The device does not necessarily respond to an opcode within the
wakeup period. To exit the Hibernate mode, the controller may send a “dummy” read, for example, and wait for
the remaining tEXTHIB time.
Enters
Hibernate Mode
Recovers from
Hibernate Mode
tENTHIB
tEXTHIB
CS
0
1
2
3
4
5
6
7
0
1
2
SCK
tSU
SI
1
0
1
1
1
0
0
1
hi-Z
SO
Opcode (B9h)
Figure 19
Hibernate mode operation
Endurance
The CY15B102QM devices are capable of being accessed at least 1015 times, reads or writes.
An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a
row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows
and columns of 32K rows of 64-bit each. The entire row is internally accessed once, whether a single byte or all
eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. Table 9
shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a
sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually unlimited at a 50-MHz clock rate.
Table 9
Time to reach endurance limit for repeating 64-byte loop
SCK freq (MHz)
Endurance cycles/sec
Endurance cycles/year
2.90 × 1012
Years to reach 1015 limit
50
40
20
10
5
91,900
73,040
36,520
18,380
9,190
345
43.
2.30 × 1012
1.16 × 1012
864
5.79 × 1011
1727
3454
2.90 × 1011
Datasheet
19
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Maximum ratings
5
Maximum ratings
Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested.
Storage temperature ........................................................................................................................... –65°C to +125°C
Maximum accumulated storage time
At 125°C ambient temperature .......................................................................................................................... 1000 h
At 85°C ambient temperature ......................................................................................................................... 10 Years
Maximum junction temperature ......................................................................................................................... 125°C
Supply voltage on VDD relative to VSS
:
CY15B102QM: ....................................................................................................................................... –0.5 V to +4.1 V
Input voltage ....................................................................................................................................... VIN VDD + 0.5 V
DC voltage applied to outputs in High-Z state ............................................................................ –0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on any pin to ground potential ....................................................... –2.0 V to VDD + 2.0 V
Package power dissipation capability (TA = 25°C) .............................................................................................. 1.0 W
Surface mount lead soldering temperature (3 seconds) ................................................................................. +260°C
DC output current (1 output at a time, 1s duration) .......................................................................................... 15 mA
Electrostatic discharge voltage
Human Body Model (JEDEC Std JESD22-A114-B) ................................................................................................ 2 kV
Charged Device Model (JEDEC Std JESD22-C101-A) ...........................................................................................500 V
Latch-up current ............................................................................................................................................. >140 mA
Datasheet
20
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Operating range
6
Operating range
Table 10
Operating range
Device
CY15B102QM
Range
Industrial
Ambient temperature
VDD
1.8 V to 3.6 V
–40°C to +85°C
Datasheet
21
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
DC electrical characteristics
7
DC electrical characteristics
Table 11
DC electrical characteristics
Over the Operating range
Parameter Description
VDD
Typ[2, 3]
3.30
Test conditions
Min
1.80
–
Max
3.60
3
Unit
V
Power supply
–
V
DD = 1.8 V to 3.6 V;
f
SCK = 40 MHz
2.4
mA
SCK toggling
between
IDD
VDD supply current VDD – 0.2 V and VSS
other inputs
,
fSCK = 50 MHz
–
3
3.7
mA
VSS or VDD – 0.2 V.
SO = Open
VDD = 1.8 V to 3.6 V; TA = 25°C
–
70
–
µA
µA
µA
µA
µA
µA
CS = VDD
.
ISB
V
DD standby current
–
–
2.6
0.8
All other inputs
VSS or VDD
TA = 85°C
VDD = 1.8 V to 3.6 V; TA = 25°C
CS = VDD
.
Deep power down
current
IDPD
All other inputs
VSS or VDD
TA = 85°C
16
–
VDD = 1.8 V to 3.6 V; TA = 25°C
CS = VDD
All other inputs
VSS or VDD
.
Hibernate mode
current
IHBN
–
0.1
–
TA = 85°C
1.6
.
Input leakage
current on I/O pins
except WP pin
–1
1
µA
ILI
VSS < VIN < VDD
Input leakage
–100
–1
–
–
1
1
µA
µA
current on WP pin
Output leakage
current
ILO
VSS < VOUT < VDD
VIH
VIL
Input HIGH voltage –
0.7 × VDD
–0.3
–
–
VDD + 0.3
0.3 × VDD
V
V
Input LOW voltage
–
Output HIGH
voltage
VOH1
VOH2
IOH = –1 mA, VDD = 2.7 V
IOH = –100 µA
2.40
–
–
–
–
V
V
Output HIGH
voltage
VDD – 0.2
VOL1
Output LOW voltage IOL = 2 mA, VDD = 2.7 V
Output LOW voltage IOL = 150 µA
–
–
–
–
0.40
0.20
V
V
VOL2
Notes
2. Typical values are at 25°C, VDD = VDD (typ)
.
3. This parameter is guaranteed by characterization; not tested in production.
Datasheet
22
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Data retention and endurance
8
Data retention and endurance
Table 12
Parameter
TDR
Data retention and endurance
Description
Data retention
Test conditions
Min
10
141
151
160
1015
Max
Unit
Years
Years
Years
Years
Cycles
TA = 85°C
–
–
–
–
–
TA = 70°C
TA = 60°C
TA = 50°C
NVC
Endurance
Over operating temperature
Datasheet
23
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Capacitance
9
Capacitance
Table 13
Capacitance
For all packages.
Parameter[4]
Description
Test conditions
Max
8
6
Unit
pF
pF
CO
CI
Output pin capacitance (SO) TA = 25°C, f = 1 MHz, VDD = VDD(typ)
Input pin capacitance
Note
4. This parameter is guaranteed by characterization; not tested in production.
Datasheet
24
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Thermal resistance
10
Thermal resistance
Table 14
Thermal resistance
8-pin SOIC
package
Parameter[5]
Description
Test conditions
Unit
°C/W
°C/W
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test conditions follow standard
test methods and procedures for
measuringthermalimpedance,per
EIA/JESD51.
JA
JC
96.0
86.8
Note
5. This parameter is guaranteed by characterization; not tested in production.
Datasheet
25
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
AC test conditions
11
AC test conditions
Input pulse levels ........................................................................................................................ 10% and 90% of VDD
Input rise and fall times ......................................................................................................................................... 3 ns
Input and output timing reference levels ..................................................................................................... 0.5 × VDD
Output load capacitance ..................................................................................................................................... 30 pF
Datasheet
26
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
AC switching characteristics
12
AC switching characteristics
Table 15
AC switching characteristics
Over the Operating range
[ ]
6
Parameters
40 MHz
50 MHz
Description
Unit
Alt.
Parameter
Min
Max
Min
Max
Parameter
fSCK
tCH
tCL
tCLZ
tCSS
tCSH
tCSH1
tHZCS
tCO
–
–
–
–
SCK clock frequency
Clock HIGH time
Clock LOW time
Clock LOW to Output low-Z
Chip select setup
Chip select hold - mode 0
Chip select hold - mode 3
Output disable time
Output data valid time
Output hold time
Deselect time
Data setup time
Data hold time
WP setup time (w.r.t CS)
WP hold time (w.r.t CS)
0
11
11
0
5
5
10
–
–
1
40
5
40
–
–
–
–
–
–
12
9
–
0
9
9
0
5
5
10
–
–
1
40
5
5
20
20
50
–
–
–
–
–
–
10
8
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
]
[7
tCSU
tCSH
tCSH1
]
[8, 9
tOD
tODV
–
tD
tSU
tH
tOH
tCS
tSD
–
–
–
–
–
–
–
–
tHD
tWPS
tWPH
5
20
20
tWHSL
tSHWL
–
–
Notes
6. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse
levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown in
“AC test conditions” on page 26.
7. Guaranteed by design.
8. tHZCS is specified with a load capacitance of 5 pF. Transition is measured when the output enters a
high-impedance state.
9. This parameter is guaranteed by characterization; not tested in production.
Datasheet
27
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
AC switching characteristics
tCS
CS
tCSS
tCH
tCL
tCSH1
tCSH
Mode 3
Mode 0
SCK
SI
tSD
tHD
X
X
VALID DATA IN
tCO
tOH
tHZCS
tCLZ
Hi-Z
Hi-Z
SO
DATA OUT
X
X
Figure 20
Synchronous data timing (Mode 0 and Mode 3)
tWPS
tWPH
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0
MSb LSb
Hi-Z
SO
Opcode (01h)
Write Data
Figure 21
Write protect timing during write status register (WRSR) operation
Datasheet
28
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Power cycle timing
13
Power cycle timing
Table 16
Power cycle timing
Over the Operating range
Parameters[10]
Description
Min
Max
Unit
Alt.
Parameter
Parameter
tPU
–
–
–
Power-up VDD(min) to first access (CS LOW)
450
50
–
–
–
µs
[11]
VDD power-up ramp rate
µs/V
µs/V
tVR
tVF
[11, 12]
13
VDD power-down ramp rate
100
CS HIGH to enter deep power-down
(CS HIGH to deep power-down mode current)
[
]
–
3
µs
tENTDPD
tCSDPD
tPD
–
CS pulse width to wake up from deep power-down
mode
0.015 4 × 1/fSCK µs
CS LOW to exit deep-power-down
(CS LOW to ready for access)
–
–
–
10
3
µs
µs
µs
tEXTDPD
tRPD
–
CS HIGH to enter hibernate
(CS HIGH to enter hibernate mode current)
[14]
tENTHIB
tEXTHIB
CS LOW to exit hibernate
(CS LOW to ready for access)
450
tREC
VDD (min)
VDD (min)
tVR
VDD
tVF
tPU
Device is accessible
Device is not accessible
CS
Figure 22
Power cycle timing
Notes
10.Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse
levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown
in “AC test conditions” on page 26.
11.Slope measured at any point on the VDD waveform.
12.This parameter is guaranteed by characterization; not tested in production.
13.Guaranteed by design. Refer to Figure 17 for Deep Power Down mode timing.
14.Guaranteed by design. Refer to Figure 19 for Hibernate mode timing.
Datasheet
29
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Ordering information
14
Ordering information
Table 17
Ordering part numbers
Ordering code
CY15B102QM-50SWXI
CY15B102QM-50SWXIT
Device ID
Package diagram
Package type
8-pin SOIC
Operating range
7F7F7F7F7F7FC26A00
51-85066
Industrial
All these parts are Pb-free. Contact your local sales representative for availability of these parts.
14.1
Ordering code definitions
CY 15
B
102
Q
M
- 50 SW
X
I
T
Options:
ES = Engineering sample ;
Blank = Standard; T = Tape and reel
Temperature range:
I = Industrial (40°C to +85°C)
X = Pb-free
Package type:
SW = 8-pin SOIC
Frequency:
50 = 50 MHz
M = WEL Enabled
Interface:
Q = SPI F-RAM
Density:
102 = 2-Mbit
Voltage:
B = 1.8 V to 3.6 V
15 = F-RAM
CY = CYPRESS™ (An Infineon company)
Datasheet
30
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Package diagram
15
Package diagram
51-85066 *I
Figure 23
8-pin SOIC (150 Mils) package outline, 51-85066
Datasheet
31
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Acronyms
16
Acronyms
Table 18
Acronyms used in this document
Acronym
Description
CPHA
CPOL
EEPROM
EIA
F-RAM
I/O
Clock Phase
Clock Polarity
Electrically Erasable Programmable Read-Only Memory
Electronic Industries Alliance
Ferroelectric Random Access Memory
Input/Output
JEDEC
JESD
LSb
Joint Electron Devices Engineering Council
JEDEC standards
Least Significant Bit
MSb
Most Significant Bit
RoHS
SPI
Restriction of Hazardous Substances
Serial Peripheral Interface
SOIC
Small Outline Integrated Circuit
Datasheet
32
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Document conventions
17
Document conventions
17.1
Units of measure
Table 19
Units of measure
Symbol
Unit of measure
°C
degree Celsius
hertz
kilohertz
kilohm
Hz
kHz
k
Mbit
MHz
µA
µF
µs
megabit
megahertz
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
mA
ms
ns
W
%
percent
pF
V
picofarad
volt
W
watt
Datasheet
33
002-33164 Rev. *B
2022-09-12
2Mb EXCELON™ LP Ferroelectric RAM (F-RAM)
WEL enabled, Serial (SPI), 256K × 8, industrial
Revision history
Revision history
Document
Date
Description of changes
revision
*A
2022-01-20
Post to external web.
Updated Features:
Updated description.
Updated Pin definitions:
Updated Table 1.
*B
2022-09-12
Updated to new template.
Datasheet
34
002-33164 Rev. *B
2022-09-12
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Edition 2022-09-12
Published by
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Document reference
002-33164 Rev. *B
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相关型号：
CY15B102QM-50SWXIT
2Mb 3.3V Industrial 50MHz SPI EXCELON™ F-RAM in 8-pin SOIC with WEL enabled
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