CY15V108QN-20LPXC

更新时间:2024-10-30 05:39:08
品牌:INFINEON
描述:8Mb 1.8V Commercial 20MHz SPI EXCELON™ F-RAM in 8-pin GQFN

CY15V108QN-20LPXC 概述

8Mb 1.8V Commercial 20MHz SPI EXCELON™ F-RAM in 8-pin GQFN

CY15V108QN-20LPXC 数据手册

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CY15B108QN, CY15V108QN  
8Mb EXCELON™ LP Ferroelectric RAM  
(F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Features  
• 8-Mb ferroelectric random access memory (F-RAM) logically organized as 1024K × 8  
- Virtually unlimited endurance 1000 trillion (1015) read/writes  
- 151-year data retention (See “Data retention and endurance” on page 26)  
- Infineon instant non-volatile write technology  
- Advanced high-reliability ferroelectric process  
• Fast serial peripheral interface (SPI)  
- Up to 40 MHz frequency  
- Supports SPI mode 0 (0, 0) and mode 3 (1, 1)  
• Sophisticated write protection scheme  
- Hardware protection using the Write Protect (WP) pin  
- Software protection using Write Disable (WRDI) instruction  
- Software block protection for 1/4, 1/2, or entire array  
• Device ID and serial number  
- Manufacturer ID and product ID  
- Unique device ID  
- Serial number  
• Dedicated 256-byte special sector F-RAM  
- Dedicated special sector write and read  
- Stored content can survive up to three standard reflow soldering cycles  
• Low-power consumption  
- 2.6 mA (typ) active current at 40 MHz  
- 3.5 µA (typ) standby current  
- 0.90 µA (typ) deep power down mode current  
- 0.1 µA (typ) hibernate mode current  
• Low-voltage operation  
- CY15V108QN: VDD = 1.71 V to 1.89 V  
- CY15B108QN: VDD = 1.8 V to 3.6 V  
• Commercial and industrial operating temperature  
- Commercial operating temperature: 0°C to +70°C  
- Industrial operating temperature: –40°C to +85°C  
• Packages  
- 8-pin small outline integrated circuit (SOIC) package  
- 8-pin grid-array quad flat no-lead (GQFN) package (NRND)[1]  
- 8-pin ultra-thin fine-pitch land grid array (UFLGA) package  
• Restriction of hazardous substances (RoHS) compliant  
Note  
1. NRND - Not Recommended for New Designs  
Datasheet  
www.infineon.com  
Please read the Important Notice and Warnings at the end of this document  
page 1  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
Functional description  
The EXCELON™ LP CY15X108QN is a low power, 8-Mb non-volatile memory employing an advanced ferroelectric  
process. A ferroelectric random access memory or F-RAM is non-volatile and performs reads and writes similar  
to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and  
system-level reliability problems caused by serial flash, EEPROM, and other non-volatile memories.  
Unlike serial flash and EEPROM, the CY15X108QN performs write operations at bus speed. No write delays are  
incurred. Data is written to the memory array immediately after each byte is successfully transferred to the  
device. The next bus cycle can commence without the need for data polling. In addition, the product offers  
substantial write endurance compared to other non-volatile memories. The CY15X108QN is capable of  
supporting 1015 read/write cycles, or 1000 million times more write cycles than EEPROM.  
These capabilities make the CY15X108QN ideal for non-volatile memory applications, requiring frequent or rapid  
writes. Examples range from data collection, where the number of write cycles may be critical, to demanding  
industrial controls where the long write time of serial flash or EEPROM can cause data loss.  
The CY15X108QN provides substantial benefits to users of serial EEPROM or flash as a hardware drop-in  
replacement. The CY15X108QN uses the high-speed SPI bus, which enhances the high-speed write capability of  
F-RAM technology. The device incorporates a read-only Device ID and Unique ID features, which allow the host  
to determine the manufacturer, product density, product revision, and unique ID for each part. The device also  
provides a writable, 8-byte serial number registers, which can be used to identify a specific board or a system.  
For a complete list of related resources, click here.  
Logic block diagram  
WP  
256-Byte  
Special Sector  
F-RAM  
CS  
Instruction Decoder  
F-RAM Control  
Control Logic  
Write Protect  
SCK  
SI  
1024K x 8  
F-RAM Array  
Data I/O Register  
SO  
Non-volatile  
Status Register  
Device ID and Serial  
Number Registers  
Datasheet  
2
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Table of contents  
Table of contents  
Features ...........................................................................................................................................1  
Functional description.......................................................................................................................2  
Logic block diagram ..........................................................................................................................2  
Table of contents...............................................................................................................................3  
1 Pinouts ..........................................................................................................................................4  
2 Pin definitions ................................................................................................................................5  
3 Functional overview .......................................................................................................................6  
3.1 Memory architecture ..............................................................................................................................................6  
3.2 SPI bus.....................................................................................................................................................................6  
3.3 SPI overview............................................................................................................................................................6  
3.4 Terms used in SPI protocol ....................................................................................................................................7  
3.4.1 SPI master ............................................................................................................................................................7  
3.4.2 SPI slave ...............................................................................................................................................................7  
3.4.3 Chip select (CS) ....................................................................................................................................................7  
3.4.4 Serial clock (SCK) .................................................................................................................................................7  
3.4.5 Data transmission (SI/SO) ...................................................................................................................................8  
3.4.6 Most significant bit (MSb) ....................................................................................................................................9  
3.4.7 Serial opcode .......................................................................................................................................................9  
3.4.8 Invalid opcode......................................................................................................................................................9  
3.4.9 Status register......................................................................................................................................................9  
3.5 SPI modes..............................................................................................................................................................10  
3.6 Power-up to first access .......................................................................................................................................10  
4 Functional description ..................................................................................................................11  
4.1 Command structure..............................................................................................................................................11  
4.1.1 Write enable control commands.......................................................................................................................12  
4.1.2 Register access commands ...............................................................................................................................13  
4.1.3 Memory operation .............................................................................................................................................14  
4.1.4 Memory write operation commands ................................................................................................................15  
4.1.5 Memory read commands...................................................................................................................................16  
4.1.6 Special sector memory access commands.......................................................................................................17  
4.1.7 Identification and serial number commands...................................................................................................18  
4.1.8 Low power mode commands............................................................................................................................20  
5 Maximum ratings..........................................................................................................................22  
6 Operating range ...........................................................................................................................23  
7 DC electrical characteristics...........................................................................................................24  
8 Data retention and endurance .......................................................................................................26  
9 Capacitance .................................................................................................................................27  
10 Thermal resistance......................................................................................................................28  
11 AC test conditions .......................................................................................................................29  
12 AC switching characteristics ........................................................................................................30  
13 Power cycle timing......................................................................................................................32  
14 Ordering information ..................................................................................................................33  
14.1 Ordering code definitions...................................................................................................................................34  
15 Package diagrams.......................................................................................................................35  
16 Acronyms ...................................................................................................................................38  
17 Document conventions................................................................................................................39  
17.1 Units of measure .................................................................................................................................................39  
Revision history ..............................................................................................................................40  
Datasheet  
3
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Pinouts  
1
Pinouts  
1
2
3
4
8
7
6
5
VDD  
CS  
SO  
DNU  
SCK  
SI  
WP  
VSS  
TOP View  
(Not to Scale)  
Figure 1  
8-pin SOIC pinout  
1
2
3
4
8
7
6
5
VDD  
CS  
SO  
DNU  
SCK  
SI  
WP  
VSS  
TOP View  
(Not to Scale)  
Figure 2  
8-pin GQFN/UFLGA pinout  
Datasheet  
4
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Pin definitions  
2
Pin definitions  
Table 1  
Pin definitions  
Pin name I/O type  
Description  
Chipselect.ThisactiveLOWinputactivatesthedevice.WhenHIGH,thedeviceenters  
low-power standby mode, ignores other inputs, and the output is tristated. When LOW,  
the device internally activates the SCK signal. A falling edge on CS must occur before  
every opcode.  
CS  
Input  
Serial clock. All I/O activity is synchronized to the serial clock. Inputs are latched on  
the rising edge and outputs occur on the falling edge of the serial clock. The clock  
frequency may be any value between 0 and 40 MHz and may be interrupted at any time  
due to its synchronous behavior.  
Serial input. All data is input to the device on this pin. The pin is sampled on the rising  
edge of SCK and is ignored at other times. It should always be driven to a valid logic  
level to meet the power (IDD) specifications.  
SCK  
Input  
Input  
SI[2]  
Serial output. This is the data output pin. It is driven during a read and remains  
Output tristated at all other times. Data transitions are driven on the falling edge of the serial  
clock SCK.  
SO[2]  
Write protect. This active LOW pin prevents write operation to the status register when  
WPEN bit in the status register is set to ‘1. This iscritical because other write protection  
WP  
Input  
features are controlled through thestatus register. A complete explanation of write  
protection is provided in Table 3 and Table 6. This pin must be tied to VDD if not used.  
DNU  
VSS  
Do not use Do not use. Either leave this pin floating (not connected on the board) or tie to VDD  
.
Power  
Ground for the device. Must be connected to the ground of the system.  
supply  
Power  
VDD  
Power supply input to the device.  
supply  
Note  
2. SI may be connected to SO for a single pin data interface.  
Datasheet  
5
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional overview  
3
Functional overview  
The CY15X108QN is a serial F-RAM memory. The memory array is logically organized as 1,048,576 × 8 bits and is  
accessed using an industry-standard serial peripheral interface (SPI) bus. The functional operation of the F-RAM  
is similar to serial flash and serial EEPROMs. The major difference between the CY15X108QN and a serial flash or  
EEPROM with the same pinout is the F-RAM’s superior write performance, high endurance, and low power  
consumption.  
3.1  
Memory architecture  
When accessing CY15X108QN, the user addresses 1,024K locations of eight data bits each. These eight data bits  
are shifted in or out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to  
permit multiple devices on the bus), an opcode, and a three-byte address. The upper four bits of the address  
range are ‘don’t care’ values. The complete address of 20 bits specifies each byte address uniquely.  
Most functions of the CY15X108QN are either controlled by the SPI interface or handled by on-board circuitry. The  
access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. That is,  
the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not necessary to  
poll the device for a ready condition because writes occur at bus speed. By the time a new bus transaction can  
be shifted into the device, a write operation is complete. This is explained in more detail in the interface section.  
3.2  
SPI bus  
The CY15X108QN is an SPI slave device and operates at speeds of up to 40 MHz. This high-speed serial bus  
provides high-performance serial communication to an SPI master. Many common microcontrollers have  
hardware SPI ports allowing a direct interface. It is simple to emulate the port using ordinary port pins for  
microcontrollers that do not have this feature. The CY15X108QN operates in SPI modes 0 and 3.  
3.3  
SPI overview  
The SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial clock (SCK) pins.  
The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports  
multiple devices on the data bus. A device on the SPI bus is activated using the CS pin.  
The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes  
0 and 3. In both of these modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first  
rising edge after CS goes active.  
The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave  
device. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode,  
any addresses and data are then transferred. The CS must go inactive after an operation is complete and before  
a new opcode can be issued.  
Datasheet  
6
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional overview  
3.4  
Terms used in SPI protocol  
The commonly used terms in the SPI protocol are as follows.  
3.4.1  
SPI master  
The SPI master device controls the operations on the SPI bus. An SPI bus may have only one master with one or  
more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices  
using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS  
pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are  
synchronized with this clock.  
3.4.2  
SPI slave  
The SPI slave device is activated by the master through the chip select line. A slave device gets the SCK as an input  
from the SPI master and all the communication is synchronized with this clock. An SPI slave never initiates a  
communication on the SPI bus and acts only on the instruction from the master.  
The CY15X108QN operates as an SPI slave and may share the SPI bus with other SPI slave devices.  
3.4.3  
Chip select (CS)  
To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued  
to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored  
and the serial output pin (SO) remains in a high-impedance state.  
Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each  
active chip select cycle.  
3.4.4  
Serial clock (SCK)  
The serial clock is generated by the SPI master and the communication is synchronized with this clock after CS  
goes LOW.  
The CY15X108QN supports SPI modes 0 and 3 for data communication. In both of these modes, the inputs are  
latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the  
first rising edge of SCK signifies the arrival of the first most significant bit (MSb) of an SPI instruction on the SI pin.  
Further, all data inputs and outputs are synchronized with SCK.  
Datasheet  
7
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional overview  
3.4.5  
Data transmission (SI/SO)  
The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as master  
out slave in (MOSI) and SO is referred to as master in slave out (MISO). The master issues instructions to the slave  
through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO  
lines as described earlier.  
The CY15X108QN has two separate pins for SI and SO, which can be connected with the master as shown in  
Figure 3. For a microcontroller that has no dedicated SPI bus, a general-purpose port may be used. To reduce  
hardware resources on the controller, it is possible to connect the two data pins (SI, SO) together and tie off  
(HIGH) the WP pin. Figure 4 shows such a configuration, which uses only three pins.  
SCK  
MOSI  
MISO  
SCK  
CS  
SI  
SO  
SCK  
CS  
SI  
SO  
SPI Hostcontroller  
or  
CY15x108QN  
CY15x108QN  
SPI Master  
WP  
WP  
CS1  
WP1  
CS2  
WP2  
Figure 3  
System configuration with SPI port  
P1.0  
P1.1  
SCK  
CS  
SI  
SO  
SPI Hostcontroller  
or  
CY15x108QN  
WP  
SPI Master  
P1.2  
Figure 4  
System configuration without SPI port  
Datasheet  
8
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional overview  
3.4.6  
Most significant bit (MSb)  
The SPI protocol requires that the first bit to be transmitted is the MSb. This is valid for both address and data  
transmission.  
The 8-Mb serial F-RAM requires a 3-byte address for any read or write operation. Because the address is only  
20 bits, the first four bits, which are fed in are ignored by the device. Although these four bits are ‘don’t care,  
Infineon recommends that these bits be set to 0s to enable seamless transition to higher memory densities.  
3.4.7  
Serial opcode  
After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the  
intended operation. CY15X108QN uses the standard opcodes for memory accesses.  
3.4.8  
Invalid opcode  
If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI  
pin until the next falling edge of CS, and the SO pin remains tristated.  
3.4.9  
Status register  
CY15X108QN has an 8-bit status register. The bits in the status register are used to configure the device. These  
bits are described in Table 4.  
Datasheet  
9
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional overview  
3.5  
SPI modes  
CY15X108QN may be driven by a microcontroller with its SPI peripheral running in either of the following two  
modes:  
• SPI mode 0 (CPOL = 0, CPHA = 0)  
• SPI mode 3 (CPOL = 1, CPHA = 1)  
For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after  
CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is  
considered. The output data is available on the falling edge of SCK. The two SPI modes are shown in Figure 5 and  
Figure 6. The status of the clock when the bus master is not transferring data is:  
• SCK remains at 0 for mode 0  
• SCK remains at 1 for mode 3  
The device detects the SPI mode from the status of the SCK pin when the device is selected by bringing the CS  
pin LOW. If the SCK pin is LOW when the device is selected, SPI mode 0 is assumed and if the SCK pin is HIGH, it  
works in SPI mode 3.  
CS  
0
1
2
3
4
5
6
7
SCK  
SI  
7
6
5
4
3
2
1
0
Figure 5  
SPI mode 0  
CS  
0
1
2
3
4
5
6
7
SCK  
7
6
5
4
3
2
1
0
SI  
Figure 6  
SPI mode 3  
3.6  
Power-up to first access  
The CY15X108QN is not accessible for a tPU time after power-up. Users must comply with the timing parameter,  
t
PU, which is the minimum time from VDD(min) to the first CS LOW. Refer to “Power cycle timing” on page 32 for  
details.  
Datasheet  
10  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4
Functional description  
4.1  
Command structure  
There are 15 commands, called opcodes, that can be issued by the bus master to the CY15X108QN (see Table 2).  
These opcodes control the functions performed by the memory.  
Table 2  
Opcode commands  
Opcode  
Name  
Description  
Hex  
Binary  
Write enable control  
WREN  
Set write enable latch  
06h  
04h  
0000 0110b  
0000 0100b  
WRDI  
Reset write enable latch  
Register access  
RDSR  
Read status register  
Write status register  
05h  
01h  
0000 0101b  
0000 0001b  
WRSR  
Memory write  
WRITE  
Write memory data  
02h  
0000 0010b  
Memory read  
READ  
Read memory data  
03h  
0Bh  
0000 0011b  
0000 1011b  
FSTRD  
Fast read memory data  
Special sector memory access  
SSWR  
SSRD  
Special sector write  
Special sector read  
42h  
4Bh  
0100 0010b  
0100 1011b  
Identification and serial number  
RDID  
Read device ID  
9Fh  
4Ch  
C2h  
C3h  
1001 1111b  
0100 1100b  
1100 0010b  
11000 011b  
RUID  
Read unique ID  
WRSN  
Write serial number  
Read serial number  
RDSN  
Low power modes  
DPD  
HBN  
Enter deep power-down  
Enter hibernate mode  
BAh  
B9h  
1011 1010b  
1011 1001b  
Unused opcodes are reserved for future  
use.  
Reserved  
Reserved  
Datasheet  
11  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.1  
Write enable control commands  
Set write enable latch (WREN, 06h)  
4.1.1.1  
The CY15X108QN will power up with writes disabled. The WREN command must be issued before any write  
operation. Sending the WREN opcode allows the user to issue subsequent opcodes for write operations. These  
include writing to the status register (WRSR), the memory (WRITE), special sector (SSWR), and write serial number  
(WRSN).  
Sending the WREN opcode causes the internal write enable latch to be set. A flag bit in the status register, called  
WEL, indicates the state of the latch. WEL = ‘1’ indicates that writes are permitted. Attempting to write the WEL  
bit in the status register has no effect on the state of this bit - only the WREN opcode can set this bit. The WEL bit  
will be automatically cleared on the rising edge of CS following a WRDI, a WRSR, a WRITE, a SSWR, or a WRSN  
operation. This prevents further writes to the status register or the F-RAM array without another WREN command.  
Figure 7 illustrates the WREN command bus configuration.  
CS  
0
1
2
3
4
5
6
7
Mode 3  
Mode 0  
SCK  
SI  
SI  
0
0
0
0
0
1
1
0
Hi-Z  
Opcode (06h)  
Figure 7  
WREN bus configuration  
4.1.1.2  
Reset write enable latch (WRDI, 04h)  
The WRDI command disables all write activity by clearing the write enable latch. Verify that the writes are  
disabled by reading the WEL bit in the status register and verify that WEL is equal to ‘0. Figure 8 illustrates the  
WRDI command bus configuration.  
CS  
0
1
2
3
4
5
6
7
SCK  
SI  
0
0
0
0
0
1
0
0
Hi-Z  
SI  
Opcode (04h)  
Figure 8  
WRDI bus configuration  
Datasheet  
12  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.2  
Register access commands  
4.1.2.1  
Status register and write protection  
The write protection features of the CY15X108QN are multi-tiered and are enabled through the status register.  
The status register is organized as follows. (The default value shipped from the factory for WEL, BP0, BP1,  
bits 4–5, and WPEN is ‘0, and for bit 6 is ‘1.)  
Table 3  
Bit 7  
WPEN (0)  
Status register  
Bit 6  
X (1)  
Bit 5  
X (0)  
Bit 4  
X (0)  
Bit 3  
BP1 (0)  
Bit 2  
BP0 (0)  
Bit 1  
WEL (0)  
Bit 0  
X (0)  
Table 4  
Status register bit definition  
Definition  
Bit  
Description  
Bit 0  
Don’t care  
This bit is non-writable and always returns ‘0’ upon read.  
WEL indicates if the device is write enabled. This bit defaults to ‘0’  
(disabled) on power-up.  
Bit 1 (WEL)  
Write enable  
WEL = ‘1’ --> Writeenabled  
WEL = ‘0’ --> Write disabled  
Bit 2 (BP0)  
Bit 3 (BP1)  
Bit 4–5  
Block protect bit ‘0’ Used for block protection. For details, see Table 5.  
Block protect bit ‘1’ Used for block protection. For details, see Table 5.  
Don’t care  
Don’t care  
These bits are non-writable and always return ‘0’ upon read.  
This bit is non-writable and always returns ‘1’ upon read.  
Bit 6  
Used to enable the function of Write Protect Pin (WP). For details, see  
Table 6.  
Bit 7 (WPEN) Writeprotectenablebit  
Bits 0 and 4–5 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none of these bits can be modified. Note that bit 0 (“Ready or  
Write in progress” bit in serial flash and EEPROM) is unnecessary, as the F-RAM writes in real-time and is never  
busy, so it reads out as a ‘0. An exception to this is when the device is waking up either from “Deep power-down  
mode (DPD, BAh)” on page 20 or “Hibernate mode (HBN, B9h)” on page 21. The BP1 and BP0 control the  
software write-protection features and are non-volatile bits. The WEL flag indicates the state of the write enable  
latch. Attempting to directly write the WEL bit in the status register has no effect on its state. This bit is internally  
set and cleared via the WREN and WRDI commands, respectively.  
BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected  
as shown in Table 5.  
Table 5  
Block memory write protection  
BP0  
BP1  
Protected address range  
0
0
1
1
0
1
0
1
None  
C0000h to FFFFFh (upper 1/4)  
80000h to FFFFFh (upper 1/2)  
00000h to FFFFFh (all)  
The BP1 and BP0 bits and the write enable latch are the only mechanismsthatprotectthememoryfromwrites.  
Theremaining writeprotectionfeaturesprotectinadvertentchangestotheblock protect bits.  
The write protect enable bit (WPEN) in the status register controls the effect of the hardware write protect (WP)  
pin. Refer to Figure 24 for the WP pin timing diagram. When the WPEN bit is set to ‘0, the status of the WP pin is  
ignored. When the WPEN bit is set to ‘1, a LOW on the WP pin inhibits a write to the status register. Thus the status  
register is write-protected only when WPEN = ‘1’ and WP = ‘0. Table 6 summarizes the write protection  
conditions.  
Datasheet  
13  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
Table 6  
Write protection  
WEL  
WPEN  
WP  
X
Protected blocks  
Protected  
Unprotected blocks  
Protected  
Status register  
Protected  
0
1
1
1
X
0
1
1
X
Protected  
Unprotected  
Unprotected  
Unprotected  
Unprotected  
Protected  
0
Protected  
1
Protected  
Unprotected  
4.1.2.2  
Read status register (RDSR, 05h)  
The RDSR command allows the bus master to verify the contents of the status register. Reading the status register  
provides information about the current state of the write-protection features. Following the RDSR opcode, the  
CY15X108QN will return one byte with the contents of the status register.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK  
SI  
Hi-Z  
0
0
0
0
0
1
0
1
Hi-Z  
SO  
D7 D6 D5 D4 D3 D2 D1 D0  
MSb LSb  
Opcode (05h)  
Read Data  
Figure 9  
RDSR bus configuration  
4.1.2.3  
Write status register (WRSR, 01h)  
The WRSR command allows the SPI bus master to write into the status register and change the write protect  
configuration by setting the WPEN, BP0, and BP1 bits as required. Before issuing a WRSR command, the WP pin  
must be HIGH or inactive. Note that on the CY15X108QN, WP only prevents writing to the status register, not the  
memory array. Before sending the WRSR command, the user must send a WREN command to enable writes.  
Executing a WRSR command is a write operation and therefore, clears the Write Enable Latch.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK  
SI  
0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0  
MSb LSb  
Hi-Z  
SO  
Opcode (01h)  
Write Data  
Figure 10  
WRSR bus configuration (WREN not shown)  
4.1.3  
Memory operation  
The SPI interface, which is capable of a high clock frequency, highlights the fast write capability of the F-RAM  
technology. Unlike serial flash and EEPROMs, the CY15X108QN can perform sequential writes at bus speed. No  
page register is needed and any number of sequential writes may be performed.  
Datasheet  
14  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.4  
Memory write operation commands  
Write operation (WRITE, 02h)  
4.1.4.1  
All writes to the memory begin with a WREN opcode with CS being asserted and deasserted. The next opcode is  
WRITE. The WRITE opcode is followed by a three-byte address containing the 20-bit address (A19–A0) of the first  
data byte to be written into the memory. The upper four bits of the three-byte address are ignored. Subsequent  
bytes are data bytes, which are written sequentially. Addresses are incremented internally as long as the bus  
master continues to issue clocks and keeps CS LOW. If the last address of FFFFFh is reached, the internal address  
counter will roll over to 00000h. Every data byte to be written is transmitted on SI in 8-clock cycles with MSb first  
and the LSb last. The rising edge of CS terminates a write operation. The CY15X108QN write operation is shown  
in Figure 11.  
Notes:  
• When a burst write reaches a protected block address, the automatic address increment stops and all the  
subsequent data bytes received for write will be ignored by the device. EEPROMs use page buffers to increase  
their write throughput. This compensates for the technology’s inherently slow write operations. F-RAM  
memories do not have page buffers because each byte is written to the F-RAM array immediately after it is  
clocked in (after the eighth clock). This allows any number of bytes to be written without page buffer delays.  
• If power is lost in the middle of the write operation, only the last completed byte will be written.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23  
0
1
2
3
4
5
6
7
SCK  
SI  
A23 A22 A21 A20  
A3  
A2  
A1 A0  
0
0
0
0
0
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0  
MSb  
LSb  
Hi-Z  
Hi-Z  
SO  
Opcode (02h)  
Address  
Write Data  
Figure 11  
Memory write (WREN not shown) operation  
Datasheet  
15  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.5  
Memory read commands  
4.1.5.1  
Read operation (READ, 03h)  
After the falling edge of CS, the bus master can issue a READ opcode. Following the READ command is a three-byte  
address containing the 20-bit address (A19–A0) of the first byte of the read operation. The upper four bits of the  
address are ignored. After the opcode and address are issued, the device drives out the read data on the next  
eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes, which are read out  
sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks and CS is  
LOW. If the last address of FFFFFh is reached, the internal address counter will roll over to 00000h. Every read data  
byte on SO is driven in 8-clock cycles with MSb first and the LSb last. The rising edge of CS terminates a read  
operation and tristates the SO pin. The CY15X108QN read operation is shown in Figure 12.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23  
0
1
2
3
4
5
6
7
SCK  
SI  
Hi-Z  
A23 A22 A21 A20  
A3  
A2  
A1 A0  
0
0
0
0
0
0
1
1
Hi-Z  
SO  
D7 D6 D5 D4 D3 D2 D1 D0  
MSb LSb  
Opcode (03h)  
Address  
Read Data  
Figure 12  
Memory read operation  
4.1.5.2  
Fast read operation (FAST_READ, 0Bh)  
The CY15X108QN supports a FAST READ opcode (0Bh) that is provided for opcode compatibility with serial flash  
devices. The FAST READ opcode is followed by a three-byte address containing the 20-bit address (A19–A0) of the  
first byte of the read operation and then a dummy byte. The dummy byte inserts a read latency of 8-clock cycle.  
The fast read operation is otherwise the same as an ordinary read operation except that it requires an additional  
dummy byte. After receiving the opcode, address, and a dummy byte, the CY15X108QN starts driving its SO line  
with data bytes, with MSb first, and continues transmitting as long as the device is selected and the clock is  
available. In case of bulk read, the internal address counter is incremented automatically, and after the last  
address FFFFFh is reached, the internal address counter rolls over to 00000h. When the device is driving data on  
its SO line, any transition on its SI line is ignored. The rising edge of CS terminates a fast read operation and  
tristates the SO pin. The CY15X108QN Fast Read operation is shown in Figure 13.  
Note The dummy byte can be any 8-bit value but Axh (8’b1010xxxx). The lower 4 bits of Axh are don’t care bits.  
Hence, Axh essentially represents 16 different 8-bit values which shouldn’t be transmitted as the dummy byte.  
00h is typically used as the dummy byte in most use cases.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK  
SI  
Hi-Z  
A23 A22 A21 A20  
MSb  
A3  
A2  
A1 A0  
0
0
0
0
1
0
1
x
x
x
x
x
x
x
x
1
LSb  
Hi-Z  
SO  
D7 D6 D5 D4 D3 D2 D1 D0  
MSb  
LSb  
Opcode (0Bh)  
Address  
Dummy Byte  
Read Data  
Figure 13  
Fast read operation  
Datasheet  
16  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.6  
Special sector memory access commands  
Special sector write (SSWR, 42h)  
4.1.6.1  
All writes to the 256-byte special begin with a WREN opcode with CS being asserted and deasserted. The next  
opcode is SSWR. The SSWR opcode is followed by a three-byte address containing the 8-bit sector address  
(A7–A0) of the first data byte to be written into the special sector memory. The upper 16 bits of the three-byte  
address are ignored. Subsequent bytes are data bytes, which are written sequentially. Addresses are  
incremented internally as long as the bus master continues to issue clocks and keeps CS LOW. Once the internal  
address counter auto increments to XXXFFh, CS should toggle HIGH to terminate the ongoing SSWR operation.  
Every data byte to be written is transmitted on SI in 8-clock cycles with MSb first and the LSb last. The rising edge  
of CS terminates a write operation. The CY15X108QN special sector write operation is shown in Figure 14.  
Notes  
• If power is lost in the middle of the write operation, only the last completed byte will be written.  
• The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow  
soldering.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23  
0
1
2
3
4
5
6
7
SCK  
SI  
A23 A22 A21 A20  
A3  
A2  
A1 A0  
0
1
0
0
0
0
1
D7 D6  
MSb  
D5  
D4 D3  
D2  
D1  
D0  
0
LSb  
Hi-Z  
Hi-Z  
SO  
Opcode (42h)  
Address  
Write Data  
Figure 14  
Special sector write (WREN not shown) operation  
4.1.6.2  
Special sector read (SSRD, 4Bh)  
After the falling edge of CS, the bus master can issue an SSRD opcode. Following the SSRD command is a  
three-byte address containing the 8-bit address (A7–A0) of the first byte of the special sector read operation. The  
upper 16 bits of the address are ignored. After the opcode and address are issued, the device drives out the read  
data on the next eight clocks. The SI input is ignored during read data bytes. Subsequent bytes are data bytes,  
which are read out sequentially. Addresses are incremented internally as long as the bus master continues to  
issue clocks and CS is LOW. Once the internal address counter auto increments to XXXFFh, CS should toggle HIGH  
to terminate the ongoing SSRD operation. Every read data byte on SO is driven in 8-clock cycles with MSb first  
and the LSb last. The rising edge of CS terminates a special sector read operation and tristates the SO pin. The  
CY15X108QN special sector read operation is shown in Figure 15.  
Note The special sector F-RAM memory guarantees to retain data integrity up to three cycles of standard reflow  
soldering.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
20 21 22 23  
0
1
2
3
4
5
6
7
SCK  
SI  
Hi-Z  
A23 A22 A21 A20  
A3  
A2  
A1 A0  
0
1
0
0
1
0
1
1
Hi-Z  
SO  
D7 D6 D5 D4 D3 D2 D1 D0  
MSb LSb  
Opcode (4Bh)  
Address  
Read Data  
Figure 15  
Special sector read operation  
Datasheet  
17  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.7  
Identification and serial number commands  
Read device ID (RDID, 9Fh)  
4.1.7.1  
The CY15X108QN device can be interrogated for its manufacturer, product identification, and die revision. The  
RDID opcode 9Fh allows the user to read the 9-byte manufacturer ID and product ID, both of which are read-only  
bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7; therefore, there are six bytes  
of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which includes  
a family code, a density code, a sub code, and the product revision code. Table 7 shows 9-byte device ID field  
description. Refer to “Ordering information” on page 33 for 9-byte device ID of an individual part. The  
CY15X108QN read device ID operation is shown in Figure 16.  
Note The least significant data byte (byte 0) shifts out first and the most significant data byte (byte 8) shifts out  
last.  
Table 7  
9-byte device ID  
Device ID field description  
Manufacturer ID  
Family  
[15:13]  
Density  
Inrush  
[8]  
Sub type Revision Voltage  
Frequency  
[1:0]  
[71:16]  
[12:9]  
[7:5]  
[4:3]  
[2]  
56-bit  
3-bit  
4-bit  
1-bit  
3-bit  
2-bit  
1-bit  
2-bit  
Refer to “Ordering information” on page 33 for 9-Byte device ID of an individual part.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
60 61 62 63 64 65 66 67 68 69 70 71  
SCK  
SI  
Hi-Z  
1
0
0
1
1
1
1
1
MSb  
D7  
LSb  
Hi-Z  
D6  
D5  
D4  
D3  
D2  
D1 D0  
SO  
D7 D6  
D5  
D4  
D3  
D2  
D1  
D0  
Byte 0  
Byte 8  
Opcode (9Fh)  
9-Byte Device ID  
Figure 16  
Read device ID  
4.1.7.2  
Read unique ID (RUID, 4Ch)  
The CY15X102QN device can be interrogated for unique ID which is a factory programmed, 64-bit number unique  
to each device. The RUID opcode, 4Ch allows to read the 8-byte, read only unique ID. The CY15X102QN read  
unique ID operation is shown in Figure 17.  
Notes:  
• The least significant data byte (byte 0) shifts out first and the most significant data byte (byte 7) shifts out last.  
• The unique ID registers are guaranteed to retain data integrity of up to three cycles of the standard reflow  
soldering.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63  
SCK  
SI  
Hi-Z  
0
1
0
0
1
1
0
0
MSb  
D7  
LSb  
Hi-Z  
D6  
D5  
D4  
D3  
D2  
D1 D0  
SO  
D7 D6  
D5  
D4  
D3  
D2  
D1  
D0  
Byte 0  
Byte 7  
Opcode (4Ch)  
8-Byte Unique ID  
Figure 17  
Read unique ID  
Datasheet  
18  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.7.3  
Write serial number (WRSN, C2h)  
The serial number is an 8-byte one-time programmable memory space provided to the user to uniquely identify  
a PC board or a system. A serial number typically consists of a two-byte customer ID, followed by five bytes of a  
unique serial number and one byte of CRC check. However, the end application can define its own format for the  
8-byte serial number. All writes to the serial number register begin with a WREN opcode with CS being asserted  
and deasserted. The next opcode is WRSN. The WRSN instruction can be used in burst mode to write all the  
8 bytes of serial number. After the last byte of the serial number is shifted in, CS must be driven high to complete  
the WRSN operation. The CY15X108QN write serial number operation is shown in Figure 18.  
Note: The CRC checksum is not calculated by the device. The system firmware must calculate the CRC checksum  
on the 7-byte content and append the checksum to the 7-byte user-defined serial number before programming  
the 8-byte serial number into the serial number register. The factory default value for the 8-byte Serial Number  
is ‘0000000000000000h.  
Table 8  
8-byte serial number  
16-bit customer identifier  
40-bit unique number  
SN[39:32] SN[31:24] SN[23:16]  
8-bit CRC  
SN[7:0]  
SN[63:56]  
SN[55:48]  
SN[47:40]  
SN[15:8]  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63  
SCK  
SI  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
1
0
0
0
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0  
LSb  
MSb  
Hi-Z  
Hi-Z  
SO  
Opcode (C2h)  
Write 8-Byte Serial Number  
Figure 18  
Write serial number (WREN not shown) operation  
4.1.7.4  
Read serial number (RDSN, C3h)  
The CY15X108QN device incorporates an 8-byte serial space provided to the user to uniquely identify the device.  
The serial number is read using the RDSN instruction. A serial number read may be performed in burst mode to  
read all the eight bytes at once. After the last byte of the serial number is read, the device loops back to the first  
byte of the serial number. An RDSN instruction can be issued by shifting the opcode for RDSN after CS goes LOW.  
The CY15X108QN read serial number operation is shown in Figure 19.  
Note: The least significant data byte (Byte 0) shifts out first and the most significant data byte (Byte 7) shifts out  
last.  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
52 53 54 55 56 57 58 59 60 61 62 63  
SCK  
SI  
Hi-Z  
1
1
0
0
0
0
1
1
MSb  
D7  
LSb  
Hi-Z  
D6  
D5  
D4  
D3  
D2  
D1 D0  
SO  
D7 D6  
D5  
D4  
D3  
D2  
D1  
D0  
Byte 0  
Byte 7  
Opcode (C3h)  
8-Byte Serial Number  
Figure 19  
Read serial number operation  
Datasheet  
19  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.8  
Low power mode commands  
4.1.8.1  
Deep power-down mode (DPD, BAh)  
A power-saving deep power-down mode is implemented on the CY15X108QN device. The device enters the deep  
power-down mode after tENTDPD time after the DPD opcode BAh is clocked in and a rising edge of CS is applied.  
When in deep power-down mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues  
to monitor the CS pin.  
A CS pulse-width of tCSDPD exits the DPD mode after tEXTDPD time. The CS pulse-width can be generated either by  
sending a dummy command cycle or toggling CS alone while SCK and I/Os are don’t care. The I/Os remain in hi-Z  
state during the wakeup from deep power down. Refer to Figure 20 for DPD entry and Figure 21 for DPD exit  
timing.  
E n te rs D P D  
tE N T D P D  
C S  
0
1
2
3
4
5
6
7
S C K  
S I  
1
0
1
1
1
0
1
0
h i-Z  
S O  
O p c o d e (B A h )  
Figure 20  
DPD entry timing  
tE  
X T D P D  
tC  
S
D P D  
C S  
0
1
2
S C K  
tS U  
X
I/O s  
Figure 21  
DPD exit timing  
Datasheet  
20  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Functional description  
4.1.8.2  
Hibernate mode (HBN, B9h)  
A lowest power hibernate mode is implemented on the CY15X108QN device. The device enters hibernate mode  
after tENTHIB time after the HBN opcode B9h is clocked in and a rising edge of CS is applied. When in hibernate  
mode, the SCK and SI pins are ignored and SO will be Hi-Z, but the device continues to monitor the CS pin. On the  
next falling edge of CS, the device will return to normal operation within tEXTHIB time. The SO pin remains in a Hi-Z  
state during the wakeup from hibernate period. The device does not necessarily respond to an opcode within the  
wakeup period. To exit the hibernate mode, the controller may send a “dummy” read, for example, and wait for  
the remaining tEXTHIB time.  
E nters  
H ibernate M ode  
R ecovers from  
H ibernate M ode  
tE N T H IB  
tE X T H IB  
C S  
0
1
2
3
4
5
6
7
0
1
2
S C K  
tS U  
S I  
1
0
1
1
1
0
0
1
hi-Z  
S O  
O pcode (B 9h )  
Figure 22  
Hibernate mode operation  
4.1.8.3  
Endurance  
The CY15X108QN devices are capable of being accessed at least 1015 times, reads or writes.  
An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a  
row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows  
and columns of 128K rows of 64-bit each. The entire row is internally accessed once, whether a single byte or all  
eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. Table 9  
shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a  
sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop.  
F-RAM read and write endurance is virtually unlimited at a 40-MHz clock rate.  
Table 9  
Time to reach endurance limit for repeating 64-byte loop  
SCK freq (MHz)  
Endurance cycles/sec  
Endurance cycles/year  
2.30 × 1012  
Years to reach 1015 limit  
40  
20  
10  
5
73,040  
36,520  
18,380  
9,190  
432  
864  
1727  
3454  
1.16 × 1012  
5.79 × 1011  
2.90 × 1011  
Datasheet  
21  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Maximum ratings  
5
Maximum ratings  
Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested.  
Table 10 Absolute maximum ratings  
Parameter  
Max ratings  
Storage temperature  
–65°C to +125°C  
Maximum accumulated storage time  
At 125°C ambient temperature  
At 85°C ambient temperature  
Maximum junction temperature  
1000 h  
10 Years  
125°C  
Supply voltage on VDD relative to VSS  
CY15V108QN:  
CY15B108QN:  
:
–0.5 V to +2.4 V  
–0.5 V to +4.1 V  
VIN VDD + 0.5 V  
–0.5 V to VDD + 0.5 V  
–2.0 V to VDD + 2.0 V  
1.0 W  
Input voltage  
DC voltage applied to outputs in High-Z state  
Transient voltage (< 20 ns) on any pin to ground potential  
Package power dissipation capability (TA = 25°C)  
Surface mount lead soldering temperature (3 seconds)  
DC output current (1 output at a time, 1s duration)  
Electrostatic discharge voltage  
+260°C  
15 mA  
Human Body Model (JEDEC Std JESD22-A114-B)  
Charged Device Model (JEDEC Std JESD22-C101-A)  
Latch-up current  
2 kV  
500 V  
> 140 mA  
Datasheet  
22  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Operating range  
6
Operating range  
Table 11  
Operating range  
Device  
CY15V108QN  
CY15B108QN  
CY15V108QN  
CY15B108QN  
Range  
Ambient temperature  
VDD  
1.71 V to 1.89 V  
1.8 V to 3.6 V  
1.71 V to 1.89 V  
1.8 V to 3.6 V  
Commercial  
0°C to +70°C  
Industrial  
–40°C to +85°C  
Datasheet  
23  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
DC electrical characteristics  
7
DC electrical characteristics  
Table 12  
DC electrical characteristics  
Over the Operating range  
Parameter Description  
[3, 4]  
Test conditions  
CY15V108QN  
Temperature  
Min  
1.71  
1.80  
Max  
1.89  
3.60  
0.38  
1.5  
Unit  
Typ  
1.80  
V
Power supply  
V
DD  
CY15B108QN  
= 1.71 V to 1.89 V;  
3.30  
0.3  
V
f
f
f
= 1 MHz  
= 20 MHz  
= 1 MHz  
DD  
SCK  
SCK  
SCK  
Commercial  
Industrial  
SCK toggling between  
– 0.2 V and V ,  
1.3  
0.3  
V
DD  
SS  
other inputs  
0.58  
V
or V – 0.2 V.  
DD  
SS  
SO = Open;  
CY15V108QN-20LP  
part  
f
= 20 MHz  
1.3  
1.6  
SCK  
V
= 1.8 V to 3.6 V;  
f
f
f
= 1 MHz  
= 20 MHz  
= 1 MHz  
0.35  
1.4  
0.52  
1.6  
DD  
SCK  
SCK  
SCK  
Commercial  
Industrial  
SCK toggling between  
– 0.2 V and V ,  
V
DD  
SS  
other inputs  
0.35  
0.7  
V
or V – 0.2 V.  
DD  
SS  
SO = Open;  
f
= 20 MHz  
1.4  
1.75  
SCK  
CY15B108N-20LP part  
V
supply  
V
= 1.71 V to 1.89 V;  
DD  
DD  
I
mA  
DD  
current  
SCK toggling between  
– 0.2 V and V ,  
V
DD  
SS  
other inputs  
f
= 40 MHz  
Industrial  
Industrial  
2.6  
3.2  
SCK  
V
or V – 0.2 V.  
DD  
SS  
SO = Open;  
CY15V108QN-40LP  
parts  
V
= 1.8 V to 3.6 V;  
DD  
SCK toggling  
between  
V
– 0.2 V and V ,  
SS  
DD  
f
= 40 MHz  
2.6  
3.2  
other inputs  
SCK  
V
or V – 0.2 V.  
SS  
DD  
SO = Open;  
CY15B108QN-40LP  
parts  
V
= 1.71 V to 1.89 V; T = 25°C  
3.5  
DD  
A
CS = V  
All other inputs V or  
V
.
T = 70°C  
52  
DD  
A
SS  
T = 85°C  
110  
A
.
V
standby  
DD  
DD  
I
µA  
SB  
current  
V
= 1.8 V to 3.6 V;  
T = 25°C  
3.8  
DD  
A
CS = V  
All other inputs V or  
V
.
DD  
T = 70°C  
55  
A
SS  
T = 85°C  
120  
A
.
DD  
Notes  
3. Typical values are at 25°C, V = V (typ).  
DD  
DD  
4. This parameter is guaranteed by characterization; not tested in production.  
Datasheet  
24  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
DC electrical characteristics  
Table 12  
DC electrical characteristics (continued)  
Over the Operating range  
Parameter Description  
[3, 4]  
Test conditions  
= 1.71 V to 1.89 V; T = 25°C  
Temperature  
Min  
Max  
Unit  
Typ  
0.9  
V
DD  
A
CS = V  
All other inputs V or  
.
T = 70°C  
11  
DD  
A
SS  
T = 85°C  
24  
Deep  
A
V
.
DD  
I
I
power-down  
current  
µA  
DPD  
V
= 1.8 V to 3.6 V;  
T = 25°C  
1
DD  
A
CS = V  
.
T = 70°C  
12  
DD  
A
All other inputs V or  
SS  
T = 85°C  
26  
A
V
.
DD  
V
= 1.71 V to 1.89 V; T = 25°C  
0.1  
DD  
A
CS = V  
All other inputs V or  
V
.
DD  
T = 70°C  
0.4  
A
SS  
T = 85°C  
0.9  
A
.
DD  
Hibernate  
µA  
HBN  
mode current  
V
= 1.8 V to 3.6 V;  
T = 25°C  
0.1  
DD  
A
CS = V  
All other inputs V or  
V
.
DD  
T = 70°C  
0.75  
A
SS  
T = 85°C  
1.6  
A
.
DD  
Input leakage  
current on I/O  
pins except  
WP pin  
–1  
1
I
I
V
< V < V  
LI  
SS  
IN  
DD  
Input leakage  
current on WP  
pin  
µA  
–100  
–1  
1
1
Output  
leakage  
current  
V
< V  
< V  
DD  
LO  
SS  
OUT  
Input HIGH  
voltage  
V
V
V
V
V
V
I
0.7 × V  
–0.3  
2.4  
V
+ 0.3  
DD  
IH  
DD  
Input LOW  
voltage  
0.3 × V  
IL  
DD  
Output HIGH  
voltage  
= –1 mA, V = 2.7 V.  
OH1  
OH2  
OL1  
OL2  
DD  
OH  
OH  
OL  
OL  
V
Output HIGH  
voltage  
I
I
I
= –100 µA  
V
– 0.2  
DD  
Output LOW  
voltage  
= 2 mA, V = 2.7 V  
0.4  
0.2  
DD  
Output LOW  
voltage  
= 150 µA  
Notes  
3. Typical values are at 25°C, V = V (typ).  
DD  
DD  
4. This parameter is guaranteed by characterization; not tested in production.  
Datasheet  
25  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Data retention and endurance  
8
Data retention and endurance  
Table 13  
Data retention and endurance  
Parameter  
Description  
Test condition  
Min  
10  
141  
151  
160  
1015  
Max  
Unit  
Years  
Cycles  
TA = 85°C  
TA = 70°C  
TA = 60°C  
TA = 50°C  
TDR  
NVC  
Data retention  
Endurance  
Over operating temperature  
Datasheet  
26  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Capacitance  
9
Capacitance  
Table 14  
Capacitance  
For all packages.  
Parameter [5]  
Description  
Test conditions  
Max  
Unit  
CO  
CI  
Output pin capacitance (SO)  
Input pin capacitance  
8
6
TA = 25°C, f = 1 MHz, VDD = VDD(typ)  
pF  
Note  
5. This parameter is guaranteed by characterization; not tested in production.  
Datasheet  
27  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Thermal resistance  
10  
Thermal resistance  
Table 15  
Thermal resistance  
8-pin SOIC 8-pin GQFN 8-pin UFLGA  
Parameter[6]  
Description  
Test conditions  
Test conditions  
Unit  
package  
package  
package  
Thermal resistance  
(junction to ambient) follow standard test  
methods and  
ΘJA  
81.5  
113.5  
103.5  
procedures for  
°C/W  
Thermal resistance  
measuring thermal  
ΘJC  
96.5  
99  
35.3  
(junction to case)  
impedance, per  
EIA/JESD51.  
Note  
6. This parameter is guaranteed by characterization; not tested in production.  
Datasheet  
28  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
AC test conditions  
11  
AC test conditions  
Table 16  
AC test conditions  
Parameter  
Value  
10% and 90% of VDD  
3 ns  
Input pulse levels  
Input rise and fall times  
Input and output timing reference levels  
Output load capacitance  
0.5 × VDD  
30 pF  
Datasheet  
29  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
AC switching characteristics  
12  
AC switching characteristics  
Table 17  
AC switching characteristics  
Over the Operating range  
Parameters[7]  
20 MHz  
40 MHz  
Description  
Unit  
Alt.  
Parameter  
Min  
Max  
Min  
Max  
parameter  
fSCK  
tCH  
tCL  
SCK clock frequency  
Clock HIGH time  
0
22  
22  
0
20  
0
11  
11  
0
40  
MHz  
Clock LOW time  
8]  
[
tCLZ  
tCSS  
tCSH  
Clock LOW to Output low-Z  
Chip select setup  
tCSU  
tCSH  
10  
10  
10  
5
Chip select hold - SPI mode 0  
Chip select hold - SPI mode 3  
Output disable time  
Output data valid time  
Output hold time  
5
tCSH1  
tHZCS  
tCO  
10  
9 10]  
[ ,  
20  
20  
12  
9
tOD  
tODV  
ns  
tOH  
1
1
tD  
tCS  
Deselect time  
60  
5
40  
5
tSD  
tSU  
tH  
Data setup time  
tHD  
Data hold time  
5
5
tWPS  
tWPH  
tWHSL  
tSHWL  
WP setup time (w.r.t. CS)  
WP hold time (w.r.t. CS)  
20  
20  
20  
20  
Notes  
7. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input  
pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance  
shown in “AC test conditions” on page 29.  
8. Guaranteed by design.  
9. tHZCS is specified with a load capacitance of 5 pF. Transition is measured when the output enters a  
high-impedance state.  
10.This parameter is guaranteed by characterization; not tested in production.  
Datasheet  
30  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
AC switching characteristics  
tCS  
CS  
tCSS  
tCH  
tCL  
tCSH1  
tCSH  
Mode 3  
Mode 0  
SCK  
SI  
tSD  
tHD  
X
X
VALID DATA IN  
tCO  
tOH  
tHZCS  
tCLZ  
Hi-Z  
Hi-Z  
SO  
X
DATA OUT  
X
Figure 23  
Synchronous data timing (Mode 0 and Mode 3)  
tWPS  
tWPH  
CS  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK  
SI  
0
0
0
0
0
0
0
1
D7 D6 D5 D4 D3 D2 D1 D0  
MSb LSb  
Hi-Z  
SO  
Opcode (01h)  
Write Data  
Figure 24  
Write protect timing during write status register (WRSR) operation  
Datasheet  
31  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Power cycle timing  
13  
Power cycle timing  
Table 18  
Power cycle timing  
Over the Operating range  
Parameters[11]  
Description  
Min  
Max  
Unit  
Alt.  
Parameter  
parameter  
tPU  
Power-up VDD(min) to first access (CS LOW)  
VDD power-up ramp rate  
450  
30  
µs  
[12]  
tVR  
tVF  
µs/V  
[12, 13]  
14  
VDD power-down ramp rate  
20  
CS high to enter deep power-down (CS HIGH to  
hibernate mode current)  
[
]
3
tENTDPD  
tCSDPD  
tDP  
CS pulse width to wake up from deep power-down  
mode  
0.015 4 × 1/fSCK  
Recovery time from deep power-down mode (CS LOW  
to ready for access)  
10  
3
µs  
tEXTDPD  
tRDP  
Time to enter hibernate (CS HIGH to enter hibernate  
mode current)  
[15]  
tENTHIB  
Recovery time from hibernate mode (CS LOW to ready  
for access)  
[15]  
450  
tEXTHIB  
tREC  
V
DD(low)[13]  
Low VDD where initialization must occur  
VDD(low) time when VDD(low) at 0.6 V  
VDD(low) time when VDD(low) at VSS  
0.6  
130  
70  
V
[13]  
tPD  
µs  
VDD  
VDD  
VDD (max)  
No Device Access  
Allowed  
VDD (max)  
VDD (min)  
Device Access  
Allowed  
tVF tVR  
VDD (min)  
tVR  
tPU  
Device Access  
Allowed  
tPU  
VDD (low)  
tPD  
Time  
Time  
Figure 25  
Notes  
Power cycle timing  
11.Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse  
levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30-pF load capacitance shown  
in “AC test conditions” on page 29.  
12.Slope measured at any point on the VDD waveform.  
13.This parameter is guaranteed by characterization; not tested in production.  
14.Guaranteed by design. Refer to Figure 20 for Deep power down mode timing.  
15.Guaranteed by design. Refer to Figure 22 for Hibernate mode timing.  
Datasheet  
32  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Ordering information  
14  
Ordering information  
Table 19  
Ordering information  
Package  
diagram  
Operating  
range  
Ordering code  
Device ID  
Package type  
CY15B108QN-40SXI  
CY15B108QN-40SXIT  
CY15B108QN-20LPXC  
CY15B108QN-20LPXCT  
CY15V108QN-20LPXC  
CY15V108QN-20LPXCT  
CY15B108QN-20LPXI  
CY15B108QN-20LPXIT  
CY15V108QN-20LPXI  
CY15V108QN-20LPXIT  
CY15B108QN-40LPXI  
CY15B108QN-40LPXIT  
CY15V108QN-40LPXI  
CY15V108QN-40LPXIT  
CY15B108QN-20BFXI  
CY15B108QN-20BFXIT  
CY15B108QN-40BFXI  
CY15B108QN-40BFXIT  
CY15V108QN-20BFXI  
CY15V108QN-20BFXIT  
CY15V108QN-40BFXI  
CY15V108QN-40BFXIT  
7F7F7F7F7F7FC22E03  
001-85261 8-pin SOIC (EIAJ)  
Industrial  
7F7F7F7F7F7FC22EA1  
7F7F7F7F7F7FC22EA5  
7F7F7F7F7F7FC22E01  
7F7F7F7F7F7FC22E05  
7F7F7F7F7F7FC22E03  
7F7F7F7F7F7FC22E07  
7F7F7F7F7F7FC22E01  
7F7F7F7F7F7FC22E03  
7F7F7F7F7F7FC22E05  
7F7F7F7F7F7FC22E07  
Commercial  
002-18131 8-pin GQFN (NRND)[16]  
Industrial  
002-34146 8-pin UFLGA  
Industrial  
All these parts are Pb-free. Contact your local sales representative for availability of these parts.  
Note  
16.NRND - Not Recommended for New Designs  
Datasheet  
33  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Ordering information  
14.1  
Ordering code definitions  
CY 15  
B
108  
Q
- 20 LP  
X
C
T
N
Options:  
Blank = Standard; T = Tape and reel  
Temperature range:  
C = Commercial (0°C to +70°C);  
I = Industrial (40°C to +85°C)  
X = Pb-free  
Package type:  
LP = 8-pin GQFN;  
S = 8-pin SOIC (EIAJ);  
BF = 8-pin UFLGA  
Frequency:  
20 = 20 MHz;  
40 = 40 MHz  
N = No inrush current control  
Interface: Q = SPI F-RAM  
Density: 108 = 8-Mbit  
Voltage:  
B = 1.8 V to 3.6 V;  
V = 1.71 V to 1.89 V  
15 = F-RAM  
CY = CYPRESS (An Infineon company)  
Datasheet  
34  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Package diagrams  
15  
Package diagrams  
001-85261 Rev. **  
Figure 26  
8-pin SOIC (208 Mils) SZ820 package outline, 001-85261  
Datasheet  
35  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Package diagrams  
TOP VIEW  
BOTTOM VIEW  
SIDE VIEW  
DIMENSIONS  
SYMBOL  
NOTES:  
MIN.  
NOM.  
0.65 BSC  
8
MAX.  
1. ALL DIMENSIONS ARE IN MILLIMETERS.  
e
N
L
0.40  
0.45  
0.30  
3.23  
3.28  
0.50  
-
0.50  
0.55  
0.35  
3.28  
3.33  
0.55  
0.05  
0.30  
0.35  
0.25  
3.18  
3.23  
0.45  
0.00  
L1  
b
D
E
A
A1  
002-18131 Rev. *C  
Figure 27  
8-pin GQFN (3.23 × 3.28 × 0.55 mm) LP08A package outline, 002-18131  
Datasheet  
36  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Package diagrams  
A
D
7 X L  
(datum A)  
B
E
8
1
5
4
5
8
5
(datum B)  
PIN 1 INDEX  
AREA  
L2  
C0.10  
3
0.10  
C
2X  
4
1
2X  
0.10 C  
SEE DETAIL A  
4
N X b  
e
0.15 M C  
0.08 M C  
A B  
TOP VIEW  
(ND-1) X e  
(datum A)  
BOTTOM VIEW  
L
0.10 C  
0.08  
SEATING PLANE  
C
A
C
L1  
e/2  
SIDE VIEW  
TERMINAL TIP  
3
e
DETAIL A  
DIMENSIONS  
NOTES:  
SYMBOL  
MIN.  
NOM.  
MAX.  
1. ALL DIMENSIONS ARE IN MILLIMETERS.  
2. N IS THE TOTAL NUMBER OF LANDS.  
3. DIMENSION "b" IS MEASURED AT THE MAXIMUM  
LAND WIDTH IN A PLANE PARALLEL TO DATUM C.  
e
N
0.65 BSC  
8
4
ND  
L
4. ND REFERS TO THE NUMBER OF LANDS ON D SIDE.  
0.40  
0.30  
0.50  
0.35  
0.30  
0.25  
5. PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE  
INDICATED ZONE.  
b
D
3.28 BSC  
3.23 BSC  
E
A
0.55  
0.55  
-
-
L1  
L2  
0.10 REF  
0.45  
0.35  
002-34146 Rev. **  
Figure 28  
8-pin UFLGA (3.28 × 3.23 × 0.55 mm) BF08A package outline, 002-34146  
Datasheet  
37  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Acronyms  
16  
Acronyms  
Table 20  
Acronym  
CPHA  
CPOL  
EEPROM  
EIA  
F-RAM  
GQFN  
I/O  
Acronyms used in this document  
Description  
clock phase  
clock polarity  
electrically erasable programmable read-only memory  
electronic industries alliance  
ferroelectric random access memory  
grid array flat no-lead  
input/output  
JEDEC  
JESD  
LSb  
Joint Electron Devices Engineering Council  
JEDEC standards  
least significant bit  
MSb  
most significant bit  
RoHS  
SOIC  
SPI  
restriction of hazardous substances  
small outline integrated circuit  
serial peripheral interface  
ultra thin fine-pitch land grid array  
UFLGA  
Datasheet  
38  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Document conventions  
17  
Document conventions  
17.1  
Units of measure  
Table 21  
Symbol  
°C  
Units of measure  
Unit of measure  
degree Celsius  
hertz  
Hz  
kHz  
kΩ  
kilohertz  
kilohm  
Mb  
MHz  
µA  
µF  
µs  
mA  
ms  
ns  
megabit  
megahertz  
microampere  
microfarad  
microsecond  
milliampere  
millisecond  
nanosecond  
ohm  
Ω
%
percent  
pF  
V
picofarad  
volt  
W
watt  
Datasheet  
39  
002-21761 Rev. *L  
2023-06-07  
8Mb EXCELON™ LP Ferroelectric RAM (F-RAM)  
Serial (SPI), 1024K × 8, 40 MHz, industrial  
Revision history  
Revision history  
Document  
Date  
Description of changes  
revision  
*I  
2019-07-15  
Post to external web.  
Updated Document Title to read as “CY15B108QN, CY15V108QN, 8Mb  
EXCELON™ LP Ferroelectric RAM(F-RAM) Serial (SPI), 1024K × 8, 40 MHz,  
industrial.  
*J  
2022-02-01  
2022-09-07  
Migrated to Infineon template.  
Updated Pin definitions:  
Updated Table 1.  
Updated Functional description:  
Updated Command structure:  
Updated Low power mode commands:  
Updated Endurance:  
*K  
Updated description.  
Updated to new template.  
Added 8-pin UFLGA package related information in all instances across the  
document.  
Updated Features:  
Added Note 1 and referred the same note in “8-pin grid-array quad flat  
no-lead (GQFN) package (NRND).  
Updated Ordering information:  
Updated Table 19 (Updated part numbers; updated details under “Package  
type” column).  
*L  
2023-06-07  
Added Note 16 and referred the same note in “8-pin GQFN (NRND)” in  
Table 19.  
Updated Ordering code definitions.  
Updated Package diagrams:  
Added spec 002-34146 Rev. **.  
Updated to new template.  
Datasheet  
40  
002-21761 Rev. *L  
2023-06-07  
Please read the Important Notice and Warnings at the end of this document  
Trademarks  
All referenced product or service names and trademarks are the property of their respective owners.  
IMPORTANT NOTICE  
WARNINGS  
The information given in this document shall in no Due to technical requirements products may contain  
Edition 2023-06-07  
Published by  
event be regarded as a guarantee of conditions or dangerous substances. For information on the types  
characteristics (“Beschaffenheitsgarantie”).  
in question please contact your nearest Infineon  
Technologies office.  
With respect to any examples, hints or any typical  
Infineon Technologies AG  
81726 Munich, Germany  
values stated herein and/or any information Except as otherwise explicitly approved by Infineon  
regarding the application of the product, Infineon Technologies in a written document signed by  
Technologies hereby disclaims any and all authorized  
representatives  
of  
Infineon  
warranties and liabilities of any kind, including Technologies, Infineon Technologies’ products may  
without limitation warranties of non-infringement of not be used in any applications where a failure of the  
intellectual property rights of any third party.  
product or any consequences of the use thereof can  
reasonably be expected to result in personal injury.  
© 2023 Infineon Technologies AG.  
All Rights Reserved.  
In addition, any information given in this document  
is subject to customer’s compliance with its  
obligations stated in this document and any  
applicable legal requirements, norms and standards  
concerning customer’s products and any use of the  
product of Infineon Technologies in customer’s  
applications.  
Do you have a question about this  
document?  
Email:  
erratum@infineon.com  
The data contained in this document is exclusively  
intended for technically trained staff. It is the  
responsibility of customer’s technical departments  
to evaluate the suitability of the product for the  
intended application and the completeness of the  
product information given in this document with  
respect to such application.  
Document reference  
002-21761 Rev. *L  

CY15V108QN-20LPXC 相关器件

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