CY25560SXCT [INFINEON]
1-Output Programmable Spread Spectrum Clock Generator;
| 型号： | CY25560SXCT |
| 厂家： | 
Infineon |
| 描述： | 1-Output Programmable Spread Spectrum Clock Generator 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY25560
Spread Spectrum Clock Generator
CY25560, Spread Spectrum Clock Generator
Features
Applications
■ 25 MHz to 100 MHz operating frequency range
■ Nine different spread select options
■ Accepts clock and crystal inputs
■ Desktop, notebook, and tablet PCs
■ VGA controllers
■ LCD panels and monitors
■ Low power dissipation:
❐ 56 mW at Fin = 25 MHz
❐ 89 mW at Fin = 65 MHz
❐ 139 mW at Fin = 100 MHz
■ Printers and multifunction devices (MFP)
Benefits
■ Peak electromagnetic interference (EMI) reduction by 8 to
■ Frequency spread disable function
■ Center spread modulation
16 dB
■ Fast time to market
■ Cost reduction
■ Low cycle-to-cycle jitter
■ 8-pin SOIC package
Functional Description
■ Commercial and industrial temperature ranges
For a complete list of related documentation, click here.
Logic Block Diagram
250 K
REFERENCE
DIVIDER
Xin/
1
CLK
Loop
Filter
PD
CP
Xout
8
MODULATION
CONTROL
FEEDBACK
DIVIDER
vco
VDD
2
INPUT
DECODER
LOGIC
DIVIDER
&
MUX
SSCLK
4
3
VSS
VDD
20 K
VDD
20 K
20 K
VSS
20 K
VSS
7
5
6
SSCC
S1
S0
Cypress Semiconductor Corporation
Document Number: 38-07425 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 24, 2020
CY25560
Contents
Pinouts ..............................................................................3
Pin Description .................................................................3
General Description .........................................................3
Frequency and Spread% Selection (Center Spread) .....4
Tri-Level Logic ..................................................................4
SSCG Theory of Operation ..............................................4
EMI ..............................................................................4
SSCG ..........................................................................5
Modulation Rate ..........................................................5
CY25560 Application Schematic .....................................6
Absolute Maximum Ratings ............................................7
DC Electrical Characteristics ..........................................7
XIN/CLK DC Specifications ..............................................7
Electrical Timing Characteristics ....................................7
Absolute Maximum Conditions .......................................8
DC Electrical Characteristics ..........................................8
Electrical Timing Characteristics ....................................8
Thermal Resistance ..........................................................8
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Drawing and Dimensions ...............................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support .......................13
Products ....................................................................13
PSoC® Solutions .......................................................13
Cypress Developer Community .................................13
Technical Support .....................................................13
Document Number: 38-07425 Rev. *K
Page 2 of 13
CY25560
Pinouts
Figure 1. 8-pin SOIC pinout
1
2
3
4
8
7
XIN/CLK
XOUT
S0
VDD
VSS
CY25560
6 S1
SSCLK
5
SSCC
Pin Description
Pin Number Pin Name
Type
Pin Description
1
Xin/CLK
I
Clock or crystal connection input. See the Table on page 4 for input frequency range
selection.
2
3
4
VDD
GND
P
P
O
Positive power supply.
Power supply ground.
SSCLK
Modulated clock output, that is the same frequency as the input clock or the crystal
frequency.
5
6
SSCC
S1
I
I
Spread spectrum clock control (enable/disable) function. SSCG function is enabled when
input is high and disabled when input is low. This pin is pulled high internally.
Tri-level logic input control pin used to select input frequency range and spread percent.
See the Tri-Level Logic on page 4 for programming details. Pin 6 has an internal resistor
divider network to VDD and VSS. See the Logic Block Diagram on page 1.
7
8
S0
I
Tri-level logic input control pin used to select input frequency range and spread percent.
See the Tri-Level Logic on page 4 for programming details. Pin 7 has an internal resistor
divider network to VDD and VSS. See the Logic Block Diagram on page 1.
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock
is used to drive xin/clk input (Pin 1).
one of the nine available spread% ranges. See the Frequency
and Spread% Selection (Center Spread) on page 4 for
General Description
programming details.
The Cypress CY25560 is a spread spectrum clock generator
(SSCG) IC used to reduce the EMI found in today’s high-speed
digital electronic systems.
CY25560 is optimized for SVGA (40 MHz) and XVGA (65 MHz)
controller clocks and also suitable for applications where the
frequency range is 25 MHz to 100 MHz.
The CY25560 uses Cypress’s proprietary phase-locked loop
(PLL) and spread spectrum clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies of
clock (SSCLK) is greatly reduced.
A wide range of digitally selectable spread percentages is made
possible by using three-level (High, Low, and Middle) logic at the
S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading system performance.
Spread spectrum clock control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The CY25560 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1 digital inputs. These inputs use three (3) logic states
including High (H), Low (L), and Middle (M) logic levels to select
The CY25560 is available in an 8-pin SOIC package with 0 °C to
70 °C Commercial and –40 °C to 85 °C Industrial operating
temperature ranges.
Document Number: 38-07425 Rev. *K
Page 3 of 13
CY25560
Frequency and Spread% Selection (Center Spread)
25 – 50 MHz (Low Range)
Input
Frequency
(MHz)
25 – 35
35 – 40
40 – 45
45 – 50
S1=M
S0=M
(%)
4.3
3.9
3.7
3.4
S1=M
S0=0
(%)
3.8
3.5
3.3
3.1
S1=1
S0=0
(%)
3.4
3.1
2.8
S1=0
S0=0
(%)
2.9
2.5
2.4
S1=0
S0=M
(%)
2.8
2.4
2.3
2.1
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
2.6
2.2
50 – 100 MHz (High Range)
Input
Frequency
(MHz)
50 – 60
60 – 70
70 – 80
80 – 100
S1=1
S0=M
(%)
2.9
2.8
2.6
2.4
S1=0
S1=1
S0=1
(%)
1.5
1.4
1.3
S1=M
Select the
S0=1
(%)
2.1
2.0
1.8
S0=1
(%)
1.2
1.1
1.1
Frequency and
Center Spread %
desired and then
set S1, S0 as
indicated.
1.7
1.2
1.0
of these states have a defined voltage range that is interpreted
by the CY25560 as a ‘0’, ‘M’, or ‘1’ logic state. See the DC
Electrical Characteristics on page 7 for voltage ranges for each
logic state. The CY25560 has two equal value resistor dividers
connected internally to Pins 6 and 7 that produce the default ‘M’
(Middle) state if these pins are left unconnected (NC). Pins 6
and/or 7 can be tied directly to ground or VDD to program a logic
‘0’ or ‘1’ state, respectively.
Tri-Level Logic
With binary logic, four states can be programmed with two
control lines, whereas three-level logic can program nine logic
states using two control lines. Three-level logic in the CY25560
is implemented by defining a third logic state in addition to the
standard logic ‘1’ and ‘0’. Pins 6 and 7 of the CY25560 recognize
a logic state by the voltage applied to their respective pin. These
states are defined as ‘0’ (Low), ‘M’ (Middle), and ‘1’ (One). Each
Figure 2. Three-Level Logic Examples
VDD
VDD
CY25560
CY25560
S0 = "1"
CY25560
S0
S0
S0
S1
S0 = "M" (N/C)
7
6
7
7
6
5
S0 = "1"
S1 = "0" (GND)
SSCC = "1"
S1
S1
S1 = "0" (GND)
SSCC = "1"
S1 = "1"
6
5
VDD
VDD
5
SSCC = "1"
EMI
SSCG Theory of Operation
All digital clocks generate unwanted energy in their harmonics.
Conventional digital clocks are square waves with a duty cycle
that is very close to 50 percent. Because of this 50/50 duty cycle,
digital clocks generate most of their harmonic energy in the odd
harmonics, i.e., third, fifth, seventh, and so on. It is possible to
reduce the amount of energy contained in the fundamental and
odd harmonics by increasing the bandwidth of the fundamental
clock frequency. Conventional digital clocks have a very high Q
factor, that means that all of the energy at that frequency is
The CY25560 is a PLL-type clock generator using a proprietary
Cypress design. By precisely controlling the bandwidth of the
output clock, the CY25560 becomes a low-EMI clock generator.
The theory and detailed operation of the CY25560 is discussed
in the following sections.
Document Number: 38-07425 Rev. *K
Page 4 of 13
CY25560
concentrated in a very narrow bandwidth, consequently, higher
energy peaks. Regulatory agencies test electronic equipment by
the amount of peak energy radiated from the equipment. By
reducing the peak energy at the fundamental and harmonic
frequencies, the equipment under test is able to satisfy agency
requirements for EMI. Conventional methods of reducing EMI
have been to use shielding, filtering, multilayer PCBs, and so on.
The CY25560 uses the approach of reducing the peak energy in
the clock by increasing the clock bandwidth, and lowering the Q
factor.
calculate to total amount of spread or bandwidth applied to the
reference clock at Pin 1. As the clock is making the transition
from F1 to F2, the amount of time and sweep waveform play a
very important role in the amount of EMI reduction realized from
an SSCG clock.
The modulation domain analyzer is used to visualize the sweep
waveform and sweep period. Figure 3 shows the modulation
profile of a 65 MHz SSCG clock. Notice that the actual sweep
waveform is not a simple sine or sawtooth waveform. Figure 3
also shows a scan of the same SSCG clock using a spectrum
analyzer. In this scan you can see a 6.48 dB reduction in the peak
RF energy when using the SSCG clock.
SSCG
SSCG uses a patented technology of modulating the clock over
a very narrow bandwidth and controlled rate of change, both
peak and cycle-to-cycle. The CY25560 takes a narrow band
digital reference clock in the range of 25 to 100 MHz and
produces a clock that sweeps between a controlled start and
stop frequency and precise rate of change. To understand what
happens to a clock when SSCG is applied, consider a 65 MHz
clock with a 50 percent duty cycle. From a 65 MHz clock we know
the following:
Modulation Rate
SSCGs utilize frequency modulation (FM) to distribute energy
over a specific band of frequencies. The maximum frequency of
the clock (Fmax) and minimum frequency of the clock (Fmin)
determine this band of frequencies. The time required to
transition from Fmin to Fmax and back to Fmin is the period of
the Modulation Rate, Tmod. Modulation Rates of SSCG clocks
are generally referred to in terms of frequency or
Fmod = 1/Tmod.
50 %
50 %
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the Modulation Rate. In some SSCG clock
generators, the selected range determines the internal divider
count. In other SSCG clocks, the internal divider count is fixed
over the operating range of the device. The CY25560 has a fixed
divider count of 1166.
Clock frequency = fc = 65 MHz
Clock period = Tc =1/65 MHz = 15.4 ns
Tc = 15.4 ns
If this clock is applied to the Xin/CLK pin of CY25560, the output
clock at Pin 4 (SSCLK) sweeps back and forth between two
frequencies. These two frequencies, F1 and F2, are used to
Figure 3. SSCG Clock, CY25560, Fin = 65 MHz
Spectrum Analyzer
Modulation Profile
BW = 2.46%
Document Number: 38-07425 Rev. *K
Page 5 of 13
CY25560
CY25560 Application Schematic
The schematic in Figure 4 demonstrates how the CY25560 is configured in a typical application. This application is shown as using
a 30 MHz fundamental crystal. In most applications, an external reference clock is used. Apply the external clock signal at Xin (Pin 1)
and leave Xout (Pin 8) unconnected (see Pin Description on page 3 for pin descriptions).
Contact Cypress if higher order crystal is to be used.
Figure 4. Application Schematic
VDD
C3
0.1 uF
2
C2
VDD
1
XIN/CLK
XOUT
4
27 pF
C3
SSCLK
Y1
30 MHz
8
27 pF
CY25560
6
7
S1
S0
5
VDD
SSCC
VSS
3
Document Number: 38-07425 Rev. *K
Page 6 of 13
CY25560
Junction Temperature .............................. –40 °C to +140 °C
Operating Temperature .................................... 0 °C to 70 °C
Storage Temperature ............................... –65 °C to +150 °C
Static Discharge Voltage (ESD) ......................... 2,000 V-Min
Absolute Maximum Ratings
[1, 2]
Commercial Grade
Supply Voltage (V ) ...................................–0.5 V to +6.0 V
DD
DC Input Voltage ................................–0.5 V to V + 0.5 V
DD
DC Electrical Characteristics
V
= 3.3 V ± 10%, T = 0 °C to 70 °C and C (Pin 4) = 15 pF, Unless Otherwise Noted
L
DD
Parameter
Description
Power supply range
Input high voltage
Input middle voltage
Input low voltage
Conditions
Min
Typ
Max
Unit
V
V
±10%
2.97
3.3
3.63
DD
IH
V
S0 and S1 only
S0 and S1 only
S0 and S1 only
0.85 × V
V
V
DD
V
DD
DD
V
V
V
V
0.40 × V
0.50 × V
0.60 × V
V
IM
IL
DD
DD
DD
0.0
2.4
–
0.0
–
0.15 × V
V
DD
Output high voltage
Output low voltage
Input capacitance
Input capacitance
Input capacitance
Power supply current
Power supply current
Power supply current
I
I
= 6 mA
= 6 mA
–
0.4
5
V
OH
OL
OH
OH
–
V
C
C
C
Xin/CLK (Pin 1)
3
4
pF
pF
pF
mA
mA
mA
in1
in2
Xout (Pin 8)
6
8
10
5
S0, S1, SSCC (Pins 7, 6, 5)
FIN = 25 MHz, CL = 0
FIN = 65 MHz, CL = 0
FIN = 100 MHz, CL = 0
3
4
in2
I
I
I
–
17
27
42
23
41
59
DD1
DD2
DD3
–
–
X /CLK DC Specifications
IN
Parameter
Description
Input high voltage,
Clock Input
Conditions
Min
Max
Units
V
V
F < 100 MHz
80
–
% of V
IH(X)
DD
X
IN
Input low voltage,
Clock Input
–
15
% of V
IL(X)
DD
X
IN
Electrical Timing Characteristics
V
= 3.3 V ± 10%, T = 0 °C to 70 °C and C (Pin 4) = 15 pF, Unless Otherwise Noted
L
DD
Parameter
Description
Input clock frequency range
Clock rise time (Pin 4)
Clock fall time (Pin 4)
Input clock duty cycle
Output clock duty cycle
Cycle-to-cycle jitter
Conditions
= 3.30 V
Min
25
1.0
1.0
25
45
–
Typ
–
Max
100
2.8
2.8
75
Unit
MHz
ns
I
t
t
V
DD
CLKFR
SSCLK at 0.4 V–2.4 V
SSCLK at 0.4 V–2.4 V
XIN/CLK (Pin 1)
1.8
1.8
50
F
ns
R
D
D
%
TYin
TYout
CC1
SSCLK (Pin 4)
50
55
%
J
J
Fin = 25 MHz–50 MHz, SSCC = 1
Fin = 50 MHz–100 MHz, SSCC = 1
150
130
300
200
ps
Cycle-to-cycle jitter
–
ps
CC2
Notes
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document Number: 38-07425 Rev. *K
Page 7 of 13
CY25560
Junction Temperature .............................. –40 °C to +140 °C
Operating Temperature ................................ –40 °C to 85 °C
Storage Temperature ............................... –65 °C to +150 °C
Static Discharge Voltage (ESD) ......................... 2,000 V-Min
Absolute Maximum Conditions
[3, 4]
Industrial Grade
Supply Voltage (V ) ...................................–0.5 V to +6.0 V
DD
DC Input Voltage ..................................–0.5 V to V +0.5 V
DD
DC Electrical Characteristics
V
= 3.3 V ± 10%, T= –40 °C to 85 °C and C (Pin 4) = 15 pF, Unless Otherwise Noted
L
DD
Parameter
Description
Power supply range
Input high voltage
Input middle voltage
Input low voltage
Conditions
Min
Typ
Max
Unit
V
V
±10%
2.97
3.3
3.63
DD
IH
V
S0 and S1 only
S0 and S1 only
S0 and S1 only
0.85 × V
V
V
DD
V
DD
DD
V
V
V
V
0.40 × V
0.50 × V
0.60 × V
V
IM
IL
DD
DD
DD
0.0
2.2
–
0.0
–
0.15 × V
V
DD
Output high voltage
Output low voltage
Input capacitance
Input capacitance
Input capacitance
Power supply current
Power supply current
Power supply current
I
I
= 6 mA
= 6 mA
–
0.4
5
V
OH
OL
OH
OH
–
V
C
C
C
Xin/CLK (Pin 1)
3
4
pF
pF
pF
mA
mA
mA
in1
in2
Xout (Pin 8)
6
8
10
5
S0, S1, SSCC (Pins 7, 6, 5)
FIN = 25 MHz, CL= 0
FIN = 65 MHz, CL= 0
FIN = 100 MHz, CL= 0
3
4
in2
I
I
I
–
17
27
42
24
41
61
DD1
DD2
DD3
–
–
Electrical Timing Characteristics
V
= 3.3 V ± 10%, T= –40 °C to 85 °C and C (Pin 4) = 15 pF, Unless Otherwise Noted
L
DD
Parameter
Description
Input clock frequency range
Clock rise time (Pin 4)
Clock fall time (Pin 4)
Input clock duty cycle
Output clock duty cycle
Cycle-to-cycle jitter
Conditions
= 3.30 V
Min
25
1.0
1.0
25
45
–
Typ
–
Max
100
3.0
3.0
75
Unit
MHz
ns
I
t
t
V
DD
CLKFR
SSCLK at 0.4 V–2.4 V
SSCLK at 0.4 V–2.4 V
XIN/CLK (Pin 1)
1.8
1.8
50
F
ns
R
D
D
%
TYin
TYout
CC1
SSCLK (Pin 4)
50
55
%
J
J
Fin = 25 MHz–50 MHz, SSCC = 1
Fin = 50 MHz–100 MHz, SSCC = 1
150
130
300
200
ps
Cycle-to-cycle jitter
–
ps
CC2
Thermal Resistance
[5]
Parameter
Description
Test Conditions
8-pin SOIC
Unit
θ
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
131
°C/W
JA
θ
Thermal resistance
(junction to case)
41
°C/W
JC
Notes
3. Operation at any Absolute Maximum Rating is not implied.
4. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. These parameters are guaranteed by design and are not tested.
Document Number: 38-07425 Rev. *K
Page 8 of 13
CY25560
Ordering Information
Part Number
Pb-free
Package Type
Product Flow
CY25560SXC
CY25560SXCT
CY25560SXI
8-pin SOIC
Commercial, 0 °C to 70 °C
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
8-pin SOIC – Tape and Reel
8-pin SOIC
CY25560SXIT
8-pin SOIC – Tape and Reel
Ordering Code Definitions
CY 25560
S
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package: S = 8-pin SOIC
Base Device Part Number
Company ID: CY = Cypress
Document Number: 38-07425 Rev. *K
Page 9 of 13
CY25560
Package Drawing and Dimensions
Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066
51-85066 *I
Document Number: 38-07425 Rev. *K
Page 10 of 13
CY25560
Acronyms
Document Conventions
Units of Measure
Acronym
Description
EMI
Electromagnetic Interference
Electrostatic Discharge
Symbol
°C
Unit of Measure
ESD
degree Celsius
megahertz
milliampere
nanosecond
percent
MHz
mA
ns
PLL
Phase Locked Loop
SOIC
SSC
Small Outline Integrated Circuit
Spread Spectrum Clock
%
SSCG
SVGA
XVGA
Spread Spectrum Clock Generator
Super Video Graphics Array
Extended Video Graphics Array
pF
ps
picofarad
picosecond
watt
W
Document Number: 38-07425 Rev. *K
Page 11 of 13
CY25560
Document History Page
Document Title: CY25560, Spread Spectrum Clock Generator
Document Number: 38-07425
Submission
Revision
ECN
Description of Change
Date
**
115261
119441
122704
125549
06/12/02
10/17/02
12/30/02
05/15/03
New data sheet.
*A
*B
*C
Corrected the values in the Absolute Maximum Ratings to match the device.
Added power up requirements to maximum ratings information.
Added Industrial Temperature Range to the device.
Removed V
and V
spec in the DC specs table
OL2
OH2
Changed IDD Values from 11/17/25 typ and 14/22/34max to 17/27/42 typ and 23/41/59 max
Changed T /T values from 1.3/1.3 typ and 1.6/1.6 max to 1.8/1.8 typ and 2.8/2.8 max in
F
R
the Electrical Char. table.
Changed J values from 200/250 typ and 250/300 max to 150/130 typ to 300/200 max
CC1/2
in the Electrical Char. table.
Changed the low power dissipation from 36/56/82mW to 56/89/139mW respectively.
Changed the low cycle-to-cycle jitter from 195/175/100ps-typ to 450/225/150 ps-max
*D
*E
314293
See ECN Updated Ordering Information:
Added Pb-free devices.
2762435
09/11/09
Updated SSCG Theory of Operation:
Updated SSCG:
Fixed the frequency in figure.
Updated Ordering Information:
Removed Pb devices.
*F
2819309
3343531
12/01/09
Minor change - updated revision number and corrected the document number at the
beginning of this table.
*G
08/12/2011 Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated Package Drawing and Dimensions.
*H
4511394
09/26/2014 Added XIN/CLK DC Specifications.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*I
4586478
5270202
03/12/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
05/13/2016 Updated SSCG Theory of Operation:
Updated SSCG:
Updated Figure 3.
Added Thermal Resistance.
Updated Package Drawing and Dimensions:
spec 51-85066 – Changed revision from *F to *H.
Updated to new template.
*K
6866984
04/24/2020 Updated Spec 51-85066 – Changed revision from *H to *I.
Updated to template.
Document Number: 38-07425 Rev. *K
Page 12 of 13
CY25560
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
®
®
Arm Cortex Microcontrollers
Automotive
cypress.com/arm
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© Cypress Semiconductor Corporation, 2005-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
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circuit described in this document.Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility
of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any
device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.
“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect
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data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07425 Rev. *K
Revised April 24, 2020
Page 13 of 13
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
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Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided
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that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
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