CY27410LTXI-008T [INFINEON]
Universal Programmable Clock Generator with VCXO and Spread Spectrum;
| 型号： | CY27410LTXI-008T |
| 厂家： | 
Infineon |
| 描述： | Universal Programmable Clock Generator with VCXO and Spread Spectrum 石英晶振 压控振荡器 |
| 文件： | 总31页 (文件大小：889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CY27410
4-PLL Spread-Spectrum Clock Generator
4-PLL Spread-Spectrum Clock Generator
■ Up to 100-ps skew for differential outputs within a bank
Features
■ Four fractional N-type phase-locked loops (PLLs) with
❐ VCXO (±120 ppm with steps of 0.23 ppm)
❐ Spread-spectrum capability (Logic SS and Lexmark profile
0.1% to 5% in 0.1% steps, down or center spread)
■ Input frequencies
❐ Crystal input: 8 MHz to 48 MHz
❐ Reference clock: 8 MHz to 250 MHz LVCMOS
❐ Reference clock: 8 MHz to 700 MHz differential
■ Supply voltage: 1.8 V, 2.5 V, and 3.3 V
■ Output frequencies
❐ 25 MHz to 700 MHz LVDS, LVPECL, HCSL, CML
❐ 3 MHz to 250 MHz LVCMOS
■ Zero-delay buffer (ZDB) and non-zero delay buffer (NZDB)
configurations
■ I2C configurable with onboard programming
❐ 1 kHz to 8 MHz for one LVCMOS output
■ RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset
■ PCIe 1.0/2.0/3.0 compliant
■ Industrial-grade device, offered in 48-pin QFN (7 × 7 × 1.0 mm)
package
■ SATA 2.0, USB 2.0/3.0, 1/10-GbE compliant
■ Maximum 12 outputs split in two banks with six outputs each.
❐ Up to eight differential output pairs (HCSL, LVPECL, CML,
or LVDS)
Functional Description
The CY27410 device configuration can be created using
ClockWizard 2.1. For programming support, contact Cypress
technical support or send an email to clocks@cypress.com.
❐ Up to 12 LVCMOS outputs
For a complete list of related documentation, click here.
Logic Block Diagram
Output Drivers 1
VIN
ADC
FS2
FS1
O1[1..4]
PLL1
O2[1..4]
PLL2
FS
I2C
FS0
SCLK
SDAT
XIN
XOUT
IN1P
IN1N
IN2P
IN2N
RCAL
RCCAL
BG
INI
IN1S
IN2S
INC
Reference
System
Register
Memory
OSC
POR
QP
PLL3
PLL4
NV
Memory
O3[1..4]
O4[1..4]
PRG
Block
VDD
LDOs
Output Drivers 2
Cypress Semiconductor Corporation
Document Number: 001-89074 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 15, 2019
CY27410
Contents
Functional Overview ........................................................3
Input System ...............................................................3
VCXO Input Block .......................................................3
Frequency Select Input ...............................................3
I2C Block (SCLK, SDAT) .............................................4
Synthesis Section ........................................................4
Output Section .............................................................4
Onboard Programming ................................................5
Functional Features
and Application Considerations ..........................................5
Pinouts ............................................................................10
Electrical Specifications ................................................13
Absolute Maximum Ratings .......................................13
Operating Temperature .............................................13
Operating Power Supply ...........................................13
DC Chip-Level Specifications ....................................14
DC Output Specifications ..........................................15
AC Input Clock Specifications ...................................16
AC Output Specifications ..........................................16
Test and Measurement Circuits ................................23
Voltage and Timing Definitions ..................................24
Packaging Information ...................................................26
Solder Reflow Specifications .....................................26
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Acronyms ........................................................................28
Document Conventions .................................................28
Units of Measure .......................................................28
Document History Page .................................................29
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products ....................................................................30
PSoC® Solutions ......................................................30
Cypress Developer Community .................................30
Technical Support .....................................................30
Document Number: 001-89074 Rev. *M
Page 2 of 30
CY27410
If a crystal is used, XIN and XOUT are connected to a crystal
oscillator to generate the required internal frequency, as shown
in Figure 2. The supported differential tuning capacitor range is
8 pF to 12 pF.
Functional Overview
The CY27410 is a standard-performance programmable clock
generator with four independent fractional PLLs, which
generates any frequency with a zero-ppm synthesis error. Each
PLL is followed by a set of four independent dividers to generate
four different frequencies from a single PLL. All four dividers are
synchronized to generate phase-aligned clock outputs with
minimal skew. The PLLs also support the spread-spectrum
feature to reduce EMI. PLL 1 has VCXO functionality to achieve
ppm granularity of output frequency.
Figure 2. Connecting a Crystal
XIN
XO
Crystal
XOUT
The
CY27410
accepts
a
crystal
clock
or
a
single-ended/differential reference clock. The device supports
up to 12 outputs, divided into two banks with six outputs each.
Four outputs of PLL 1 and PLL 2 are multiplexed to
output Bank 1, and four clock outputs of PLL 3 and PLL 4 are
multiplexed to output Bank 2. The 12 outputs of the two banks
are configurable as eight differential outputs, 12 single-ended
outputs, or a combination of differential and single-ended
outputs.
IN1 and IN2 are designed to accept either a single-ended or
differential reference input. IN2 can be used to accept the
feedback signal to implement the ZDB functionality of the device.
The differential inputs are capable of interfacing with multiple
standards, such as LVPECL, LVDS, CML, and HCSL. The
differential signals must be of AC-coupling, as shown in Figure 3.
The CY27410 has an on-chip volatile and nonvolatile memory,
composed of eight registers, which store the device
configuration settings. These registers can be accessed and
programmed onboard through the I2C interface. You can also
configure the device on-the-fly to completely reprogram the
device on the application board. Besides the I2C interface,
external signals can be applied to multifunction pins for different
functions such as the following:
Figure 3. Interfacing Differential and Single-Ended Signals
100 pF
Differential Signal
INxP
Termination
INxN
■ Dynamically change the output frequency
■ Output enable/disable
■ Power down
100 pF
INxP
R
S
INxN
LVCMOS Signal
■ Spread ON/OFF
One low-frequency clock output, in kilohertz, is provided to meet
the need of widely used reference frequencies, such as
32.768 kHz. The jitter specs of the CY27410 make it an ideal
choice for the following communication protocols: PCIe
1.0/2.0/3.0, USB 2.0/3.0, SATA 1.0/2.0, and 1/10GbE.
VCXO Input Block
The VIN input is used for the VCXO functionality of the device.
In this functionality, the output can change with respect to an
input voltage required for audio-visual applications. The output
frequency can vary up to ±120 ppm. This input voltage directly
controls the PLL 1 fractional divider to provide the VCXO
functionality.
Input System
The input system supports the following (see Figure 1):
■ XIN/XOUT supports crystal input.
Frequency Select Input
■ IN1 supports differential and single-ended clock inputs.
■ IN2 supports differential and single-ended clock inputs.
Figure 1. Oscillator/Clock Input Block Diagram
The CY27410 supports frequency-select features with which the
customer can change output frequencies on-the-fly. The device
has eight configuration register sets, which can be
preprogrammed or written through I2C. Changing the signal level
of the FS pins (high and low) selects the appropriate
configuration registers and changes the output frequency
accordingly.
INC
XIN
MUX
INI
XO
XOUT
IN1P
IN1N
IN1S
DIV-R1
DIV-R2
IN2P
IN2N
IN2S
Document Number: 001-89074 Rev. *M
Page 3 of 30
CY27410
2
I C Block (SCLK, SDAT)
Synthesis Section
The CY27410 supports I2C programming of internal registers,
which can be used to configure the device. The CY27410 also
supports user-profile programming to flash memory and allows
partial updates. Read, Write, or Read/Write protection is also
available. The device is compliant with the I2C-bus Specification,
version 2.1 or later. The critical I2C specifications are as follows:
The CY27410 contains four PLLs, which are the core synthesis
blocks of the chip. Each PLL has a fractional N capability, which
supports output frequency generation based on an input
reference frequency to an accuracy of 100 ppb. The output of the
PLL is fed into four dividers and then moves to synchronizers to
generate glitch-free clock transition features, variable delay
generation circuits to support the programmable delay feature,
and so on. The output dividers and multiplexers are also included
as part of this subsystem. All the four PLLs have the same
architecture, as shown in Figure 4.
■ 400 kb/s (Fast mode)
■ 7-bit addressing support
■ Selectable device address (programmable), default = 69 hex
(7 bits)
Figure 4. PLL Architecture
DLY=0‐4 cycles
DELAY
INC
5
REF
FBK
P‐Path
LF
PDET
+
CP
IN1S
DIV O1
DIV O2
DIV O3
DIV O4
DIV 2
DIV 2
DIV 2
DIV 2
SYNC
SYNC
SYNC
SYNC
Ox1
Ox2
Ox3
Ox4
VCO
I‐Path
LF
IN2S
FRAC
DIV N
SYNC
SYNC
DIV 2
OUTC
SYNC
DIV 2
DIV C
Figure 6. Bank2 Outputs
Output Section
The CY27410 has two banks of outputs, which are located at the
top and bottom of the device. Each bank consists of six outputs
with OUT11–OUT14 and OUT21–OUT24 supporting both
differential and single-ended outputs and OUT15–OUT16 and
OUT25–OUT26 supporting only single-ended outputs.
INI
DIV I
1/2/4/8
DIV I
1/2/4/8
O44
O43
O42
O41
O34
O33
O32
O31
DIV L
Each output is fed from a PLL through a divider and then to a
MUX, which helps in selecting the source for the output, as
shown in Figure 5 and Figure 6.
MUX
MUX
MUX
MUX
MUX
MUX
Figure 5. Bank1 Outputs
MUX
MUX
MUX
MUX
MUX
MUX
O11
O12
O13
O14
O21
O22
O23
O24
DIV L
DIV I
1/2/4/8
DIV I
1/2/4/8
INI
Document Number: 001-89074 Rev. *M
Page 4 of 30
CY27410
Figure 8. PLL Block Diagram, Clock Generation
Onboard Programming
One can write the device memory on the customer board,
enabling the use of a blank device that is not preprogrammed.
This enables use of the same device across multiple projects and
lets you program the device based on individual projects.
Conceptual onboard programming is shown in Figure 7.
Reference
Outputs
I1
Synthesis Block
O1 DLY
R1
R2
PLL
O2
O3
O4
Figure 7. Onboard Programming
FracN
C1
POR, Initialize
I2
L1
Non Volatile
Control Store Control Registers
Volatile
Device
Configuration
from Adjacent PLL
PCIE (HCSL) Clock Generation
On Board
I2C
For PCIe applications, the CY27410 provides eight differential
outputs that have the same spread on it at any particular point of
time.
Programming
VCXO and Related Frequencies
Functional Features and Application Considerations
The CY27410 provides VCXO functionality and a cascading PLL
option to generate critical frequencies with a fixed reference.
Digital televisions have a requirement for the audio and video
clocks to follow a 27-MHz VCXO signal so that they are
synchronized. The architecture of the chip must ensure that this
is met by cascading, as shown in Figure 9.
The CY27410 is a 4-PLL spread-spectrum clock generator
targeted at consumer, industrial, and low-end networking
applications. The key specifications of the part are differential
inputs (2) and outputs (12), supporting frequencies up to
700 MHz. The device has a low RMS phase jitter of 1-ps max
and value-added features, such as VCXO, Frequency Select,
and PLL Bypass modes. This part is designed to support key
standards, such as PCIe 1.0/2.0/3.0, USB 2.0/3.0, and 10GbE.
Figure 9. Cascading PLLs
REF
XBUF
100MHz HCSL
66.66MHz LVCMOS
The product supports LVDS, LVPECL, CML, HCSL, and
LVCMOS logic levels.
SS_PLL
VCFS
(PLL1)
27MHz VCXO
VIN
Clock Generator
The main feature of the CY27410 is frequency generation from
an external reference (IN1) or a crystal. There are four variables
to determine the final output frequency. They are input REF, the
DIV-R (R1), FracN (DIV-N) dividers, and the post dividers
(DIV-O). The basic formula for determining the final output
frequency is:
PLL
PLL
VIDEO 74.25MHz
AUDIO 36.864MHz
FS
FS
Apart from having the audio and video clocks following the
27-MHz VCXO input, they also need complex divider ratios to
generate the output frequencies. Commonly used divider ratios
for audio and video signals are listed in Table 1.
■ Clock Generator mode
❐ fOUT = ((REF x DIV-N) / DIV-R) / DIV-O
■ PLL Bypass mode
❐ fOUT = REF / DIV-I or REF / DIV-I / DIV-L
Table 1. Audio and Video Frequencies
The basic PLL block diagram is shown in Figure 8. Each of the
outputs from the PLL is fed to the output MUX through a Delay
circuit that provides a certain delay to the individual clock, if
needed.
Output Frequency
74.17582418
33.8688
Ratios
91:250
625:784
1875:1568
1250:784
1875:784
1875:392
375:512
22.5792
16.9344
11.2896
5.6448
36.864
Document Number: 001-89074 Rev. *M
Page 5 of 30
CY27410
Zero-Delay Buffer Functionality
Figure 12. Early/Late Phase in ZDB Configuration
The CY27410 acts as a zero-delay buffer (ZDB) for one output
from a single PLL block. To implement this feature, take one of
the outputs and send it back as a feedback reference to the PLL.
By providing a divider in the feedback loop, the device can also
act as a frequency-multiplying ZDB (see Figure 10). This
functionality is supported only when the PLL is in the integer N
mode.
Reference
Outputs
I1
Synthesis Block
O1 DLY
R1
R2
PLL
O2
O3
O4
FracN
C1
Figure 10. ZDB Configuration
I2
L1
Reference
Outputs
I1
Synthesis Block
O1 DLY
from Adjacent PLL
R1
R2
REF
PLL
O2
O3
O4
Non-Zero Delay Buffer
FracN
C1
I2
L1
The CY27410 supports the PLL-bypass mode, which bypasses
the entire synthesis block to act as a configurable non-zero delay
buffer (NZDB) with level translation and selectable inputs, as
shown in Figure 13.
from Adjacent PLL
Figure 13. NZDB Configuration
Reference
Outputs
The CY27410 provides the frequency-multiplying ZDB by
modulating the R1 and R2 values in the integer ratio. If both the
values are identical, the CY27410 acts as a simple ZDB.
I1
Synthesis Block
O1 DLY
R1
R2
Early/Late Output Phase
PLL
O2
O3
O4
The CY27410 supports a delay circuit in the divider to provide 0
to 4 × VCO/2 cycles. Therefore, an output has a certain lag
phase or lead phase to other outputs when this feature is used.
This functionality is also available in the ZDB mode and provides
“early” phase or “delayed” phase to the Reference input. Refer
to Figure 11 and Figure 12.
FracN
C1
I2
L1
from Adjacent PLL
Figure 11. Early/Delayed Phase Output
Reference
Outputs
Combination Clock Generator and Buffer
I1
Synthesis Block
O1 DLY
The CY27410 provides a combination of a clock generator and
a buffer in one device. This is achieved by configuring the input
and output selectors for the desired split configuration. An
example of such an application is shown in Figure 14.
R1
R2
PLL
O2
O3
O4
FracN
C1
Figure 14. Clock Generator and NZDB
I2
L1
Reference
Outputs
I1
Synthesis Block
O1 DLY
from Adjacent PLL
R1
R2
PLL
O2
O3
O4
FracN
C1
I2
L1
from Adjacent PLL
Document Number: 001-89074 Rev. *M
Page 6 of 30
CY27410
Low-Frequency Output
Figure 16. Spread-Spectrum Profile
Nonlinear Profile
The CY27410 integrates low-frequency generator counters for
LVCMOS outputs that may be used for watchdog-time and/or
kHz-order clocks for application, as shown in Figure 15.
Linear Profile
MAX
MIN
MAX
IN
Figure 15. Low-frequency Output Option
Time
Time
Reference
Outputs
Typical Clock
EMI
Typical Clock
I1
SS Clock
SS Clock
Synthesis Block
O1 DLY
EMI
Reduction
Reduction
R1
PLL
O2
O3
O4
R2
FracN
C1
Frequency
Frequency
I2
L1
VCXO (VCFS) Functionality
from Adjacent PLL
The CY27410 supports VCXO functionality without pulling the
crystal frequency. This function is implemented by modulating
the FracN counter according to the VIN level, as shown in
Figure 17. Therefore, this is called voltage-controlled frequency
shift (VCFS).
Spread Spectrum
To help reduce electromagnetic interference (EMI), the CY27410
supports spread-spectrum modulation. The output clock
frequencies can be modulated to spread energy across a
broader range of frequencies and lower system EMI. The
CY27410 implements two types of spread profiles for
modulation: linear and nonlinear.
The VCFS function is implemented by modulating the FracN
divider, which means all the parameters are independent of the
process, voltage, and temperature variations.
It is not possible to combine the VCFS operation with spread
spectrum (see Figure 18).
The spread spectrum can be applied to any output clock, any
frequency, and any spread amount ranging from 0.1% to 5% in
0.1% steps. The center or down spread can be programmable.
Figure 17. VCFS Profile
Frequency
ppm
The spread modulation rate is limited from 30 kHz to 60 kHz.
The spread spectrum is generated digitally in the FracN
modulation, which means all the parameters are independent of
process, voltage, and temperature variations. All the frequencies
generated by the same PLL have the same amount of
modulation.
0
VIN
1/2 * VDD
As shown in Figure 16, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction in the nonlinear profile is:
Figure 18. VCFS and Spread Spectrum
Reference
Outputs
dB = 6.5 + 9 log10(P) + 9 * log10(F)
I1
Synthesis Block
where P is the percentage of deviation and F is the frequency in
megahertz where the reduction is measured.
O1 DLY
R1
R2
PLL
O2
O3
O4
FracN
C1
I2
L1
from Adjacent PLL
VCFS
SSC
VIN
Document Number: 001-89074 Rev. *M
Page 7 of 30
CY27410
Crystal Oscillator
Start Bit; 7-bit Device Address; R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; and more until STOP Bit.
The CY27410 supports various low-cost crystals as a reference
oscillator at IN1 (XIN/XOUT) to generate multiple frequencies in
a single chip. The CY27410 supports a crystal with a nominal
load capacitance specification from 8 pF to 12 pF. As shown in
Figure 2 on page 3, the CY27410 integrates all the components,
such as a feedback resistor and tuning capacitor, to oscillate the
clock with a particular crystal for the following specifications.
The basic serial format is shown in Figure 19.
Figure 19. Data Transfer Sequence on the Serial Bus
To enable proper operation, the crystal specification is divided
into three ranges:
SCLK
SDAT
■ Low range (FNOM) = 8 to 12 MHz
■ Midrange = 12 to 20 MHz
START
Address or
Data may
STOP
Condition
Condition
Acknowledge be changed
Valid
■ High range = 20 to 48 MHz
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (SDAT = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (SDAT = 0/LOW), and the master must end the
write sequence with a STOP condition (see Figure 20).
The corresponding crystal parameters are listed in Table 2.
Table 2. Crystal Specifications
Min
Max
Max R1
(ohms)
Max DL
(µW)
Range
Frequency Frequency
(MHz)
8
(MHz)
12
Low
Mid
150
70
100
100
100
Figure 20. Data Frame Architecture (Write)
Random Write
12
20
High
20
48
50
CL (pF) for all Ranges Associated Max C0 (pF)
Memory Address
Memory Data
Device Address
8
9
2
2
2
3
Sequential Write
10
12
Memory Address
Memory Data
Memory Data
Device Address
Serial Programming Interface Protocol
The CY27410 uses the SDAT and SCLK pins for a 2-wire serial
interface that operates up to 400 Kb/s in Read and Write modes.
It complies with the I2C bus standard. The basic Write protocol is:
Document Number: 001-89074 Rev. *M
Page 8 of 30
CY27410
Read operations are initiated the same way as write operations,
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are two basic read operations: random read and
sequential read. Figure 21 illustrates these operations.
Figure 21. Data Frame Architecture (Read)
Random Read
Memory Address
Memory Address
Memory Data
Memory Data
Device Address
Device Address
Device Address
Sequential Read
Device Address
Memory Data
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. Send the address to the CY27410 as part of
a write operation. After the word address is sent, the master
generates a START condition following the acknowledge. This
terminates the write operation before any data is stored in the
address, but not before the internal address pointer is set. Next,
the master reissues the control byte with the R/W byte set to ‘1’.
Sequential read operations follow the same process as random
reads, except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action results in an incrementing of the internal address
pointer, and subsequently output of the next 8-bit data word. By
continuing to issue acknowledges instead of STOP conditions,
the master may serially read the entire contents of the slave
device memory.
Then, the CY27410 issues an acknowledge and transmits the
8-bit word. The master device does not acknowledge the
transfer, but does generate a STOP condition, which causes the
CY27410 to stop transmission.
Document Number: 001-89074 Rev. *M
Page 9 of 30
CY27410
Pinouts
The CY27410 devices are available in the 48-pin QFN package.
Table 3. CY27410 Pin Definitions
Name
XIN
I/O
Type
# of Pins
Pin #
Function
I
O
I
Crystal
Crystal
1
1
1
8
9
6
XIN for crystal
XOUT
IN1P
XOUT for crystal
LVCMOS/
Differential
True input for IN1 differential pair. IN1 for LVCMOS input. Need
external series capacitor for differential input.
IN1N
IN2P
I
I
Differential
1
1
5
4
Complement input for IN1 differential pair. None for LVCMOS
input. Need external series capacitor for differential input.
LVCMOS /
Differential
Feedback input for ZDB mode.
True input for IN2 differential pair. IN2 for LVCMOS input
Need external series CAPS for differential input.
IN2N
I
Differential
1
3
Feedback input for ZDB mode.
Complement input for IN2 differential pair. None for LVCMOS
input. Need external series CAPS for differential input.
OUT15
OUT16
OUT11P
O
O
O
LVCMOS
LVCMOS
1
1
1
39
37
48
LVCMOS clock output 15
LVCMOS clock output 16
LVCMOS /
Differential
Output 11 true output (differential) or Output 11 LVCMOS
OUT11N
OUT12P
OUT12N
OUT13P
OUT13N
OUT14P
OUT14N
OUT21P
OUT21N
OUT22P
OUT22N
OUT23P
OUT23N
OUT24P
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Differential
1
1
1
1
1
1
1
1
1
1
1
1
1
1
47
46
45
43
42
41
40
13
14
15
16
18
19
20
Output 11 complement output (differential) connect to OUT11P
for LVCMOS
LVCMOS /
Differential
Output 12 true output (differential) or LVCMOS clock output 12
Differential
Output 12 complement output (differential) connect to OUT12P
for LVCMOS
LVCMOS /
Differential
Output 13 complement output (differential) or Output 13
LVCMOS
Differential
Output 13 complement output (differential) connect to OUT13P
for LVCMOS
LVCMOS /
Differential
Output 14 true output (differential) or Output 14 LVCMOS output
Differential
Output 14 complement output (differential) connect to OUT14P
for LVCMOS
LVCMOS /
Differential
Output 21 true output (differential) or Output 21 LVCMOS output
Differential
Output 21 complement output (differential) connect to OUT21P
for LVCMOS
LVCMOS /
Differential
Output 22 true output (differential) or Output 22 LVCMOS output
Differential
Output 22 complement output (differential) connect to OUT22P
for LVCMOS
LVCMOS /
Differential
Output 23 true output (differential) or Output 23 LVCMOS output
Differential
Output 23 complement output (differential) connect to OUT23P
for LVCMOS
LVCMOS /
Differential
Output 24 true output (differential) or Output 24 LVCMOS output
Document Number: 001-89074 Rev. *M
Page 10 of 30
CY27410
Table 3. CY27410 Pin Definitions (continued)
Name
I/O
Type
# of Pins
Pin #
Function
OUT24N
O
Differential
1
21
Output 24 complement output (differential) connect to OUT24P
for LVCMOS
OUT25
OUT26
DNU
O
O
LVCMOS
LVCMOS
1
1
1
1
22
24
10
33
LVCMOS clock output 25
LVCMOS clock output 26
Pin for test purpose
SDAT
I/O
LVCMOS /
Open Drain
I2C serial data pin
SCLK
FS0
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
PWR
1
1
1
1
1
1
1
1
1
9
34
30
31
32
26
44
38
17
23
I2C clock pin
I
Frequency Select pin
FS1
I
Frequency Select pin
FS2
I
Frequency Select pin
VIN
I
Voltage input for ADC
VDDIO_D1
VDDIO_S1
VDDIO_D2
VDDIO_S2
VDD
PWR
PWR
PWR
PWR
PWR
Output power supply for Bank 1 differential outputs
Output power supply for Bank 1 LVCMOS outputs
Output power supply for Bank 2 Differential outputs
Output power supply for Bank 2 LVCMOS outputs
PWR
PWR
PWR
PWR
1, 2, 7, 11, Core power supply
12, 25, 29,
35, 36
XRES
GND
I
LVCMOS
GND
1
E-PAD
1
27
28
Active low RESET SIGNAL
GND
Analog
Supply ground
VCCD
Analog
For 1.8-V operation, connect to VDD.
For 2.5-V or 3.3-V operation, do not connect to VDD; connect a
100-nF capacitor between this pin and GND.
Document Number: 001-89074 Rev. *M
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CY27410
Figure 22. 48-Pin QFN Pinout
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VDD
VDD
VDD
SCLK
SDAT
FS2
2
3
IN2N
4
IN2P
IN1N
IN1P
VDD
5
6
FS1
7
FS0
8
XIN
XOUT
DNU
VDD
VCCD
XRES
VIN
9
10
11
12
VDD
VDD
VDD
Document Number: 001-89074 Rev. *M
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CY27410
Electrical Specifications
Exceeding maximum ratings may shorten the useful life of the device.
Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings
Symbol
VDD
VDDIOX
VIN
VINI2C
TS
Description
Core supply voltage
Output bank supply voltage
Input voltage
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–55
2000
500
200
–
Typ
–
Max
Units
V
4.6
–
4.6
V
Relative to VSS
–
VDD + 0.4
V
I2C Bus input voltage
Storage temperature
ESD (human body model)
ESD (charged device model)
ESD (machine model)
Latchup
SCLK, SDAT pins
Non functional
–
6
+150
–
V
–
°C
V
ESDHBM
ESDCDM
ESDMM
LU
JEDEC JS-001-2012
JEDEC JESD22-C101E
JEDEC JESD22-A115B
JEDEC JESD78D
V-0 at 1/8 in
–
–
–
V
–
–
V
–
140
10
–
mA
ppm
UL-94
MSL
Flammability rating
–
–
Moisture sensitivity level
–
3
Operating Temperature
Table 5. Operating Temperature
Symbol
Description
Ambient temperature
Junction temperature
Conditions
Min
–40
–40
Typ
–
Max
+85
Units
°C
TA
TJ
–
+100
°C
Operating Power Supply
Table 6. Operating Power Supply
Symbol
VDD
Description
Conditions
1.8-V range: ±5%
2.5-V range: ±10%
3.3-V range: 5%
Min
1.71
2.25
3.13
1.71
2.25
3.13
–
Typ
1.80
2.50
3.3
Max
1.89
2.75
3.46
1.89
2.75
3.46
38.0
Units
V
Core supply voltage
V
V
VDDIO
Output supply voltage
1.8-V range: ±5%
2.5-V range: ±10%
3.3-V range: 5%
1.80
2.50
3.30
–
V
V
V
IDDO
Power supply current per pair
LVPECL, output pair terminated 50
to VTT (VDD – 2 V)
mA
LVPECL, output pair terminated 50
to VTT (VDD – 1.7 V)
–
–
27.0
mA
IDDO
IDDO
Power supply current per pair
Power supply current per pair
LVDS, output pair terminated 100
–
–
–
–
13.25
26.5
mA
mA
HCSL, output pair terminated 33 to
49.9 to GND
IDDO
Power supply current per pair
CML, output pair terminated 50 to
VDD
–
–
18.0
mA
IDDO
Power supply current per pair
Current consumption per PLL
CMOS, 10-pF load, 33 MHz
Includes DIVC
–
–
–
–
–
–
6.0
26.5
3.5
mA
mA
mA
IDDPLL1
IDDXO
XO/Input block current
consumption
XO or IN1 input buffer on, IN2 input
buffer off
Document Number: 001-89074 Rev. *M
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CY27410
Table 6. Operating Power Supply (continued)
Symbol
IDDPM
Description
Conditions
Min
Typ
Max
Units
Power management block
current consumption
–
–
2.5
mA
tPLLLOCK
tLOCK
PLL lock time
Time from PLL enabled to PLL stable
(PLL reaches at ±1-ppm accuracy)
–
–
–
–
250
s
Device power-up time
Time from minimum specified VDD to
Output Stable in XO-based clock gen
mode. In the case of external clock
input, tLOCK will reduce by the crystal
oscillator startup time (tOSCSTART).
This specification is valid when the
reference is available and stable at
startup.
10.0
ms
For supply ramps slower than the
tPU_SR spec where customers use
XRES during power up. Power-up time
will be calculated from the release of
XRES to output stable.
tOSCSTART
Crystal oscillator startup time
Time from crystal oscillator power-up
to crystal oscillator stable. Crystal
FNOM = 25 MHz, C1>1 fF
–
1
–
–
4
ms
tPU_SR
Power supply slew rate during
power up
Power-supply ramp rate for VDD to
reach minimum specified voltage
(power ramp must be monotonic). For
supply ramps slower than 1 V/ms, use
XRES to externally keep the part in
RESET during power-up and release
XRES after VDD reaches the minimum
specification.
67
V/ms
DC Chip-Level Specifications
Table 7. DC Electrical Specifications Input
Symbol
VIH33
Description
Input high voltage
Conditions
Min
2.0
1.7
1.1
–
Typ
–
Max
–
Units
LVCMOS and logic inputs, VDD = 3.3 V
LVCMOS and logic inputs, VDD = 2.5 V
LVCMOS and logic inputs, VDD = 1.8 V
LVCMOS and logic inputs, VDD = 3.3 V
LVCMOS and logic inputs, VDD = 2.5 V
LVCMOS and logic inputs, VDD = 1.8 V
V
V
V
V
V
V
V
VIH25
VIH18
VIL33
VIL25
VIL18
VDIFF
Input high voltage
Input high voltage
Input low voltage
Input low voltage
Input low voltage
Differential input
–
–
–
–
–
0.8
0.7
0.5
1.45
–
–
–
–
LVDS, CML, PECL, HCSL. Differential
amplitude, pk.
0.30
–
DCDIFF
Duty cycle, differential clock input Measured at crossing point
40
40
50
50
–
60
60
%
%
DCLVCMOS Duty cycle, LVCMOS clock input Measured at 1/2 VDD
IIH
Input high current
Input = VDD
–
150
–
A
A
pF
V
IIL
Input low current
Input = GND
–150
–
–
CIN
Input capacitance, IN1, IN2
AC input swing pk
Measured at 10 MHz, differential
–
3.0
1.2
VPPSINE
Clipped sine wave, AC coupled
through a 1000-pF capacitor.
0.8
1.0
RP
Input pull-down resistance
LVCMOS clock input
75
115
170
k
Document Number: 001-89074 Rev. *M
Page 14 of 30
CY27410
DC Output Specifications
Table 8. DC Specifications for LVCMOS Output
Symbol
VOH
VOL
Description
Output high voltage
Output low voltage
Conditions
Min
VDDIO – 0.3
–
Typ
–
Max
–
Units
4-mA load
4-mA load
V
V
–
0.3
Table 9. DC Specifications for LVDS Output (VDDIO = 2.5-V or 3.3-V range)
Symbol
VPP
Description
Conditions
8 MHz to 325 MHz
Min
Typ
Max
Units
LVDS output AC single-ended
pk-pk,
250
–
510
mV
VPP
LVDS output AC single-ended
pk-pk
325 MHz to 700 MHz
200
–
–
510
50
mV
mV
V
VPP
VOCM
VOCM
IOZ
Change in VPP between comple-
mentary output states
–
1.200
–
Output common-mode voltage
Met only at 2.5 V and 3.3 V. Need AC
coupling for 1.8-V operation
1.125
–
1.375
50
Change in VOCM between
complementary output states
mV
A
Output leakage current
Output off, VOUT = 0.75 V to 1.75 V
–20
–
20
Table 10. DC Specifications for LVPECL Output (VDDIO = 2.5-V or 3.3-V range)
Symbol Description Conditions
VOH Output high voltage
Output low voltage
Min
Typ
–
Max
Units
V
R-term = 50 to VTT (VDDIO – 2.0 V) VDDIO – 1.165
R-term = 50 to VTT (VDDIO – 2.0 V) VDDIO – 2.0
VDDIO – 0.800
VOL
VPP
–
VDDIO – 1.620
V
LVPECL output AC single ended fOUT = 8 MHz to 150 MHz
450
320
–
–
–
mV
mV
pk-pk,
fOUT = 150 MHz to 700 MHz
–
Table 11. DC Specifications for CML Output (VDDIO = 2.5-V or 3.3-V range)
Symbol
VOH
Description
Output high voltage
Output low voltage
Conditions
R-term= 50 to VDDIO
R-term= 50 to VDDIO
fOUT = 8 MHz to150 MHz
Min
Typ
–
Max
–
Units
V
VDDIO – 0.1
VDDIO – 0.7
250
VOL
VPP
–
VDDIO – 0.3
700
V
CML output AC single-ended
pk-pk
–
mV
VPP
CML output AC single-ended
pk-pk
150 < fOUT < 700 MHz
200
–
600
mV
Document Number: 001-89074 Rev. *M
Page 15 of 30
CY27410
Table 12. DC Specifications for HCSL Output (VDDIO = 2.5-V or 3.3-V range)
Symbol
VOCM
Description
Conditions
Common mode
Min
350
150
Typ
–
Max
400
–
Units
mV
Output common mode voltage
Differential output high voltage
VOHDIFF
VOLDIFF
VCROSS
Measurementtakenfromdifferential
waveform
–
mV
Differential output low voltage
Measurementtakenfromdifferential
waveform
–
250
–
–
–
–
–150
550
mV
mV
mV
Absolute crossing point voltage Measurement taken from
single-ended waveform
VCROSSDELTA Variation of VCROSS over all rising Measurement taken from
140
clock edges
single-ended waveform
Table 13. Input Frequency Range
Symbol
Description
Crystal frequency
Conditions
Fundamental AT CUT crystal
Internal reference to PLL
Buffer mode, all PLLs OFF
Buffer mode, one or more PLL active
CLKGEN mode
Min
8
Typ
–
Max
48
Units
MHz
MHz
MHz
MHz
MHz
MHz
FCRYSTAL
FREFERENCE Reference frequency
8
–
40
FINCMOS
FINCMOS
FINCMOS
FINCMOS
LVCMOS input frequency
LVCMOS input frequency
LVCMOS input frequency
LVCMOS input frequency
8
–
250
125
250
250
8
–
8
–
ZDB mode, PLL in integer N configu-
ration
8
–
FINDIFF
FINDIFF
FINDIFF
FINDIFF
Differential clock input frequency Buffer mode, all PLLs OFF
Differential clock input frequency Buffer mode, one or more PLL active
Differential clock input frequency CLKGEN mode
8
8
8
8
–
–
–
–
700
125
300
300
MHz
MHz
MHz
MHz
Differential clock input frequency ZDB mode, PLL in integer N configu-
ration
FINCAS
Cascading clock frequency
Internal cascading frequency in the
Buffer mode
8
–
125
MHz
AC Input Clock Specifications
Table 14. AC Input Clock Electrical Specification
Symbol
Description
Conditions
Min
Typ
Max
Units
tCMOSDC
LVCMOS clock input duty cycle Measured at 1/2 VDD 20%–80%,
Functional
40
50
60
%
tDIFFDC
Differential clock input duty cycle Measured at VOCM 20%–80%,
Functional
40
–
50
–
60
4
tRFCMOS
LVCMOS clock input rise/fall time Measured between 20%–80% of VDD
ns
AC Output Specifications
Table 15. AC Electrical Specifications LVCMOS Output. Load: 15 pF < 100MHz, 7.5 pF < 200 MHz, 5 pF > 200 MHz
Symbol
Description
Conditions
Min
Typ
Max
Units
Common AC Electrical Specifications
tRFCMOS
tRFCMOS
tRFCMOS
Rise/fall time
fOUT < 100MHz, 20%–80%
fOUT < 200MHz, 20%–80%
fOUT < 250MHz, 20%–80%
Equally loaded, measured at 1/2 VIOX
–
–
–
–
–
–
–
–
2.0
1.5
1.3
150
ns
ns
ns
ps
Rise/fall time
Rise/fall time
Output to output skew
,
tSKEW
in a bank, derived from the same PLL,
Document Number: 001-89074 Rev. *M
Page 16 of 30
CY27410
Table 15. AC Electrical Specifications LVCMOS Output. Load: 15 pF < 100MHz, 7.5 pF < 200 MHz, 5 pF > 200 MHz (continued)
Symbol
Buffer Mode
fOUT
Description
Conditions
Min
Typ
Max
Units
Output frequency
All PLLs off
With one or more PLL running
8
8
–
–
250
125
60
MHz
MHz
%
fOUT
Output frequency
Output duty cycle
tDC
Measured at 1/2 VIOX
.
40
50
Input DC = 50%
tJIT_ADD
Additive RMS phase jitter
fOUT = 156.25 MHz,
–
–
0.7
–
1.0
ps
12 kHz-20 MHz offset, DIVI=1.
Input slew rate 1.8 V/ns,
20%–80% VDD
tDELAY
Propagation delay
Input to output delay
7.0
ns
ZDB Mode (IN1 = REF, Differential or LVCMOS feedback to IN2)
fOUT
tDC
Output frequency
Output duty cycle
8
–
250
60
MHz
%
Measured at 1/2 VIOX,
fOUT > 200 MHz,
VDDIO = 2.5 V or 3.3 V.
fOUT > 100MHz, VDDIO = 1.8 V
40
50
tDC
Output duty cycle
Cycle-to-cycle jitter
Measured at 1/2 VIOX,
45
–
50
–
55
50
%
fOUT 200 MHz VDDIO = 2.5 V or 3.3 V.
fOUT 100 MHz, VDDIO = 1.8 V
tOCCJ
pk, measured at 1/2 VIOX over
10-k cycle, fOUT = 100 MHz.
Input slew rate 1.8 V/ns,
ps
20%–80% VDD
.
Configuration dependent
tPJ
Period jitter
pk-pk, measured at 1/2 VIOX over
10-k cycle, fOUT = 100 MHz.
Input slew rate 1.8 V/ns,
–
–
–
100
350
ps
ps
20%–80% VDD
.
Configuration dependent
tPDELAY
Propagation delay
Measured at 1/2 VIOX
–350
±250 ps excludes any delay added
onboard (from output to inputs).
Delay onboard (tDELAY_BOARD) must
not exceed 2-ns max.
Total delay in the ZDB mode is
t
DELAY_BOARD + tPDELAY
CLKGEN Mode
fOUT
Output frequency
3
–
–
250
50
MHz
MHz
fOUTL
Low frequency output
1 kHz is supported when the max input
frequency to DIVL is 48 MHz
0.001
tDC
Output duty cycle
Measured at 1/2 VIOX,
fOUT > 200 MHz,
VDDIO = 2.5 V or 3.3 V.
fOUT > 100 MHz, VDDIO = 1.8 V
40
50
60
%
tDC
tCCJ
tPJ
Output duty cycle
Cycle-to-cycle jitter
Period jitter
Measured at 1/2 VIOX,
45
–
–
–
–
55
50
%
ps
ps
fOUT 200 MHz VDDIO = 2.5 V or 3.3 V.
fOUT 100 MHz, VDDIO = 1.8 V
pk, measured at 1/2 VIOX over 10-k
cycle, fOUT=100 MHz. Configuration
dependent
pk-pk, measured at 1/2 VIOX over 10-k
cycle, fOUT = 100 MHz. Input reference
25-MHz crystal. Configuration
dependent
–
100
Document Number: 001-89074 Rev. *M
Page 17 of 30
CY27410
Table 15. AC Electrical Specifications LVCMOS Output. Load: 15 pF < 100MHz, 7.5 pF < 200 MHz, 5 pF > 200 MHz (continued)
Symbol
SSC Mode
fOUT
Description
Conditions
Min
Typ
Max
Units
Output frequency
3
–
250
60
MHz
%
tDC
Output duty cycle
Measured at 1/2 VIOX,
fOUT > 200 MHz,
VDDIO = 2.5 V or 3.3 V.
fOUT > 100 MHz, VDDIO = 1.8 V
40
50
tDC
Output duty cycle
Cycle-to-cycle jitter
Measured at 1/2 VIOX
,
45
–
50
–
55
%
fOUT 200 MHz VDDIO = 2.5 V or 3.3 V.
fOUT 100 MHz, VDDIO = 1.8 V
tCCJ
pk, measured at 1/2 VIOX over
10-k cycle, fOUT = 100 MHz, with a
spread of 0.5%.
Input reference 25-MHz crystal.
Configuration dependent
100
ps
Table 16. AC Electrical Specifications, Differential Output (LVPECL, CML, LVDS) [1]
Symbol
Description
Conditions
Min
Typ
Max
Units
COMMON AC Electrical Specifications
tRF
tRF
tRF
tSK1
PECL output rise/fall time
CML output rise/fall time
LVDS output rise/fall time
Output skew
20%–80% of AC levels, measured at
622.08 MHz
–
–
–
–
–
–
–
–
450
450
450
100
ps
ps
ps
ps
20%–80% of AC levels, measured at
622.08 MHz
20%–80% of AC levels, measured at
622.08 MHz
Four differential output pairs in a bank,
derived from the same PLL, with same
standard and load conditions
BUFFER Mode
tODC
tODC
tPD
Output duty cycle
Differential input signal at 50% duty
cycle, differential signal, 622.08 MHz
45
40
–
50
50
–
55
60
4
%
%
ns
fs
Output duty cycle
LVCMOS input signal at 50% duty
cycle, differential signal, 250 MHz
Propagation delay
Measured at differential signal,
156.25 MHz
tJIT_ADD
Additive RMS phase jitter
fOUT = 156.25 MHz, 12-k to 20-MHz
offset, DIV1 = 1. Input slew rate 4 V/ns
differential 400-mV amplitude.
–
–
400
ZDB Mode (REF=IN1, 1 pair of output is feedback to IN2)
tODC
Output duty cycle
Measured at differential signal,
100 MHz
45
–
50
–
55
50
%
tCCJ
Cycle-to-cycle jitter
pk, measured differential signal over
10-k cycle, fOUT =156.25 MHz. Input
slew rate 4 V/ns differential 400-mV
amplitude. (all differential outputs on)
ps
tPJ
Period jitter
pk-pk, measured differential signal
over 10-k cycle, fOUT = 156.25 MHz.
Input slew rate 4 V/ns differential
400-mV amplitude. (all differential
outputs on)
–
–
50
ps
Note
1. AC parameters for differential outputs are guaranteed for only differential outputs. LVCMOS is Off.
Document Number: 001-89074 Rev. *M
Page 18 of 30
CY27410
Table 16. AC Electrical Specifications, Differential Output (LVPECL, CML, LVDS) [1] (continued)
Symbol
tPD
Description
Propagation delay
Conditions
Min
Typ
Max
Units
Measured differential signal,
fOUT = 156.25 MHz,
–300
–
300
ps
±250 ps is excluding any delay added
onboard (from output to inputs).
Delay onboard (tDELAY_BOARD) must
not exceed 2-ns max.
Total delay in the ZDB mode is
t
DELAY_BOARD + tPDELAY
tJRMS
RMS phase jitter
fIN = fOUT = 156.25 MHz,
–
–
–
–
–
–
0.7
–
1.0
ps
12-k to 20-MHz offset. Input slew rate
4 V/ns differential 400-mV amplitude
PNg10k
PNg100k
PNg1M
PNg10M
PN-SPUR
Phase noise, offset = 10 kHz
Phase noise, offset = 100 kHz
Phase noise, offset = 1 MHz
Phase noise, offset = 10 MHz
Spur
fIN = fOUT = 156.25 MHz.
Input slew rate 4 V/ns differential
400-mV amplitude.
–110
–119
–131
–147
–65
dBc/
Hz
fIN = fOUT = 156.25 MHz.
Input slew rate 4 V/ns differential
400-mV amplitude.
–
dBc/
Hz
fIN = fOUT = 156.25 MHz.
Input slew rate 4 V/ns differential
400-mV amplitude.
–
dBc/
Hz
fIN = fOUT = 156.25 MHz.
Input slew rate 4 V/ns differential
400-mV amplitude.
–
dBc/
Hz
At frequency offsets equal to and
greater than the update rate of the
PLL. Input slew rate 4 V/ns differential
400-mV amplitude.
–
dBc/
Hz
CLKGEN Mode
tODC Output duty cycle
Measured at differential signal,
622.08 MHz
45
–
50
–
55
50
%
tCCJ
Cycle-to-cycle jitter
pk, measured at differential signal,
156.25 MHz, over 10-k cycles. Input
frequency (24 MHz to 40 MHz) crystal.
(all differential outputs on)
ps
tPJ
Period jitter
pk-pk, measured at differential signal
156.25 MHz, over 10-k cycles. Input
frequency (24 MHz to 40 MHz) crystal.
(all differential outputs on)
–
–
50
ps
ps
tJRMS
RMS phase jitter
fOUT = 156.25 MHz,
12-k to 20-MHz offset
–
–
–
–
–
–
0.7
–
1.0
PNg10k
PNg100k
PNg1M
PNg10M
PN-SPUR
Phase noise, offset = 10 kHz
Phase noise, offset = 100 kHz
Phase noise, offset = 1 MHz
Phase noise, offset = 10 MHz
Spur
fOUT=156.25 MHz. Input reference
25-MHz crystal
–110
–119
–131
–147
–65
dBc/
Hz
fOUT=156.25 MHz. Input reference
25-MHz crystal
–
dBc/
Hz
fOUT = 156.25 MHz. Input reference
25-MHz crystal
–
dBc/
Hz
fOUT = 156.25 MHz. Input reference
25-MHz crystal
–
dBc/
Hz
At frequency offsets equal to and
greater than the update rate of the PLL
–
dBc/
Hz
Document Number: 001-89074 Rev. *M
Page 19 of 30
CY27410
Table 16. AC Electrical Specifications, Differential Output (LVPECL, CML, LVDS) [1] (continued)
Symbol
SSC Mode
tCCJ
Description
Conditions
Min
Typ
Max
Units
Cycle-to-cycle jitter
pk, measured at differential signal,
156.25 MHz, over 10-k cycles. Input
frequency (24 MHz to 40 MHz) crystal,
with a spread of 0.5% (all differential
outputs on).
–
–
70
ps
Table 17. AC Electrical Specification HSCL Output [2, 3]
Symbol Description
Common AC Electrical Specifications
Conditions
Min
Typ
Max
Units
fOC
ER
Output frequency
Rising edge rate
HCSL
Measurement
96
–
–
400
4
MHz
V/ns
taken
from
from
0.6
differential waveform,
–150 mV to +150 mV
EF
Falling edge rate
Measurement
differential waveform, –150 mV to
+150 mV
taken
0.6
500
–
–
–
–
–
4
–
V/ns
ps
TSTABLE
Time before VRB is allowed
Measurement taken from
differential waveform,
–150 mV to +150 mV
TPERIOD_AVG Average clock period accuracy, Measurement taken from
–300
9.874
–20
2800
10.203
+20
ppm
ns
100 MHz
differential waveform, Spread
Spectrum On, 0.5% down spread
TPERIOD_ABS
Absolute period, 100 MHz
Measurement taken from
differential waveform, Spread
Spectrum On, 0.5% down spread
R-FMATCHING Rise-fall matching
Measurement
taken
from
%
single-ended waveform. Rising
edge rate to falling edge rate
matching 100 MHz
BUFFER Mode
TDC
Duty cycle
Measurement taken from
differential waveform
45
–
50
–
55
%
tRMS_ADD
Additive phase noise
Input slew rate 4 V/ns differential
400-mV amplitude.
0.4
ps
(RMS)
ZDB Mode (REF = IN1, 1 output pair fed back to IN2)
TDC
Duty cycle
Measurement taken from
differential waveform
45
–
50
–
55
50
%
TCCJITTER
Cycle-to-cycle jitter
pk, measured at differential signal
100 MHz, over 10-k cycles. Input
slew rate 4 V/ns differential
400-mV amplitude (all differential
outputs on).
ps
JRMS
Random jitter PCIe 3.0 Common PCIe Gen3 filters. Input slew rate
–
0.7
–
1.0
ps
clocked
4 V/ns differential 400-mV
amplitude.
(RMS)
tPD
Propagation delay
Early/Late option is OFF
–300
300
ps
Notes
2. AC parameters for differential outputs are guaranteed for only differential outputs. LVCMOS is Off.
3. All output clocks 100MHz HCSL format. Jitter is from PCIE jitter filter combination that produces the highest jitter.
Document Number: 001-89074 Rev. *M
Page 20 of 30
CY27410
Table 17. AC Electrical Specification HSCL Output [2, 3] (continued)
Symbol
CLKGEN Mode
TDC
Description
Duty cycle
Cycle-to-cycle jitter
Conditions
Min
Typ
Max
Units
Measurement taken from
differential waveform
45
–
50
–
55
50
%
TCCJITTER
pk, measured at differential signal,
100 MHz, over 10-k cycles. Input
frequency (24 MHz–40 MHz)
ps
crystal (all differential outputs on).
JRMS
Random jitter PCIe 3.0 Common REF = 25-MHz crystal,
clocked fOUT = 100 MHz, PCIe Gen3 filters
–
0.7
1.0
ps
Table 18. AC I2C Specifications
Symbol Description
fSCK
Conditions
Min
Typ
Max
400
–
Units
kHz
s
SCK clock frequency
0
–
–
0.6
t
t
Hold time START condition
HD:STA
1.3
–
–
s
Low period of the SCK clock
High period of the SCK clock
LOW
tHIGH
0.6
0.6
–
–
–
–
s
s
tSU:STA
Setup time for a repeated START
condition
tHD:DAT
tSU:DAT
tR
Data hold time
Data setup time
Rise time
0
100
–
–
–
–
–
–
–
–
–
s
ns
ns
ns
s
s
300
300
–
tF
Fall time
–
tSU:STO
tBUF
Setup time for STOP condition
0.6
1.3
Bus-freetimebetweenSTOPand
START conditions
–
Table 19. Spread-Spectrum Specifications
Symbol Description
FMOD Modulation rate
Conditions
Min
30
0.1
–
Typ
–
Max
60
Units
kHz
%
SSper
Spread spectrum amount
Spread spectrum% step
Total %
–
5.0
–
SSStep
0.1
%
Document Number: 001-89074 Rev. *M
Page 21 of 30
CY27410
Table 20. Output Selection Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
tFS
Frequency switching time
Frequency switching time for
OUT13,14, 23, 24. Both PLLs are
active (change MUX selection Bit).
–
–
500
µs
tFS
tFS
Frequency switching time
Frequency switching time
Output turn-on time
Frequency switching time for all
outputs, DIVO value change
–
–
–
–
–
–
–
–
–
–
500
1000
500
µs
µs
µs
µs
µs
Frequency switching time for all
outputs. PLL value change.
Output turn-on time from FS. PLL is
active, change OE or MUX.
t
t
t
FS
Output turn-on time
Output turn-on time from FS.
Resume PLL from Power Down.
1000
500
FS
Output turn-off time
Output turn-off time from FS. PLL is
active, change OE or MUX.
OFF
Table 21. NV Memory Specification
Symbol
DRET
PROGCYCLE
Description
NV memory data retention
Programming cycle
Conditions
Min
Typ
Max
–
Units
Years
Cycle
10
–
–
Programming cycle for NV
memory
100K
–
Table 22. Miscellaneous Specifications
Symbol Description
tXRES XRES Low time
TPROG
CINADC
Conditions
Min
10
5
Typ
–
Max
–
Units
µs
Flash programming temperature
Input capacitance VIN pin
–
55
10
°C
–
–
pF
Table 23. Thermal Resistance
Parameter [4]
Description
Test Conditions
48-pin QFN
Unit
θJA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
15.64
°C/W
θJC
Thermal resistance
(junction to case)
2.21
°C/W
Note
4. These parameters are guaranteed by design and are not tested.
Document Number: 001-89074 Rev. *M
Page 22 of 30
CY27410
Test and Measurement Circuits
Figure 23. LVPECL Output Load and Test Circuit
Figure 24. LVDS Output Load and Test Circuit
V
– 2 V
V
DDIO
DDIO
V
DDIO
50
50
50
50
50
50
TP
TP
TP
TP
100
Figure 25. CML Output Load and Test Circuit
Figure 26. HCSL Output Load and Test Circuit
V
DDIO
V
V
DDIO
DDIO
5”
50
50
50
50
33
TP
TP
50
TP
TP
2 pF
2 pF
33
50
49.9
49.9
Figure 27. LVCMOS Output Load and Test Circuit
V
DDIO
TP
C
LOAD
Document Number: 001-89074 Rev. *M
Page 23 of 30
CY27410
Voltage and Timing Definitions
Figure 28. LVCMOS Input Definitions
Figure 29. LVCMOS Output Definitions
t
= t1 / (t1 + t2)
t
= t1 / (t1 + t2)
DC
ODC
t1
t2
t1
80% of V
t2
V
V
IH
OH
80% of V
DD
DD
IOX
50% of V
Clock
50% of V
OUT
DD
IOX
20% of V
20% of V
V
IOX
IL
V
OL
t
t
t
t
R
F
R
F
Figure 30. Differential Input Definitions
Figure 31. Differential Output Definitions
t
= t
/ t
PW PERIOD
t
= t
/ t
V
= (V + V ) / 2
OCM A B
DC
V
= (V + V ) / 2
A B
DC
PW PERIOD
OCM
t
t
PERIOD
PERIOD
t
t
PW
PW
V
V
A
OUT-P
OUT-N
A
Clock-P
Clock-N
80% 80%
V
V
PP
PP
ID
20%
20%
V
V
B
B
t
t
R
F
Figure 32. Skew Definition
Figure 33. Propagation Delay Definition
50% of V
50% of V
IOX
OUTx
OUTy
IOX
INx
50% of V
50% of V
IOX
IOX
OUTy
t
t
PD
SK1
OUTx
OUTy
INx
V
V
OCM
OCM
OUTy
V
V
OCM
OCM
Figure 34. Output Enable/Disable/Frequency Select Timing
Figure 35. HCSL Single-ended Measurement Point-2
Rise and Fall Time Matching
Original Clock
New Clock
TFALL
TRISE
OUT‐N
VCROSS MEDIAN +75 mV
VCROSS MEDIAN
CLOCK
FS
OUT‐N
VCROSS MEDIAN
VCROSS MEDIAN ‐75 mV
tOFF
tFS
OUT‐P
OUT‐P
Figure 36. HCSL Differential Measurement Point
Figure 37. HCSL Differential Measurement for Ringback
Duty Cycle and Period
TSTABLE
VRB
Clock Period (Differential)
Negative Duty
V
= +150 mV
VRIHB = +100 mV
Cycle (Differential)
Positive Duty
Cycle (Differential)
V
RB = ‐100 mV
0.0 V
V
IL = ‐150 mV
OUT‐P +
OUT‐N
OUT‐P +
OUT‐N
VRB
TSTABLE
Document Number: 001-89074 Rev. *M
Page 24 of 30
CY27410
Figure 38. HCSL Rise and Fall Time
Figure 39. Power Ramp and PLL Lock Time
Rise and Fall Time
V
(min)
t
DD
PU
Rising Edge Rate
Falling Edge Rate
Supply
Voltage
0.5 V
LOCK
t
VIH = +150 mV
0.0 V
Stable Output
VIL = ‐150 mV
Output
OUT‐P +
OUT‐N
Figure 40. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDAT
SCLK
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
tr
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tHIGH
P
S
S
Sr
Document Number: 001-89074 Rev. *M
Page 25 of 30
CY27410
Packaging Information
This section illustrates the packaging specifications for the CY27410 device.
Important Note The EPAD must be connected to ground to reduce the thermal resistance and for signaling ground.
Figure 41. 48-Pin QFN (7 × 7 × 1.00 mm) LT48D 5.6 × 5.6 E-Pad (Sawn) Package Outline
001-45616 *F
For information on the preferred dimensions for mounting QFN packages, refer to the Cypress application note
AN72845 - Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices.
Solder Reflow Specifications
Table 24 shows the solder reflow temperature limits that must not be exceeded.
Table 24. Solder Reflow Specifications
Package
Maximum Peak Temperature (TC)
Maximum Time above TC – 5 °C
30 seconds
48-pin QFN
260 C
Document Number: 001-89074 Rev. *M
Page 26 of 30
CY27410
Ordering Information
The following table lists the CY27410 device’s key package features and ordering codes.
Table 25. Ordering Information
Part Number
CY27410FLTXI
Configuration
Field programmable
Field programmable
Factory configured
Factory configured
Package
48-pin QFN
48-pin QFN – Tape and Reel Industrial, –40 °C to +85 °C
48-pin QFN Industrial, –40 °C to +85 °C
48-pin QFN – Tape and Reel Industrial, –40 °C to +85 °C
Production Flow
Industrial, –40 °C to +85 °C
CY27410FLTXIT
CY27410LTXI-xxx
CY27410LTXI-xxxT
Ordering Code Definitions
CY
27410
F
LT
X I - xxx
T
Tape and Reel
Customer part configuration code
Temperature Range: I = Industrial
Pb-free: X= Pb free
Package Type: LT: 48-pin QFN
Configuration: F = Field programmable, Blank= Factory Configured
Marketing code: 274XX = Device number
Company ID: CY = Cypress
Document Number: 001-89074 Rev. *M
Page 27 of 30
CY27410
Acronyms
Document Conventions
Table 26. Acronyms Used in this Document
Units of Measure
Acronym
AC
Description
Table 27. Units of Measure
alternating current
Symbol
°C
Unit of Measure
ADC
API
analog-to-digital converter
application programming interface
current-mode logic
degree Celsius
decibels relative to the carrier
femtofarad
dBc
fF
CML
CMOS
DC
fs
femtosecond
gram
complementary metal oxide semiconductor
direct current
g
GHz
Hz
KHz
Ksps
k
MHz
M
A
F
H
s
gigahertz
ESD
FS
electrostatic discharge
hertz
frequency select
kilohertz
GUI
graphical user interface
high-speed current steering logic
inter-integrated circuit
kilo samples per second
kilohm
HCSL
2
I C
megahertz
I/O
input/output
megaohm
ISSP
JEDEC
LDO
LSB
in-system serial programming
Joint Electron Devices Engineering Council
low dropout (regulator)
microampere
microfarad
microhenry
microsecond
microwatt
least-significant bit
W
mA
ms
mV
nA
nF
LVCMOS low voltage complementary metal oxide semicon-
ductor
milliampere
millisecond
millivolt
LVDS
LVPECL
MSB
NV
low-voltage differential signals
low-voltage positive emitter-coupled logic
most-significant byte
non-volatile
nanoampere
nanofarad
ns
nanosecond
nanovolt
NZDB
OE
non-zero delay buffer
output enable
nV
ohm
PCIe
POR
PCI express
pA
pF
picoampere
picofarad
power-on reset
®
PSoC
Programmable System-on-Chip
quad flat no-lead
pp
peak-to-peak
parts per million
parts per billion
picosecond
samples per second
sigma: one standard deviation
volt
QFN
ppm
ppb
ps
RMS
SCLK
SDAT
TSSOP
USB
root mean square
2
serial I C clock
2
serial I C data
sps
thin shrunk small outline package
universal serial bus
crystal
V
XTAL
ZDB
W
watt
zero delay buffer
Document Number: 001-89074 Rev. *M
Page 28 of 30
CY27410
Document History Page
Document Title: CY27410, 4-PLL Spread-Spectrum Clock Generator
Document Number: 001-89074
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
*G
4866820
BPIN
XHT
XHT
07/31/2015 Changed status from Preliminary to Final.
Post to external web.
*H
*I
4889775
4930976
08/19/2015 Updated Features:
Replaced “75-ps skew” with “100-ps skew”.
09/23/2015 Updated Functional Overview:
Updated Input System:
Updated description.
*J
5090700
XHT
01/18/2016 Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Completing Sunset Review.
*K
*L
5351208
5682054
XHT
PSR
07/14/2016 Updated Cy Logo and Copyright.
04/03/2017 Added Functional Description.
Updated Packaging Information:
spec 001-45616 – Changed revision from *E to *F.
Updated to new template.
*M
6486386
XHT
02/15/2019 Updated to new template.
Completing Sunset Review.
Document Number: 001-89074 Rev. *M
Page 29 of 30
CY27410
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
®
®
Arm Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-89074 Rev. *M
Revised February 15, 2019
Page 30 of 30
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