CY62126EV30LL-45BVXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62126EV30LL-45BVXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 |
| 文件： | 总18页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62126EV30 MoBL®
1-Mbit (64 K × 16) Static RAM
1-Mbit (64
K × 16) Static RAM
Features
Functional Description
■ High speed: 45 ns
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write
operation (CE LOW and WE LOW).
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62126DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A
■ Ultra low active power
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
■ Offered in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP) II
packages
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
64K x 16
I/O0–I/O7
RAM Array
I/O8–I/O15
A2
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05486 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 24, 2017
CY62126EV30 MoBL®
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure .......................................................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support .......................18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support .....................................................18
Document Number: 38-05486 Rev. *P
Page 2 of 18
CY62126EV30 MoBL®
Pin Configuration
Figure 1. 48-ball VFBGA pinout (Top View)
Figure 2. 44-pin TSOP II pinout (Top View) [1]
1
2
4
3
5
6
NC
I/O
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
A
A
2
A
OE
A
A
A
BLE
0
1
A
B
C
2
1
0
A
A
I/O BHE
CE
I/O
4
3
0
8
CE
I/O
I/O
I/O
I/O
0
A
A
6
I/O I/O
I/O
2
5
10
1
1
2
3
9
14
9
10
11
12
13
14
15
16
V
12
A
V
I/O
I/O
3
NC
NC
cc
D
E
F
SS
7
11
V
V
SS
CC
V
SS
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
Vss
NC
V
I/O
I/O
CC
4
12
4
11
10
5
6
7
9
A
A
15
I/O
I/O
I/O
I/O
14
13
5
14
6
8
WE 17
NC
A
A
15
A
14
A
13
A
12
18
19
20
21
22
A
A
G
H
I/O
I/O
NC
WE
8
13
12
15
7
A
9
A
10
A
A
A
NC
A
NC
10
9
11
A
11
NC
8
NC
Product Portfolio
Power Dissipation
Operating, ICC (mA)
f = 1 MHz f = fmax
VCC Range (V)
Speed
(ns)
Standby, ISB2
Product
Range
(A)
Min
Typ[2]
3.0
Max
3.6
3.6
3.6
Typ[2]
Max
Typ[2]
Max
16
Typ[2]
Max
4
CY62126EV30LL
Industrial
2.2
2.2
2.2
45
45
55
1.3
1.3
1.3
2
2
4
11
11
11
1
1
1
CY62126EV30LL Automotive-A
CY62126EV30LL Automotive-E
3.0
16
4
3.0
35
30
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 38-05486 Rev. *P
Page 3 of 18
CY62126EV30 MoBL®
DC input voltage [3, 4] 0.3 V to 3.6 V (VCCmax + 0.3 V)
Maximum Ratings
Output current into outputs (LOW) ............................. 20 mA
Exceeding maximum ratings may shorten the battery life of the
device. These user guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch up current .................................................... > 200 mA
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Operating Range
Supply voltage
to ground potential [3, 4] .....–0.3 V to 3.6 V (VCCmax + 0.3 V)
Ambient
[5]
Device
Range
VCC
Temperature
DC voltage applied to outputs
in High Z state [3, 4] .............–0.3 V to 3.6 V (VCCmax + 0.3 V)
CY62126EV30LL Industrial / –40 °C to +85 °C 2.2 V to
Automotive-A
3.6 V
Automotive-E –40 °C to +125 °C
Electrical Characteristics
Over the Operating Range
45 ns (Industrial /
Automotive-A)
Min Typ[6]
Max
55 ns (Automotive-E)
Parameter
Description
Test Conditions
IOH = –0.1 mA
Unit
Min Typ[6]
Max
VOH
Output high voltage
2.0
2.4
–
–
–
–
–
–
–
–
–
–
–
–
2.0
2.4
–
–
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
–
VOL
VIH
VIL
Output low voltage
Input high voltage
Input low voltage
0.4
0.4
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
GND < VI < VCC
–
–
–
–
–
–
–
–
–
0.4
V
1.8
2.2
–0.3
–0.3
–1
VCC + 0.3 1.8
VCC + 0.3 2.2
VCC + 0.3
VCC + 0.3
0.6
V
V
0.6
0.8
+1
–0.3
–0.3
–4
V
0.8
V
IIX
Input leakage current
+4
A
A
IOZ
Output leakage current GND < VO < VCC, Output
Disabled
–1
+1
–4
+4
ICC
VCC operating supply
current
f = fmax = 1/tRC VCC = VCCmax
–
–
11
16
–
–
11
35
mA
IOUT = 0 mA
f = 1 MHz
1.3
2.0
1.3
4.0
CMOS levels
[7]
ISB1
Automatic CE power
down current —CMOS
inputs
CE > VCC 0.2 V,
–
–
1
1
4
4
–
–
1
1
35
30
A
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
V
CC = 3.60 V
CE > VCC – 0.2 V,
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
[7]
ISB2
Automatic CE power
down current —CMOS
inputs
A
V
Notes
3.
4.
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
V
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
5. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
cc
cc
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
7. Chip enable (CE) needs to be tied to CMOS levels to meet the I
/ I
/ I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
Document Number: 38-05486 Rev. *P
Page 4 of 18
CY62126EV30 MoBL®
Capacitance
Parameter [8]
Description
Test Conditions
Max
10
Unit
pF
CIN
Input capacitance
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
Output capacitance
10
pF
Thermal Resistance
48-ballVFBGA 44-pin TSOP II
Parameter [8]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 4.25 × 1.125 inch,
two-layer printed circuit board
58.85
28.2
°C/W
JC
Thermal resistance
(junction to case)
17.01
3.4
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
VCC
OUTPUT
VCC
GND
90%
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.2 V–2.7 V
16600
15400
8000
2.7 V–3.6 V
1103
Unit
R1
R2
1554
RTH
VTH
645
1.2
1.75
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05486 Rev. *P
Page 5 of 18
CY62126EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
Typ [9]
Max
Unit
V
1.5
–
–
[10]
ICCDR
VCC = VDR
,
Industrial /
Automotive-A
A
–
–
3
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
A
Automotive-E
–
0
–
–
30
–
VIN < 0.2 V
[11]
tCDR
Chip deselect to data retention
time
ns
ns
[12]
tR
Operation recovery time
CY62126EV30LL-45
CY62126EV30LL-55
45
55
–
–
–
–
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
> 1.5 V
VCC
CE
DR
t
t
R
CDR
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
10. Chip enable (CE) needs to be tied to CMOS levels to meet the I
/ I
/ I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device AC operation requires linear V ramp from V to V > 100 s.
CC
DR
CC(min)
Document Number: 38-05486 Rev. *P
Page 6 of 18
CY62126EV30 MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Industrial /
Automotive-A)
55 ns (Automotive-E)
Parameter [13, 14]
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
10
–
10
–
tACE
45
22
–
55
25
–
–
–
tDOE
OE LOW to data valid
OE LOW to Low Z [15]
OE HIGH to High Z [15, 16]
CE LOW to Low Z [15]
CE HIGH to High Z [15, 16]
tLZOE
5
–
5
–
tHZOE
18
–
20
–
tLZCE
10
–
10
–
tHZCE
18
–
20
–
tPU
CE LOW to power up
0
–
–
0
–
–
tPD
CE HIGH to power down
BHE / BLE LOW to data valid
BHE / BLE LOW to Low Z [15]
BHE / BLE HIGH to High Z [15, 16]
45
22
–
55
25
–
tDBE
tLZBE
5
–
5
–
tHZBE
18
20
Write Cycle [17, 18]
tWC
Write cycle time
45
–
–
–
–
–
–
–
–
–
55
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
CE LOW to write end
35
35
0
40
40
0
ns
ns
ns
ns
Address setup to write end
Address hold from write end
Address setup to write start
tSA
0
0
tPWE
tBW
tSD
WE pulse width
35
35
25
0
40
40
25
0
ns
ns
ns
ns
BHE / BLE pulse width
Data setup to write end
Data hold from write end
tHD
WE LOW to High Z [15, 16]
WE HIGH to Low Z [15]
18
–
20
–
ns
ns
–
–
tHZWE
tLZWE
10
10
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels of 0 to V
, and output loading of the specified
CC(typ)
CC(typ)
I
/I and 30-pF load capacitance.
OL OH
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
16. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
17. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
18. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to sum of t and t
SD
.
HZWE
Document Number: 38-05486 Rev. *P
Page 7 of 18
CY62126EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address transition controlled) [19, 20]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Figure 6. Read Cycle No. 2 (OE controlled) [20, 21]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
19. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V .
IL
IL
20. WE is high for read cycle.
21. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05486 Rev. *P
Page 8 of 18
CY62126EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE controlled) [22, 23, 24]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 25
DATAIN
DATA I/O
t
HZOE
Figure 8. Write Cycle No. 2 (CE controlled) [22, 23, 24]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 25
t
HZOE
Notes
22. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any
IL
IL
of these signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.
23. Data I/O is high impedance if OE = V
.
IH
24. If CE goes high simultaneously with WE = V , the output remains in a high impedance state.
IH
25. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05486 Rev. *P
Page 9 of 18
CY62126EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW [26, 27]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA I/O
NOTE 28
DATAIN
t
LZWE
t
HZWE
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW) [26]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 28
DATAIN
DATA I/O
tLZWE
Notes
26. If CE goes high simultaneously with WE = V , the output remains in a high impedance state.
IH
27. The minimum write cycle pulse width should be equal to sum of t and t
.
SD
HZWE
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05486 Rev. *P
Page 10 of 18
CY62126EV30 MoBL®
Truth Table
CE[29]
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Deselect/power down
Output disabled
Read
Power
H
L
L
L
Standby (ISB)
X
X
H
H
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
H
L
L
L
Data out (I/O0–I/O15)
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data in (I/O0–I/O15)
L
H
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC
)
Note
29. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05486 Rev. *P
Page 11 of 18
CY62126EV30 MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62126EV30LL-45BVXI
CY62126EV30LL-45ZSXI
CY62126EV30LL-45ZSXA
CY62126EV30LL-55BVXE
CY62126EV30LL-55ZSXE
45
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Industrial
Industrial
Automotive-A
Automotive-E
Automotive-E
55
Contact your local Cypress sales representative for availability of other parts.
Ordering Code Definitions
V30 LL - XX XX
E
X
X
2
621
CY
6
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
Voltage: V30 = 3 V Typical
Process Technology: E = 90 nm
Bus Width: 6 = × 16
Density: 2 = 1-Mbit
Family Code: 621= MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05486 Rev. *P
Page 12 of 18
CY62126EV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *H
Document Number: 38-05486 Rev. *P
Page 13 of 18
CY62126EV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05486 Rev. *P
Page 14 of 18
CY62126EV30 MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
Chip Enable
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
°C
MHz
µA
µs
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
OE
Output Enable
RAM
SRAM
TSOP
VFBGA
WE
Random Access Memory
Static Random Access Memory
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05486 Rev. *P
Page 15 of 18
CY62126EV30 MoBL®
Document History Page
Document Title: CY62126EV30 MoBL®, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05486
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
202760
300835
See ECN
See ECN
AJU
SYT
New data sheet.
*A
Converted from Advance Information to Preliminary
Specified Typical standby power in the Features Section
Changed E3 ball from DNU to NC in the Pin Configuration for the FBGA
Package and removed the footnote associated with it on page #2
Changed tOHA from 6 ns to 10 ns for both 35- and 45-ns speed bins,
respectively
Changed tDOE, tSD from 15 to 18 ns for 35-ns speed bin
Changed tHZOE, tHZBE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 ns
and 45 ns speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35- and 45-ns speed
bins, respectively
Changed tSCE,tBW from 25 and 40 ns to 30 and 35 ns for the 35- and 45-ns
speed bins, respectively
Changed tAW from 25 to 30 ns and 40 to 35 ns for 35 and 45-ns speed bins
respectively
Changed tDBE from 35 and 45 ns to 18 and 22 ns for the 35 and 45 ns speed
bins respectively
Removed footnote that read “BHE.BLE is the AND of both BHE and BLE. Chip
can be deselected by either disabling the chip enable signals or by disabling
both BHE and BLE” on page # 4
Removed footnote that read “If both BHE and BLE are toggled together, then
tLZBE
is 10 ns” on page # 5
Added Pb-free package information
*B
461631
See ECN
NXR
Converted from Preliminary to Final
Removed 35 ns Speed Bin
Removed “L” version of CY62126EV30
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for
f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz, ISB1, ISB2 (max) from
1 A to 4 A, ISB1, ISB2 (Typ) from 0.5 A to 1 A, ICCDR (max) from 1.5 A to
3 A, AC Test load Capacitance value from 50 pF to 30 pF, tLZOE from 3 to
5 ns, tLZCE from 6 to 10 ns, tHZCE from 22 to 18 ns, tLZBE from 6 to 5 ns, tPWE
from 30 to 35 ns, tSD from 22 to 25 ns, tLZWE from 6 to 10 ns, and updated the
Ordering Information table.
*C
*D
*E
*F
925501
1045260
2631771
2944332
See ECN
See ECN
01/07/09
VKN
VKN
Added footnote #7 related to ISB2 and ICCDR
Added footnote #11 related AC timing parameters
Added Automotive information
Updated Ordering Information table
NXR / PYRS Changed CE condition from X to L in Truth table for Output Disable mode
Updated template
06/04/2010
VKN
Added Contents
Removed byte enable from footnote #2 in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Updated links in Sales, Solutions, and Legal Information
*G
*H
2996166
3113864
07/29/2010
12/17/2010
AJU
Added CY62126EV30LL-45ZSXA part in Ordering Information.
Added Ordering Code Definitions.
Modified table footnote format.
PRAS
Updated Figure 1 and Package Diagram, and fixed Typo in Figure 3.
Document Number: 38-05486 Rev. *P
Page 16 of 18
CY62126EV30 MoBL®
Document History Page (continued)
Document Title: CY62126EV30 MoBL®, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05486
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
*I
3270487
05/31/2011
RAME
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Electrical Characteristics.
Updated Data Retention Characteristics.
Added Acronyms and Units of Measure.
Updated to new template.
*J
4205722
11/29/2013
MEMJ
Updated Features:
Added Automotive-A range information.
Updated Product Portfolio:
Added Automotive-A range information.
Updated Operating Range:
Segregated Automotive-A and Automotive-E ranges.
Updated Electrical Characteristics:
Added Automotive-A with Industrial for 45 ns speed bin.
Renamed Automotive as Automotive-E for 55 ns speed bin.
Updated Data Retention Characteristics:
Segregated Automotive-A and Automotive-E in conditions for ICCDR
parameter.
Updated Switching Characteristics:
Added Automotive-A with Industrial for 45 ns speed bin.
Renamed Automotive as Automotive-E for 55 ns speed bin.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Updated to new template.
*K
*L
4211675
4410948
12/12/2013
06/17/2014
MEMJ
VINI
No technical updates.
Removed the border lines in Package Diagram specs.
Updated Switching Characteristics:
Added Note 18 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 27 and referred the same note in Figure 9.
Completing Sunset Review.
*M
*N
*O
*P
4576475
4612072
4797476
5975641
11/21/2014
01/05/2015
06/15/2015
VINI
VINI
VINI
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Maximum Ratings:
Referred Notes 3, 4 in “Supply voltage to ground potential”.
Updated to new template.
Completing Sunset Review.
11/24/2017 AESATMP9 Updated logo and Copyright.
Document Number: 38-05486 Rev. *P
Page 17 of 18
CY62126EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
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cypress.com/arm
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
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Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
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cypress.com/support
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cypress.com/psoc
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Wireless Connectivity
cypress.com/pmic
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© Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05486 Rev. *P
Revised November 24, 2017
Page 18 of 18
相关型号：
CY62126EV30LL-45BVXIT
Standard SRAM, 64KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
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