CY621472E30LL-45ZSXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY621472E30LL-45ZSXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY621472E30 MoBL
4-Mbit (256K × 16) Static RAM
4-Mbit (256K
× 16) Static RAM
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE1
HIGH or CE2 LOW or both BLE and BHE are HIGH). The input
and output pins (I/O0 through I/O15) are placed in a high
impedance state when:
Features
■ Very high speed: 45 ns
■ Temperature range
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Deselected (CE1 HIGH or CE2 LOW)
■ Outputs are disabled (OE HIGH)
■ Ultra low standby power
❐ Typical standby current: 2.5 A
❐ Maximum standby current: 7 A (Industrial)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE Features
■ Write operation is active (CE1 LOW and CE2 HIGH and WE
LOW)
■ Automatic power down when deselected
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A17). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A17).
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 44-pin thin small outline package
(TSOP) II package
■ Byte power down feature
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
11 for a complete description of read and write modes.
Functional Description
The CY621472E30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
I/O0–I/O7
RAM Array
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
POWER DOWN
CIRCUIT
BHE
BLE
CE
1
CE
2
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-67798 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY621472E30 MoBL
Contents
Product Portfolio ..............................................................3
Pin Configuration .............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagram ............................................................13
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................16
Worldwide Sales and Design Support .......................16
Products ....................................................................16
PSoC® Solutions ......................................................16
Cypress Developer Community .................................16
Technical Support .....................................................16
Document Number: 001-67798 Rev. *G
Page 2 of 16
CY621472E30 MoBL
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fmax
VCC Range (V)
Speed
(ns)
Standby ISB2
Product
Range
(A)
Min
2.2
Typ [1] Max
3.0 3.6
Typ [1] Max Typ [1] Max Typ [1] Max
CY621472E30LL
Industrial
45
3.5
6
15
20
2.5
7
Pin Configuration
Figure 1. 44-pin TSOP II pinout
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
A
A
A
2
1
0
CE
I/O
I/O
I/O
1
0
1
14
9
2
I/O
10
11
12
13
14
15
16
3
12
V
V
CC
SS
V
SS
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
4
11
10
5
6
7
9
8
WE 17
CE
A
2
A
A
A
A
A
18
19
20
17
16
15
8
A
9
A
A
A
10
14 21
13 22
11
12
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 001-67798 Rev. *G
Page 3 of 16
CY621472E30 MoBL
DC input voltage [2, 3] ......... –0.3 V to 3.9 V (VCCmax + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch up current......................................................> 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Supply voltage to ground
potential ...........................–0.3 V to +3.9 V (VCCmax + 0.3 V)
Ambient
[4]
Device
Range
VCC
DC Voltage Applied to Outputs
Temperature
in High Z State [2, 3] ............–0.3 V to 3.9 V (VCCmax + 0.3 V)
CY621472E30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
45 ns
Typ [5]
Parameter
VOH
Description
Test Conditions
Unit
Min
2.0
2.4
–
Max
Output HIGH voltage
IOH = –0.1 mA
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
–
0.4
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
–
V
IOL = 2.1 mA, VCC = 2.70 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC= 2.7 V to 3.6 V
GND < VI < VCC
–
–
0.4
V
1.8
2.2
–0.3
–0.3
–1
–1
–
–
VCC + 0.3
VCC + 0.3
0.6
V
–
V
–
V
–
0.8
V
IIX
Input leakage current
Output leakage current
–
+1
A
A
mA
IOZ
ICC
GND < VO < VCC, Output Disabled
–
+1
VCC operating supply current f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
OUT = 0 mA
CMOS levels
15
3.5
20
I
–
6
[6]
[6]
ISB1
Automatic CE power-down
current – CMOS inputs
CE1 > VCC – 0.2 V, CE2 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
–
2.5
7
A
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
ISB2
Automatic CE Power down
current – CMOS inputs
–
2.5
7
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
2.
3.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
4. Full device AC operation assumes a minimum of 100 s ramp time from 0 to V
and 200 s wait time after V stabilization.
CC
CC(min)
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
CC
CC(typ)
A
6. Chip enables (CE and CE ) need to be tied to CMOS levels to meet the I
/I
/I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
Document Number: 001-67798 Rev. *G
Page 4 of 16
CY621472E30 MoBL
Capacitance
Parameter [7]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
44-pin TSOP II
Package
Parameter [7]
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
77
C/W
JC
Thermal resistance
(junction to case)
13
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
90%
90%
VCC
OUTPUT
10%
10%
Fall Time = 1 V/ns
GND
R2
30 pF
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50 V
16667
15385
8000
3.0 V
1103
1554
645
Unit
R1
R2
RTH
VTH
1.20
1.75
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-67798 Rev. *G
Page 5 of 16
CY621472E30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.5
–
Typ [8]
Max
–
Unit
V
–
3
[9]
ICCDR
VCC = 1.5 V,
8.8
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
[10]
tCDR
Chip deselect to data retention
time
0
–
–
–
–
ns
ns
[11]
tR
Operation recovery time
45
Data Retention Waveform
Figure 3. Data Retention Waveform [12, 13]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5 V
VCC
t
t
CDR
R
CE or
BHE.BLE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
9. Chip enables (CE and CE ) need to be tied to CMOS levels to meet the I / I / I spec. Other inputs can be left floating.
SB1 SB2 CCDR
1
2
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V ramp from V to V > 100 s or stable at V
> 100 s.
CC
DR
CC(min)
CC(min)
12. CE refers to the internal logical combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.
1
2
1
2
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-67798 Rev. *G
Page 6 of 16
CY621472E30 MoBL
Switching Characteristics
Over the Operating Range
45 ns
Unit
Parameter [14]
Description
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
CE1 LOW/CE2 HIGH to data valid
OE LOW to data valid
OE LOW to Low Z [15]
OE HIGH to High Z [15, 16]
CE1 LOW/CE2 HIGH to Low Z [15]
CE1 HIGH/CE2 LOW to High Z [15, 16]
CE1 LOW/CE2 HIGH to Power-up
CE1 HIGH/CE2 LOW to Power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z [15, 17]
BLE/BHE HIGH to High Z [15, 16]
10
–
45
22
–
–
5
–
18
–
10
–
18
–
0
tPD
–
45
45
–
tDBE
tLZBE
tHZBE
–
5
–
18
Write Cycle [18, 19]
tWC
tSCE
tAW
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW/CE2 HIGH to Write End
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
tHA
–
tSA
0
–
tPWE
tBW
tSD
35
35
25
0
–
BLE/BHE LOW to write end
Data setup to write end
–
–
tHD
Data hold from write end
WE LOW to High Z [15, 16]
WE HIGH to Low Z [15]
–
tHZWE
tLZWE
–
18
–
10
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the Figure 2 on page 5.
CC(typ)
OL OH
15. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
16. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
17. If both byte enables are together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for WRITE Cycle 4 (WE controlled, OE LOW) should be equal to the sum of t
and t
.
HZWE
SD
Document Number: 001-67798 Rev. *G
Page 7 of 16
CY621472E30 MoBL
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22, 23]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
20. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V .
IL
IL
21. WE is HIGH for read cycle.
22. CE refers to the internal logical combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.
1
2
1
2
23. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-67798 Rev. *G
Page 8 of 16
CY621472E30 MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [24, 25, 26, 27]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 28
DATAIN
DATA I/O
t
HZOE
Figure 7. Write Cycle No. 2 (CE Controlled) [24, 25, 26, 27]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 28
t
HZOE
Notes
24. CE refers to the internal logical combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.
1
2
1
2
25. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE, or both = V . All signals must be active to initiate a write and any
IL
IL
of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
26. Data I/O is high impedance if OE = V
.
IH
27. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
28. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-67798 Rev. *G
Page 9 of 16
CY621472E30 MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [29, 30, 31]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA I/O
NOTE 32
DATAIN
t
LZWE
t
HZWE
Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [29, 30]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 32
DATAIN
DATA I/O
tLZWE
Notes
29. CE refers to the internal logical combination of CE and CE such that when CE is LOW and CE is HIGH, CE is LOW. For all other cases CE is HIGH.
1
2
1
2
30. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
31. The minimum write cycle pulse width should be equal to the sum of t
and t
HZWE
SD.
32. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-67798 Rev. *G
Page 10 of 16
CY621472E30 MoBL
Truth Table
CE2
X[33]
L
I/Os
Mode
Power
CE1
H
WE
X
OE
X
BHE
X
BLE
X
High Z
High Z
High Z
Deselect/Power-down Standby (ISB
Deselect/Power-down Standby (ISB
Deselect/Power-down Standby (ISB
)
)
)
X[33]
X[33]
L
X
X
X
X
X[33]
X
X
H
H
H
H
L
L
L
Data out (I/O0–I/O15
)
Read
Read
Active (ICC
)
)
L
H
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Active (ICC
L
H
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data in (I/O0–I/O15)
L
H
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
L
H
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC
)
Note
33. The ‘X’ (Don’t care) state for the chip enables (CE and CE ) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
1
2
pins is not permitted.
Document Number: 001-67798 Rev. *G
Page 11 of 16
CY621472E30 MoBL
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
45
CY621472E30LL-45ZSXI
51-85087 44-pin TSOP II (Pb-free)
Industrial
Ordering Code Definitions
30 LL - 45 ZS
X
I
4
621
E
CY
7 2
Temperature Range: I = Industrial
Pb-free
Package Type: ZS = 44-pin TSOP II
Speed Grade: 45 = 45 ns
Low Power
Voltage Range: 30 = 3 V Typical
Process Technology: E = 90 nm
Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-67798 Rev. *G
Page 12 of 16
CY621472E30 MoBL
Package Diagram
Figure 10. 44-pin TSOP II (18.4 × 10.2 × 1.194 mm) Package Outline, 51-85087
51-85087 *F
Document Number: 001-67798 Rev. *G
Page 13 of 16
CY621472E30 MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
Unit of Measure
°C
MHz
A
s
mA
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
nanosecond
ohm
OE
Output Enable
SRAM
TSOP
WE
Static Random Access Memory
Thin Small Outline Package
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-67798 Rev. *G
Page 14 of 16
CY621472E30 MoBL
Document History Page
Document Title: CY621472E30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 001-67798
Submission
Rev.
ECN No.
Description of Change
Date
**
3184883
3223503
03/01/2011 New data sheet.
*A
04/15/2011 Updated Truth Table:
Removed overline bar for CE2 in column heading.
Updated to new template.
*B
*C
3261142
3365953
05/19/2011 Updated Switching Characteristics:
Changed minimum value of tLZBE parameter from 10 ns to 5 ns.
Added Ordering Information and Ordering Code Definitions.
Added Acronyms and Units of Measure.
09/08/2011 Changed status from Preliminary to Final.
Updated Package Diagram:
spec 51-85087 – Changed revision from *C to *D.
*D
*E
3414567
4331825
10/20/2011 Replaced CY62147EV30 with CY621472E30 in all instances across the document.
04/03/2014 Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 31 and referred the same note in Figure 8.
Updated Package Diagram:
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*F
4573121
6906316
11/18/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*G
06/26/2020 Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to
“f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 0.8 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagram:
spec 51-85087 – Changed revision from *E to *F.
Updated to new template.
Document Number: 001-67798 Rev. *G
Page 15 of 16
CY621472E30 MoBL
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Document Number: 001-67798 Rev. *G
Revised June 26, 2020
Page 16 of 16
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor Corporation.
相关型号：
CY62147CV18LL-70BAIT
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
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