CY62177G30-55BAXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62177G30-55BAXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 |
| 文件： | 总23页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62177G30/CY62177GE30 MoBL
32-Mbit (2M words × 16-bit/
4M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
CY62177G30/CY62177GE30 MoBL, 16-Mbit (1M words
× 16-bit/2M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
through I/O15) and address pins (A0 through A20) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
Features
■ Ultra-low standby current
❐ Typical standby current: 3 µA
❐ Maximum standby current: 19 µA
■ High speed: 55 ns
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. You can
access read data on the I/O lines (I/O0 through I/O15). To perform
byte accesses, assert the required byte enable signal (BHE or
BLE) to read either the upper byte or the lower byte of data from
the specified address location.
■ Embedded error-correcting code (ECC) for single-bit error
correction[1]
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.5-V data retention
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE1 HIGH / CE2 LOW for a dual chip enable device),
or the control signals are de-asserted (OE, BLE, BHE).
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ 48-pin TSOP I package configurable as 2M × 16 or 4M × 8
SRAM
These devices have a unique Byte Power-down feature where,
if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switch to the standby mode irrespective of
the state of the chip enables, thereby saving power.
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
On the CY62177GE30 devices, the detection and correction of
a single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
– CY62177G30/CY62177GE30 on page 15 for a complete
description of read and write modes.
Functional Description
CY62177G30 and CY62177GE30 are high-performance CMOS,
low-power (MoBL®) SRAM devices with embedded ECC[2]. Both
devices are offered in single and dual chip enable options and in
multiple pin configurations. The CY62177GE30 device includes
an ERR pin that signals a single-bit error-detection and
correction event during a read cycle.
The CY62177G30 and CY62177GE30 devices are available in
a Pb-free 48-pin TSOP I package and 48-ball VFBGA packages.
The logic block diagrams are on page 2.
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
The device in the 48-pin TSOP I package can also be configured
to function as a 4M words × 8 bit device. Refer to the Pin
Configurations section for details.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
For a complete list of related documentation, click here.
Product Portfolio
Current Consumption
Features and Options
(see Pin Configurations
section)
Operating ICC, (mA) Standby, ISB2 (µA)
Speed
(ns)
Product
Range
VCC Range (V)
f = fmax
Max
Typ[3]
Max
Typ[3]
CY62177G30/C Single or dual Chip Enables
Y62177GE30 Optional ERR pin
Industrial
2.2 V–3.6 V
55
35
45
3
19
Notes
1. SER FIT rate <0.1 FIT/Mb. Refer to AN88889 for details.
2. This device does not support automatic write-back on error detection.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.
CC
CC
A
Cypress Semiconductor Corporation
Document Number: 002-24704 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 9, 2021
CY62177G30/CY62177GE30 MoBL
Logic Block Diagram – CY62177G30
DATAIN
DRIVERS
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O0‐I/O7
I/O8‐I/O15
RAM ARRAY
COLUM N DECODER
BYTE
BHE
CE2
POW ER
DOW N
CIRCUIT
CE1
CE2
CE1
W E
OE
BHE
BLE
BLE
Logic Block Diagram – CY62177GE30
D ATAIN
ECC EN CO D ER
D RIV ERS
A0
A1
A2
A3
ERR
I/O 0‐I/O 7
I/O 8‐I/O 15
A4
A 5
A6
A7
A8
A 9
RAM A RRAY
CO LU M N D ECO D ER
B Y TE
B H E
CE2
CE1
PO W ER
D O W N
CIRCU IT
CE2
CE1
W E
O E
B H E
B LE
B LE
Document Number: 002-24704 Rev. *C
Page 2 of 22
CY62177G30/CY62177GE30 MoBL
Contents
Pin Configuration – CY62177G30 ....................................4
Pin Configuration – CY62177GE30 .................................5
Maximum Ratings .............................................................7
Operating Range ...............................................................7
DC Electrical Characteristics ..........................................7
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Loads and Waveforms .......................................8
Data Retention Characteristics .......................................9
Data Retention Waveform ................................................9
Switching Characteristics ..............................................10
Switching Waveforms ....................................................11
Truth Table – CY62177G30/CY62177GE30 ...................15
ERR Output – CY62177GE30 .........................................15
Ordering Information ......................................................16
Ordering Code Definitions .........................................16
Package Diagrams ..........................................................17
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support .......................22
Products ....................................................................22
PSoC® Solutions ......................................................22
Cypress Developer Community .................................22
Technical Support .....................................................22
Document Number: 002-24704 Rev. *C
Page 3 of 22
CY62177G30/CY62177GE30 MoBL
Pin Configuration – CY62177G30
Figure 1. 48-ball VFBGA/BGA Pinout (Dual Chip Enable without ERR) – CY62177G30[4]
1
2
4
3
A0
A3
5
6
A1
A2
CE2
A
OE
BLE
A
I/O BHE
CE1 I/O
B
C
4
0
8
A
A
I/O I/O
I/O
I/O
5
6
9
10
1
2
VCC
A
V
I/O
I/O
3
A17
NC
D
E
F
SS
7
11
Vss
A
V
CC
I/O
I/O
16
12
4
A
A
15
I/O
I/O
I/O
I/O
14
13
5
14
6
A
A
G
H
I/O
I/O
A19
WE
13
12
15
7
A
A
A
A
A20
A18
10
9
11
8
Figure 2. 48-pin TSOP I Pinout (Dual Chip Enable without ERR) – CY62177G30[4, 5]
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
A8
A19
A20
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
CE1
A0
Notes
4. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
5. Tie the BYTE pin in the 48-pin TSOP I package to V to use the device as a 2M × 16 SRAM. The 48-pin TSOP I package can also be used as a 4M × 8 SRAM by
CC
tying the BYTE signal to V . In the 4M × 8 configuration, pin 45 is the extra address lineA21, while BHE, BLE, and I/O to I/O pins are not used and can be left floating.
SS
8
14
Document Number: 002-24704 Rev. *C
Page 4 of 22
CY62177G30/CY62177GE30 MoBL
Pin Configuration – CY62177GE30
Figure 3. 48-ball VFBGA/BGA Pinout (Single Chip Enable with ERR) – CY62177GE30 [6, 7]
1
4
2
5
3
6
A
A
A
ERR
A
OE
BLE
0
1
2
A
A
I/O BHE
8
CE
I/O
I/O
B
C
3
4
0
A
A
6
I/O I/O
I/O
2
5
9
10
1
V
A
V
I/O
I/O
3
A
CC
D
E
F
SS
7
11
17
Vss
NC
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
5
I/O
I/O
6
14
13
14
A
A
G
H
I/O
A
WE
I/O
7
13
12
15
19
A
A
9
A
A
A
20
A
10
11
8
18
Figure 4. 48-ball VFBGA/BGA Pinout (Dual Chip Enable with ERR) – CY62177GE30 [6, 7]
1
4
2
5
3
6
A
A
A
CE
OE
BLE
0
1
2
2
A
B
C
A
A
I/O BHE
CE
I/O
I/O
0
3
4
8
1
A
A
6
I/O I/O
I/O
2
5
9
10
1
V
A
V
I/O
I/O
3
A
CC
D
E
F
SS
7
11
17
Vss
ERR
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
5
I/O
I/O
14
13
14
6
A
A
G
H
I/O
A
WE
I/O
13
12
15
19
7
A
A
A
A
A20
A
10
9
11
8
18
Notes
6. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
7. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 002-24704 Rev. *C
Page 5 of 22
CY62177G30/CY62177GE30 MoBL
Pin Configuration – CY62177GE30 (continued)
Figure 5. 48-pin TSOP I Pinout (Dual Chip Enable with ERR) – CY62177GE30 [8, 9]
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A21
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
A8
A19
A20
WE
CE2
ERR
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
CE1
A0
Notes
8. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
9. Tie the BYTE pin in the 48-pin TSOP I package to V to use the device as a 2M × 16 SRAM. The 48-pin TSOP I package can also be used as a 4M × 8 SRAM by
CC
tying the BYTE signal to V . In the 4M × 8 configuration, pin 45 is the extra address line A21, while the BHE, BLE, and I/O to I/O pins are not used and can be
SS
8
14
left floating.
Document Number: 002-24704 Rev. *C
Page 6 of 22
CY62177G30/CY62177GE30 MoBL
DC input voltage[10] ............................ –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Storage temperature ............................... –65 °C to + 150 °C
Latch-up current .....................................................>140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
[11]
Grade
Ambient Temperature
VCC
to ground potential .............................. –0.5 V to VCC + 0.5 V
Industrial
–40 C to +85 C
2.2 V to 3.6 V
DC voltage applied to outputs
in High Z state[10]................................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
55 ns
Typ[12]
Parameter
Description
Test Conditions
Unit
Min
2.0
2.4
–
Max
–
VOH
Output HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
–
–
V
–
VOL
VIH
VIL
Output LOW
voltage
–
0.4
–
–
0.4
Input HIGH
voltage[10]
2.2 V to 2.7 V
2.7 V to 3.6 V
2.2 V to 2.7 V
2.7 V to 3.6 V
–
1.8
2.0
–0.3
–0.3
–1.0
–1.0
–
–
VCC + 0.3
VCC + 0.3
0.6
–
–
Input LOW
voltage[10]
–
–
–
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–
+1.0
+1.0
45.0
µA
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VOUT < VCC, Output disabled
–
VCC = Max,
OUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
35.0
mA
I
f = 1 MHz
–
–
10.0
3.0
18.0
19.0
[13]
ISB1
Automatic Power-down
Current – CMOS Inputs;
µA
µA
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
V
CC = 2.2 V to 3.6 V
V
IN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
[13]
ISB2
Automatic Power-down
Current – CMOS Inputs
–
3.0
19.0
CE1 > VCC – 0.2V or CE2 < 0.2 V or
(BHE and BLE) > VCC – 0.2 V,
V
CC = 2.2 V to 3.6 V
V
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
10. V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IL(min)
IH(max) CC
11. Full device AC operation assumes a 100-µs ramp time from 0 to V (min) and 400-µs wait time after V stabilizes to its operational value.
CC
CC
12. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
13. The I
maximum limits at 25 °C are guaranteed by design and not 100% tested.
SB2
Document Number: 002-24704 Rev. *C
Page 7 of 22
CY62177G30/CY62177GE30 MoBL
Capacitance
Parameter [14]
Description
Input capacitance
Output capacitance
Test Conditions
Max
15.0
15.0
Unit
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
pF
COUT
Thermal Resistance
Parameter [14]
Description
Test Conditions
48-ball VFBGA 48-ball FBGA 48-pin TSOP I Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
54.8
51.5
50.98
°C/W
JC
Thermal resistance
(junction to case)
11.9
7.8
9.4
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms
ALL INPUT PULSES
R1
VCC
OUTPUT
VHIGH
90%
10%
90%
10%
GND
Fall Time = 1 V/ns
R2
30 pF
Rise Time = 1 V/ns
INCLUDING
JIG AND
Equivalent to: THÉVENIN EQUIVALENT
RTH
SCOPE
OUTPUT
VTH
Parameters
R1
2.5 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
Unit
R2
RTH
VTH
1.75
3.0
V
VHIGH
2.5
Note
14. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 002-24704 Rev. *C
Page 8 of 22
CY62177G30/CY62177GE30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.5
–
Typ [15]
Max
–
Unit
V
–
–
[16, 17]
ICCDR
2.2 V < VCC < 3.6 V
3.0
19.0
µA
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
1.5 V < VCC < 2.2 V,
–
–
20.0
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
[18]
tCDR
Chip deselect to data retention
time
–
0.0
55
–
–
–
–
–
[18, 19]
tR
Operation recovery time
–
ns
Data Retention Waveform
Figure 7. Data Retention Waveform [20]
DATA RETENTION MODE
VCC
VDR = 1.0 V
VCC (min)
tCDR
VCC (min)
tR
CE1 or
BHE. BLE
CE2
Notes
15. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
16. Chip enables (CE and CE ) and BYTE must be tied to CMOS levels to meet the I
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
17. I
is guaranteed only after the device is first powered up to V
and then brought down to V
.
DR
CCDR
CC(min)
18. These parameters are guaranteed by design and are not tested.
19. Full-device operation requires linear V ramp from V to V
20. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
> 400 s or stable at V > 400 s.
CC(min)
CC
DR
CC(min)
Document Number: 002-24704 Rev. *C
Page 9 of 22
CY62177G30/CY62177GE30 MoBL
Switching Characteristics
55 ns
Unit
Parameter[21]
Description
Min
Max
Read Cycle
tRC
Read cycle time
55.0
–
–
ns
tAA
Address to data valid / Address to ERR valid
Data hold from address change / ERR hold from address change
CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid
OE LOW to data valid / OE LOW to ERR valid
OE LOW to Low Z [22, 23]
55.0
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
10.0
–
55.0
25.0
–
–
5.0
–
OE HIGH to High Z [22, 23, 24]
18.0
–
CE1 LOW and CE2 HIGH to Low Z [22, 23]
CE1 HIGH and CE2 LOW to High Z [22, 23, 24]
CE1 LOW and CE2 HIGH to power-up [25]
CE1 HIGH and CE2 LOW to power-down [25]
BLE / BHE LOW to data valid
10.0
–
18.0
–
0.0
–
tPD
55.0
55.0
–
tDBE
tLZBE
tHZBE
–
BLE / BHE LOW to Low Z [22]
BLE / BHE HIGH to High Z [22, 24]
5.0
–
18.0
Write Cycle [26, 27]
tWC
tSCE
tAW
Write cycle time
55.0
40.0
40.0
0
–
–
ns
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
tHA
–
tSA
0
–
tPWE
tBW
tSD
40.0
40.0
25.0
0.0
–
–
BLE / BHE LOW to write end
Data setup to write end
–
–
tHD
Data hold from write end
WE LOW to High Z [22, 23, 24]
WE HIGH to Low Z [22, 23]
–
tHZWE
tLZWE
18.0
–
10.0
Notes
21. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V > 3 V) and V /2 (for V < 3 V), and input pulse levels
CC
CC
CC
of 0 to 3 V (for V > 3 V) and 0 to V (for V < 3V). Test conditions for the read cycle use the output loading shown in Figure 6 on page 8, unless specified otherwise.
CC
CC
CC
22. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
23. Tested initially and after any design or process changes that may affect these parameters.
24. t , t , t , and t transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
25. These parameters are guaranteed by design and are not tested.
26. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
27. The minimum write cycle pulse width for Write Cycle No. 1 (WE Controlled, OE LOW) should be equal to the sum of t
and t
.
SD
HZWE
Document Number: 002-24704 Rev. *C
Page 10 of 22
CY62177G30/CY62177GE30 MoBL
Switching Waveforms
Figure 8. Read Cycle No. 1 of CY62177G30 (Address Transition Controlled) [28, 29]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 9. Read Cycle No. 1 of CY62177GE30 (Address Transition Controlled) [28, 29]
tRC
ADDRESS
tAA
tOHA
DATA I/O
ERR
PREVIOUS DATAOUT VALID
DATAOUT VALID
ERR VALID
tAA
tOHA
PREVIOUS ERR VALID
Notes
28. The device is continuously selected. OE = V , CE = V , BHE or BLE, or both = V .
IL
IL
IL
29. WE is HIGH for read cycle.
Document Number: 002-24704 Rev. *C
Page 11 of 22
CY62177G30/CY62177GE30 MoBL
Switching Waveforms (continued)
Figure 10. Read Cycle No. 2 (OE Controlled) [30, 31, 32, 34]
ADD RESS
tRC
CE
tPD
tHZCE
tAC E
O E
tH ZO E
tDO E
tLZO E
BHE/
BLE
tDBE
tLZBE
tHZBE
HIG H
IM PED ANC E
H IG H IM PEDAN CE
tLZCE
DATA I/O
D ATAO UT VALID
tPU
VC C
SUPPLY
CU RR ENT
ISB
Figure 11. Write Cycle No. 1 (WE Controlled, OE LOW) [31, 33, 34, 35]
tW C
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tAW
tHA
tSA
tPW E
W E
tLZW E
tSD
t
HZW E
tHD
Note 35
DATA I/O
DATAIN VALID
Notes
30. WE is HIGH for read cycle.
31. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
32. Address valid prior to or coincident with CE LOW transition.
33. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE, or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
34. Data I/O is in the high-impedance state if CE = V , or OE = V , or BHE, and/or BLE = V .
IH
IH
IH
35. During this period, the I/Os are in the output state. Do not apply input signals.
36. The minimum write cycle pulse width should be equal to the sum of t
and t
.
HZWE
SD
Document Number: 002-24704 Rev. *C
Page 12 of 22
CY62177G30/CY62177GE30 MoBL
Switching Waveforms (continued)
Figure 12. Write Cycle No. 2 (CE Controlled) [37, 38, 39]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE/
BLE
OE
tHZOE
tHD
tSD
Note 40
DATA I/O
DATA VALID
IN
Notes
37. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the
write.
39. Data I/O is in the high-impedance state if CE = V , or OE = V , or BHE, and/or BLE = V .
IH
IH
IH
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-24704 Rev. *C
Page 13 of 22
CY62177G30/CY62177GE30 MoBL
Switching Waveforms (continued)
Figure 13. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [41, 42, 43]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
tHD
tSD
tLZWE
DATA I/O
Note 44
DATAIN VALID
Figure 14. Write Cycle No. 5 (WE Controlled) [41, 42, 43]
tW
C
A D D R E S S
tS C E
C E
tA W
tS A
tH A
tP W
E
W E
tB W
B H E /B L E
O E
tH Z O E
tH D
tS D
Note 44
D A T A I/O
D A T A IN V A L ID
Notes
41. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
42. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to
IL
1
IL
IL
2
IH
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that
terminates the write.
43. Data I/O is in the high-impedance state if CE = V , or OE = V , or BHE, and/or BLE = V .
IH
IH
IH
44. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-24704 Rev. *C
Page 14 of 22
CY62177G30/CY62177GE30 MoBL
Truth Table – CY62177G30/CY62177GE30
BYTE[45] CE1 CE2 WE
OE BHE BLE
Inputs/Outputs
High-Z
Mode
Power
Configuration
X[46]
H
X[46]
X
X
X
H
H
X
X
X
L
X
X
H
L
X
X
H
L
Deselect/Power-down Standby (ISB) 4M × 8/2M × 16
Deselect/Power-down Standby (ISB) 4M × 8/2M × 16
X
X[46]
L
High-Z
X
X[46] X[46]
High-Z
Deselect/Power-down Standby (ISB
)
2M × 16
2M × 16
2M × 16
H
L
L
H
H
Data Out (I/O0–I/O15
)
Read
Read
Active (ICC
)
H
L
H
L
Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15
Active (ICC)
)
H
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15
Read
Active (ICC
)
2M × 16
)
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High-Z
High-Z
High-Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
2M × 16
2M × 16
2M × 16
2M × 16
2M × 16
)
)
L
Data In (I/O0–I/O15
)
)
L
H
Data In (I/O0–I/O7);
High-Z (I/O8–I/O15
Write
)
)
H
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data In (I/O8–I/O15
Write
Active (ICC
)
2M × 16
)
L
L
L
L
L
L
H
H
H
H
H
L
L
H
X
X
X
X
X
X
X
Data Out (I/O0–I/O7)
High-Z
Read
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
)
2M × 16
2M × 16
4M × 8
)
Data In (I/O0–I/O7)
)
ERR Output – CY62177GE30
Output[47]
Mode
Read operation, no single-bit error in the stored data.
0
1
Read operation, single-bit error detected and corrected.
Device deselected / outputs disabled / Write operation
High-Z
Notes
45. This pin is available only in the 48-pin TSOP I package. Tie the BYTE to V to configure the device in the 2M × 16 option. The 48-pin TSOP I package can also be
CC
used as a 4M × 8 SRAM by tying the BYTE signal to V
.
SS
46. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
47. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 002-24704 Rev. *C
Page 15 of 22
CY62177G30/CY62177GE30 MoBL
Ordering Information
Speed
(ns)
Voltage
Range
Package
Diagram
Package Type Key Features / ERR Pin / Operating
Ordering Code
(all Pb-free)
Differentiators
Ball
Range
CY62177G30-55BAXI
CY62177G30-55BAXIT
CY62177G30-55BKXI
51-85191
51-85193
48-ball FBGA
48-ball VFBGA
48-pin TSOP I
No
55
2.2 V–3.6 V CY62177G30-55BKXIT
CY62177G30-55ZXI
Dual Chip Enable
Industrial
CY62177G30-55ZXIT
51-85183
CY62177GE30-55ZXI
Yes
Ordering Code Definitions
X
G
55 XX
30 -
X
I
X
7
621
E
CY
7
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Grade: I = Industrial
Pb-free
X = blank or 1
blank = Dual Chip Enable; 1 = Single Chip Enable
Package Type: XX = BA or BK or Z
BA = 48-ball FBGA; BK = 48-ball VFBGA; Z = 48-pin TSOP I
Speed Grade: XX: 55 = 55 ns
Voltage Range: 30 = 3 V typ
ERR Output: Single-bit error correction indicator
Process Technology: Ultra Low-power
Bus Width: 7 = ×16
Density: 7 = 32-Mbit
Family Code: 621 = MoBL® SRAM family
Company ID: CY = Cypress
Document Number: 002-24704 Rev. *C
Page 16 of 22
CY62177G30/CY62177GE30 MoBL
Package Diagrams
Figure 15. 48-ball FBGA (8 × 9.5 × 1.2 mm) Package Outline, 51-85191
51-85191 *C
Document Number: 002-24704 Rev. *C
Page 17 of 22
CY62177G30/CY62177GE30 MoBL
Package Diagrams (continued)
Figure 16. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
0.10
2X (N/2 TIPS)
0.10 C
8
2X
A2
2
0.10
2X
1
N
SEE DETAIL B
R
A
B
(c)
E
5
GAUGE PLANE
0.25 BASIC
e
9
N/2 +1
N/2
0°
5
A1
C
D1
D
4
PARALLEL TO
SEATING PLANE
L
C
0.20
2X (N/2 TIPS)
SEATING PLANE
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
e/2
REVERSE PIN OUT (TOP VIEW)
3
1
N
c
7
c1
X
X = A OR B
b1
BASE METAL
DETAIL B
N/2
N/2 +1
SECTION B-B
NOTES:
DIMENSIONS
SYMBOL
1. DIMENSIONS ARE IN MILLIMETERS (mm).
MIN. NOM. MAX.
A
1.20
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
0.15
0.05
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.95
0.17
0.17
1.00
0.20
1.05
0.23
0.27
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.22
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
c1
0.10
0.10
0.16
0.21
c
D
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.50 BASIC
D1
E
e
L
0
0.50
0.60 0.70
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
0°
8
0.20
R
N
0.08
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
48
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 002-24704 Rev. *C
Page 18 of 22
CY62177G30/CY62177GE30 MoBL
Package Diagrams (continued)
Figure 17. 48-pin FBGA (6 × 8 × 1.2 mm) Package Outline, 51-85193
51-85193 *E
Document Number: 002-24704 Rev. *C
Page 19 of 22
CY62177G30/CY62177GE30 MoBL
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Table 2. Units of Measure
Symbol
Acronym
BHE
Description
Byte High Enable
Byte Low Enable
Chip Enable
Unit of Measure
BLE
°C
MHz
µA
µs
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
CE
CMOS
I/O
Complementary metal oxide semiconductor
Input/output
OE
Output Enable
SRAM
TSOP
VFBGA
WE
Static random access memory
Thin small outline package
Very fine-pitch ball grid array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 002-24704 Rev. *C
Page 20 of 22
CY62177G30/CY62177GE30 MoBL
Document History Page
Document Title: CY62177G30/CY62177GE30 MoBL, 32-Mbit (2M words × 16-bit/4M words × 8-bit) Static RAM with
Error-Correcting Code (ECC)
Document Number: 002-24704
Submission
Rev.
ECN No.
Description of Change
Date
*C
7085237
02/09/2021 Release to web.
Document Number: 002-24704 Rev. *C
Page 21 of 22
CY62177G30/CY62177GE30 MoBL
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2018-2021. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves
all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If
the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
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of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device" means any
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as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,
costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical
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data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a
Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-24704 Rev. *C
Revised February 9, 2021
Page 22 of 22
相关型号：
CY62187EV30LL-55BAXIT
Standard SRAM, 4MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1.40 MM HEIGHT, LEAD FREE, MO-205, FBGA-48
CYPRESS
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