CY7C1020D-10VXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY7C1020D-10VXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1020D
512-Kbit (32 K × 16) Static RAM
512-Kbit (32
K × 16) Static RAM
■ Deselected (CE HIGH)
Features
■ Outputs are disabled (OE HIGH)
■ Pin- and function-compatible with CY7C1020B
■ BHE and BLE are disabled (BHE, BLE HIGH)
■ When the write operation is active (CE LOW, and WE LOW)
■ High speed
❐ tAA = 10 ns
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A14). If Byte High
■ Low active power
❐ ICC = 80 mA @ 10 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15
)
is written into the location specified on the address pins (A0
through A14).
❐ ISB2 = 3 mA
■ 2.0 V data retention
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Independent control of upper and lower bits
■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
The CY7C1020D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
Functional Description
[1]
The CY7C1020D
is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO0 through IO15) are placed in a high-impedance state when:
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A
A
7
6
5
4
A
32K x 16
A
A
A
A
A
IO –IO
0
7
RAM Array
3
2
1
0
IO –IO
8
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05463 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 28, 2014
CY7C1020D
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure .......................................................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC® Solutions ......................................................17
Cypress Developer Community .................................17
Technical Support .....................................................17
Document Number: 38-05463 Rev. *J
Page 2 of 17
CY7C1020D
Pin Configurations
Figure 1. 44-pin SOJ/TSOP II pinout (Top View) [2]
A
A
A
7
OE
BHE
BLE
IO
15
IO
IO
13
IO
NC
A
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
5
6
3
A
2
A
1
A
0
CE
IO
0
1
2
3
IO
IO
IO
V
14
9
10
11
12
13
14
15
16
17
18
19
20
21
22
12
V
SS
CC
V
V
CC
IO
IO
SS
IO
4
5
6
7
11
10
IO
IO
IO
IO
IO
9
8
NC
WE
A
A
8
4
14
A
A
9
A
13
12
A
A
10
11
A
NC
NC
Selection Guide
Description
-10 (Industrial)
Unit
ns
Maximum access time
10
80
3
Maximum operating current
Maximum CMOS standby current
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05463 Rev. *J
Page 3 of 17
CY7C1020D
DC input voltage [3] ............................. –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(per MIL-STD-883, Method 3015) ...........................>2001 V
Storage temperature ................................ –65 C to +150 C
Latch-up current .....................................................>200 mA
Ambient temperature with
power applied .......................................... –55 C to +125 C
Operating Range
Supply voltage on
V
CC to Relative GND [3] ...............................–0.5 V to +6.0 V
Ambient
Temperature
Range
VCC
Speed
DC voltage applied to outputs
in High Z State [3] ................................ –0.5 V to VCC + 0.5 V
Industrial
–40 °C to +85 °C
5 V 0.5 V
10 ns
Electrical Characteristics
Over the Operating Range
-10 (Industrial)
Parameter
VOH
Description
Test Conditions
Unit
Min
2.4
–
Max
Output HIGH voltage
IOH = –4.0 mA
IOH = –0.1 mA
IOL = 8.0 mA
–
–
V
3.4 [4]
0.4
VOL
VIH
VIL
IIX
Output LOW voltage
Input HIGH voltage
Input LOW voltage [3]
–
V
2.2
–0.5
–1
–1
–
VCC + 0.5
0.8
V
–
V
Input load current
GND < VI < VCC
+1
A
A
mA
mA
mA
mA
mA
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VI < VCC, output disabled
+1
VCC = Max, IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
80
–
72
–
58
–
37
ISB1
ISB2
Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fmax
–
10
Automatic CE Power-Down
current – CMOS inputs
Max VCC, CE > VCC – 0.3 V,
IN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–
3
mA
V
Note
3.
V (min) = –2.0 V and V (max) = V + 1 V for pulse durations of less than 5 ns.
IL IH CC
4. Please note that the maximum V limit does not exceed minimum CMOS V of 3.5V. If you are interfacing this SRAM with 5V legacy processors that require a
OH
IH
minimum V of 3.5V, please refer to Application Note AN6081 for technical details and options you may consider.
IH
Document Number: 38-05463 Rev. *J
Page 4 of 17
CY7C1020D
Capacitance
[5]
Parameter
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max
8
Unit
pF
CIN
COUT
8
pF
Thermal Resistance
[5]
Parameter
Description
Test Conditions
SOJ
TSOP II
Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
53.91
C/W
JC
Thermal resistance
(junction to case)
36.75
21.24
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [6]
ALL INPUT PULSES
3.0V
Z = 50
90%
10%
90%
10%
OUTPUT
50
GND
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
Fall Time: 3 ns
Rise Time: 3 ns
(b)
(a)
High-Z characteristics:
R1 480
5V
OUTPUT
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load shown
in Figure 2 (c).
Document Number: 38-05463 Rev. *J
Page 5 of 17
CY7C1020D
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min
2.0
Max
Unit
V
–
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
IN > VCC – 0.3 V or VIN < 0.3 V
3
mA
V
[7]
tCDR
Chip deselect to data retention
time
–
0
ns
ns
[8]
tR
Operation recovery time
–
tRC
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
4.5V
4.5V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear V ramp from V to V
> 50 s or stable at V
> 50 s.
CC
DR
CC(min)
CC(min)
Document Number: 38-05463 Rev. *J
Page 6 of 17
CY7C1020D
Switching Characteristics
Over the Operating Range
-10 (Industrial)
Parameter [9]
Description
Unit
Min
Max
Read Cycle
[10]
tpower
tRC
VCC(typical) to the first access
100
10
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
tAA
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z [12]
OE HIGH to High Z [11, 12]
CE LOW to Low Z [12]
CE HIGH to High Z [11, 12]
CE LOW to power-up
CE HIGH to power-down
Byte enable to data valid
Byte enable to Low Z
Byte disable to High Z
10
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
3
10
5
0
5
3
5
[13]
tPU
0
[13]
tPD
10
5
tDBE
tLZBE
tHZBE
Write Cycle [14, 15]
0
5
tWC
tSCE
tAW
Write cycle time
10
7
7
0
0
7
6
0
3
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
tHA
tSA
tPWE
tSD
Data set-up to write end
Data hold from write end
WE HIGH to Low Z [12]
WE LOW to High Z [11, 12]
Byte enable to end of write
tHD
tLZWE
tHZWE
tBW
7
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I /I
OL OH
and 30-pF load capacitance.
10. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER
CC
11. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance state.
HZOE HZBE HZCE
HZWE
12. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
13. This parameter is guaranteed by design and is not tested.
14. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and the
transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
15. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of t
and t
.
HZWE
SD
Document Number: 38-05463 Rev. *J
Page 7 of 17
CY7C1020D
Switching Waveforms
Figure 4. Read Cycle No.1 (Address Transition Controlled) [16, 17]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No.2 (OE Controlled) [17, 18]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
DATA VALID
t
LZCE
t
PD
ICC
t
PU
50%
50%
SUPPLY
ISB
CURRENT
Notes
16. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05463 Rev. *J
Page 8 of 17
CY7C1020D
Switching Waveforms(continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [19, 20]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
HD
SD
DATA IO
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled) [19, 20]
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Notes
19. Data IO is high impedance if OE or BHE and/or BLE= V
.
IH
20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 38-05463 Rev. *J
Page 9 of 17
CY7C1020D
Switching Waveforms(continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 22]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Notes
21. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of t
22. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
and t
SD.
HZWE
Document Number: 38-05463 Rev. *J
Page 10 of 17
CY7C1020D
Truth Table
CE
H
OE
X
WE
X
BLE BHE
IO0–IO7
High Z
IO8–IO15
High Z
Mode
Power
X
X
L
Power-down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
L
H
L
Data out
Data out
High Z
Data in
Data in
High Z
High Z
High Z
Data out
High Z
Data out
Data in
High Z
Data in
High Z
High Z
Read – All bits
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
)
L
H
L
Write – Lower bits only
Write – Upper bits only
Selected, outputs disabled
selected, outputs disabled
)
H
X
H
)
L
L
H
X
H
X
X
H
)
)
Document Number: 38-05463 Rev. *J
Page 11 of 17
CY7C1020D
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY7C1020D-10VXI
CY7C1020D-10ZSXI
10
51-85082 44-pin SOJ (400 Mils) Pb-free
51-85087 44-pin TSOP (Type II) Pb-free
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7
C
1 02
0
D - 10 XX
X
I
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = V or ZS
V = 44-pin Molded SOJ
ZS = 44-pin TSOP Type II
Speed: 10 ns
Process Technology: D = C9, 90 nm Technology
Data width: 0 = × 16-bits
Density: 02 = 512-Kbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05463 Rev. *J
Page 12 of 17
CY7C1020D
Package Diagrams
Figure 9. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082
51-85082 *E
Document Number: 38-05463 Rev. *J
Page 13 of 17
CY7C1020D
Package Diagrams(continued)
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05463 Rev. *J
Page 14 of 17
CY7C1020D
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BGA
Ball Grid Array
Symbol
°C
Unit of Measure
CMOS
FBGA
I/O
Complementary Metal Oxide Semiconductor
Fine-Pitch Ball Gird Array
Input/Output
degree Celsius
megahertz
microampere
milliampere
nanosecond
ohm
MHz
A
mA
ns
SRAM
TSOP
TTL
Static Random Access Memory
Thin Small Outline Package
Transistor-Transistor Logic
pF
V
picofarad
volt
W
watt
Document Number: 38-05463 Rev. *J
Page 15 of 17
CY7C1020D
Document History Page
Document Title: CY7C1020D, 512-Kbit (32 K × 16) Static RAM
Document Number: 38-05463
Orig. of
Rev.
ECN No.
Issue Date
Description of Change
Advance Data sheet for C9 IPP
Change
**
201560
233695
See ECN
See ECN
SWI
*A
RKF
1) DC parameters modified as per EROS (Spec # 01-0216)
2) Pb-free Offering in the ‘Ordering Information’
*B
263769
See ECN
RKF
1) Corrected pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4
2) Changed IO1 - IO16 to IO0 - IO15 on the Pin-out diagram
3) Added Tpower Spec in Switching Characteristics Table
4) Added Data Retention Characteristics Table and Waveforms
5) Shaded ‘Ordering Information’
*C
*D
307594
560995
See ECN
See ECN
RKF
VKN
Reduced Speed bins to –10, –12 and –15 ns
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3
*E
*F
*G
802877
3109992
3219056
See ECN
12/14/2010
04/07/2011
VKN
AJU
Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for
83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
Added Ordering Code Definitions.
Updated Package Diagrams.
PRAS
Added TOC
Added Acronyms and Units of Measure table.
Updated Datasheet as per template.
*H
4033925
06/19/2013
MEMJ
Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “IOH = –0.1mA” for VOH parameter and added
maximum value corresponding to that Test Condition.
Added Note 4 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “IOH = –0.1mA”.
Updated Package Diagrams:
spec 51-85082 – Changed revision from *C to *E.
spec 51-85087 – Changed revision from *C to *E.
*I
4385769
4576526
05/21/2014
11/21/2014
MEMJ
MEMJ
No technical updates.
Completing Sunset Review.
*J
Added related documentation hyperlink in page 1.
Document Number: 38-05463 Rev. *J
Page 16 of 17
CY7C1020D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
®
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Community | Forums | Blogs | Video | Training
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© Cypress Semiconductor Corporation, 2010-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05463 Rev. *J
Revised November 28, 2014
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
CY7C1020DV33-10VXIT
Standard SRAM, 32KX16, 10ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CYPRESS
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