CY7C1518KV18-300BZXI [INFINEON]
DDR-II CIO;
| 型号： | CY7C1518KV18-300BZXI |
| 厂家： | 
Infineon |
| 描述： | DDR-II CIO 时钟 双倍数据速率 静态存储器 内存集成电路 |
| 文件： | 总32页 (文件大小：790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1518KV18
CY7C1520KV18
72-Mbit DDR-II SRAM Two-Word
Burst Architecture
72-Mbit DDR-II SRAM Two-Word Burst Architecture
Features
Configurations
■ 72-Mbit density (4M × 18, 2M × 36)
CY7C1518KV18 – 4M × 18
CY7C1520KV18 – 2M × 36
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
Functional Description
■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
The CY7C1518KV18, and CY7C1520KV18 are 1.8 V
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1518KV18 and CY7C1520KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518KV18 and two 36-bit words in the case of
CY7C1520KV18 sequentially into or out of the device.
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
■ Operates similar to DDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD
)
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
❐ Supports both 1.5 V and 1.8 V IO supply
■ Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible Test Access Port
For a complete list of related documentation, click here.
■ Phase-locked loop (PLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
333 MHz
333
300 MHz
300
250 MHz Unit
250
430
530
MHz
mA
Maximum Operating Current
× 18
× 36
520
490
640
600
Cypress Semiconductor Corporation
Document Number: 001-00437 Rev. *V
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 6, 2017
CY7C1518KV18
CY7C1520KV18
Logic Block Diagram – CY7C1518KV18
Burst
Logic
A0
Write
Reg
Write
Reg
22 21
A
A
(21:0)
Address
Register
(21:1)
18
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
C
C
DOFF
Read Data Reg.
36
18
CQ
CQ
V
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
R/W
18
18
BWS
DQ
[1:0]
[17:0]
Logic Block Diagram – CY7C1520KV18
Burst
Logic
A0
Write
Reg
Write
Reg
21 20
A
A
(20:0)
Address
Register
(20:1)
36
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
C
C
DOFF
Read Data Reg.
72
36
CQ
CQ
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
R/W
36
36
BWS
DQ
[3:0]
[35:0]
Document Number: 001-00437 Rev. *V
Page 2 of 32
CY7C1518KV18
CY7C1520KV18
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................6
Byte Write Operations .................................................7
Single Clock Mode ......................................................7
DDR Operation ............................................................7
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
PLL ..............................................................................7
Application Example ........................................................8
Truth Table ........................................................................9
Burst Address Table ........................................................9
Write Cycle Descriptions ...............................................10
Write Cycle Descriptions ...............................................11
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12
Disabling the JTAG Feature ......................................12
Test Access Port .......................................................12
Performing a TAP Reset ...........................................12
TAP Registers ...........................................................12
TAP Instruction Set ...................................................12
TAP Controller State Diagram .......................................14
TAP Controller Block Diagram ......................................15
TAP Electrical Characteristics ......................................15
TAP AC Switching Characteristics ...............................16
TAP Timing and Test Conditions ..................................17
Identification Register Definitions ................................18
Scan Register Sizes .......................................................18
Instruction Codes ...........................................................18
Boundary Scan Order ....................................................19
Power Up Sequence in DDR II SRAM ...........................20
Power Up Sequence .................................................20
PLL Constraints .........................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Neutron Soft Error Immunity .........................................21
Electrical Characteristics ...............................................21
DC Electrical Characteristics .....................................21
AC Electrical Characteristics .....................................23
Capacitance ....................................................................23
Thermal Resistance ........................................................23
AC Test Loads and Waveforms .....................................23
Switching Characteristics ..............................................24
Switching Waveforms ....................................................26
Read/Write/Deselect Sequence ................................26
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagram ............................................................28
Acronyms ........................................................................29
Document Conventions .................................................29
Units of Measure .......................................................29
Document History Page .................................................30
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products ....................................................................32
PSoC® Solutions ......................................................32
Cypress Developer Community .................................32
Technical Support .....................................................32
Document Number: 001-00437 Rev. *V
Page 3 of 32
CY7C1518KV18
CY7C1520KV18
Pin Configurations
The pin configurations for CY7C1518KV18, and CY7C1520KV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1518KV18 (4M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
4
5
BWS1
NC/288M
A
6
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
A
B
C
D
E
F
A
R/W
A
K
LD
DQ9
NC
NC
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
NC
NC
A
C
A
NC
DQ0
TDI
TCK
A
A
C
A
A
TMS
CY7C1520KV18 (2M × 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
3
4
5
BWS2
BWS3
A
6
7
BWS1
BWS0
A
8
9
A
10
A
11
A
B
C
D
E
F
A
R/W
A
K
LD
CQ
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ17
NC
DQ29
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
A
C
A
DQ9
TMS
TCK
A
A
C
A
A
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-00437 Rev. *V
Page 4 of 32
CY7C1518KV18
CY7C1520KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the C and C clocks during read operations or K and K when in single
clock mode. When read access is deselected, Q[x:0] are automatically tristated.
CY7C1518KV18 DQ[17:0]
CY7C1520KV18 DQ[35:0]
LD
Input-
Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C1518KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1520KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A, A0
Input-
Address inputs. These address inputs are multiplexed for both read and write operations. Internally,
Synchronous the device is organized as 4M × 18 (2 arrays each of 2M × 18) for CY7C1518KV18, and 2M × 36 (2
arrays each of 1M × 36) for CY7C1520KV18.
CY7C1518KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 22 address inputs are needed to access the entire memory array.
CY7C1520KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 21 address inputs are needed to access the entire memory array. All the address inputs are
ignored when the appropriate port is deselected.
R/W
C
Input-
Synchronous read or write input. When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Input Clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
C
Input Clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
K
Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
Input Clock Negative input clock input. K is used to capture synchronous data being presented to the device and
K
to drive out data through Q[x:0] when in single clock mode.
CQ
Output Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
Output Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
CQ
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-00437 Rev. *V
Page 5 of 32
CY7C1518KV18
CY7C1520KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
DOFF
Input
PLL turn off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull up through a 10 k or less pull up resistor. The device behaves in DDR-I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR-I timing.
TDO
Output
Input
Input
Input
N/A
Test data out (TDO) pin for JTAG
TCK
Test clock (TCK) pin for JTAG
TDI
Test data in (TDI) pin for JTAG
TMS
Test mode select (TMS) pin for JTAG
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/144M
NC/288M
VREF
Input
Input
Input-
Reference measurement points.
VDD
VSS
Power Supply Power supply Inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
On the subsequent rising edge of C the next 18-bit data word
from the address location generated by the burst counter is
driven onto the Q[17:0]. The requested data is valid 0.45 ns from
the rising edge of the output clock (C or C, or K and K when in
single clock mode, 250 MHz, and 300 MHz device). To maintain
the internal logic, each read access must be allowed to
complete. Read accesses can be initiated on every rising edge
of the positive input clock (K).
Functional Overview
The CY7C1518KV18, and CY7C1520KV18 are synchronous
pipelined Burst SRAMs equipped with a DDR interface, which
operates with a read latency of one and a half cycles when DOFF
pin is tied HIGH. When DOFF pin is set LOW or connected to
VSS the device behaves in DDR-I mode with a read latency of
one clock cycle.
When read access is deselected, the CY7C1518KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive output clock (C). This enables for a transition
between devices without the insertion of wait states in a depth
expanded memory.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments the
address in a linear fashion. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit write
data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the Negative Input Clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1518KV18 is described in the following sections. The
same basic descriptions apply to CY7C1520KV18.
Read Operations
The CY7C1518KV18 is organized internally as a two arrays of
2M × 18. Accesses are completed in a burst of 2 sequential 18-bit
data words. Read operations are initiated by asserting R/W
HIGH and LD LOW at the rising edge of the positive input clock
(K). The address presented to address inputs is stored in the
read address register and the least significant bit of the address
is presented to the burst counter. The burst counter increments
the address in a linear fashion. Following the next K clock rise,
the corresponding 18-bit word of data from this address location
is driven onto the Q[17:0] using C as the output timing reference.
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Document Number: 001-00437 Rev. *V
Page 6 of 32
CY7C1518KV18
CY7C1520KV18
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Byte Write Operations
Byte write operations are supported by the CY7C1518KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature is used to simplify
read, modify, or write operations to a byte write operation.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Single Clock Mode
The CY7C1518KV18 is used with a single clock that controls
both the input and output registers. In this mode, the device
recognizes only a single pair of input clocks (K and K) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C clocks. All timing parameters remain the same in this mode.
To use this mode of operation, the user must tie C and C HIGH
at power on. This function is a strap option and not alterable
during device operation.
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the DDR II. In single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in the
Switching Characteristics on page 24.
DDR Operation
The CY7C1518KV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1518KV18 requires a single
No Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications may require a
second NOP cycle to avoid contention.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR-I mode (with one cycle latency and a longer
access time).
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
Document Number: 001-00437 Rev. *V
Page 7 of 32
CY7C1518KV18
CY7C1520KV18
Application Example
Figure 2 shows two DDR II used in an application.
Figure 2. Application Example (Width Expansion)
ZQ
ZQ
SRAM#1
SRAM#2
CQ/CQ
CQ/CQ
RQ
RQ
DQ[x:0]
DQ[x:0]
A
LD R/W BWS C C K K
A LD R/W BWS C C K K
DQ[2x:0]
ADDRESS
LD
R/W
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
DELAYED K
DELAYED K
FPGA / ASIC
Document Number: 001-00437 Rev. *V
Page 8 of 32
CY7C1518KV18
CY7C1520KV18
Truth Table
The truth table for the CY7C1518KV18, and CY7C1520KV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write cycle:
Load address; wait one cycle;
L–H
L
L
D(A1) at K(t + 1) D(A2) at K(t + 1)
input write data on consecutive K and K rising edges.
Read cycle:
L–H
L
H
Q(A1) at C(t + 1) Q(A2) at C(t + 2)
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No operation
L–H
H
X
X
X
High Z
High Z
Standby: Clock stopped
Stopped
Previous State
Previous State
Burst Address Table
(CY7C1518KV18, CY7C1520KV18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1518KV18 and CY7C1520KV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document Number: 001-00437 Rev. *V
Page 9 of 32
CY7C1518KV18
CY7C1520KV18
Write Cycle Descriptions
The write cycle description table for CY7C1518KV18 follows. [8, 9]
BWS0 BWS1
K
Comments
K
L
L
L–H
–
During the data portion of a write sequence
CY7C1518KV18 both bytes (D[17:0]) are written into the device.
L
L
–
L–H
–
L–H During the data portion of a write sequence:
CY7C1518KV18 both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence:
CY7C1518KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1518KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence
CY7C1518KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1518KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
8. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
9. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a
0
1
2
3
write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-00437 Rev. *V
Page 10 of 32
CY7C1518KV18
CY7C1520KV18
Write Cycle Descriptions
The write cycle description table for CY7C1520KV18 follows. [10, 11]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a
0
1
2
3
write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-00437 Rev. *V
Page 11 of 32
CY7C1518KV18
CY7C1520KV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
High Z state.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-00437 Rev. *V
Page 12 of 32
CY7C1518KV18
CY7C1520KV18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-00437 Rev. *V
Page 13 of 32
CY7C1518KV18
CY7C1520KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
1
SHIFT-DR
1
SHIFT-IR
1
1
0
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-00437 Rev. *V
Page 14 of 32
CY7C1518KV18
CY7C1520KV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
TDO
Instruction Register
Circuitry
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [13, 14, 15]
Description
Output HIGH voltage
Test Conditions
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH =2.0 mA
IOH =100 A
IOL = 2.0 mA
IOL = 100 A
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
–
V
0.4
0.2
V
–
V
0.65 × VDD VDD + 0.3
V
VIL
Input LOW voltage
–0.3
–5
0.35 × VDD
5
V
IX
Input and output load current
GND VI VDD
A
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in Electrical Characteristics on page 21.
14. Overshoot: V < V + 0.85 V (Pulse width less than t /2), Undershoot: V /2).
> 1.5 V (Pulse width less than t
IH(AC)
DDQ
CYC
IL(AC)
CYC
15. All voltage referenced to Ground.
Document Number: 001-00437 Rev. *V
Page 15 of 32
CY7C1518KV18
CY7C1520KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [16, 17]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Output Times
tTDOV
tTDOX
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
Notes
16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-00437 Rev. *V
Page 16 of 32
CY7C1518KV18
CY7C1520KV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [18]
Figure 3. TAP Timing and Test Conditions
0.9 V
ALL INPUT PULSES
1.8 V
50
0.9 V
TDO
0 V
Z = 50
0
C = 20 pF
L
t
t
TL
TH
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Note
18. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-00437 Rev. *V
Page 17 of 32
CY7C1518KV18
CY7C1520KV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1518KV18
CY7C1520KV18
Revision number (31:29)
Cypress device ID (28:12)
Cypress JEDEC ID (11:1)
000
000
Version number.
11010100010010100
00000110100
11010100010100100 Defines the type of SRAM.
00000110100
Allows unique identification of SRAM
vendor.
ID register presence (0)
1
1
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-00437 Rev. *V
Page 18 of 32
CY7C1518KV18
CY7C1520KV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
Bit #
84
Bump ID
1J
1
6P
5B
5A
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
4A
87
3J
4
7N
5C
4B
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
3A
90
2L
7
8P
2A
91
3L
8
9R
1A
92
1M
1L
9
11P
10P
10N
9P
2B
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
3B
94
3N
1C
1B
95
3M
1N
96
10M
11N
9M
9D
3D
3C
1D
2C
3E
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
2D
2E
3R
4R
10L
11K
10K
9J
1E
4P
8B
2F
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-00437 Rev. *V
Page 19 of 32
CY7C1518KV18
CY7C1520KV18
PLL Constraints
Power Up Sequence in DDR II SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
DDR II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
Figure 4. Power Up Waveforms
K
K
Unstable Clock
> 20μs Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
)
DDQ
DOFF
Document Number: 001-00437 Rev. *V
Page 20 of 32
CY7C1518KV18
CY7C1520KV18
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Ambient
Temperature (TA)
Range
[20]
[20]
VDD
VDDQ
Storage temperature ................................ –65 °C to +150 °C
Commercial
Industrial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to VDD
Ambient temperature
with power applied ................................... –55 °C to +125 °C
–40 °C to +85 °C
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in High Z ........–0.5 V to VDDQ + 0.3 V
DC input voltage [19] ...........................–0.5 V to VDD + 0.3 V
Current into outputs (LOW) ........................................ 20 mA
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
25 °C
85 °C
197 216 FIT/M
b
Static discharge voltage
(MIL-STD-883, M 3015) .......................................... >2001 V
Latch up current ..................................................... >200 mA
Logical
multi-bit
upsets
0
0
0.01 FIT/M
b
Single event
latch up
0.1 FIT/D
ev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [21]
VDD
Description
Power supply voltage
IO supply voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
V
1.9
VDD
VDDQ
VOH
1.4
V
Output HIGH voltage
Output LOW voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
Note 22
Note 23
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
VOL
–
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, Nominal impedance
–
V
IOL = 0.1 mA, Nominal impedance
–
0.2
V
VREF + 0.1
–0.3
–
VDDQ + 0.3
VREF – 0.1
5
V
VIL
–
V
IX
GND VI VDDQ
5
–
A
A
V
IOZ
GND VI VDDQ, Output disabled
5
–
5
VREF
Input reference voltage [24] Typical value = 0.75 V
0.68
0.75
0.95
Notes
19. Overshoot: V
20. Power up: assumes a linear ramp from 0 V to V
< V
+ 0.85 V (Pulse width less than t
/2), Undershoot: V
> 1.5 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
within 200 ms. During this time V < V and V
< V
.
DD(min)
IH
DD
DDQ
DD
21. All voltage referenced to Ground.
22. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OH
DDQ
23. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OL
DDQ
24. V
= 0.68 V or 0.46 V
, whichever is larger, V
= 0.95 V or 0.54 V
, whichever is smaller.
REF(min)
DDQ
REF(max)
DDQ
Document Number: 001-00437 Rev. *V
Page 21 of 32
CY7C1518KV18
CY7C1520KV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [21]
Description
Test Conditions
Min
–
Typ
–
Max
520
640
490
600
430
530
290
290
280
280
270
270
Unit
[25]
IDD
VDD operating supply
VDD = Max, IOUT = 0 mA, 333 MHz (× 18)
f = fMAX = 1/tCYC
mA
(× 36)
–
–
300 MHz (× 18)
(× 36)
–
–
mA
mA
mA
mA
mA
–
–
250 MHz (× 18)
(× 36)
–
–
–
–
ISB1
Automatic power down
current
Max VDD
,
333 MHz (× 18)
(× 36)
–
–
Both Ports Deselected,
–
–
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
Inputs Static
,
300 MHz (× 18)
(× 36)
–
–
–
–
250 MHz (× 18)
(× 36)
–
–
–
–
Note
25. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-00437 Rev. *V
Page 22 of 32
CY7C1518KV18
CY7C1520KV18
AC Electrical Characteristics
Over the Operating Range
Parameter [26]
Description
Input HIGH voltage
Input LOW voltage
Test Conditions
Min
VREF + 0.2
–
Typ
–
Max
–
Unit
V
VIH
VIL
–
VREF – 0.2
V
Capacitance
Parameter [27]
Description
Test Conditions
Max
4
Unit
pF
CIN
CO
Input capacitance
Output capacitance
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [27]
Description
Test Conditions
Unit
JA (0 m/s)
JA (1 m/s)
JA (3 m/s)
Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed
circuit board
14.43
13.40
12.66
11.38
°C/W
°C/W
°C/W
°C/W
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
3.30
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[28]
ALL INPUT PULSES
1.25 V
Z = 50
0
OUTPUT
Device
R = 50
L
0.75 V
Under
Device
Under
0.25 V
Test
5 pF
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
(b)
250
INCLUDING
JIG AND
SCOPE
(a)
Notes
26. Overshoot: V
< V
+ 0.85 V (Pulse width less than t
/2), Undershoot: V
> 1.5 V (Pulse width less than t
/2).
IH(AC)
DDQ
CYC
IL(AC)
CYC
27. Tested initially and after any design or process change that may affect these parameters.
28. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250, V
= 1.5 V, input pulse
DDQ
REF
levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.
OL OH
Document Number: 001-00437 Rev. *V
Page 23 of 32
CY7C1518KV18
CY7C1520KV18
Switching Characteristics
Over the Operating Range
Parameters [29, 30]
333 MHz
300 MHz
250 MHz
Unit
Description
Cypress Consortium
Parameter Parameter
Min
Max
Min
Max
Min
Max
tPOWER
tCYC
tKH
VDD(typical) to the first access [31]
K clock and C clock cycle time
Input clock (K/K and C/C) HIGH
Input clock (K/K and C/C) LOW
1
–
8.4
–
1
–
8.4
–
1
–
8.4
–
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
3.0
3.3
4.0
1.6
1.6
1.8
1.20
1.20
1.35
1.32
1.32
1.49
tKL
–
–
–
tKHKH
K clock rise to K clock rise and C
to C rise (rising edge to rising
edge)
–
–
–
tKHCH
tKHCH
K/K clock rise to C/C clock rise
(rising edge to rising edge)
0.0
1.30
0.0
1.45
0.0
1.8
ns
Setup Times
tSA tAVKH
tSC tIVKH
Address setup to K clock rise
0.4
0.4
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
Control setup to K clock rise (LD,
R/W)
tSCDDR
tIVKH
Double data rate control setup to
clock (K/K) Rise (BWS0, BWS1,
BWS2, BWS3)
0.3
0.3
–
–
0.3
0.3
–
–
0.35
0.35
–
–
ns
ns
tSD
tDVKH
D[X:0] setup to clock (K/K) rise
Hold Times
tHA
tHC
tKHAX
tKHIX
Address hold after K clock rise
0.4
0.4
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
Control hold after K clock rise
(LD, R/W)
tHCDDR
tKHIX
Double data rate control hold
after clock (K/K) rise (BWS0,
BWS1, BWS2, BWS3)
0.3
0.3
–
–
0.3
0.3
–
–
0.35
0.35
–
–
ns
ns
tHD
tKHDX
D[X:0] hold after clock (K/K) rise
Notes
29. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250, V
= 1.5 V, input pulse
DDQ
REF
levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 23.
OL OH
30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.
31. This part has an internal voltage regulator; t
is the time that the power is supplied above V min initially before a read or write operation can be initiated.
DD
POWER
Document Number: 001-00437 Rev. *V
Page 24 of 32
CY7C1518KV18
CY7C1520KV18
Switching Characteristics (continued)
Over the Operating Range
Parameters [29, 30]
333 MHz
300 MHz
250 MHz
Unit
Description
Cypress Consortium
Parameter Parameter
Min
Max
Min
Max
Min
Max
Output Times
tCO
tCHQV
tCHQX
C/C clock rise (or K/K in single
clock mode) to data valid
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
tDOH
Data output hold after output C/C –0.45
clock rise (Active to Active)
–0.45
–0.45
tCCQO
tCQOH
tCHCQV
tCHCQX
C/C clock rise to echo clock valid
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
Echo clock hold after C/C clock –0.45
rise
–0.45
–0.45
tCQD
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
Echo clock high to data valid
Echo clock high to data invalid
Output clock (CQ/CQ) HIGH [32]
–
0.25
–
0.27
–
0.30
ns
ns
ns
ns
tCQDOH
tCQH
–0.25
1.25
1.25
–
–
–
–0.27
1.40
1.40
–
–
–
–0.30
1.75
1.75
–
–
–
tCQHCQH
CQ clock rise to CQ clock rise
(rising edge to rising edge) [32]
tCHZ
tCHQZ
Clock (C/C) rise to High Z (Active
to High Z) [33, 34]
Clock (C/C) rise to Low Z [33, 34]
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
tCLZ
tCHQX1
–0.45
–0.45
–0.45
PLL Timing
tKC Var
tKC Var
Clock phase jitter
PLL lock time (K, C) [35]
–
0.20
–
–
0.20
–
–
0.20
–
ns
s
ns
tKC lock
tKC lock
tKC Reset
20
30
20
30
20
30
tKC Reset
K static to PLL reset
–
–
–
Notes
32. These parameters are extrapolated from the input timing parameters (t
design and are not tested in production.
/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
33. t
, t
are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 23. Transition is measured 100 mV from steady-state voltage.
CHZ CLZ
34. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
35. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (t lock) of 20 µs (min. spec.) and will
KC
lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
Document Number: 001-00437 Rev. *V
Page 25 of 32
CY7C1518KV18
CY7C1520KV18
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Read/Write/Deselect Sequence [36, 37, 38]
Notes
36. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
37. Outputs are disabled (High Z) one clock cycle after a NOP.
38. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-00437 Rev. *V
Page 26 of 32
CY7C1518KV18
CY7C1520KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
333 CY7C1518KV18-333BZC
CY7C1518KV18-333BZXC
CY7C1520KV18-333BZXC
CY7C1520KV18-333BZXI
300 CY7C1518KV18-300BZXC
CY7C1518KV18-300BZXI
CY7C1520KV18-300BZXI
250 CY7C1520KV18-250BZC
CY7C1518KV18-250BZXC
CY7C1520KV18-250BZXC
CY7C1518KV18-250BZI
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
Commercial
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Industrial
Commercial
Industrial
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
Commercial
Industrial
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
CY7C1520KV18-250BZI
CY7C1518KV18-250BZXI
CY7C1520KV18-250BZXI
51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
Ordering Code Definitions
CY 7 C 15XX K V18 - XXX BZ
X X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
BZ = 165-ball FBGA
Frequency range: 333 MHz or 300 MHz or 250 MHz
V18 = 1.8 V
Die Revision
Part Identifier:
15XX = 1518 or 1520
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-00437 Rev. *V
Page 27 of 32
CY7C1518KV18
CY7C1520KV18
Package Diagram
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 001-00437 Rev. *V
Page 28 of 32
CY7C1518KV18
CY7C1520KV18
Acronyms
Document Conventions
Units of Measure
Acronym
Description
DDR
FBGA
HSTL
I/O
Double Data Rate
Fine-Pitch Ball Grid Array
Symbol
°C
Unit of Measure
degree Celsius
kilohm
k
MHz
µA
µs
High-Speed Transceiver Logic
Input/Output
megahertz
microampere
microsecond
milliampere
millisecond
millimeter
millivolt
JEDEC
JTAG
LMBU
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Logical Multiple Bit Upset
Least Significant Bit
Logical Single Bit Upset
Most Significant Bit
mA
ms
mm
mV
ns
LSBU
MSB
PLL
nanosecond
ohm
Phase-Locked Loop
Quad Data Rate
QDR
SEL
%
percent
Single Event Latch-up
Static Random Access Memory
Test Access Port
pF
V
picofarad
volt
SRAM
TAP
W
watt
TCK
Test Clock
TMS
TDI
Test Mode Select
Test Data-In
TDO
TTL
Test Data-Out
Transistor-Transistor Logic
Document Number: 001-00437 Rev. *V
Page 29 of 32
CY7C1518KV18
CY7C1520KV18
Document History Page
Document Title: CY7C1518KV18/CY7C1520KV18, 72-Mbit DDR-II SRAM Two-Word Burst Architecture
Document Number: 001-00437
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
374703
SYT
VKN
See ECN New data sheet.
*A
1103864
See ECN Updated Selection Guide (Updated Maximum Operating Current parameter).
Updated Ordering Information (Updated part numbers, added disclaimer at the
top of the Ordering Information table).
*B
*C
1699246 VKN / AESA See ECN Changed status from Advance Information to Preliminary.
1939726 VKN / AESA See ECN Updated Electrical Characteristics (Added Note 25 and referred the same Note
in IDD parameter).
Updated SwitchingCharacteristics(UpdatedNote 32, changedminimumvalue
of tKC lock parameter from 1024 cycles to 20 s).
*D
2606839 VKN / PYRS
11/13/08
Updated IdentificationRegisterDefinitions (Changed Revision Number (31:29)
from 001 to 000).
Updated Power Up Sequence in DDR II SRAM (Updated description and
Figure 4).
Updated Maximum Ratings (Changed Ambient Temperature with Power
Applied from “–10 °C to +85 °C” to “–55 °C to +125 °C”).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for 165-ball FBGA Package).
Updated Ordering Information (Updated Package Type column (Changed the
package size from 15 × 17 × 1.4 mm to 13 × 15 × 1.4 mm)).
Updated Package Diagram (Changed the package size from 15 × 17 × 1.4 mm
to 13 × 15 × 1.4 mm (Removed spec 51-85195 and included 51-85180)).
*E
2681899 VKN / PYRS 04/01/2009 Changed status from Preliminary to Final.
Updated Ordering Information (Modified the disclaimer for the Ordering
information).
Post to external web.
*F
2747635 VKN / AESA 08/03/2009 Added Neutron Soft Error Immunity.
Updated Ordering Information (By including parts that are available, and
modified the disclaimer for the Ordering information).
*G
2767155 VKN / AESA 09/23/2009 Updated Capacitance (Changed value of Input Capacitance (CIN) from 2 pF to
4 pF, changed value of Output Capacitance (CO) from 3 pF to 4 pF).
Updated Ordering Information (Modified the disclaimer for the Ordering
information).
*H
*I
2870201
2896003
3216622
3298193
NJY
NJY
NJY
OSN
02/01/2010 No technical updates.
03/19/2010 Updated Ordering Information (Removed inactive parts).
04/05/2011 Updated to new template.
*J
*K
06/30/2011 Updated Ordering Information (Removed pruned part number
CY7C1520KV18-200BZC).
*L
3404578
3441341
PRIT
PRIT
10/13/2011 Updated Ordering Information (Removed prune part number
CY7C1520KV18-300BZI).
Updated to new template.
*M
11/21/2011 Updated Switching Characteristics (Added Note 35 and referred the same note
in description of tKC lock parameter).
Updated Package Diagram.
Document Number: 001-00437 Rev. *V
Page 30 of 32
CY7C1518KV18
CY7C1520KV18
Document History Page (continued)
Document Title: CY7C1518KV18/CY7C1520KV18, 72-Mbit DDR-II SRAM Two-Word Burst Architecture
Document Number: 001-00437
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*N
3598158
PRIT
04/24/2012 Updated Features (Removed CY7C1516KV18, CY7C1527KV18 related
information).
Updated Configurations (Removed CY7C1516KV18, CY7C1527KV18 related
information).
Updated Functional Description (Removed CY7C1516KV18, CY7C1527KV18
related information).
Updated Selection Guide (Removed 167 MHz and 200 MHz frequencies
related information, removed CY7C1516KV18, CY7C1527KV18 related
information).
Removed Logic Block Diagram – CY7C1516KV18.
Removed Logic Block Diagram – CY7C1527KV18.
Updated Pin Configurations (Removed CY7C1516KV18, CY7C1527KV18
related information).
Updated Pin Definitions (Removed CY7C1516KV18, CY7C1527KV18 related
information).
Updated Functional Overview (Removed CY7C1516KV18, CY7C1527KV18
related information).
Updated Truth Table (Removed CY7C1516KV18, CY7C1527KV18 related
information).
Updated Write Cycle Descriptions (Removed CY7C1516KV18 related
information).
Removed Write Cycle Descriptions (Corresponding to CY7C1527KV18).
Updated Identification Register Definitions (Removed CY7C1516KV18,
CY7C1527KV18 related information).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Removed 167 MHz and 200 MHz frequencies related information, removed
CY7C1516KV18, CY7C1527KV18 related information)).
Updated Switching Characteristics (Removed 167 MHz and 200 MHz
frequencies related information).
Updated Ordering Information (Updated part numbers).
Updated Package Diagram (spec 51-85180 (changed revision from *D to *E)).
*O
*P
*Q
3666992
3841481
4371693
PRIT
07/05/2012 No technical updates.
Completing Sunset review.
YHB /
GOPA
12/14/2012 Updated Ordering Information (Updated part numbers).
Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)).
PRIT
05/06/2014 Updated Application Example:
Updated Figure 2.
Updated Thermal Resistance:
Updated values of JA and JC parameters.
Included JB parameter and its details.
Updated to new template.
*R
*S
4489182
4569232
PRIT
PRIT
08/31/2014 Updated Ordering Information (Updated part numbers).
11/14/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*T
4811102
5125408
PRIT
PRIT
06/25/2015 Updated Ordering Information (Updated part numbers).
Updated to new template.
Completing Sunset Review.
*U
02/04/2016 Updated Switching Waveforms:
Updated Read/Write/Deselect Sequence:
Updated Figure 6.
Updated Package Diagram:
spec 51-85180 – Changed revision from *F to *G.
*V
5985781 AESATMP9 12/06/2017 Updated logo and copyright.
Document Number: 001-00437 Rev. *V
Page 31 of 32
CY7C1518KV18
CY7C1520KV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
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cypress.com/clocks
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cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
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Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
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cypress.com/support
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Wireless Connectivity
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© Cypress Semiconductor Corporation, 2005-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-00437 Rev. *V
Revised December 6, 2017
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