CY7C65223D-32LTXI [INFINEON]
USB-UART dual channel bridge controller with 4 GPIOs, RS485, software/hardware flow control, 24-pin QFN;
| 型号： | CY7C65223D-32LTXI |
| 厂家： | 
Infineon |
| 描述： | USB-UART dual channel bridge controller with 4 GPIOs, RS485, software/hardware flow control, 24-pin QFN |
| 文件： | 总31页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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when appropriate, and any changes will be set out on the document history page.
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY7C65223D
USB-Dual UART with Flow Control
CY7C65223D, USB-Dual UART with Flow Control
■ Driver support for VCOM and DLL
❐ Windows 10: 32- and 64-bit versions
❐ Windows 8.1: 32- and 64-bit versions
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Windows CE
Features
■ USB 2.0 compliant, Full-Speed (12 Mbps)
❐ Support for communication driver class (CDC), personal
health care device class (PHDC), and vendor device class
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification Rev 1.2 (Peripheral Detect only)
❐ Integrated USB termination resistors
■ Two-channel configurable UART interfaces
❐ Mac OS-X: 10.6, and later versions
❐ Linux: Kernel version 2.6.35 onwards
❐ CY7C65223D supports 2-pin, 4-pin, 6-pin, and 8-pin UART
interface
■ Clocking: Integrated 48-MHz clock oscillator
■ Supports bus-/self-powered configurations
■ USB suspend mode for low power
❐ Data rates up to 3 Mbps
❐ 190 bytes each transmit and receive buffer per channel
❐ Data format:
• 7 or 8 data bits
• 1 or 2 stop bits
■ Operating voltage: 1.71 to 5.5 V
• No parity, even, odd, mark, or space parity
❐ Supports parity, overrun, and framing errors
❐ Supports Software flow control and hardware flow control
❐ Supports UART break signal
■ Operating temperature
❐ Commercial: 0 °C to 70 °C
❐ Industrial: –40 °C to 85 °C
■ ESD protection: 2.2 kV HBM
❐ CY7C65223D supports RS232/RS422/RS485 interfaces
■ General-purpose input/output (GPIO) pins: 4
■ RoHS compliant package
■ Supports unique serial number feature for each device, which
fixes the COM port number permanently when USB-Serial
Bridge controller as CDC device plugs in
❐ 32-pin QFN (5 × 5 × 1 mm. 0.5 mm pitch)
■ Ordering part number
❐ CY7C65223D-32LTXI
■ Configuration utility (Windows) to configure the following:
❐ Vendor ID (VID), Product ID (PID), and Product and Manu-
Applications
facturer descriptors
❐ UART
■ Medical/healthcare devices
■ Point-of-Sale (POS) terminals
■ Test and measurement system
■ Gaming systems
❐ Charger detection
❐ GPIO
■ Set-top box PC-USB interface
■ Industrial
■ Networking
■ Enabling USB connectivity in legacy peripherals
USB Compliant
The USB-Dual UART with Software Flow Control (CY7C65223D) is fully compliant with the USB2.0
Specification and Battery Charging Specification v1.2. USB- IF compliant.
Errata: For information on silicon errata, see “Errata” on page 28. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 002-31603 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 25, 2020
CY7C65223D
USB Serial Bridge Controller Family
USB Serial bridge Controllers are a family of configurable products for most common applications requiring no firmware changes.
Configuration utility is provided to Configure USB-VID, USB-PID, USB Product and Manufacturer Descriptors. The same configuration
utility can be used to configure UART, I2C, SPI, Battery Charger Detection, GPIOs, Power mode, and so on.
Figure 1. USB Serial Bridge Controller Family
CY7C65211
24-QFN 10 GPIO
Configurable as:
USB-SPI
CY7C65223
24-QFN 4 GPIO
RS485 Support
S/W and H/W Flow
Control
USB-I2C
USB-UART
H/W Flow Control
CY7C65213A
32-QFN 8 GPIO
RS485 Support
S/W and H/W Flow
Control
CY7C652148
24-QFN
6 GPIO
CY7C65216
24-QFN
8 GPIO
Single Channel
CY7C65211A
24-QFN 10 GPIO
Configurable as:
USB-SPI
CY7C65213
32-QFN 8 GPIO
RS485 Support
H/W Flow Control
USB-I2C
USB-UART
H/W Flow Control
CY7C65215
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
H/W Flow Control
CY7C65223D
32-QFN 4 GPIOs
RS485 Support
S/W and H/W Flow
Control
CY7C65214D
32-QFN
8 GPIO
CY7C65216D
32-QFN
12 GPIO
Dual Channel
CY7C65215A
32-QFN 17 GPIO*
Configurable as:
USB-SPI
USB-I2C
USB-UART
RS485 Support
H/W Flow Control
USB-I2C
Bridge Controller
USB-Serial Configurable
Bridge Controller
USB-UART
Bridge Controller
USB-SPI
Bridge Controller
Document Number: 002-31603 Rev. **
Page 2 of 30
CY7C65223D
Table 1. USB Serial Family Feature Comparison
# of
USB-UART
USB-SPI
USB-I2C
Software Hardware
SPI Serial
Data
MPN
GPIO
RS485
UART
Pins**
SPI Master/ I2C Master/
Channels
Flow
Control
Flow
Control
Support
Slave
Slave
Width (bit)
CY7C65213
CY7C65213A
CY7C65223
CY7C65223D
CY7C652148
CY7C65214D
CY7C65216
CY7C65216D
CY7C65211
CY7C65211A
CY7C65215
1
1
1
2
1
2
1
2
1
1
2
2
8
8
N
Y
Y
Y
–
N
N
Y
Y
–
Y
Y
Y
Y
–
8
–
–
–
–
–
–
–
–
–
8
–
4
2 / 4 / 6
–
4
2 / 4 / 6 / 8
–
6
–
4-16 bits Master/Slave
4-16 bits Master/Slave
–
8
–
–
–
–
–
8
–
–
–
–
–
–
–
–
Master/Slave
Master/Slave
12
10*
10*
17*
17*
–
–
–
–
N
Y
N
Y
N
N
N
N
Y
Y
Y
Y
2 / 4 / 6
2 / 4 / 6
2 / 4 / 6
4-16 bits Master/Slave Master/Slave
4-16 bits Master/Slave Master/Slave
4-16 bits Master/Slave Master/Slave
CY7C65215A
2 / 4 / 6 / 8 4-16 bits Master/Slave Master/Slave
Legend
2
* Represents the total GPIO count offered by the part. This count can dynamically change based on UART / SPI / I C pin configuration.
** UART Pins
**UART Pins
UART Signal
2
4
6
8
RxD and TxD
RxD, TxD, RTS#, CTS#
RxD, TxD, RTS#, CTS#, DTR#, DSR#
RxD, TxD, RTS#, CTS#, DTR#, DSR#, DCD#, RI#
Document Number: 002-31603 Rev. **
Page 3 of 30
CY7C65223D
Table 2. Default Serial Channel Configuration
# of
USB- UART
USB-SPI
USB-I2C
USB
Protocol
SPI Master/ I2C Master/
MPN
GPIO
Is RS485
Channels
UART Pins
Enabled
Slave
Slave
CY7C65213
CY7C65213A
CY7C65223
CY7C65223D
CY7C652148
CY7C65214D
CY7C65216
CY7C65216D
CY7C65211
CY7C65211A
CY7C65215
CY7C65215A
1
1
1
2
1
2
1
2
1
1
2
2
4
4
CDC**
CDC**
N
N
Y
Y
8
8
4
4
–
–
–
–
6
6
6
6
–
–
–
–
–
–
–
–
4
CDC**
4
CDC**
6
Vendor***
Vendor***
Vendor***
Vendor***
CDC**
–
–
Master
–
8
Master
–
8
–
–
–
–
–
–
–
Slave
12
3
–
Master
N
N
N
N
–
–
–
–
3
CDC**
4
CDC**
4
CDC**
** USB CDC Protocol allows the USB host Operating System to detect the device as Virtual COM Port Device.
*** USB Vendor Protocol allows the USB host operating system to detect the device as general USB device. This device is accessible using Cypress Application Library.
Document Number: 002-31603 Rev. **
Page 4 of 30
CY7C65223D
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the document USB-Serial Bridge
Controller Product Overview.
■ Overview: USB Portfolio, USB Roadmap
For a complete list of knowledge base articles, click here.
■ USB2.0 ProductSelectors:USB-SerialBridge Controller, USB
■ Code Examples: USB Full-Speed
to UART Controller (Gen I)
■ Development Kits:
■ Knowledge Base Articles: Cypress offers a large number of
USB knowledge base articles covering a broad range of topics,
from basic to advanced level. Recommended knowledge base
articles for getting started with USB-Serial Bridge Controller
are:
❐ CYUSBS232, Cypress USB-UART LP Reference Design Kit
❐ CYUSBS234, Cypress USB-Serial (Single Channel)
Development Kit
❐ CYUSBS236, Cypress USB-Serial (Dual Channel)
Development Kit
❐ KBA85909 – Key Features of the Cypress® USB-Serial
■ Models: IBIS
Bridge Controller
❐ KBA85920 – USB-UART and USB-Serial
❐ KBA85921 – Replacing FT232R with CY7C65213
USB-UART LP Bridge Controller
❐ KBA85913 – Voltage supply range for USB-Serial
❐ KBA89355 – USB-Serial: Cypress Default VID and PID
❐ KBA92641 – USB-Serial Bridge Controller Managing I/Os
using API
❐ KBA92442–Non-StandardBaudRatesinUSB-SerialBridge
Controllers
❐ KBA91366 – Binding a USB-Serial Device to a
Microsoft® CDC Driver
❐ KBA92551 – Testing a USB-Serial Bridge Controller
Configured as USB-UART with Linux®
❐ KBA91299 – Interfacing an External I2C Device with the
CYUSBS234/236 DVK
Document Number: 002-31603 Rev. **
Page 5 of 30
CY7C65223D
Block Diagram
nXRES
Reset
SCB0
8 Bytes
Tx FIFO
Internal
48 MHz OSC
VDDD
VCCD
Voltage
Regulator
Channel 0 UART
UART
UART
Internal
32 KHz OSC
8 Bytes
RX FIFO
USB
VBUS Regulator
VBUS
SCB1
8 Bytes
Tx FIFO
Memory
SIE
Battery Charger
Detection
USBDP
Channel 1 UART
8 Bytes
RX FIFO
USBDM
GND
32 KB
Flash
USB Transceiver
with Integrated
Resistor
512
Bytes
Memory
GPIO
GPIO
Document Number: 002-31603 Rev. **
Page 6 of 30
CY7C65223D
Contents
Functional Overview ........................................................8
USB and Charger Detect .............................................8
Serial Communication .................................................8
GPIO Interface ............................................................9
Default Configuration ...................................................9
Memory .......................................................................9
System Resources ......................................................9
Suspend and Resume .................................................9
WAKEUP .....................................................................9
Software ......................................................................9
Internal Flash Configuration ......................................10
Electrical Specifications ................................................11
Absolute Maximum Ratings .......................................11
Operating Conditions .................................................11
Device Level Specifications .......................................11
GPIO .........................................................................12
nXRES .......................................................................13
Flash Memory Specifications ....................................13
Pin Description ...............................................................14
USB Power Configurations ............................................18
USB Bus-Powered Configuration ..............................18
Self-Powered Configuration ......................................19
USB Bus Powered with Variable I/O Voltage ............20
Application Examples ....................................................21
USB-to-Dual UART Bridge with Battery-Charge
Detection ...................................................................21
USB to RS232 Bridge ................................................23
USB to RS485 Application ........................................24
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Package Information ......................................................26
Acronyms ........................................................................27
Document Conventions .................................................27
Units of Measure .......................................................27
Errata ...............................................................................28
Document History Page .................................................29
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products ....................................................................30
PSoC® Solutions ......................................................30
Cypress Developer Community .................................30
Technical Support .....................................................30
Document Number: 002-31603 Rev. **
Page 7 of 30
CY7C65223D
Charger Detection
Functional Overview
CY7C65223D supports BCD for Peripheral Detect only and
complies with the USB Battery Charging Specification Rev. 1.2.
It supports the following charging ports:
The CY7C65223D is a Full-Speed USB controller that enables
seamless PC connectivity for peripherals with dual-channel
interface. CY7C65223D also integrates BCD, which is
compliant with the USB Battery Charging Specification Rev. 1.2.
It integrates a voltage regulator, oscillator, and flash memory for
storing configuration parameters, offering a cost-effective
■ Standard Downstream Port (SDP): allows the system to draw
up to 500 mA current from the host
■ Charging Downstream Port (CDP): allows the system to draw
up to 1.5 A current from the host
solution.
CY7C65223D
supports
bus-powered
and
self-powered modes, and enables efficient system power
management with suspend and remote wake-up signals. It is
available in a 32-pin QFN package.
■ Dedicated Charging Port (DCP): allows the system to draw up
to 1.5 A of current from the wall charger
Serial Communication
USB and Charger Detect
CY7C65223D has two serial communication blocks (SCBs)
implementing UART interface. A 256-byte buffer is available in
both the TX and RX lines.
USB
CY7C65223D has a built-in USB 2.0 Full-Speedtransceiver. The
transceiver incorporates the internal USB series termination
resistors on the USB data lines and a 1.5-k pull-up resistor on
USBDP.
Table 3 shows maximum speed supported on both SCBs when
they are configured as UART.
Table 3. Maximum Speed supported on both SCBs
No.
1
Configuration
SCB0 Maximum Speed
3M (TX/RX) with Flow Control
1M (TX/RX) with Flow Control
SCB1 Maximum Speed
NA
SCB0 = UART, SCB1 = Disabled
SCB0 = UART, SCB1 = UART
2
1M (TX/RX) with Flow Control
UART Interface
Hardware flow control uses signal pairs such as RTS# (Request
to Send) / CTS# (Clear to Send) to control the data flow between
partner UART devices.
The UART interface provides asynchronous serial
communication with other UART devices operating at speeds of
up to 3 Mbps. It supports 7 to 8 data bits, 1 to 2 stop bits, odd,
even, mark, space, and no parity. The UART interface supports
full duplex communication with a signaling format that is
compatible with the standard UART protocol. In CY7C65223D,
these UART pins may be interfaced to RS232/RS422/RS485.
Software flow control do not use additional hardware signaling
pairs. But, software flow control uses in-band communication
using special characters called XON or XOFF. These XON or
XOFF characters are exchanged at UART PHY level for data
flow control. These XON or XOFF characters doesn't reflect in
the actual data received by the USB host application.default.
Flow control can be disabled using the configuration utility.
Default configuration will not have flow control enabled.
CY7C65223D supports common UART functions such as parity
error and frame error. In addition, CY7C65223D supports baud
rates ranging from 300 baud to 3 Mbaud. UART baud rates can
be set using the configuration utility.
The following section describes the flow control signals:
Notes
■ CTS# (Input) / RTS# (Output)
■ Parity error gets detected when UART transmitter device is
configured for odd parity and UART receiver device is
configured for even parity.
CTS# can pause or resume data transmission over the UART
interface. Data transmission can be paused by de-asserting the
CTS signal and resumed with CTS# assertion. The pause and
resume operation does not affect data integrity. With flow control
enabled, receive buffer has a watermark level of 93%. After the
data in the receive buffer reaches that level, the RTS# signal is
de-asserted, instructing the transmitting device to stop data
transmission. The start of data consumption by the application
reduces device data backlog. When it reaches the 75%
watermark level, the RTS# signal is asserted to resume data
reception.
■ Frame error gets detected when UART transmitter device is
configured for 7 bits data width and 1 stop bit, whereas UART
receiver device is configured for 8 bit data width and 2 stop bits.
UART Flow Control
UART Data Flow control is the process of signaling the UART
partner device to WAIT or RESUME the data transmission. This
flow control process is required for the slower device to catch up
with the partner device without data loss. The CY7C65223D
device supports both UART hardware and software flow control.
■ DSR# (Input) /DTR# (Output)
DSR#/DTR# signals are used to establish the communication
link with the UART. These signals complement each other in their
functionality, similar to CTS# and RTS#.
By default, flow control is disabled. USB host UART terminal
applications can enable or disable either hardware or software
flow control through operating system software interfaces.
Document Number: 002-31603 Rev. **
Page 8 of 30
CY7C65223D
GPIO Interface
Suspend and Resume
CY7C65223D has four GPIOs. The configuration utility allows
configuration of the GPIO pins. The configurable options are as
follows:
The CY7C65223D device asserts the SUSPEND pin when the
USB bus enters the suspend state. This helps in meeting the
stringent suspend current requirement of the USB 2.0 specifi-
cation, while using the device in bus-powered mode. The device
will resume from the suspend state under any of the following
conditions:
■ GPIO can be tristated through Config Utility
■ DRIVE 1: Output static 1
■ DRIVE 0: Output static 0
1. Any activity is detected on the USB bus
■ POWER#: Power control for bus power designs
■ TXLED#: Drives LED during USB transmit
■ RXLED#: Drives LED during USB receive
■ TX or RX LED#: Drives LED during USB transmit or receive
GPIO can be configured to drive LED at 8-mA drive strength.
2. The WAKEUP pin is asserted to generate remote wakeup to
the host
WAKEUP
The WAKEUP pin is used to generate a remote wakeup signal
on the USB bus. The remote wakeup signal is sent only if the
host enables this feature through the SET_FEATURE request.
The device communicates support for the remote wakeup to the
host through the configuration descriptor during the USB
enumeration process. The CY7C65223D device allows
enabling/disabling and polarity of the remote wakeup feature
through the configuration utility.
■ BCD0/BCD1: Two-pin output to indicate the type of USB
charger
■ BUSDETECT: Connects VBUS pin for USB host detection
Default Configuration
CY7C65223D is configured as Dual 4-Pin UART Device.
Software
Memory
Cypress delivers a complete set of software drivers and the
configuration utility to enable product configuration during
system development.
CY7C65223D has a 512-byte flash. The flash is used to store
the USB parameters such as VID/PID, serial number, Product,
and Manufacturer Descriptors, which can be programmed by the
configuration utility.
Drivers for Linux Operating Systems
Cypress provides a User Mode USB driver library (libcyusb-
serial.so) that abstracts vendor commands for the UART
interface and provides a simplifiedAPI interface to the user appli-
cations. This library makes use of the standard open source
libUSB library to enable the USB communication. The Cypress
serial library supports the USB plug-and-play feature using the
Linux ‘udev’ mechanism.
System Resources
Power System
CY7C65223D supports theUSB Suspend mode to control power
usage. CY7C65223D operates in bus-powered or self-powered
modes over a range of 3.15 to 5.5 V.
CY7C65223D supports the standard USB CDC UART class
driver, which is bundled with the Linux kernel.
Clock System
CY7C65223D has a fully integrated clock and does not require
any external components. The clock system is responsible for
providing clocks to all subsystems.
Drivers for Mac OSx
Cypress delivers
a
dynamically linked shared library
(CyUSBSerial.dylib) based on libUSB, which enables
communication to the CY7C65223D device.
Internal 48-MHz Oscillator
The internal 48-MHz oscillator is the primary source of internal
clocking in CY7C65223D.
Drivers for Windows Operating Systems
For Windows operating systems (XP, Vista, Win7, Win8, Win8.1,
and Win10), Cypress delivers a User Mode dynamically linked
library–CyUSBSerial DLL–that abstracts vendor-specific
interface of CY7C65223D devices and provides convenientAPIs
to the user. It provides interface APIs for vendor-specific
UART/SPI/I2C and class-specific APIs for PHDC.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator is primarily used to generate
clocks for peripheral operation in the USB Suspend mode.
Reset
The reset block ensures reliable power-on reset and brings the
device back to the default known state. The nXRES (active low)
pin can be used by external devices to reset the CY7C65223D.
USB-Serial Bridge Controller works with the Windows-standard
USB CDC class driver, when either CY7C65223D is configured
as CDC USB to UART device. Avirtual COM port driver–CyUSB-
Serial.sys–is also delivered, which implements the USB CDC
class driver. The Cypress Windows drivers are Windows
hardware certification kit-compliant.
These drivers are bound to device through WU (Windows
Update) services.
Cypress drivers also support Windows plug-and-play and power
management and USB Remote Wake-up.
Document Number: 002-31603 Rev. **
Page 9 of 30
CY7C65223D
Windows-CE Support
Internal Flash Configuration
The CY7C65223D solution includes a CDC UART driver library
for Windows-CE platforms.
The internal flash memory can be used to store the configuration
parameters shown in the following table. A free configuration
utility is provided to configure the parameters listed in the table
to meet application specific requirements over USB interface.
The configuration utility can be downloaded from
www.cypress.com/usbserial.
Device Configuration Utility (Windows Only)
A Windows-based configuration utility is available to configure
various device initialization parameters. This graphical user
application provides an interactive interface to define the various
boot parameters stored in the device flash.
This utility allows the user to save a user-selected configuration
to text or xml formats. It also allows users to load a selected
configuration from text or xml formats.
The configuration utility allows the following operations:
■ View current device configuration
■ Configure USB VID, PID, and string descriptors
■ Save or Load configuration
You can download the free configuration utility and drivers from
www.cypress.com.
Table 4. Internal Flash Configuration for CY7C65223D
Parameter
USB Configuration
USB Vendor ID (VID)
USB Product ID (PID)
Manufacturer string
Product string
Default Value
Description
0x04B4
0x0005
Cypress
Default Cypress VID. Can be configured to customer VID
Default Cypress PID. Can be configured to customer PID
Can be configured with any string up to 64 characters
USB-Serial (Dual Channel) Can be configured with any string up to 64 characters
Serial string
–
Can be configured with any string up to 64 characters
Can be configured to bus-powered or self-powered mode
Power mode
Bus powered
Can be configured to any value from 0 to 500 mA. Based on this, the
configuration descriptor will be updated.
Max current draw
100 mA
Remote wakeup
Enabled
CDC
Can be disabled. Remote wakeup is initiated by asserting WAKEUP pin
Can be configured to function in CDC, PHDC, or Cypress vendor class
USB interface protocol
Charger detect is disabled by default. When BCD is enabled, three of the
GPIOs must be configured for BCD.
BCD
Disabled
Document Number: 002-31603 Rev. **
Page 10 of 30
CY7C65223D
Electrical Specifications
Absolute Maximum Ratings
Exceeding maximum ratings[1] may shorten the useful life of the
device.
■ 2.2-kV HBM per JESD22-A114
Latch-up current ...................................................... 140 mA
Current per GPIO ...................................................... 25 mA
Storage temperature ......................... ...... –55 °C to +100 °C
Ambient temperature with
power supplied (Industrial) ................. ...... –40 °C to +85 °C
Operating Conditions
TA (ambient temperature under bias)
Industrial ................................................... –40 °C to +85 °C
Supply voltage to ground potential
VDDD ............................................................................. 6.0 V
VBUS supply voltage ................................... 3.15 V to 5.25 V
VBUS ............................................................................. 6.0 V
VCCD ...........................................................................1.95 V
VGPIO .......................................................... .....VDDD + 0.5 V
Static discharge voltage ESD protection levels:
VDDD supply voltage ................................... 1.71 V to 5.50 V
CCD supply voltage ................................... 1.71 V to 1.89 V
V
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C, TJ 100 °C, and 1.71 V to 5.50 V, except where noted.
Table 5. DC Specifications
Parameter
VBUS
Description
VBUS supply voltage
Min
Typ
Max
Units
Details/Conditions
3.15
3.30
3.45
V
Set and configure correct voltage
range using the configuration
4.35
1.71
5.00
1.80
5.25
1.89
V
V
utility for VBUS
.
Used to set I/O and core voltage.
Set and configure correct voltage
range using the configuration
VDDD
VDDD supply voltage
2.0
3.3
5.5
V
utility for VDDD
.
Do not use this supply to drive
external device.
• 1.71 V VDDD 1.89 V: Short
the VCCD pin with the VDDD pin
VCCD
Output voltage (for core logic)
–
1.80
–
V
• VDDD > 2 V – connect a 1-µF
capacitor (Cefc) between the
VCCD pin and ground
Cefc
IDD1
External regulator voltage bypass
Operating supply current
1.00
–
1.30
13
1.60
18
µF
X5R ceramic or better
USB 2.0 FS, UART at 1 Mbps
single channel,
no GPIO switching at
mA
VBUS = 5 V, VDDD = 5 V
Does not include current through
a pull-up resistor on USBDP.
In USB suspend mode, the D+
voltage can go up to a maximum
of 3.8 V.
IDD2
USB Suspend supply current
–
5
–
µA
Table 6. AC Specifications
Parameter
Description
Min
28
–
Typ
–
Max
44
–
Units
Details/Conditions
Zout
USB driver output impedance
–
Twakeup
Wakeup from USB Suspend mode
25
µs
–
Note
1. Usage above the absolute maximum conditions may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of
time may affect device reliability. When used below Absolute Maximum conditions but above normal operating conditions the device may not operate to specification.
Document Number: 002-31603 Rev. **
Page 11 of 30
CY7C65223D
GPIO
Table 7. GPIO DC Specifications
Parameter
Description
Min
Typ
–
Max
Units
Details/Conditions
[2]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD< 2.7 V
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD > 2.7 V
LVTTL input, VDDD > 2.7 V
0.7 × VDDD
–
V
V
V
V
V
V
CMOS Input
VIL
VIH
VIL
VIH
VIL
–
–
0.3 × VDDD
CMOS Input
[2]
[2]
0.7 × VDDD
–
–
–
–
–
–
–
2
–
–
0.3 × VDDD
–
–
–
0.8
IOH = 4 mA,
VDDD = 5 V ± 10%
VOH
VOH
VOH
VOL
VOL
VOL
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage high level
CMOS output voltage low level
CMOS output voltage low level
CMOS output voltage low level
VDDD – 0.4
–
–
–
–
–
–
–
–
V
V
V
V
V
V
IOH = 4 mA,
VDDD = 3.3 V ± 10%
VDDD – 0.6
IOH = 1 mA,
VDDD = 1.8 V ± 5%
VDDD – 0.5
–
IOL = 8 mA,
VDDD = 5 V ± 10%
–
–
–
0.4
0.6
0.6
IOL = 8 mA,
VDDD = 3.3 V ± 10%
IOL = 4 mA,
VDDD = 1.8 V ± 5%
Rpullup
Rpulldown
IIL
Pull-up resistor
3.5
5.6
5.6
–
8.5
8.5
2
kΩ
kΩ
nA
pF
–
Pull-down resistor
3.5
–
Input leakage current (absolute value)
Input capacitance
–
25 °C, VDDD = 3.0 V
CIN
–
25
–
7
–
–
–
Vhysttl
Vhyscmos
Input hysteresis LVTTL; VDDD > 2.7 V
Input hysteresis CMOS
40
–
–
mV
mV
0.05 × VDDD
–
Table 8. GPIO AC Specifications
Parameter Description
TRiseFast1
Min
Typ
Max
Units
Details/Conditions
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
–
12
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TFallFast1
TRiseSlow1
TFallSlow1
2
–
–
–
12
60
60
ns
ns
ns
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
10
10
VDDD = 3.3 V/ 5.5 V,
Cload = 25 pF
TRiseFast2
TFallFast2
TRiseSlow2
TFallSlow2
Rise Time in Fast mode
Fall Time in Fast mode
Rise Time in Slow mode
Fall Time in Slow mode
2
20
2
–
–
–
–
20
100
20
ns
ns
ns
ns
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
VDDD = 1.8 V, Cload = 25 pF
20
100
Note
2.
V
must not exceed V
+ 0.2 V.
IH
DDD
Document Number: 002-31603 Rev. **
Page 12 of 30
CY7C65223D
nXRES
Table 9. nXRES DC Specifications
Parameter
VIH
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
0.7 × VDDD
–
–
–
–
–
–
VIL
–
3.5
–
–
0.3 × VDDD
V
Rpullup
CIN
5.6
5
8.5
–
kΩ
pF
Input capacitance
Vhysxres
Input voltage hysteresis
–
100
–
mV
Table 10. nXRES AC Specifications
Parameter
Description
Reset pulse width
Min
Typ
Max
Units
Details/Conditions
Details/Conditions
Tresetwidth
1
–
–
µs
–
Table 11. UART AC Specifications
Parameter Description
FUART UART bit rate
Min
Typ
Max
Units
Single SCB: TX + RX
Dual SCB: TX or RX
0.3
–
3000
kbps
Flash Memory Specifications
Table 12. Flash Memory Specifications
Parameter
Fend
Description
Flash endurance
Min
Typ
Max
Units
Details/Conditions
100 K
–
–
cycles
–
Flash retention. TA 85 °C, 10 K
program/erase cycles
Fret
10
–
–
years
–
Document Number: 002-31603 Rev. **
Page 13 of 30
CY7C65223D
Pin Description
Pin[3]
Type
Name
Default
Description
1
2
Power
SCB0
VDDD
RxD_0
Supply to the device core and Interface, 1.71 to 5.5 V
UART Rx SCB0
3
SCB/GPIO DTR#_0/GPIO_9 GPIO Input Pin GPIO IN (see Table 15)
4
Power
SCB1
VSSD
RxD_1
Digital Ground
5
UART Rx SCB1
6
SCB1
TxD_1
UART Tx SCB1
7
SCB/GPIO
SCB/GPIO
SCB/GPIO
SCB/GPIO
RTS#_1
CTS#_1
TXLED_1
RXLED_1
UART RTS SCB1 Hardware Flow Control Signal
UART CTS SCB1 Hardware Flow Control Signal
Notification LED for UART SCB1 Tx
Notification LED for UART SCB1 Rx
8
9
10
Indicates device in suspend mode. Can be configured as active high/low
using configuration utility
11
Output
Suspend
Wakeup device from suspend mode. Can be configured as active
high/low using configuration utility
12
13
14
Input
GPIO
Wakeup
TxEN_1
USBDP
SCB1 UART RS485 Transmitter Enable
USB Data Signal Plus, integrates termination resistor and 1.5-k pull up
resistor
USBIO
15
16
17
USBIO
Power
Power
USBDM
VCCD
VSSD
USB Data Signal Minus, integrates termination resistor
Regulated supply, connect to 1-µF cap or 1.8 V (Internal LDO Output)
Digital Ground
Chip Reset active, low. Can be left unconnected or have a pull up resistor
connected when not in use.
18
Reset
nXRES
19
20
21
22
23
24
25
26
27
Power
Power
GPIO
VBUS
VBUS Supply, 3.15 V to 5.25 V
Digital Ground
VSSD (VBUS)
GPIO_17
GPIO_18
VDDD_IO
GPIO Output Pin GPIO OUT (see Table 15)
GPIO Output Pin GPIO OUT (see Table 15)
Supply to the device core and Interface, 1.71 to 5.5 V
GPIO
Power
Power
GPIO
VSSA
Analog Ground
TXLED_0
Notification LED for SCB0 UART Tx (see Table 15)
Notification LED for SCB0 UART Rx (see Table 15)
GPIO
RXLED_0
SCB/GPIO
GPIO_2
GPIO Input Pin GPIO IN (see Table 15)
28
SCB/GPIO
RTS#_0
SCB0 UART Hardware Flow Control
29
30
SCB/GPIO
SCB0
CTS#_0
TxD_0
SCB0 UART Hardware Flow Control
SCB0 UART Tx
Signal to external logic to indicate USB Unconfigured state and USB
Suspend
31
Output
GPIO
POWER#
TxEN_0
32
SCB0 UART RS485 Transmit Enable
Note
3. Any pin acting as an input pin should not be left unconnected.
Document Number: 002-31603 Rev. **
Page 14 of 30
CY7C65223D
Figure 2. 32-Pin QFN Pinout
VDDD
RxD_0
1
2
3
4
5
6
7
8
VSSA
24
23
22
21
20
19
18
17
VDDD_IO
GPIO_18
GPIO_17
GPIO_9
VSSD
CY7C65223D-32 QFN
Top View
VSSD
VBUS
RxD_1
TxD_1
nXRES
VSSD
RTS#_1
CTS#_1
Document Number: 002-31603 Rev. **
Page 15 of 30
CY7C65223D
Table 13. Serial Communication Block (SCB0) Configuration
Mode 0[4]
Mode 1
6-pin UART
RxD_0
Mode 2
2-pin UART
RxD_0
Mode 3
8-pin UART
RxD_0
Pin
Serial Port 0
4-pin UART
RxD_0
2
SCB0_0
SCB0_1
SCB0_2
SCB0_3
SCB0_4
SCB0_5
SCB0_6
SCB0_7
27
28
29
30
3
GPIO_2
RTS#_0
CTS#_0
TxD_0
DSR#_0
RTS#_0
CTS#_0
TxD_0
GPIO_2
GPIO_3
GPIO_4
TxD_0
DSR#_0
RTS#_0
CTS#_0
TxD_0
GPIO_9
GPIO_17
GPIO_16
DTR#_0
GPIO_17
GPIO_16
GPIO_9
GPIO_17
GPIO_16
DTR#_0
DCD#_0
RI#_0
21
13
Table 14. Serial Communication Block (SCB1) Configuration
Mode 0[4]
Mode 1
6-pin UART
RxD_1
Mode 2
2-pin UART
RxD_0
Mode 3
8-pin UART
RxD_1
Pin
Serial Port 1
4-pin UART
RxD_1
5
6
SCB1_0
SCB1_1
SCB1_2
SCB1_3
SCB1_4
SCB1_5
SCB1_6
SCB1_7
TxD_1
TxD_1
TxD_1
TxD_1
7
RTS#_1
CTS#_1
GPIO_14
GPIO_15
GPIO_18
GPIO_1
RTS#_1
CTS#_1
DSR#_1
DTR#_1
GPIO_18
GPIO_1
GPIO_12
GPIO_13
GPIO_14
GPIO_9
RTS#_1
CTS#_1
DSR#_1
DTR#_1
DCD#_1
RI#_1
8
9
10
22
26
GPIO_17
GPIO_16
Legend
GPIO
SCB0
SCB1
Note
4. Device configured in Mode 0 as default. Other modes can be configured through Cypress-supplied configuration utility.
Document Number: 002-31603 Rev. **
Page 16 of 30
CY7C65223D
Table 15. GPIO Configuration[5]
GPIO Configuration Option
Description
TRISTATE
DRIVE 1
DRIVE 0
I/O tristated
Output static 1
Output static 0
This output is used to control power to an external logic via switch to cut power off during unconfigured
USB device and USB suspend.
0 - USB device in Configured state
POWER#
1 - USB device in Unconfigured state or during USB suspend mode
TXLED#
RXLED#
Drives LED during USB transmit
Drives LED during USB receive
TX or RX LED#
Drives LED during USB transmit or receive
Configurable battery charger detect pins to indicate type of USB charger (SDP, CDP, or DCP)
Configuration example:
00 - Draw up to 100 mA (Unconfigured state)
01 - SDP (up to 500 mA)
10 - CDP/DCP (up to 1.5 A)
BCD0
BCD1
11 - Suspend (up to 2.5 mA)
This truth table can be configured using the configuration utility
VBUS detection. Connect VBUS to this pin via resistor network for VBUS detection when using BCD
feature (see Figure 7).
BUSDETECT
Note
5. These signal options can be configured on any of the available GPIO pins using Cypress-supplied configuration utility.
Document Number: 002-31603 Rev. **
Page 17 of 30
CY7C65223D
The USB bus-powered system must comply with the following
requirements:
USB Power Configurations
The following section describes possible USB power configura-
tions for the CY7C65223D. Refer to the Pin Description on page
14 for signal details.
1. The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
2. The system should not draw more than 2.5 mA during USB
Suspend mode.
USB Bus-Powered Configuration
3. A high-power bus-powered system (can draw more than
100 mA when operational) must use POWER# (configured
over GPIO) to keep the current consumption below 100 mA
prior to USB enumeration, and 2.5 mA during USB Suspend
state.
Figure 3 shows an example of the CY7C65223D in a
bus-powered design. VBUS is connected directly to the
CY7C65223D because it has an internal regulator.
4. The system should not draw more than 500 mAfrom the USB
host.
The configuration descriptor in the CY7C65223D flash should be
updated to indicate bus power and the maximum current
required by the system using the configuration utility.
Figure 3. Bus-Powered Configuration
CY7C65223D
25 TXLED_0
26 RXLED_0
27 GPIO_2
28 RTS#_0
29 CTS#_0
30 TxD_0
31 POWER#
32 TxEN_0
2
3
RxD_0
1
GPIO_9
VDDD
USB
CONNECTOR
19
14
15
5
6
7
8
9
RxD_1
VBUS
USBDP
USBDM
VBUS
D+
D-
TxD_1
RTS#_1
CTS#_1
TXLED_1
GND
4.7 uF
0.1 uF
10 RXLED_1
13 TxEN_1
21 GPIO_17
22 GPIO_18
18
nXRES
VCCD
16
11 SUSPEND
12 WAKEUP
1 uF
24 20 17
4
Document Number: 002-31603 Rev. **
Page 18 of 30
CY7C65223D
When VBUS is present, CY7C65223D enables an internal,
1.5-k pull-up resistor on USBDP. When VBUS is absent (USB
host is powered down), CY7C65223D removes the 1.5-k
pull-up resistor on USBDP, and this ensures no current flows
from the USBDP to the USB host via a 1.5-k pull-up resistor, to
comply with USB 2.0 specification.
Self-Powered Configuration
Figure 4 shows an example of CY7C65223D in a self-powered
design.
In this configuration:
■ VBUS is powered from USB VBUS. VBUS pin is also used to
detect USB connection.
When reset is asserted to CY7C65223D, all the I/O pins are
tristated.
■ VDDD is powered from an external power supply.
Using the configuration utility, the configuration descriptor in the
CY7C65223D flash should be updated to indicate that it is
self-powered.
Figure 4. Self-Powered Configuration
CY7C65223D
3.3 V
3.3 V
25 TXLED_0
26 RXLED_0
27 GPIO_2
28 RTS#_0
29 CTS#_0
30 TxD_0
1
VDDD
VBUS
19
31 POWER#
32 TxEN_0
2
3
RxD_0
GPIO_9
USB
CONNECTOR
5
6
7
8
9
RxD_1
TxD_1
VBUS
D+
D-
14
15
USBDP
USBDM
RTS#_1
CTS#_1
TXLED_1
GND
0.1 uF
4.7 uF
10 RXLED_1
13 TxEN_1
21 GPIO_17
22 GPIO_18
4.7 KΩ
18
nXRES
VCCD
10 KΩ
16
11 SUSPEND
12 WAKEUP
1 uF
24 20 17
4
Document Number: 002-31603 Rev. **
Page 19 of 30
CY7C65223D
The USB bus-powered system must comply with the following:
USB Bus Powered with Variable I/O Voltage
Figure 5 shows CY7C65223D in a bus-powered system with
variable I/O voltage. A low dropout (LDO) regulator is used to
supply 1.8 V or 3.3 V (using a jumper switch) the input of which
is 5 V from VBUS. Another jumper switch is used to select 1.8/3.3
V or 5 V from VBUS for the VDDD pin of CY7C65223D. This
allows I/O voltage and supply to external logic to be selected
among 1.8 V, 3.3 V, or 5 V.
■ The system should not draw more than 100 mA prior to USB
enumeration (Unconfigured state).
■ The system should not draw more than 2.5 mA during USB
Suspend mode.
■ A high-power bus-powered system (can draw more than 100
mA when operational) must use POWER# (configured over
GPIO) to keep the current consumption below 100 mA prior to
USB enumeration and 2.5 mA during USB Suspend state.
Figure 5. USB Bus-Powered with 1.8 V, 3.3 V, or 5 V Variable I/O Voltage[6]
CY7C65223D
25 TXLED_0
26 RXLED_0
27 GPIO_2
28 RTS#_0
29 CTS#_0
30 TxD_0
Power
Switch
1.8V or 3.3V or 5V
Supply to External Logic
31 POWER#
32 TxEN_0
1.8/3.3 V
2
3
RxD_0
GPIO_9
1
2
3
1
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
5
6
7
8
9
RxD_1
TxD_1
19
14
15
VBUS
USBDP
USBDM
VBUS
D+
D-
GND
RTS#_1
CTS#_1
TXLED_1
USB
CONNECTOR
0.1uF
10 RXLED_1
13 TxEN_1
21 GPIO_17
22 GPIO_18
18
nXRES
VCCD
VBUS
16
11 SUSPEND
12 WAKEUP
TC 1070
Vout Vin
SHDn
Vadj GND
1.8/3.3 V
1 uF
0.1 uF
24 20 17
4
1uF
1M
1 2 3
VBUS
VDDD
3.3 V
562K
1.8 V
2M
4.7 uF
0.1 uF
4.7 uF
0.1 uF
Jumper to select
1.8 V or 3.3 V
Note
6. 1.71 V VDDD 1.89 V - Short VCCD pin with VDDD pin; VDDD > 2 V - connect a 1-µF decoupling capacitor to the VCCD pin.
Document Number: 002-31603 Rev. **
Page 20 of 30
CY7C65223D
To comply with the first requirement, VBUS from the USB host is
connected to the battery charger as well as CY7C65223D as
shown in Figure 6. When VBUS is connected, CY7C65223D
initiates battery charger detection and indicates the type of USB
charger over BCD0 and BCD1. If the USB charger is SDP or
CDP, CY7C65223D enables a 1.5-K pull-up resistor on the
USBDP for Full-Speed enumeration. When VBUS is
disconnected CY7C65223D indicates absence of the USB
charger over BCD0 and BCD1, and removes the 1.5-K pull-up
resistor on USBDP. Removing this resistor ensures no current
flows from the supply to the USB host through the USBDP, to
comply with the USB 2.0 specification.
To comply with the second and third requirements, two signals
(BCD0 and BCD1) are configured over GPIO to communicate
the type of USB host charger and the amount of current it can
draw from the battery charger. The BCD0 and BCD1 signals can
be configured using the configuration utility.
Application Examples
The following section provides CY7C65223D application
examples.
USB-to-Dual UART Bridge with Battery-Charge
Detection
CY7C65223D can connect any embedded system, with a serial
port, to a host PC through USB. CY7C65223D enumerates as a
dual COM port on the host PC.
SUSPEND is connected to the MCU to indicate USB suspend or
USB Unconfigured and the WAKEUP pin is used to wake up
CY7C65223D, which in turn issues a remote wakeup to the USB
host. GPIO1 and GPIO0 are configured as RXLED# and
TXLED# to drive two LEDs indicating data receive and transmit
respectively.
CY7C65223D implements the battery charger detection
functionality based on the USB Battery Charging Specification
Rev 1.2.
Battery-operated bus power systems must comply with the
following conditions:
■ Thesystemcanbe powered from the battery(if notdischarged)
and be operational if VBUS is not connected or powered down.
■ The system should not draw more than 100 mAfrom the VBUS
prior to USB enumeration and USB Suspend mode.
■ The system should not draw more than 500 mA for SDP and
1.5 A for CDP/DCP
Figure 6. USB to Dual UART Bridge with Battery Charge Detection[7, 8]
CY7C65223D
VCC
28
RTS#_0
CTS#
RTS#
29
30
2
CTS#_0
TxD_0
RxD_0
1
RXD
TXD
VDDD
MCU
EN1
EN2
22
21
BCD0
BCD1
SYS
BAT
GPIO_18
GPIO_17
Battery
Charger
(MAX8856)
12
11
I/O
I/O
WAKEUP
SUSPEND
GND
IN
4.7K
4.7K
3
GPIO_9
VBUS
BUSDETECT
VCC
VCC
7
RTSin
19
RTSout
RTS#_1
CTS#_1
TxD_1
OVP
VBUS
D+
1K
1K
14
15
8
RS232
Level
Convertor
USBDP
USBDM
CTSout
TXDin
CTSin
TXDout
RXDin
D-
GND
6
5
0.1 uF
RxD_1
RXDout
USB
CONNECTOR
18
nXRES
VCCD
25
26
TXLED_0
RXLED_0
16
1 uF
24 20 17
4
Notes
7. Add a 100-k pull-down resistor on the V
pin for quick discharge.
BUS
8. Refer Figure 7, Figure 8, Figure 9 and the corresponding descriptions for handling VBUS Over Voltage Protection (OVP).
Document Number: 002-31603 Rev. **
Page 21 of 30
CY7C65223D
In a battery charger system.a 9-V spike on the VBUS is possible. The CY7C65223D VBUS pin is intolerant to voltage above 6 V. In
the absence of over-voltage protection (OVP) on the VBUS line, VBUS should be connected to BUSDETECT (GPIO configured) using
the resistive network and the output of battery charger to the VBUS pin of CY7C65223D, as shown in Figure 7.
Figure 7. GPIO VBUS Detect (BUSDETECT)
B
A
Rs
Rs = 10 K
VBUS
VBUS = VDDD
SYS
BAT
Battery Charger
B
CY7C65223D
B
A
+
-
R1
R2
R1 ≥ 10 kΩ
R2/(R1+R2) = VDDD/VBUS
BUSDETECT
A
GPIO
VBUS > VDDD
VBUS
When VBUS and VDDD are at the same voltage potential, VBUS
can be connected to GPIO using a series resistor (Rs). This is
shown in Figure 8. If there is a charger failure and VBUS
becomes 9 V, then the 10-k resistor plays two roles. It reduces
the amount of current flowing into the forward biased diodes in
the GPIO, and it reduces the voltage seen on the pad.
When VBUS > VDDD, a resistor voltage divider is necessary to
reduce the voltage from VBUS down to VDDD for the GPIO
sensing the VBUS voltage. This is shown in Figure 9. The
resistors should be sized as follows:
R1 > 10 K
R2 / (R1 + R2) = VDDD / VBUS
The first condition limits the voltage and current for the charger
failure situation, as described in the previous paragraph, while
the second condition allows for normal-operation VBUS
detection.
Figure 8. GPIO VBUS Detection, VBUS = VDDD
VDDD
BUSDETECT
CY7C65223D
VBUS
Rs
Figure 9. GPIO VBUS Detection, VBUS > VDDD
VDDD
BUSDETECT
CY7C65223D
VBUS
R1
R2
Document Number: 002-31603 Rev. **
Page 22 of 30
CY7C65223D
In this application, as shown in Figure 10, SUSPEND is
connected to the SHDN# pin of the RS232-level converter to
indicate USB suspend or USB not enumerated.
USB to RS232 Bridge
CY7C65223D can connect any embedded system, with a serial
port, to a host PC through USB. CY7C65223D enumerates as a
COM port on the host PC.
GPIO8 and GPIO9 are configured as RXLED# and TXLED# to
drive two LEDs, indicating data transmit and receive.
The RS232 protocol follows bipolar signaling - that is, the output
signal toggles between negative and positive polarity. The valid
RS232 signal is either in the -3-V to -15-V range or in the +3-V
to +15-V range, and the range between -3 V to +3 V is invalid. In
the RS232, Logic 1 is called “Mark” and it corresponds to a
negative voltage range. Logic 0 is called “Space” and it corre-
sponds to a positive voltage range. The RS232 level converter
facilitates this polarity inversion and the voltage-level translation
between the CY7C65223D’s UART interface and RS232
signaling.
Figure 10. USB to RS232 Bridge
VCC
CY7C65223D
28
29
RTSin
RTS#_0
CTS#_0
RTSout
CTSin
CTSout
RS232
Level
Convertor
30
2
TxD_0
RxD_0
1
TXDin
TXDout
VDDD
1.8/3.3 V
RXDin
RXDout
GND
1
2
3
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
VCC
7
8
RTSin
RTS#_1
CTS#_1
RTSout
CTSin
VDDD
VDDD
CTSout
19
RS232
Level
Convertor
VBUS
VBUS
D+
D-
1K
1K
14
15
6
5
TxD_1
RxD_1
USBDP
USBDM
TXDin
TXDout
GND
RXDin
RXDout
USB
CONNECTOR
GND
18
nXRES
25
26
TXLED_0
RXLED_0
VBUS
TC 1070
1.8/3.3 V
16
Vout
Vin
VCCD
4
SHDn
VBUS
0.1 uF
VDDD
0.1 uF
0.1 uF
1 uF
Vadj GND
24 20 17
1uF
1M
1 2 3
4.7 uF
4.7 uF
3.3 V
562K
1.8 V
2M
Jumper to select
1.8 V or 3.3 V
Document Number: 002-31603 Rev. **
Page 23 of 30
CY7C65223D
RS485 is a multi-drop network – that is, many devices can
communicate with each other over a single two-wire cable
connection. The RS485 cable requires to be terminated at each
end of the cable. Links are provided to allow the cable to be
terminated if the device is physically positioned at either end of
the cable.
USB to RS485 Application
CY7C65223D can be configured as dual USB to UART interface.
This UART interface operates at TTL level and it can be
converted to RS485 interface using a GPIO and any half duplex
RS485 transceiver IC (to convert TTL level to RS485 level) as
shown in Figure 12. This GPIO (TXD Enable) enables and
disables the RS485 transceiver IC based on availability of
character in UART buffer of CY7C65223D. This GPIO can be
configured using USB-Serial Configuration utility. Figure 11
shows timing diagram of this GPIO.
Figure 11. USB-to-RS485 Bridge
CY7C65223D
VCC
30
TxD_0
RxD_0
TXDout
RXDin
RS485
Level
Convertor
TXDin
1
2
RXDout
VDDD
1.8/3.3 V
TXDEN
GND
32
TxEN_0
1
2
3
Jumper to select
1.8 V/3.3 V or 5 V
VDDD
VCC
VDDD
VDDD
19
VBUS
VBUS
D+
D-
GND
1K
1K
14
15
6
5
RS485
Level
Convertor
TxD_1
RxD_1
USBDP
USBDM
TXDout
RXDin
TXDin
RXDout
TXDEN
USB
GND
CONNECTOR
13
18
TxEN_1
nXRES
25
26
TXLED_0
RXLED_0
VBUS
TC 1070
1.8/3.3 V
16
Vout
Vin
VCCD
4
SHDn
0.1 uF
VBUS
VDDD
1 uF
Vadj GND
24 20 17
1uF
1M
1 2 3
4.7 uF
0.1 uF
4.7 uF
0.1 uF
3.3 V
562K
1.8 V
2M
Jumper to select
1.8 V or 3.3 V
Figure 12. RS485 GPIO (TXDEN) Timing Diagram
TXDEN
TXD
MSB
LSB
RXD
MSB
LSB
Document Number: 002-31603 Rev. **
Page 24 of 30
CY7C65223D
Ordering Information
Table 16 lists the CY7C65223D key package features and ordering codes. For more information, contact your local sales
representative.
Table 16. Key Features and Ordering Information
Package
Ordering Code
Operating Range
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free)
CY7C65223D-32LTXI
Industrial
32-pin QFN (5 × 5 × 1 mm, 0.5 mm pitch) (Pb-free)
– Tape and Reel
CY7C65223D-32LTXIT
Industrial
Ordering Code Definitions
CY 7C65
- 32 LTX
I
X
XXXX
X: Blank or T
Blank = Tray; T= Tape and Reel
Temperature Range: I = Industrial; C = Commercial
Package Type: LT = QFN; X = Pb-free
Number of Pins: 32
Part Number XXXX:
223 / 223D: Single/Dual Channel USB UART Bridge Controller with Flow Control
Technology Code: C = CMOS; Family Code: 65 = Full Speed USB-Serial
Company ID: CY = Cypress (An Infineon Technologies Company)
Document Number: 002-31603 Rev. **
Page 25 of 30
CY7C65223D
Package Information
The package currently planned to be supported is the 32-pin QFN.
Figure 13. 32-pin QFN 5 × 5 × 1.0 mm LT32B 3.5 × 3.5 EPAD (Sawn)
001-30999 *D
Table 17. Package Characteristics
Parameter Description
Min
–40
–
Typ
25
Max
85
–
Units
°C
TA
THJ
Operating ambient temperature
Package JA
19
°C/W
Table 18. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
32-pin QFN
260 °C
30 seconds
Table 19. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
32-pin QFN
MSL 3
Document Number: 002-31603 Rev. **
Page 26 of 30
CY7C65223D
Acronyms
Document Conventions
Table 20. Acronyms Used in this Document
Units of Measure
Acronym
BCD
CDC
CDP
DCP
DLL
Description
battery charger detection
Table 21. Units of Measure
Symbol
Unit of Measure
communication driver class
charging downstream port
dedicated charging port
dynamic link library
C
degree Celsius
DMIPS
dhrystone million instructions per second
k
kilo-ohm
KB
kilobyte
ESD
electrostatic discharge
general purpose input/output
human-body model
kHz
kV
kilohertz
GPIO
HBM
MCU
OSC
PHDC
PID
kilovolt
Mbps
MHz
mm
V
megabits per second
megahertz
millimeter
volt
Microcontroller Unit
oscillator
personal health care device class
Product Identification
SCB
serial communication block
Standard Downstream Port
serial interface engine
virtual communication port
Universal Serial Bus
SDP
SIE
VCOM
USB
UART
VID
universal asynchronous receiver transmitter
Vendor Identification
Document Number: 002-31603 Rev. **
Page 27 of 30
CY7C65223D
Errata
This section describes the errata for the CY7C65223D USB-Serial family. Details include errata trigger conditions, scope of impact,
and available workaround.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Device Characteristics
CY7C65223D
All Variants
Qualification Status
Production
Errata Summary
The following table defines the errata applicability to available USB-Serial devices.
Items
Affected Part Number
Fix Status
No Fix
[1.] USB-Serial does not report UART Frame errors.
[2.] USB-Serial does not report MARK or SPACE Parity errors.
CY7C65223D
CY7C65223D
No Fix
1. USB-Serial does not report UART Frame errors.
USB-Serial does not report UART Frame Errors while receiving UART data when the number of stop
bits is set as 1.
Problem Definition
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
USB-Serial fails to report a UART Frame error when the number of stop bits is set as 1. It correctly
reports the error when the stop bits is not 1
No impact
No workaround. In general, applications using UART will have to include checksum or CRC in the data
to ensure frame integrity.
Fix Status
No fix
2. USB-Serial does not report MARK or SPACE Parity errors.
USB-Serial does not report UART Parity error while receiving the data when configured for MARK or
SPACE parity.
Problem Definition
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
USB Serial fails to report UART Parity errors while receiving data when configured for MARK or SPACE
parity. Note that USB-Serial detects parity errors when configured for ODD or EVEN parity settings.
No impact
No workaround. In general, applications using UART will have to include checksum or CRC in the data
to ensure frame integrity.
Fix Status
No fix
Document Number: 002-31603 Rev. **
Page 28 of 30
CY7C65223D
Document History Page
Document Title: CY7C65223D, USB-Dual UART with Flow Control
Document Number: 002-31603
Submission
Revision
ECN
Description of Change
Date
**
6993251
11/25/2020 Final datasheet to NSO.
Document Number: 002-31603 Rev. **
Page 29 of 30
CY7C65223D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
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Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
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Technical Support
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cypress.com/support
Microcontrollers
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cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware
included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all
rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the
Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-31603 Rev. **
Revised November 25, 2020
Page 30 of 30
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