CY7C65642-48AXCT [INFINEON]
4 port Multi-TT hub (configurable with GPIOs, , LED indicator and EEPROM) with 48-pin TQFP - Tape and reel, C-grade;
| 型号： | CY7C65642-48AXCT |
| 厂家： | 
Infineon |
| 描述： | 4 port Multi-TT hub (configurable with GPIOs, , LED indicator and EEPROM) with 48-pin TQFP - Tape and reel, C-grade 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 外围集成电路 |
| 文件： | 总40页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C65642
HX2VL - Very Low-Power USB 2.0 TetraHub
Controller
Features
• High-performance, low-power USB 2.0 hub, optimized for low-cost designs with minimum bill-of-material
(BOM).
• USB 2.0 hub controller
- Compliant with USB2.0 specification, TID# 30000059
- Up to four downstream ports support
- Downstream ports are backward compatible with FS, LS
- Multiple translator (TT), one per downstream port for maximum performance.
• Very low-power consumption
- Supports bus-powered and self-powered modes
- Auto switching between bus-powered and self-powered
- Single MCU with 2 K ROM and 64 byte RAM
- Lowest power consumption.
• Highly integrated solution for reduced BOM cost
- Internal regulator – single power supply 5 V required.
- Provision of connecting 3.3 V with external regulator.
- Integrated upstream pull-up resistor
- Integrated pull-down resistors for all downstream ports
- Integrated upstream/downstream termination resistors
- Integrated port status indicator control
- 12-MHz +/-500 ppm external crystal with drive level 600 W (integrated PLL) clock input with optional
27/48-MHz oscillator clock input.
- Internal power failure detection for ESD recovery
• Downstream port management
- Support individual and ganged mode power management
- Overcurrent detection
- Two status indicators per downstream port
• Maximum configurability
- VID and PID are configurable through external EEPROM
- Number of ports, removable/non-removable ports are configurable through EEPROM and I/O pin
configuration
- I/O pins can configure gang/individual mode power switching, reference clock source and polarity of power
switch enable pin
- Configuration options also available through mask ROM
• Available in space saving 48-pin TQFP (7 × 7 mm) and 28-pin QFN (5 × 5 mm) packages
• Supports 0°C to +70°C temperature range
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
001-65659 Rev. *M
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Block diagram
Block diagram
I2C /
SPI
MCU
D+
D-
RAM ROM
12/27/48
MHz
OSC-in
OR 12
MHz
USB 2.0 PHY
PLL
Serial
Interface
Engine
HS USB
Control Logic
USB Upstream Port
Crystal
5 V i/p (for internal
regulator)
NC (for external regulator)
Transaction Translator x 4
1.8 V
3.3 V
Regulator
Hub Repeater
3.3 V i/p (with ext. reg. & 28-QFN
NC (with ext. reg. & 48-TQFP)
3.3 V o/p (for int. reg.)
Routing Logic
USB Downstream Port 1
USB Downstream Port 2
USB Downstream Port 3
USB Downstream Port 4
USB 2.0
PHY
Port
Control
USB 2.0
PHY
Port
Control
USB 2.0
PHY
Port
Control
USB 2.0
PHY
Port
Control
LED
LED
LED
LED
D+ D-
D+ D-
D+ D-
D+ D-
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Table of contents
Table of contents
Features ...........................................................................................................................................1
Block diagram...................................................................................................................................2
Table of contents...............................................................................................................................3
1 More information............................................................................................................................5
1.1 HX2VL Development Kit..........................................................................................................................................5
2 Introduction...................................................................................................................................6
3 HX2VL architecture .........................................................................................................................7
3.1 USB serial interface engine ....................................................................................................................................7
3.2 HS USB control logic...............................................................................................................................................7
3.3 Hub repeater ...........................................................................................................................................................7
3.4 MCU..........................................................................................................................................................................7
3.5 Transaction translator............................................................................................................................................7
3.6 Port control .............................................................................................................................................................7
4 Applications ...................................................................................................................................8
5 Functional overview .......................................................................................................................9
5.1 System initialization ...............................................................................................................................................9
5.2 Enumeration ...........................................................................................................................................................9
5.3 Multiple transaction translator support ................................................................................................................9
5.4 Upstream port.........................................................................................................................................................9
5.5 Downstream ports ................................................................................................................................................10
5.6 Power switching....................................................................................................................................................10
5.7 Overcurrent detection ..........................................................................................................................................10
5.8 Port indicators ......................................................................................................................................................11
5.9 Power regulator ....................................................................................................................................................11
5.10 External regulation scheme ...............................................................................................................................11
5.11 Internal regulation scheme ................................................................................................................................12
6 Pin configurations ........................................................................................................................13
7 Pin definitions ..............................................................................................................................15
8 Pin definitions ..............................................................................................................................18
9 EEPROM configuration options ......................................................................................................20
10 Pin configuration options ............................................................................................................23
10.1 Power on reset ....................................................................................................................................................23
10.2 Gang/individual power switching mode............................................................................................................23
10.3 Power switch enable pin polarity.......................................................................................................................24
10.4 Port number configuration.................................................................................................................................24
10.5 Non removable ports configuration ..................................................................................................................24
10.6 Reference clock configuration ...........................................................................................................................24
11 Absolute maximum ratings ..........................................................................................................25
12 Operating conditions...................................................................................................................26
13 Electrical characteristics .............................................................................................................27
13.1 DC electrical characteristics...............................................................................................................................27
13.2 AC electrical characteristics ...............................................................................................................................29
14 Thermal resistance......................................................................................................................30
15 Ordering information ..................................................................................................................31
15.1 Ordering code definitions...................................................................................................................................31
16 Package diagrams.......................................................................................................................32
17 Acronyms ...................................................................................................................................34
18 Document conventions................................................................................................................35
18.1 Units of measure .................................................................................................................................................35
Datasheet
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Table of contents
19 Silicon Errata for the HX2VL, CY7C65642 product family.................................................................36
19.1 Part numbers affected........................................................................................................................................36
19.2 HX2VL Qualification status .................................................................................................................................36
19.3 HX2VL Errata summary.......................................................................................................................................36
Revision history ..............................................................................................................................37
Datasheet
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More information
1
More information
Infineon provides a wealth of data at www.infineon.com to help you to select the right HX2VL device for your
design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list
of resources, see the HX2VL product page.
• Overview: USB portfolio
• USB 2.0 Hub Controller selectors: HX2LP, HX2VL
• Application notes: Infineon offers a large number of USB application notes covering a broad range of topics,
from basic to advanced level. Recommended application notes for getting started with HX2VL are:
- AN72332 - Guidelines on System Design using Infineon’s USB 2.0 Hub (HX2VL)
- AN69235 - Migrating from HX2/HX2LP to HX2VL
• Reference designs:
- CY4608 HX2VL Very Low-Power USB 2.0 Compliant 4-Port Hub Development Kit
- CY4607 HX2VL Very Low-Power USB 2.0 Compliant 4-Port Hub Development Kit
• Models: HX2VL (CY7C65632/34/42) - IBIS
1.1
HX2VL Development Kit
HX2VL Development Kit board is a tool to demonstrate the features of HX2VL devices (CY7C65632, CY7C65634).
In the initial phase of the design, this board helps developers to understand the chip features and limitations
before proceeding with a complete design. The Development kit includes support documents related to board
hardware, PC application software, and EEPROM configuration data (.iic) files.
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Introduction
2
Introduction
HX2VL is Infineon’s next generation family of high-performance, very low-power USB 2.0 hub controllers. HX2VL
has integrated upstream and downstream transceivers; a USB serial interface engine (SIE); USB hub control and
repeater logic; and transaction translator (TT) logic. Infineon has also integrated external components such as
voltage regulator and pull-up/pull-down resistors, reducing the overall BOM required to implement a USB hub
system.
The CY7C65642 is a part of the HX2VL portfolio with four downstream ports and an independent TT dedicated for
each downstream port. This device option is for low-power but high-performance applications that require up to
four downstream ports. The CY7C65642 is available in 48-pin TQFP and 28-pin QFN package options.
All device options are supported by Infineon’s world class reference design kits, which include board schematics,
BOM, Gerber files, Orcad files, and thorough design documentation.
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HX2VL architecture
3
HX2VL architecture
The “Block diagram” on page 2 shows the HX2VL TetraHub™ architecture.
3.1
USB serial interface engine
The SIE allows HX2VL to communicate with the USB host. The SIE handles the following USB activities
independently of the hub control block.
• Bit stuffing and unstuffing
• Checksum generation and checking
• TOKEN type identification
• Address checking
3.2
HS USB control logic
‘Hub Control’ block co-ordinates enumeration, suspend and resume. It generates status and control signals for
host access to the hub. It also includes the frame timer that synchronizes the hub to the host. It has status/control
registers which function as the interface to the firmware in the MCU.
3.3
Hub repeater
The hub repeater manages the connectivity between upstream and downstream facing ports that are operating
at the same speed. It supports full and high-speed connectivity. According to the USB 2.0 specification, the hub
repeater provides the following functions:
• Sets up and tears down connectivity on packet boundaries
• Ensures orderly entry into and out of ‘Suspend’ state, including proper handling of remote wakeups.
3.4
MCU
The HX2VL has MCU with 2K ROM and 64 byte RAM. The MCU operates with a 12 MHz clock to decode USB
commands from host and respond to the host. It can also handle GPIO settings to provide higher flexibility to the
customers and control the read interface to the EEPROM which has extended configuration options.
3.5
Transaction translator
The TT translates data from one speed to another. A TT takes high-speed split transactions and translates them
to full or low-speed transactions when the hub is operating at high-speed (the upstream port is connected to a
high speed host controller) and has full or low-speed devices attached. The operating speed of a device attached
on a downstream port determines whether the routing logic connects a port to the TT or to hub repeater. When
the upstream host and downstream device are functioning at different speeds, the data is routed through the TT.
In all other cases, the data is routed through the repeater. For example, If a full or low-speed device is connected
to the high-speed host upstream through the hub, then the data transfer route includes TT. If a high-speed device
is connected to the high-speed host upstream through the hub, the transfer route includes the repeater. When
the hub is connected to a full-speed host controller upstream, then high-speed peripheral does not operate at its
full capability. These devices only work at full speed. Full and low-speed devices connected to this hub operate
at their normal speed.
3.6
Port control
The downstream ‘Port Control’ block handles the connect/disconnect and over current detection as well as the
power enable and LED control. It also generates the control signals for the downstream transceivers.
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Applications
4
Applications
Typical applications for the HX2VL device family are:
• Docking stations
• Standalone hubs
• Monitor hubs
• Multi-function printers
• Digital televisions
• Advanced port replicators
• Keyboard hubs
• Gaming consoles
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Functional overview
5
Functional overview
The Infineon CY7C65642 USB 2.0 Hubs are low-power hub solutions for USB which provide maximum transfer
efficiency with no TT multiplexing between downstream ports. The CY7C65642 USB 2.0 Hubs integrate 1.5 k
upstream pull-up resistors for full speed operation and all downstream 15 k pull-down resistors and series
termination resistors on all upstream and downstream D+ and D– pins. This results in optimization of system
costs by providing built-in support for the USB 2.0 specification.
5.1
System initialization
On power up, CY7C65642 has an option to enumerate from the default settings in the mask ROM or from reading
an external EEPROM for configuration information. At the most basic level, this EEPROM has the Vendor ID (VID)
and the Product ID (PID), for the customer’s application. For more specialized applications, other configuration
options can be specified. See “EEPROM configuration options” on page 20 for more details. CY7C65642 verifies
the checksum before loading the EEPROM contents as the descriptors.
5.2
Enumeration
CY7C65642 enables the pull-up resistor on D+ to indicate its presence to the upstream hub, after which a USB Bus
Reset is expected. After a USB Bus Reset, CY7C65642 is in an unaddressed, unconfigured state (configuration
value set to ‘0’). During the enumeration process, the host sets the hub's address and configuration. After the hub
is configured, the full hub functionality is available.
5.3
Multiple transaction translator support
After TetraHub is configured in a high speed system, it is in single TT mode. The host may then set the hub into
multiple TT mode by sending a SetInterface command. In multiple TT mode, each full speed port is handled
independently and thus has a full 12 Mbps bandwidth available. In Single TT mode, all traffic from the host
destined for full or low-speed ports are forwarded to all of those ports. This means that the 12 Mbps bandwidth
is shared by all full and low-speed ports.
5.4
Upstream port
The upstream port includes the transmitter and the receiver state machine. The transmitter and receiver operate
in high speed and full speed depending on the current hub configuration. The transmitter state machine
monitors the upstream facing port while the Hub Repeater has connectivity in the upstream direction. This
machine prevents babble and disconnect events on the downstream facing ports of this hub from propagating
and causing the hub to be disabled or disconnected by the hub to which it is attached.
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Functional overview
5.5
Downstream ports
The CY7C65642 supports a maximum of four downstream ports, each of which may be marked as usable or
removable in the EEPROM configuration, see “EEPROM configuration options” on page 20. Additionally, it can
also be configured by pin strapping, see “Pin configuration options” on page 23.
Downstream D+ and D– pull-down resistors are incorporated in CY7C65642 for each port. Before the hubs are
configured, the ports are driven Single Ended Zero, ((SE0) where both D+ and D– are driven low) and are set to
the unpowered state. When the hub is configured, the ports are not driven and the host may power the ports by
sending a SetPortPower command for each port. After a port is powered, any connect or disconnect event is
detected by the hub. Any change in the port state is reported by the hubs back to the host through the Status
Change Endpoint (endpoint 1). On receipt of SetPortReset request for a port with a device connected, the hub
does as follows:
• Performs a USB Reset on the corresponding port
• Puts the port in an enabled state
• Enables babble detection after the port is enabled.
Babble consists of a non idle condition on the port after EOF2. If babble is detected on an enabled port, that port
is disabled. A ClearPortEnable request from the host also disables the specified port.
Downstream ports can be individually suspended by the host with the SetPortSuspend request. If the hub is not
suspended, a remote wakeup event on that port is reflected to the host through a port change indication in the
Hub Status Change Endpoint. If the hub is suspended, a remote wakeup event on this port is forwarded to the
host. The host may resume the port by sending a ClearPortSuspend command.
5.6
Power switching
The CY7C65642 includes interface signals for external port power switches. Both ganged and individual (per-port)
configurations are supported by pin strapping, see “Pin configuration options” on page 23.
After enumerating, the host may power each port by sending a SetPortPower request for that port. Power
switching and overcurrent detection are managed using respective control signals (PWR#[n] and OVR#[n]) which
are connected to an external power switch device. Both High/Low enabled power switches are supported and
the polarity is configured through GPIO setting, see “Pin configuration options” on page 23.
5.7
Overcurrent detection
The OVR#[n] pins of the CY7C65642 series are connected to the respective external power switch’s port
overcurrent indication (output) signals. After detecting an overcurrent condition, hub reports overcurrent
condition to the host and disables the PWR#[n] output to the external power device. OVR#[n] has a setup time of
20 ns. It takes 3 to 4 ms from overcurrent detection to deassertion of PWR#[n].
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Functional overview
5.8
Port indicators
The USB 2.0 port indicators are also supported directly by CY7C65642. According to the specification, each
downstream port of the hub optionally supports a status indicator. The presence of indicators for downstream
facing ports is specified by bit 7 of the wHubCharacteristics field of the hub class descriptor. The default
CY7C65642 descriptor specifies that the port indicators are supported. The CY7C65642 port indicators has two
modes of operation: automatic and manual.
On power up the CY7C65642 defaults to automatic mode, where the color of the Port Indicator (green, amber, off)
indicates the functional status of the CY7C65642 port. The LEDs are turned off when the device is suspended.
Port Status
Indicator
LED
Figure 1
Port status indicator LED
5.9
Power regulator
CY7C65642 requires 3.3 V source power for normal operation of internal core logic and USB physical layer (PHY).
The integrated low-drop power regulator converts 5 V power input from USB cable (Vbus) to 3.3 V source power.
The 3.3 V power output is guaranteed by an internal voltage reference circuit when the input voltage is within the
4 V–5.5 V range. The regulator’s maximum current loading is 150 mA, which provides tolerance margin over
CY7C65642’s normal power consumption of below 100 mA. The on chip regulator has a quiescent current of 28 µA.
5.10
External regulation scheme
CY7C65642 supports both external regulation and internal regulation schemes. When an external regulation is
chosen, then for the 48-pin package, VCC and VREG are to be left open with no connection. The external regulator
output 3.3 V has to be connected to VCC_A and VCC_D pins. This connection has to be done externally, on board.
For the 28-pin package, the 3.3 V output from the external regulator has to be connected to VREG, VCC_A and
VCC_D. The VCC pin has to be left open with no connection. From the external input 3.3 V, 1.8 V is internally
generated for the chip’s internal usage.
5 V to 3.3 V
Regulator
5 V to 3.3 V
Regulator
NC
NC
NC
VCC
VREG
VREG
VCC
CY7C65642
48 Pin
CY7C65642
28 Pin
VCC_D
VCC_A
VCC_D
VCC_A
External Regulation Scheme
Figure 2
External regulation scheme
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Functional overview
5.11
Internal regulation scheme
When the built-in internal regulator is chosen, then the VCC pin has to be connected to a 5 V, in both 48-pin and
28-pin packages. Internally, the built-in regulator generates a 3.3 V and 1.8 V for the chip’s internal usage. Also a
3.3 V output is available at VREG pin, that has to be connected externally to VCC_A and VCC_D.
5 V
3.3 V
5 V
3.3 V
VCC
VREG
VREG
VCC
CY7C65642
48 Pin
CY7C65642
28 Pin
VCC_D
VCC_A
VCC_D
VCC_A
Internal Regulation Scheme
Figure 3
Internal regulation scheme
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Pin configurations
6
Pin configurations
AMBER[2] / SPI_MOSI /
PWR_PIN_POL
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
VCC_A
GND
GREEN[2] /
SPI_MISO /
FIXED_PORT2
VCC_D
D-
AMBER[3] /
SET_PORT_NUM2
D+
CY7C65642
48-pin TQFP
GREEN[3] /
FIXED_PORT3
DD-[1]
DD+[1]
VCC_A
GND
5
PWR#[3]
7
8
OVR#[3]
PWR#[4]
9
OVR#[4]
DD-[2]
DD+[2]
RREF
VCC_A
10
11
12
TEST / I2C_SCL
26
25
RESET#
SEL48
Figure 4
48-pin TQFP (7 × 7 × 1.4 mm) pinout
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Pin configurations
D -
D +
1
2
3
2 1
2 0
V C C _ D
O VR # [3]
O VR # [4]
TEST/I2C_SCL
D D - [1]
1 9
1 8
1 7
CY7C65642
4
5
D D + [1]
V C C _ A
28-pin QFN
R E S E T #
D D - [2]
D D + [2]
6
7
D D + [4]
D D - [4]
1 6
1 5
Figure 5
28-pin QFN (5 × 5 × 0.8 mm) pinout
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Pin definitions
7
Pin definitions
Table 1
Pin definitions
48-pin TQFP package
Pin name
Power and Clock
VCC_A
Pin No. Type [1]
Description
1
P
P
P
P
P
P
P
P
P
V
V
V
V
V
V
V
V
V
CC_A. 3.3 V analog power to the chip.
CC_A. 3.3 V analog power to the chip.
CC_A. 3.3 V analog power to the chip.
CC_A. 3.3 V analog power to the chip.
CC_A. 3.3 V analog power to the chip.
CC_D. 3.3 V digital power to the chip.
CC_D. 3.3 V digital power to the chip.
CC. 5 V input to the internal regulator; NC if using external regulator
REG. 5 V–3.3 V regulator o/p during internal regulation; NC if using
VCC_A
VCC_A
VCC_A
VCC_A
VCC_D
VCC_D
VCC
VREG
7
12
16
19
34
38
47
48
external regulator.
GND
GND
GND
GND
XIN
2
8
13
20
14
P
P
P
P
I
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
GND. Connect to ground with as short a path as possible.
12-MHz crystal clock input, or 12/27/48 MHz clock input
12-MHz Crystal OUT. (NC if external clock is used).
XOUT
SEL48 / SEL27
15
25 / 44
O
I
Clock source selection inputs.
00: Reserved
01: 48-MHz OSC-in
10: 27-MHz OSC-in
11: 12-MHz Crystal or OSC-in
RESET#
SELFPWR
GANG
26
37
39
I
I
Active LOW Reset. External reset input, default pull high 10 k;
When RESET = low, whole chip is reset to the initial state
Self Power. Input for selecting self/bus power. 0 is bus powered, 1
is self powered.
GANG. Default is input mode after power-on-reset.
Gang Mode: Input:1 -> Output is 0 for normal operation and 1 for
suspend
Individual Mode: Input:0 -> Output is 1 for normal operation and 0
for suspend
Refer to gang / individual power switching modes in “Pin
configuration options” on page 23 for details.
I/O
RREF
11
I/O
649 resistor must be connected between RREF and Ground.
System Interface
Notes
1. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down
Resistor, RUP = Pad internal Pull Up Resistor.
2. Pin-strapping GREEN[1] and GREEN[2] enables proprietary function that may affect the normal functionality
of HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided.
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Pin definitions
Table 1
Pin definitions (continued)
48-pin TQFP package
Pin name
Pin No. Type [1]
Description
Test
27
I(RDN
)
Test. 0: Normal Operation and 1: Chip will be put in test mode.
I2C_SCL
I/O(RDN)
I2C_SCL. Can be used as I2C clock pin to access I2C EEPROM.
Upstream Port
D–
D+
3
4
I/O/Z
I/O/Z
Upstream D– Signal.
Upstream D+ Signal.
Downstream Port 1
DD–[1]
5
6
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
DD+[1]
AMBER[1]
SPI_CS
46
O(RDN
O(RDN
O(RDN
O(RDN
I(RDN)
)
)
)
)
LED. Driver output for amber LED. port indicator support.
SPI_CS. Can be used as chip select to access external SPI EEPROM.
GREEN[1] [2]
SPI_SK
45
LED. Driver output for green LED. Port indicator support.
SPI_SK. Can be used as SPI Clock to access external SPI EEPROM.
FIXED_PORT1. At POR used to set Port1 as non removable port.
Refer “Pin configuration options” on page 23.
FIXED_PORT1
OVR#[1]
42
43
I(RUP
)
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input.
PWR#[1]
I2C_SDA
O/Z
I/O
Power Switch Driver Output. Default is Active LOW.
I2C_SDA. Can be used as I2C Data pin, connected with I2C EEPROM.
Downstream Port 2
DD–[2]
9
10
36
I/O/Z
I/O/Z
O(RDN
O(RDN
I(RDN)
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port Indicator Support.
SPI_MOSI. Can be used as Data Out to access external SPI EEPROM.
PWR_PIN_POL. Used for power switch enable pin polarity setting.
Refer “Pin configuration options” on page 23.
LED. Driver output for Green LED. Port Indicator Support.
SPI_MISO. Can be used as Data In to access external SPI EEPROM.
FIXED_PORT2. At POR used to set Port2 as non removable port.
Refer “Pin configuration options” on page 23.
DD+[2]
AMBER[2]
SPI_MOSI
PWR_PIN_POL
)
)
GREEN[2] [2]
SPI_MISO
FIXED_PORT2
35
O(RDN
)
I(RDN
I(RDN
)
)
OVR#[2]
40
41
I(RUP
O/Z
)
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input.
PWR#[2]
Downstream Port 3
DD–[3]
DD+[3]
AMBER[3]
SET_PORT_NUM2
Power Switch Driver Output. Default is Active LOW
17
18
33
I/O/Z
I/O/Z
O(RDN
I(RDN)
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port indicator support.
SET_PORT_NUM2. Used to set port numbering along with
SET_PORT_NUM1. Refer “Pin configuration options” on page 23.
)
Notes
1. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down
Resistor, RUP = Pad internal Pull Up Resistor.
2. Pin-strapping GREEN[1] and GREEN[2] enables proprietary function that may affect the normal functionality
of HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided.
Datasheet
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Pin definitions
Table 1
Pin definitions (continued)
48-pin TQFP package
Pin name
Pin No. Type [1]
Description
GREEN[3]
FIXED_PORT3
32
O(RDN
I(RDN
)
LED. Driver output for Green LED. Port indicator support.
FIXED_PORT3. At POR used to set Port3 as non removable port.
Refer “Pin configuration options” on page 23.
)
OVR#[3]
30
31
I(RUP
O/Z
)
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input.
PWR#[3]
Downstream Port 4
DD–[4]
DD+[4]
AMBER[4]
SET_PORT_NUM1
Power Switch Driver Output. Default is Active LOW.
21
22
24
I/O/Z
I/O/Z
O(RDN
I(RDN
Downstream D– Signal.
Downstream D+ Signal.
LED. Driver output for Amber LED. Port Indicator Support.
SET_PORT_NUM1. Used to set port numbering along with
SET_PORT_NUM2. Refer “Pin configuration options” on page 23
LED. Driver output for Green LED. Port Indicator Support.
FIXED_PORT4. At POR used to set Port4 as non removable port.
Refer Pin configuration options on page 23.
)
)
)
GREEN[4]
FIXED_PORT4
23
O(RDN
I(RDN)
OVR#[4]
PWR#[4]
28
29
I(RUP
O/Z
)
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input.
Power Switch Driver Output. Default is Active LOW.
Note: The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high,
unless a separate circuit is designed to support logic high. Disconnect after 60 ms of power-on reset (POR), when
these pins are reconfigured as outputs.
Notes
1. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down
Resistor, RUP = Pad internal Pull Up Resistor.
2. Pin-strapping GREEN[1] and GREEN[2] enables proprietary function that may affect the normal functionality
of HX2VL. Configuring Port #1 and #2 as non-removable by pin-strapping should be avoided.
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Pin definitions
8
Pin definitions
Table 2
Pin definitions
28-pin QFN package
Pin name
Power and Clock
VCC_A
Pin No. Type[3]
Description
5
P
P
P
P
P
V
V
V
V
V
CC_A. 3.3 V analog power to the chip.
CC_A. 3.3 V analog power to the chip.
CC_A. 3.3 V analog power to the chip.
CC_D. 3.3 V digital power to the chip.
VCC_A
VCC_A
VCC_D
VCC
9
14
21
27
CC. 5 V input to the internal regulator; NC if using external regulator
VCC. 5 V–3.3 V regulator o/p during internal regulation; 3.3 V i/p if
using external regulator.
VREG
28
P
XIN
XOUT
10
11
I
O
12-MHz crystal clock input, or 12-MHz clock input
12-MHz Crystal OUT. (NC if external clock is used).
Active LOW Reset. External reset input, default pull high 10k Ohm;
RESET#
17
22
I
I
When RESET = low, whole chip is reset to the initial state
Self Power. Input for selecting self/bus power. 0 is bus powered, 1
is self powered.
SELFPWR
GANG Default is input mode after power-on-reset.
Gang Mode: Input:1 -> Output is 0 for normal operation and 1 for
suspend
GANG
23
8
I/O
Individual Mode: Input:0 -> Output is 1 for normal operation and 0
for suspend
Refer to gang / individual power switching modes in “Pin
configuration options” on page 23 for details.
649- resistor must be connected between RREF and Ground
RREF
I/O
System Interface
Test
O(RDN
)
Test. 0: Normal Operation & 1: Chip will be put in test mode
I2C_SCL. I2C Clock pin.
18
26
I2C_SCL
I/O(RDN
)
PWR# [4]
I2C_SDA
Power switch driver output. Default is active low
I/O
I2C_SDA. I2C Data pin.
Upstream Port
D–
D+
1
2
I/O/Z
I/O/Z
Upstream D– Signal.
Upstream D+ Signal.
Notes
3. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down
Resistor, RUP = Pad internal Pull Up Resistor.
4. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin
will act as I2C_SDA, it will not switch to PWR# mode (as it does in 48-pin TQFP package).
Datasheet
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Pin definitions
Table 2
Pin definitions (continued)
28-pin QFN package
Pin name
Pin No. Type[3]
Description
Downstream Port 1
DD–[1]
3
4
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
DD+[1]
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input. Only OVR#[1](pin 25) is enabled in Gang
mode. OVR#[2](pin 24), OVR#[3](pin 20) and OVR#[4](pin 19) are
disabled in Gang mode.
OVR#[1]
25
I(RUP)
Downstream Port 2
DD–[2]
6
7
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
DD+[2]
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input. Only OVR#[1](pin 25) is enabled in Gang
mode. This (OVR#[2]) pin is disabled in Gang mode.
OVR#[2]
24
I(RUP)
Downstream Port 3
DD–[3]
12
13
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
DD+[3]
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input. Only OVR#[1](pin 25) is enabled in Gang
mode. This (OVR#[3]) pin is disabled in Gang mode.
OVR#[3]
20
I(RUP)
Downstream Port 4
DD–[4]
15
16
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
DD+[4]
Overcurrent Condition Detection Input. Active LOW Overcurrent
Condition Detection Input. Only OVR#[1](pin 25) is enabled in Gang
mode. This (OVR#[4]) pin is disabled in Gang mode.
Ground pin for the chip. It is the solderable exposed pad beneath
the chip. Refer to the Figure 9.
OVR#[4]
GND
19
I(RUP
P
)
PAD
Notes
3. Pin Types: I = Input, O = Output, P = Power/Ground, Z = High Impedance, RDN = Pad internal Pull Down
Resistor, RUP = Pad internal Pull Up Resistor.
4. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin
will act as I2C_SDA, it will not switch to PWR# mode (as it does in 48-pin TQFP package).
Datasheet
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EEPROM configuration options
9
EEPROM configuration options
Systems using CY7C65642 have the option of using the default descriptors to configure the hub. Otherwise, it
must have an external EEPROM for the device to have a unique VID, and PID. The CY7C65642 can communicate
with an SPI (microwire) EEPROM like 93C46 or I2C EEPROM like 24C02. Example EEPROM connections are shown
as follows:
SPI EEPROM Connection
VDD
AM BER[1]
GREEN[1]
AM BER[2]
GREEN[2]
CS
SK
DI
VCC
NC1
NC2
GND
DO
AT93C46
I2C EEPROM Connection
VDD
A0
VCC
W P
A1
TEST
PW R#[1]
A2
SCL
SDA
GND
AT24C02
Figure 6
Example EEPROM connections
Note The 28-pin QFN package includes only support for I2C EEPROM like ATMEL/24C02N_SU27 D,
MICROCHIP/4LC028 SN0509, SEIKO/S24CS02AVH9. The 48-pin TQFP package includes both I2C and SPI EEPROM
connectivity options. In this case, user can use either SPI or I2C connectivity at a time for communicating to
EEPROM. The 48-pin package supports ATMEL/AT93C46DN-SH-T, in addition to the above mentioned families.
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
EEPROM configuration options
HX2VL can only read from SPI EEPROM. So field programming of EEPROM will be supported only for I2C EEPROM.
The default VID and PID are 0x04B4 and 0x6572.
CY7C65642 verifies the check sum after power on reset and if validated loads the configuration from the EEPROM.
To prevent this configuration from being overwritten, AMBER[1] is disabled when the SPI EEPROM is present.
Table 3
Byte
00h
Details
VID_LSB
Value
01h
VID_MSB
02h
PID_LSB
03h
PID_MSB
04h
ChkSum
05h
06h
07h
08h
Reserved–FEh
Removable ports
Port number
Maximum power
09h–0Fh Reserved–FFh
10h Vendor string length
11h–3Fh Vendor string (ASCII code)
40h Product string length
41h–6Fh Product string (ASCII code)
70 h Serial number length
71h–80h Serial number string
Byte 0: VID (LSB)
Least Significant Byte of Vendor ID
Byte 1: VID (MSB)
Most Significant Byte of Vendor ID
Byte 2: PID (LSB)
Least Significant Byte of Product ID
Byte 3: PID (MSB)]
Most Significant Byte of Product ID
Byte 4: ChkSum
CY7C65642 will ignore the EEPROM settings if ChkSum is not equal to
VID_LSB + VID_MSB + PID_LSB + PID_MSB +1
Byte 5: Reserved
Set to FEh
Byte 6: RemovablePorts
RemovablePorts[4:1] are the bits that indicate whether the device attached to the corresponding downstream
port is removable (set to 0) or non-removable (set to 1). Bit 1 corresponds to Port 1, Bit 2 to Port 2 and so on.
Default value is 0 (removable). These bit values are reported appropriately in the
HubDescriptor:DeviceRemovable field.
Bits 0, 5, 6, 7 are set to 0.
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
EEPROM configuration options
Byte 7: Port Number
Port Number indicates the number of downstream ports. The values must be 1 to 4. Default value is 4.
Byte 8: Maximum Power
This value is reported in the Configuration Descriptor: bMax-Power field and is the current in 2 mA increments
that is required from the upstream hubs. The allowed range is 00h (0mA) to FAh(500mA). Default value is 32h
(100mA)
Byte 9–15: Reserved
Set to FFh (except 11 which is FEh)
Byte 16: Vendor String Length
Length of the Vendor String
Byte 17–63: Vendor String
Value of Vendor String in ASCII code.
Byte 64: Product String Length
Length of the Product String
Byte 65–111: Product String
Value of Product String in ASCII code
Byte 112: Serial Number Length
Length of the Serial Number
Byte 113 onwards: Serial Number String
Serial Number String in ASCII code.
Datasheet
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Pin configuration options
10
Pin configuration options
10.1
Power on reset
The power on reset can be triggered by external reset or internal circuitry. The internal reset is initiated, when
there is an unstable power event for silicon’s internal core power (3.3 V ± 10%). The internal reset is released
2.7 µs ± 1.2% after supply reaches power good voltage (2.5 V to 2.8 V). The external reset pin, continuously senses
the voltage level (5 V) on the upstream VBUS as shown in the figure. In the event of USB plug/unplug or drop in
voltage, the external reset is triggered. This reset trigger can be configured using the resistors R1 and R2. Infineon
recommends that the reset time applied in external reset circuit should be longer than that of the internal reset
time.
PCB
Silicon
VBUS
(External 5V)
Ext. VBUS power-good
detection circuit input
(Pin"RESET#")
R1
R2
EXT
Global
Reset#
INT
Int. 3.3V power-good
detection circuit input
(USB PHY reset)
Figure 7
Power on reset
10.2
Gang/individual power switching mode
A single pin is used to set individual / gang mode as well as output the suspend flag. This is done to reduce the
pin count. The individual or gang mode is decided within 20 µs after power on reset. It has a setup time of 1 ns.
50 ms to 60 ms after reset, this pin is changed to output mode. CY7C65642 outputs the suspend flag, once it is
globally suspended. Pull-down resistor of greater than 100K is needed for Individual mode and a pull-up resistor
greater than 100K is needed for Gang mode. Figure below shows the suspend LED indicator schematics. The
polarity of LED must be followed, otherwise the suspend current will be over the spec limitation (2.5 mA).
VDD (3.3V)
VDD (3.3V)
100K
PCB
Silicon
GANG MODE
GANG/SUSPEND
SUSPEND OUT
SUSPEND
INDICATOR
100K
0 : INDIVIDUAL MODE
1: GANG MODE
INDIVIDUAL MODE
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Pin configuration options
Table 4
Features supported in 48-pin and 28-pin packages
Supported features
48-pin
Yes
Yes
Yes
Yes
28-pin
No
No
No
No
Port number configuration
Non-removable port configuration
Reference clock configuration
Power switch enable polarity
LED Indicator
Yes
No
10.3
Power switch enable pin polarity
The pin polarity is set active-high by pin-strapping the PWR_PIN_POL pin to 1 and Active-Low by pin-strapping
the PWR_PIN_POL pin to 0. Thus, both kinds of power switches are supported. This feature is not supported in
28-pin QFN package.
10.4
Port number configuration
In addition to the EEPROM configuration, as described above, configuring the hub for 2/3/4 ports is also
supported using pin-strapping SET_PORT_NUM1 and SET_PORT_NUM2, as shown in following table.Pin
strapping option is not supported in the 28-pin QFN package.
Table 5
Port number configuration
SET_PORT_NUM2
SET_PORT_NUM1
# Ports
1 (Port 1)
2 (Port 1/2)
3 (Port 1/2/3)
4 (All ports)
1
1
0
0
1
0
1
0
10.5
Non removable ports configuration
In embedded systems, downstream ports that are always connected inside the system, can be set as
non-removable (always connected) ports, by pin-strapping the corresponding FIXED_PORT# pins 1~4 to High,
before power on reset. At POR, if the pin is pull high, the corresponding port is set to non-removable. This is not
supported in the 28-pin QFN package.
10.6
Reference clock configuration
This hub can support, optional 27/48-MHz clock source. When on-board 27/48-MHz clock is present, then using
this feature, system integrator can further reduce the BOM cost by eliminating the external crystal. This is
available through GPIO pin configuration shown below. This is not supported in the 28-pin QFN package.
Table 6
Reference clock configuration
SEL27 Clock source
48-MHz OSC-in
SEL48
0
1
1
1
0
1
27-MHz OSC-in
12-MHz X’tal/OSC-in
Datasheet
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Absolute maximum ratings
11
Absolute maximum ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Table 7
Absolute maximum ratings
Parameter
Ratings
Storage temperature
Ambient temperature
–60°C to +100°C
0°C to +70°C
5 V supply voltage to ground potential
3.3 V supply voltage to ground potential
Voltage at open drain input pins
(OVR#1–4, SELFPWR, RESET#)
–0.5 V to +6.0 V
–0.5 V to +3.6 V
–0.5 V to +5.5 V
3.3 V Input Voltage for Digital I/O
FOSC (oscillator or crystal frequency)
–0.5 V to +3.6 V
12 MHz ± 0.05%
Datasheet
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Operating conditions
12
Operating conditions
Table 8
Operating conditions
Parameter
Conditions
Ambient temperature
0°C to +70°C
0°C to +125°C
4.75 V to +5.25 V
3.15 V to +3.6 V
0.5 V to +3.6 V
–0.5 V to +5.0 V
78.7 °C/W
Ambient max junction temperature
5 V supply voltage to ground potential
3.3 V supply voltage to ground potential
Input voltage for USB signal pins
Voltage at open drain input pins
Thermal characteristics 48-pin TQFP
Thermal characteristics 28-pin QFN
33.3 °C/W
Datasheet
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Electrical characteristics
13
Electrical characteristics
13.1
DC electrical characteristics
Table 9
DC electrical characteristics
Max
Parameter
Description
Conditions
Min
Typ
Units
External Internal
regulator regulator
PD
Power dissipation
Excluding USB
signals
–
–
432
mW
VIH
VIL
Il
Input high voltage
Input low voltage
Input leakage current Full speed / low
speed
–
–
2
–
–10
–
–
–
–
0.8
+10
V
V
A
(0 < VIN < VCC
)
High speed mode
–5
0
+5
A
(0 < VIN < VCC
IOH = 8 mA
IOL = 8 mA
)
VOH
VOL
RDN
Output voltage high
Output low voltage
Padinternalpull-down –
resistor
2.4
–
29
–
–
59
–
0.4
135
V
V
K
RUP
CIN
Pad internal pull-up
resistor
Input pin capacitance Full speed / low
speed mode
–
80
–
108
–
140
20
5
K
pF
high speed mode
–
4
–
4.5
0.786
pF
mA
ISUSP
Suspend current
1.043
1.3
Notes
5. Current measurement is with device attached and enumerated.
6. No devices attached.
Datasheet
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Electrical characteristics
Table 9
Parameter
ICC
DC electrical characteristics (continued)
Max
Description
Conditions
Min
Typ
Units
External Internal
regulator regulator
Supply current
4 Active ports
Full speed host,
full speed devices
–
–
–
–
–
–
–
–
–
–
–
–
88.7
81.9
88.2
79.1
72.9
75.9
68.1
61.9
64.9
57.1
51.9
54.7
103.9
88.2
101.2
91.6
78.5
88.7
78.4
67.6
75.4
66.3
57.6
61.1
105.4
89.3
102.3
93
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
High speed host,
high speed devices
High speed host,
full speed devices
Full speed host,
full speed devices
High speed host,
high speed devices
High speed host,
full speed devices
3 Active ports[5]
2 Active ports
78.6
88.8
78.6
69.6
76.1
66.7
59.3
62.5
Full speed host,
full speed devices
High speed host,
high speed devices
High speed host,
full speed devices
1 Active ports
Full speed host,
full speed devices
High speed host,
high speed devices
High speed host,
full speed devices
Full speed host
High speed host
No Active ports[6]
–
–
42.8
44.2
48.9
49.1
50.3
50.6
mA
mA
Notes
5. Current measurement is with device attached and enumerated.
6. No devices attached.
Datasheet
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Electrical characteristics
13.2
AC electrical characteristics
USB Transceiver is USB 2.0 certified in low, full and high speed modes.
Both the upstream USB transceiver and all four downstream transceivers have passed the USB-IF USB 2.0
Electrical Certification Testing.
The 48-pin TQFP package can support communication to EEPROM using either I2C or SPI. The 28-pin QFN package
can support only I2C communication to EEPROM.
AC characteristics of these two interfaces to EEPROM are summarized in tables below:
Table 10
Parameter
tCSS
tCSH
tSKH
tSKL
tDIS
tDIH
tPD1
AC characteristics of SPI EEPROM interface
Parameter
CS setup time
CS hold time
SK high time
SK low time
DI setup time
DI hold time
Output delay to ‘1’
Output delay to ‘0’
Min
3.0
3.0
1.0
2.2
1.8
2.4
–
Typ
–
–
–
–
–
–
–
–
Max
–
–
–
–
–
–
1.8
1.8
Units
µs
tPD0
–
Table 11
AC characteristics of I2C EEPROM interface
Parameter
1.8 V–5.5 V
2.5 V–5.5 V
Parameter
Units
Min
Max
100
–
–
–
–
–
–
–
Min
Max
400
–
–
–
–
–
–
–
fSCL
tLOW
SCL clock frequency
Clock LOW Period
0.0
4.7
4.0
4.7
4.7
4.0
4.0
200.0
0
0.0
1.2
0.6
0.6
0.6
0.6
0.6
100.0
0
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
tHIGH
tSU:STA
tSU:STO
tHD:STA
tHD:STO
tSU:DAT
tHD:DAT
tDH
Clock HIGH Period
Start condition setup time
Stop condition setup time
Start condition hold time
Stop condition hold time
Data in setup time
Data in hold time
Data out hold time
Clock to output
–
–
100
0.1
–
–
4.5
10
50
–
tAA
0.1
–
–
5
tWR
Write cycle time
Datasheet
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Thermal resistance
14
Thermal resistance
Table 12
Thermal resistance
48-pinTQFP 28-pin QFN
Parameter
Description
Unit
package
78.7
package
33.3
JA
JC
Thermal resistance (junction to ambient)
Thermal resistance (junction to case)
°C/W
°C/W
35.3
18.4
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Ordering information
15
Ordering information
Table 13
Ordering information
Ordering code
Package type
CY7C65642-48AXC
CY7C65642-48AXCT
CY7C65642-28LTXC
48-pin TQFP - Tray
48-pin TQFP - Tape and reel
28-pin QFN - Tray
15.1
Ordering code definitions
CY 7 C 65642 - XX
A
X
C
X
X = blank or T
blank = Tray; T = Tape and reel
Temperature range:
C = Commercial
Pb-free
Package type: XX = A or LT
A = TQFP; LT = QFN
Pin count: XX = 48 or 28
Part identifier
Technology code: C = CMOS
Marketing code
Company ID: CY = Cypress, An Infineon Technologies
company
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Package diagrams
16
Package diagrams
The CY7C65642 is available in following packages:
51-85135 *C
Figure 8
48-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85135
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Package diagrams
001-64621 *A
28-pin QFN ((5 × 5 × 0.8 mm) 3.5 × 3.5 E-Pad (Sawn)) package outline, 001-64621
Figure 9
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Acronyms
17
Acronyms
Table 14
Acronyms
Acronym
Description
AC
Alternating Current
ASCII
EEPROM
EMI
ESD
GPIO
I/O
American Standard Code for Information Interchange
Electrically Erasable Programmable Read Only Memory
Electromagnetic Interference
Electrostatic Discharge
General Purpose Input/Output
Input/Output
LED
Light Emitting Diode
LSB
Least Significant Bit
MSB
PCB
PLL
Most Significant Bit
Printed Circuit Board
Phase-Locked Loop
POR
PSoC™
QFN
RAM
ROM
SIE
Power On Reset
Programmable System-on-Chip™
Quad Flat No-leads
Random Access Memory
Read Only Memory
Serial Interface Engine
TQFP
TT
Thin Quad Flat Pack
Transaction Translator
USB
Universal Serial Bus
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Document conventions
18
Document conventions
18.1
Units of measure
Table 15
Units of measure
Symbol
Unit of measure
°C
degree Celsius
kilohertz
kilohm
kHz
k
MHz
A
s
W
mA
mm
ms
mW
ns
megahertz
microampere
microsecond
microwatt
milliampere
millimeter
millisecond
milliwatt
nanosecond
ohm
%
percent
pF
ppm
V
picofarad
parts per million
volt
W
watt
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Silicon Errata for the HX2VL, CY7C65642
product family
19
Silicon Errata for the HX2VL, CY7C65642 product family
This section describes the errata for the HX2VL, CY7C65642. The details include errata trigger conditions, scope
of impact, available workarounds, and silicon revision applicability.
Contact your local Infineon Sales Representative, if you have any questions.
19.1
Part numbers affected
Part number
Device characteristics
CY7C65642
USB 2.0 Multi TT Hub
19.2
HX2VL Qualification status
Product Status: In production
19.3
HX2VL Errata summary
This table defines the errata applicability to available HX2VL family devices.
Silicon
Items
Part numbers
Workaround
Fix status
Revision
1. USB device is not
CY7C65642
Rev. **
Issue a Port-Reset from host No fix
USB application or driver if planned.
the USB device commands
STALLed
recognized properly if a
disconnect followed by a
connect event happen
during hub suspend
1. USB device is not recognized properly if a disconnect followed by a connect event happen during hub suspend
•Problem definition
HX2VL sometimes does not recognize Downstream (DS) USB device after coming out of suspend if the
connected DS device is disconnected and connected back to the same DS port during hub suspend state.
•Parameters affected
N/A.
•Trigger condition(s)
Disconnect followed by a Connect event of DS device from the hub during suspend state.
•Scope of impact
The issue is not observed with standard Microsoft driver/class devices such as mouse, keyboard, mass
storage, etc. as the standard class drivers recover the device using Port-Reset command when there is a STALL
from the DS devices.
•Workaround
Issue a Port-Reset from host USB application or driver to recover the DS device when it STALLS.
•Fix status
No fix planned.
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Revision history
Revision history
Document
Date
Description of changes
revision
**
2011-02-18
New data sheet.
Updated Functional overview:
Updated Port indicators:
Added a Note “Pin-strapping GREEN#[1] and GREEN#[2] enables proprietary
function that may affect the normal functionality of HX2VL. Configuring Port
#1 and #2 as non-removable by pin-strapping should be avoided.”.
Updated Pin configurations:
Updated Figure 4 (Pin of the 48-pin TQFP package was named SELF_PWR.
It is changed to SELFPWR.).
Updated Pin definitions (for 48-pin TQFP package):
Updated description of XIN pin to “12-MHz crystal clock input, or 12-MHz
clock input” (since 28-pin package does not support 27 and 48 MHz).
Updated description of XOUT pin to “12-MHz Crystal OUT. (NC if external
clock is used)”.
Changed value from 680 to 650 in description ofRREF pin.
Changed description ofOVR# pins from “Default is Active LOW” to “Active
LOW Overcurrent Condition Detection Input” (since the polarity is not
configurable).
Changed all seven occurrences of “Refer “48-pin TQFP Pin Configuration”
on page 5” to “Refer Pin configuration options on page 23”.
Added Note 2 and referred the same Note in GREEN#[1] and GREEN#[2]
pins).
*A
2011-06-29
Updated Pin definitions (for 28-pin QFN package):
Updated description of XIN pin to “12-MHz crystal clock input, or 12-MHz
clock input” (since 28-pin package does not support 27 and 48 MHz).
Updated description of XOUT pin to “12-MHz Crystal OUT. (NC if external
clock is used)”.
Changed description of OVR# pins from “Default is Active LOW” to “Active
LOW Overcurrent Condition Detection Input” (since the polarity is not
configurable).
Updated Functional overview:
Updated Power regulator:
Changed regulator’s maximum current loading from 200 mA to 150 mA.
Updated Pin configuration options:
Updated Power switch enable pin polarity:
Replaced first two occurrences of the word “setting” with “pin-strapping”.
Updated Electrical characteristics:
Updated DC electrical characteristics:
Updated maximum value of ISUSP parameter to 903 µA.
Updated maximum values of ICC parameter.
Changed status from Preliminary to Final.
Updated Pin definitions (for 48-pin TQFP package):
Minor edits.
*B
2011-07-27
Updated Ordering information:
Updated part numbers.
Updated Ordering code definitions.
Datasheet
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HX2VL - Very Low-Power USB 2.0 TetraHub Controller
Revision history
Document
Date
Description of changes
revision
Updated Pin configurations:
Updated Figure 4 (Renamed SPI_DI to SPI_MOSI, renamed SPI_DO to
SPI_MISO respectively for clarity).
Updated Pin definitions (for 48-pin TQFP package):
Renamed SPI_DI to SPI_MOSI, renamed SPI_DO to SPI_MISO respectively
for clarity.
*C
2012-02-16
Updated Pin definitions (for 28-pin QFN package):
Updated description of PWR# of 28-pin package (To describe the alternate
function I2C_SDA).
Completing Sunset Review.
Updated EEPROM configuration options:
Changed the value of Byte 5 to FEh to match with the tabular column.
Updated Electrical characteristics:
Updated DC electrical characteristics:
Splitted the Max column into two columns namely External regulator and
Internal regulator for ISUSP and ICC parameters and updated the
corresponding values.
*D
*E
2012-07-02
2013-05-09
Added Thermal resistance.
Updated Ordering information:
Updated part numbers.
Updated to new template.
Added Silicon Errata for the HX2VL, CY7C65642 product family.
Added More information.
Updated Functional overview:
Updated Port indicators:
Updated description.
Updated Pin definitions (for 48-pin TQFP package):
Added Note at the end of table.
Updated EEPROM configuration options:
Updated details in “Value” column corresponding to “09h–0Fh” in the table.
Updated Electrical characteristics:
Updated DC electrical characteristics:
Updated all values of RDN and RUP parameters.
Added Note 5 and referred the same note in “3 Active ports” in “Description”
column of ICC parameter.
*F
2015-03-20
Added Note 6 and referred the same note in “No Active ports” in
“Description” column of ICC parameter.
Updated Package diagrams:
spec 51-85135 – Changed revision from *B to *C.
spec 001-64621 – Changed revision from ** to *A.
Updated Silicon Errata for the HX2VL, CY7C65642 product family:
Updated HX2VL Qualification status:
Replaced “Sampling” with “In production”.
Updated to new template.
Completing Sunset Review.
Updated Features:
Updated description.
Updated Pin definitions (for 28-pin QFN package):
Updated details in “Description” column corresponding to OVR#[1],
OVR#[2], OVR#[3], and OVR#[4] pins.
Updated to new template.
*G
2016-07-21
Datasheet
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Revision history
Document
Date
Description of changes
revision
Updated More information:
Updated description.
*H
2016-12-07
2017-04-10
2017-06-22
Updated to new template.
Updated Cypress Logo and Copyright.
Completing Sunset Review.
*I
Updated Ordering information:
No change in part numbers.
Replaced “Tube” with “Tray”.
*J
Updated Pin configurations:
Updated Figure 4 (Removed old Cypress Logo).
Updated Figure 5 (Removed old Cypress Logo).
Updated Silicon Errata for the HX2VL, CY7C65642 product family:
Updated HX2VL Errata summary:
*K
2018-04-13
Updated description.
Updated to new template.
Added watermark “Not Recommended for New Designs” across the
*L
2021-05-20
2023-02-13
document.
Updated to new template.
Removed watermark “Not Recommended for New Designs” across the
document.
Updated hyperlinks across the document.
Migrated to Infineon template.
Completing Sunset Review.
*M
Datasheet
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Edition 2023-02-13
Published by
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characteristics (“Beschaffenheitsgarantie”).
in question please contact your nearest Infineon
Technologies office.
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Document reference
001-65659 Rev. *M
相关型号：
CY7C66012-PC
Microcontroller, 8-Bit, OTPROM, 12MHz, CMOS, PDIP48, 0.600 INCH, PLASTIC, DIP-48
CYPRESS
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