CY8C20324-12LQXIT [INFINEON]
CY8C20x24;
| 型号： | CY8C20324-12LQXIT |
| 厂家： | 
Infineon |
| 描述： | CY8C20x24 时钟 微控制器 |
| 文件： | 总44页 (文件大小：1117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY8C20224/CY8C20324
CY8C20424/CY8C20524
CapSense PSoC
Programmable System-on-Chip
CapSense PSoC Programmable System-on-Chip
■ High-performance CapSense
Features
❐ Ultra fast scan speed — 1 kHz (nominal)
❐ Reliable finger detection through 5 mm thick acrylic
❐ Excellent EMI and AC noise immunity
■ Low power, configurable CapSense®
❐ Configurable capacitive sensing elements
❐ operating voltage
❐ Operating voltage: 2.4 V to 5.25 V
❐ Low operating current
• Active 1.5 mA (at 3.0 V, 12 MHz)
• Sleep 2.8 µA (at 3.3 V)
❐ Supports up to 25 capacitive buttons
❐ Supports one slider
❐ Up to 10 cm proximity sensing
❐ Supports up to 28 general-purpose I/O (GPIO) pins
• Drive LEDs and other outputs
❐ Configurable LED behavior (fading, strobing)
❐ LED color mixing (RBG LEDs)
■ Industry best flexibility
❐ 8 KB flash program storage 50,000 erase and write cycles
❐ 512-bytes SRAM data storage
❐ Bootloader for ease of field reprogramming
❐ Partial flash updates
❐ Flexible flash protection modes
❐ Interrupt controller
❐ In-system serial programming (ISSP)
❐ Free complete development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator and programmer
• Full-speed emulation
• Complex breakpoint structure
• 128 KB trace memory
❐ Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
■ Additional system resources
❐ Configurable communication speeds
❐ I2C slave
❐ Internal ±5.0% 6 or12 MHz main oscillator
❐ Internal low-speed oscillator at 32 kHz
❐ Low external component count
• No external crystal or oscillator components
• No external voltage regulator required
❐ SPI master and SPI slave
❐ Watchdog and sleep timers
❐ Internal voltage reference
❐ Integrated supervisory circuit
Logic Block Diagram
Port 3 Port 2 Port 1 Port 0
3V LDO
PSoC
CORE
System Bus
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Sleep and
Watchdog
Interrupt
Controller
6/12 MHz Internal Main Oscillator
Analog
Ref.
CapSense
Basic
Block
ANALOG
SYSTEM
POR and LVD
System Resets
I2C Slave/SPI
Master-Slave
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-41947 Rev. *P
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 22, 2019
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Contents
PSoC® Functional Overview ............................................3
PSoC Core ..................................................................3
CapSense Analog System ..........................................3
Additional System Resources .....................................4
Getting Started ..................................................................4
Application Notes ........................................................4
Development Kits ........................................................4
Training .......................................................................4
CYPros Consultants ....................................................4
Solutions Library ..........................................................4
Technical Support .......................................................4
Development Tools ..........................................................5
PSoC Designer Software Subsystems ........................5
Designing with PSoC Designer .......................................6
Select User Modules ...................................................6
Configure User Modules ..............................................6
Organize and Connect ................................................6
Generate, Verify, and Debug .......................................6
Pinouts ..............................................................................7
16-pin Part Pinout ........................................................7
24-pin Part Pinout ........................................................8
28-pin Part Pinout ........................................................9
32-pin Part Pinout ......................................................10
48-pin OCD Part Pinout .............................................12
Electrical Specifications ................................................14
Absolute Maximum Ratings .......................................14
Operating Temperature .............................................14
DC Electrical Characteristics .....................................15
AC Electrical Characteristics .....................................19
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Packaging Dimensions ..................................................27
Thermal Impedances .................................................30
Solder Reflow Specifications .....................................30
Development Tool Selection .........................................31
Software ....................................................................31
Development Kits ......................................................31
Evaluation Tools ........................................................31
Device Programmers .................................................32
Accessories (Emulation and Programming) ..............32
Acronyms ........................................................................33
Acronyms Used .........................................................33
Reference Documents ....................................................33
Document Conventions .................................................34
Units of Measure .......................................................34
Numeric Conventions ................................................34
Glossary ..........................................................................34
Document History Page .................................................39
Sales, Solutions, and Legal Information ......................43
Worldwide Sales and Design Support .......................43
Products ....................................................................43
PSoC® Solutions ......................................................43
Cypress Developer Community .................................43
Technical Support .....................................................43
Document Number: 001-41947 Rev. *P
Page 2 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
®
Figure 1. Analog System Block Diagram
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU based system
components with one, low cost single chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
enables the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
IDAC
Vr
The PSoC architecture for this device family is comprised of
three main areas: core, system resources, and CapSense
analog system. A common, versatile bus enables connection
between I/O and the analog system. Each CY8C20x24 PSoC
device includes a dedicated CapSense block that provides
sensing and scanning control circuitry for capacitive sensing
applications. Depending on the PSoC package, up to 28 GPIOs
are also included. The GPIOs provide access to the MCU and
analog mux.
Reference
Buffer
Cinternal
Comparator
Mux
Mux
Refs
PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low-speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
12 MHz. The M8C is a 2-MIPS, 8-bit Harvard-architecture
microprocessor.
Cap Sense Counters
CSCLK
Relaxation
CapSense
Clock Select
IMO
Oscillator
(RO)
System resources provide additional capability, such as a
configurable I2C slave or SPI master-slave communication
interface and various system resets supported by the M8C.
The analog system is composed of the CapSense PSoC block
and an internal 1.8-V analog reference. Together, they support
capacitive sensing of up to 28 inputs.
Analog Multiplexer System
The analog mux bus connects to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
CapSense Analog System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. The
analog multiplexer system in the CY8C20x24 device family is
optimized for basic CapSense functionality. It supports sensing
of CapSense buttons, proximity sensors, and a single slider.
Other multiplexer applications include:
■ Capacitive slider interface.
■ Chip-wide mux that enables analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal to noise signal level requirements application notes,
which are found in http://www.cypress.com > Design Resources
> Application Notes. In general, and unless otherwise noted in
the relevant application notes, the minimum signal-to-noise ratio
(SNR) requirement for CapSense applications is 5:1.
Document Number: 001-41947 Rev. *P
Page 3 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Typical Application
Getting Started
Figure 2 illustrates a typical application: CapSense multimedia
keys for a notebook computer with a slider, four buttons, and four
LEDs.
This datasheet is an overview of the PSoC integrated circuit and
presents specific pin, register, and electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
Figure 2. CapSense Multimedia Button-Board Application
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Additional System Resources
System resources, some of which are previously listed, provide
additional capability useful to complete systems. Additional
resources include low voltage detection (LVD) and power on
reset (POR). Brief statements describing the merits of each
system resource follow.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
■ The I2C slave and SPI master-slave module provides 50, 100,
or 400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
■ LVD interrupts signal the application of falling voltage levels,
while the advanced POR circuit eliminates the need for a
system supervisor.
Solutions Library
■ An internal 1.8-V reference provides an absolute reference for
capacitive sensing.
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
■ The 5 V maximum input, 3 V fixed output, low dropout regulator
(LDO) provides regulation for I/Os. A register controlled bypass
mode enables the user to disable the LDO.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Document Number: 001-41947 Rev. *P
Page 4 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Code Generation Tools
Development Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
PSoC Designer™ is the revolutionary Integrated Design
Environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■ Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■ Extensive user module catalog
■ Integrated source-code editor (C and assembly)
■ Free C compiler with no size restrictions or time limits
■ Built-in debugger
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
■ In-circuit emulation
■ Built-in support for communication interfaces:
❐ Hardware and software I2C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In-Circuit Emulator
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
A low-cost, high-functionality In-Circuit Emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24-MHz) operation.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC’s resources for a given application.
Document Number: 001-41947 Rev. *P
Page 5 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Organize and Connect
Designing with PSoC Designer
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules”. User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations, and external signals
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, an
EzI2Cs User Module configures the I2C block in PSoC. Using
these parameters, you can establish the slave address and I2C
speed. Configure the parameters and properties to correspond
to your chosen application. Enter values directly or by selecting
values from drop-down menus. All of the user modules are
documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
data sheets explain the internal operation of the user module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
that you may need to successfully implement your design.
Document Number: 001-41947 Rev. *P
Page 6 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Pinouts
This section describes, lists, and illustrates the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC device pins and pinout
configurations.
The CY8C20x24 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not
capable of Digital I/O.
16-pin Part Pinout
Figure 3. CY8C20224 16-pin PSoC Device
AI, P2[5]
AI, P2[1]
1
2
P0[4], AI
XRES
P1[4], AI, EXTCLK
P1[2], AI
12
11
QFN
(Top
3
4
View )10
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI M ISO , P1[5]
9
Table 1. 16-pin Part Pinout (COL)
Pin No.
Digital
I/O
Analog
Name
Description
1
2
3
I
I
I
P2[5]
P2[1]
P1[7]
I/O
I2C SCL, SPI SS
IOH
I2C SDA, SPI MISO
4
IOH
I
P1[5]
5
6
IOH
IOH
I
I
P1[3] SPI CLK
CLK[1], I2C SCL, SPI MOSI
Ground connection
P1[1]
7
8
Power
VSS
DATA[1], I2C SDA
IOH
I
P1[0]
9
IOH
IOH
I
I
P1[2]
10
11
12
13
14
15
16
P1[4] Optional external clock input (EXTCLK)
XRES Active high external reset with internal pull-down
P0[4]
Input
Power
I/O
I
VDD
Supply voltage
I/O
I/O
I/O
I
I
I
P0[7]
P0[3] Integrating input
P0[1] Integrating input
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
1. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-41947 Rev. *P
Page 7 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
24-pin Part Pinout
Figure 4. CY8C20324 24-pin PSoC Device
AI, P2[5]
P0[4], AI
18
1
2
3
4
5
6
17 P0[2], AI
16
AI, P2[3]
AI, P2[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
P0[0], AI
QFN
(Top View)
15
14
13
P2[0], AI
XRES
P1[6], AI
Table 2. 24-pin Part Pinout (QFN [2]
)
Pin No.
Digital
I/O
Analog
Name
P2[5]
P2[3]
P2[1]
Description
1
2
3
4
I
I
I
I
I/O
I/O
I2C SCL, SPI SS
I2C SDA, SPI MISO
IOH
P1[7]
P1[5]
5
IOH
I
6
7
IOH
IOH
I
I
P1[3]
P1[1]
SPI CLK
CLK[3], I2C SCL, SPI MOSI
No connection
8
9
NC
VSS
Power
Ground connection
DATA[3], I2C SDA
10
IOH
I
P1[0]
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CP
IOH
IOH
IOH
I
I
I
P1[2]
P1[4]
P1[6]
XRES
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
Input
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
Power
Power
Supply voltage
I/O
I/O
I/O
I/O
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Integrating input
Integrating input
Center pad is connected to ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Notes
2. The center pad on the QFN package is connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically
SS
floated and not connected to any other signal.
3. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-41947 Rev. *P
Page 8 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
28-pin Part Pinout
Figure 5. CY8C20524 28-pin PSoC Device
Table 3. 28-pin Part Pinout (SSOP)
Pin No.
Digital
I/O
Analog
Name
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
VSS
Description
1
2
I
I
I
I
I
I
I
I
I/O
3
I/O
Integrating input
Integrating input
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
Power
Ground connection
I2C SCL, SPI SS
I2C SDA, SPI MISO
10
IOH
IOH
IOH
IOH
I
I
P1[7]
11
P1[5]
12
13
I
I
P1[3]
P1[1]
SPI CLK
CLK[4], I2C SCL, SPL MOSI
Ground connection
Data[4], I2C SDA
14
15
Power
VSS
IOH
I
P1[0]
16
17
18
19
20
21
22
23
24
25
26
27
28
IOH
IOH
IOH
I
I
I
P1[2]
P1[4]
P1[6]
Optional external clock input (EXTCLK)
Input
XRES Active high external reset with internal pull-down
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Power
VDD
Supply voltage
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Note
4. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-41947 Rev. *P
Page 9 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
32-pin Part Pinout
Figure 6. CY8C20424 32-pin PSoC Device
AI, P0[1]
AI, P2[7]
AI, P2[5]
AI, P2[3]
AI, P2[1]
AI, P3[3]
1
2
3
4
5
6
7
8
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
24
23
22
21
20
19
18
17
QFN
(Top View)
AI, P3[1]
SPI SS, P1[7]
AI, I2C SCL
Table 4. 32-pin Part Pinout (QFN [5]
)
Pin No.
Digital
I/O
Analog
Name
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
Description
1
2
3
4
5
6
7
8
I
I
I
I
I
I
I
I
Integrating Input
I/O
I/O
I/O
I/O
I/O
I/O
I2C SCL, SPI SS
IOH
I2C SDA, SPI MISO
SPI CLK
9
IOH
I
P1[5]
10
11
IOH
IOH
I
I
P1[3]
P1[1]
CLK[6], I2C SCL, SPI MOSI
Ground connection
12
13
Power
VSS
DATA[6], I2C SDA
IOH
I
P1[0]
14
15
16
17
IOH
IOH
IOH
I
I
I
P1[2]
P1[4]
P1[6]
Optional external clock input (EXTCLK)
Input
XRES Active high external reset with internal pull-down
Notes
5. The center pad on the QFN package is connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically
SS
floated and not connected to any other signal.
6. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-41947 Rev. *P
Page 10 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Table 4. 32-pin Part Pinout (QFN [5]) (continued)
Pin No.
18
Digital
I/O
Analog
Name
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Description
I
I
I
I
I
I
I
I
I
I
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
Power
Supply voltage
29
I/O
I/O
I/O
I
I
I
P0[7]
P0[5]
P0[3]
VSS
30
31
Integrating input
32
Power
Power
Ground connection
CP
VSS
Center pad is connected to ground
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Document Number: 001-41947 Rev. *P
Page 11 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
48-pin OCD Part Pinout
The 48-pin QFN part table and pin diagram is for the CY8C20024 On-Chip Debug (OCD) PSoC device. This part is only used for
in-circuit debugging. It is NOT available for production.
Figure 7. CY8C20024 OCD PSoC Device
NC
AI, P0[1]
36
35
34
33
32
31
30
P0[4], AI
1
2
P0[2], AI
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
AI, P2[7]
3
4
5
6
AI, P2[5]
OCD
QFN
AI, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
P2[0], AI
P3[2], AI
P3[0], AI
XRES
7
8
9
10
11
12
(Top View)
29
28
27
AI, I2C SDA, SPI MISO, P1[5]
NC
26
25
P1[6], AI
P1[4], EXTCLK, AI
NC
Table 5. 48-pin OCD Part Pinout (QFN [7]
)
Pin No.
Digital
Analog
Name
NC
Description
1
2
3
4
5
6
7
8
9
No connection
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
Integrating Input
I2C SCL, SPI SS
I2C SDA, SPI MISO
No connection
No connection
No connection
No connection
SPI CLK
10
IOH
I
P1[5]
11
12
13
14
15
16
NC
NC
NC
NC
IOH
IOH
I
I
P1[3]
P1[1]
CLK[8], I2C SCL, SPI MOSI
17
18
19
20
Power
Vss
Ground connection
CCLK OCD CPU clock output
HCLK OCD high speed clock output
DATA[8], I2C SDA
IOH
I
P1[0]
Notes
7. The center pad on the QFN package is connected to ground (V ) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically
SS
floated and not connected to any other signal.
8. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 001-41947 Rev. *P
Page 12 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Table 5. 48-pin OCD Part Pinout (QFN [7]) (continued)
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CP
Digital
Analog
Name
P1[2]
NC
Description
IOH
I
No connection
No connection
No connection
NC
NC
IOH
IOH
I
I
P1[4]
P1[6]
Optional external clock input (EXTCLK)
Input
XRES Active high external reset with internal pull-down
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
P3[0]
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
NC
NC
No connection
No connection
No connection
NC
I/O
I
P0[6]
VDD
Power
Supply voltage
OCDO OCD odd data output
OCDE OCD even data I/O
I/O
I/O
I/O
I
I
I
P0[7]
P0[5]
P0[3]
VSS
NC
Integrating input
Power
Power
Ground connection
No connection
VSS
Center pad is connected to ground
A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.
Document Number: 001-41947 Rev. *P
Page 13 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC
devices. For the latest electrical specifications, visit the web at http://www.cypress.com/psoc.
Specifications are valid for –40 °C T 85 °C and T 100 °C as specified, except where noted.
A
J
Refer to Table 16 on page 19 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 8. Voltage versus CPU Frequency and IMO Frequency Trim Options
5.25
4.75
5.25
SLIMO SLIMO SLIMO
Mode=1 Mode=1 Mode=0
4.75
3.60
SLIMO SLIMO
Mode=1 Mode=0
SLIMO
3.00
2.70
3.00
2.70
SLIMO
Mode=0
Mode=1
2.40
2.40
750 kHz
3 MHz
6 MHz
750 kHz
3 MHz
6 MHz
12 MHz
12 MHz
IMO Frequency
CPU Frequency
Absolute Maximum Ratings
Table 6. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
Min
Typ
Max
Units
Notes
–55
25
+100
°C
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C
degrades reliability.
TA
Ambient temperature with power applied
Supply voltage on VDD relative to VSS
DC input voltage
–40
–0.5
–
–
–
–
–
–
–
+85
+6.0
°C
V
VDD
VIO
VIOZ
IMIO
ESD
LU
VSS – 0.5
VSS – 0.5
–25
VDD + 0.5
VDD + 0.5
+50
V
DC voltage applied to tri-state
Maximum current into any port pin
Electrostatic discharge voltage
Latch-up current
V
mA
V
2000
–
Human Body Model ESD.
–
200
mA
Operating Temperature
Table 7. Operating Temperature
Symbol
TA
TJ
Description
Min
–40
–40
Typ
–
Max
+85
Units
°C
Notes
Ambient temperature
Junction temperature
–
+100
°C
Thetemperaturerisefromambient
to junction is package specific.
See Table 31 on page 30. The
user must limit the power
consumption to comply with this
requirement.
Document Number: 001-41947 Rev. *P
Page 14 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
DC Electrical Characteristics
DC Chip Level Specifications
Table 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 8. DC Chip Level Specifications
Symbol
VDD
IDD12
Description
Supply voltage
Min
2.40
–
Typ
–
Max
5.25
2.5
Units
Notes
V
Supply current, IMO = 12 MHz
1.5
mA Conditions are VDD = 3.0 V,
TA = 25 °C, CPU = 12 MHz.
IDD6
Supply current, IMO = 6 MHz
–
–
1
1.5
4
mA Conditions are VDD = 3.0 V,
TA = 25 °C, CPU = 6 MHz.
ISB27
Sleep (Mode) current with POR,
LVD, sleep timer, WDT, and
internal slow oscillator active. Mid
temperature range.
2.6
µA VDD = 2.55 V, 0 °C TA 40 °C.
ISB
Sleep (Mode) current with POR,
LVD, sleep timer, WDT, and
internal slow oscillator active.
–
2.8
5
µA VDD = 3.3 V, –40 °C TA 85 °C.
DC GPIO Specifications
Unless otherwise noted, Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, and 2.7 V at 25 °C. These are for design guidance only.
Table 9. 5 V and 3.3 V DC GPIO Specifications
Symbol
RPU
Description
Pull-up resistor
Min
4
Typ
5.6
–
Max
8
Units
k
Notes
VOH1
VOH2
VOH3
High output voltage,
port 0, 2, or 3 pins
VDD – 0.2
–
V
IOH < 10 µA, VDD > 3.0 V, maximum of
20 mA source current in all I/Os.
High output voltage,
port 0, 2, or 3 pins
VDD – 0.9
VDD – 0.2
–
–
–
–
V
V
IOH = 1 mA, VDD > 3.0 V, maximum of
20 mA source current in all I/Os.
High output voltage,
port 1 pins with LDO regulator
disabled
IOH < 10 µA, VDD > 3.0 V, maximum of
10 mA source current in all I/Os.
VOH4
VOH5
VOH6
VOH7
VOH8
VOH9
VOH10
High output voltage,
port 1 pins with LDO regulator
disabled
VDD – 0.9
2.7
–
3.0
–
–
3.3
–
V
V
V
V
V
V
V
IOH = 5 mA, VDD > 3.0 V, maximum of
20 mA source current in all I/Os.
High output voltage,
port 1 pins with 3.0 V LDO
regulator enabled
IOH < 10 µA, VDD > 3.1 V, maximum of
4 I/Os all sourcing 5 mA.
High output voltage,
port 1 pins with 3.0 V LDO
regulator enabled
2.2
IOH = 5 mA, VDD > 3.1 V, maximum of
20 mA source current in all I/Os.
High output voltage,
port 1 pins with 2.4 V LDO
regulator enabled
2.1
2.4
–
2.7
–
IOH < 10 µA, VDD > 3.0 V, maximum of
20 mA source current in all I/Os.
High output voltage,
port 1 pins with 2.4 V LDO
regulator enabled
2.0
IOH < 200 µA, VDD > 3.0 V, maximum
of 20 mA source current in all I/Os.
High output voltage,
port 1 pins with 1.8 V LDO
regulator enabled
1.6
1.8
–
2.0
–
IOH < 10 µA, 3.0 V VDD 3.6 V,
0 °C TA85 °C, maximum of 20 mA
source current in all I/Os.
High output voltage,
port 1 pins with 1.8 V LDO
regulator enabled
1.5
IOH < 100 µA, 3.0 V VDD 3.6 V,
0 °C TA85 °C, maximum of 20 mA
source current in all I/Os.
Document Number: 001-41947 Rev. *P
Page 15 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Table 9. 5 V and 3.3 V DC GPIO Specifications (continued)
Symbol
VOL
Description
Low output voltage
Min
Typ
Max
Units
Notes
–
–
0.75
V
IOL = 20 mA, VDD > 3.0V, maximum of
60 mA sink current on even port pins
(for example, P0[2] and P1[4]) and 60
mA sink current on odd port pins (for
example, P0[3] and P1[5]).
IOH2
IOH4
IOL
High level source current,
port 0, 2, or 3 pins
1
5
–
–
–
–
–
mA VOH = VDD – 0.9, for the limitations of
the total current and IOH at other VOH
levels see the notes for VOH
.
High level source current,
port 1 pins with LDO regulator
disabled
mA VOH = VDD – 0.9, for the limitations of
the total current and IOH at other VOH
levels see the notes for VOH
.
Low level sink current
20
–
mA VOH = 0.75 V, see the limitations of the
total current in the note for VOL
.
VIL
VIH
VH
IIL
Input low voltage
–
2.0
–
–
–
0.8
V
V
3.0 V VDD 5.25 V
Input high voltage
3.0 V VDD 5.25 V
Input hysteresis voltage
Input leakage (absolute value)
Capacitive load on pins as input
140
1
–
–
5
mV
–
nA Gross tested to 1 µA
CIN
0.5
1.7
pF Package and pin dependent
temperature = 25 °C
COUT
Capacitive load on pins as output
0.5
1.7
5
pF Package and pin dependent
temperature = 25 °C
Table 10. 2.7 V DC GPIO Specifications
Symbol Description
RPU Pull-up resistor
Min
4
Typ
5.6
–
Max
8
Units
Notes
k
VOH1
VOH2
VOL
High output voltage,
port 1 pins with LDO regulator
disabled
VDD – 0.2
–
V
IOH < 10 µA, maximum of 10 mA
source current in all I/Os.
High output voltage,
port 1 pins with LDO regulator
disabled
VDD – 0.5
–
–
–
V
V
IOH = 2 mA, maximum of 10 mA source
current in all I/Os.
Low output voltage
–
0.75
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5]).
IOH2
High level source current,
port 1 pins with LDO regulator
disabled
2
–
–
mA VOH = VDD – 0.5, for the limitations of
the total current and IOH at other VOH
levels see the notes for VOH
.
IOL
Low level sink current
10
–
–
–
–
mA VOH = 0.75 V, see the limitations of the
total current in the note for VOL
.
VOLP1
Low output voltage port 1 pins
0.4
V
IOL = 5 mA, maximum of 50 mA sink
current on even port pins (for example,
P0[2] and P3[4]) and 50 mA sink
current on odd port pins (for example,
P0[3] and P2[5]).
2.4 V VDD 3.0 V
VIL
Input low voltage
–
1.4
1.6
–
–
–
0.75
V
V
2.4 V VDD 3.0 V
2.4 V VDD 2.7 V
2.7 V VDD 3.0 V
VIH1
VIH2
VH
Input high voltage
–
–
–
–
Input high voltage
–
V
Input hysteresis voltage
Input leakage (absolute value)
60
1
mV
IIL
–
nA Gross tested to 1 µA
Document Number: 001-41947 Rev. *P
Page 16 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Table 10. 2.7 V DC GPIO Specifications (continued)
Symbol
CIN
Description
Min
Typ
Max
Units
Notes
Capacitive load on pins as input
0.5
1.7
5
pF Package and pin dependent
temperature = 25 °C
COUT
Capacitive load on pins as output
0.5
1.7
5
pF Package and pin dependent
temperature = 25 °C
DC Analog Mux Bus Specifications
Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 11. DC Analog Mux Bus Specifications
Symbol
RSW
Description
Min
Typ
Max
Units
Notes
Switch resistance to common
analog bus
–
–
400
800
Vdd 2.7 V
2.4 V Vdd 2.7 V
DC Low Power Comparator Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 12. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VREFLPC
Low power comparator (LPC)
reference voltage range
0.2
–
VDD – 1.0
V
ISLPC
LPC supply current
LPC voltage offset
–
–
10
40
30
µA
VOSLPC
2.5
mV
DC POR and LVD Specifications
Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 13. DC POR and LVD Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD is greater than or equal to 2.5 V
during startup, reset from the XRES
pin, or reset from Watchdog.
VPPOR0
VPPOR1
VPPOR2
–
–
–
2.36
2.60
2.82
2.40
2.65
2.95
V
V
V
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
2.39
2.54
2.75
2.85
2.96
–
2.45
2.71
2.92
3.02
3.13
–
2.51[9]
2.78[10]
2.99[11]
3.09
3.20
–
V
V
V
V
V
V
V
V
–
–
–
4.52
4.73
4.83
Notes
9. Always greater than 50 mV above V
10. Always greater than 50 mV above V
11. Always greater than 50 mV above V
(PORLEV = 00) for falling supply.
(PORLEV = 01) for falling supply.
(PORLEV = 10) for falling supply.
PPOR
PPOR
PPOR
Document Number: 001-41947 Rev. *P
Page 17 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
DC Programming Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 14. DC Programming Specifications
Symbol
VDDP
Description
Min
Typ
Max
Units
Notes
VDD for programming and erase
4.5
5
5.5
V
This specification applies to the
functional requirements of external
programmer tools
VDDLV
Low VDD for verify
High VDD for verify
2.4
5.1
2.7
2.5
5.2
–
2.6
5.3
V
V
V
This specification applies to the
functional requirements of external
programmer tools
VDDHV
This specification applies to the
functional requirements of external
programmer tools
VDDIWRITE Supply voltage for flash write
operation
5.25
Thisspecificationappliestothisdevice
when it is executing internal flash
writes
IDDP
VILP
VIHP
IILP
Supply current during
programming or verify
–
–
5
–
–
–
25
0.8
–
mA
V
Input low voltage during
programming or verify
Input high voltage during
programming or verify
2.2
–
V
Input current when applying Vilp
to P1[0] or P1[1] during
programming or verify
0.2
mA Driving internal pull-down resistor.
mA Driving internal pull-down resistor.
IIHP
Input current when applying Vihp
to P1[0] or P1[1] during
programming or verify
–
–
1.5
VOLV
VOHV
Output low voltage during
programming or verify
–
–
–
VSS + 0.75
VDD
V
V
Output high voltage during
programming or verify
VDD – 1.0
FlashENPB Flash endurance (per block)[12]
50,000
–
–
–
–
–
–
Erase/write cycles per block.
Erase/write cycles.
Flash endurance (total)[13]
FlashENT
FlashDR
1,800,000
Flash data retention
10
–
–
Years
DC I2C Specifications
Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 15. DC I2C Specifications[14]
Symbol
VILI2C
Description
Input low level
Min
Typ
–
Max
0.3 × VDD
0.25 × VDD
–
Units
Notes
2.4 V VDD 3.6 V
–
–
V
V
V
–
4.75 V VDD 5.25 V
2.4 V VDD 5.25 V
VIHI2C
Input high level
0.7 × VDD
–
Notes
12. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V
and 4.75 V to 5.25 V.
13. A maximum of 36 × 50,000 block endurance cycles is allowed. This is balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks
of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever
sees more than 50,000 cycles).
2
14. All GPIO meet the DC GPIO V and V specifications found in the DC GPIO Specifications sections. The I C GPIO pins also meet the above specs.
IL
IH
Document Number: 001-41947 Rev. *P
Page 18 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
AC Electrical Characteristics
AC Chip Level Specifications
Table 16 and Table 17 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 16. 5 V and 3.3 V AC Chip-Level Specifications
Symbol
FCPU1
Description
CPU frequency (3.3 V nominal)
ILO frequency
Min
0.75
15
Typ
–
Max
12.6
64
Units
Notes
MHz 12 MHz only for SLIMO Mode = 0
kHz
F32K1
32
–
F32K_U
ILO untrimmed frequency
5
100
kHz After a reset and before the M8C starts
to run, the ILO is not trimmed. See the
System Resets section of the PSoC
Technical Reference Manual for
details on this timing.
FIMO12
IMO stability for 12 MHz
11.4
5.5
12
12.6
6.5
MHz Trimmed for 3.3 V operation using
factory trim values.
(Commercial temperature)[15]
See Figure 8 on page 14,
SLIMO Mode = 0.
FIMO6
IMO stability for 6 MHz
(Commercial temperature)
6.0
MHz Trimmed for 3.3 V operation using
factory trim values.
See Figure 8 on page 14,
SLIMO Mode = 1.
DCIMO
DCILO
Duty cycle of IMO
ILO duty cycle
40
20
0
50
50
–
60
80
–
%
%
tRAMP
Supply ramp time
External reset pulse width
µs
µs
tXRST
10
–
–
–
tPOWERUP
Time from end of POR to CPU
executing code
16
100
ms Power up from 0 V. See the System
Resets section of the PSoC Technical
Reference Manual.
[16]
tjit_IMO
12 MHz IMO cycle-to-cycle jitter
(RMS)
–
–
–
200
600
100
1600
1400
900
ps
12 MHz IMO long term N
cycle-to-cycle jitter (RMS)
ps N = 32
ps
12 MHz IMO period jitter (RMS)
Notes
15. 0 °C to 70 °C ambient, VDD = 3.3 V.
16. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information.
Document Number: 001-41947 Rev. *P
Page 19 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Table 17. 2.7 V AC Chip Level Specifications
Symbol
FCPU1A
FCPU1B
F32K1
Description
Min
0.75
0.75
8
Typ
–
Max
3.25
6.3
96
Units
Notes
CPU frequency (2.7 V nominal)
CPU frequency (2.7 V minimum)
ILO frequency
MHz 2.4 V < VDD < 3.0 V.
MHz 2.7 V < VDD < 3.0 V.
kHz
–
32
–
F32K_U
ILO untrimmed frequency
5
–
kHz After a reset and before the M8C starts
to run, the ILO is not trimmed. See the
System Resets section of the PSoC
Technical Reference Manual for
details on this timing.
FIMO12
IMO stability for 12 MHz
11.0
5.5
12
12.9
6.5
MHz Trimmed for 2.7 V operation using
factory trim values. See Figure 8 on
page 14, SLIMO Mode = 0.
(Commercial temperature)[17]
FIMO6
IMO stability for 6 MHz
(Commercial temperature)
6.0
MHz Trimmed for 2.7 V operation using
factory trim values.
See Figure 8 on page 14,
SLIMO Mode = 1.
DCIMO
DCILO
Duty cycle of IMO
ILO duty cycle
40
20
0
50
50
–
60
80
–
%
%
tRAMP
Supply ramp time
External reset pulse width
µs
µs
tXRST
10
–
–
–
tPOWERUP
16
100
ms Power-up from 0 V. See the System
Resets section of the PSoC Technical
Reference Manual.
[18]
tjit_IMO
12 MHz IMO cycle-to-cycle jitter
(RMS)
–
–
–
500
800
300
900
1400
500
ps
12 MHz IMO long term N
cycle-to-cycle jitter (RMS)
ps N = 32
ps
12 MHz IMO period jitter (RMS)
Notes
17. 0 °C to 70 °C ambient, VDD = 3.3 V.
18. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information.
Document Number: 001-41947 Rev. *P
Page 20 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
AC GPIO Specifications
Table 18 an d Table 19 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 18. 5 V and 3.3 V AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
6
Units
Notes
GPIO operating frequency
MHz Normal strong mode, Port 1.
tRise023
tRise1
tFall
Rise time, strong mode,
Cload = 50 pF,
15
–
80
ns VDD = 3.0 V to 3.6 V and 4.75 V to
5.25 V, 10% to 90%
ports 0, 2, 3
Rise time, strong mode,
Cload = 50 pF,
port 1
10
10
–
–
50
50
ns VDD = 3.0 V to 3.6 V, 10% to 90%
Fall time, strong mode,
Cload = 50 pF,
all ports
ns VDD = 3.0 V to 3.6 V and 4.75 V to
5.25 V, 10% to 90%
Table 19. 2.7 V AC GPIO Specifications
Symbol
FGPIO
Description
Min
Typ
Max
Units
Notes
GPIO operating frequency
0
–
1.5
MHz Normal Strong Mode, Port 1.
tRise023
tRise1
tFall
Rise time, strong mode,
Cload = 50 pF,
15
10
10
–
–
–
100
70
ns VDD = 2.4 V to 3.0 V, 10% to 90%
ports 0, 2, 3
Rise time, strong mode,
Cload = 50 pF,
port 1
ns VDD = 2.4 V to 3.0 V, 10% to 90%
ns VDD = 2.4 V to 3.0 V, 10% to 90%
Fall time, strong mode,
Cload = 50 pF,
all ports
70
Figure 9. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TFall
TRise023
TRise1
AC Comparator Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 20. AC Comparator Specifications
Symbol
tCOMP
Description
Min
Typ
Max
Units
ns VDD 3.0 V
Notes
Comparator response time,
50 mV overdrive
–
–
100
200
ns 2.4 V < VCC <3.0 V
Document Number: 001-41947 Rev. *P
Page 21 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
AC Low Power Comparator Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 21. AC Low Power Comparator Specifications
Symbol
tRLPC
Description
LPC response time
Min
Typ
Max
Units
Notes
–
–
50
µs 50 mV overdrive comparator
reference set within VREFLPC
.
AC External Clock Specifications
Table 22, Table 23, and Table 24 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges:
4.75 V to 5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 22. 5 V AC External Clock Specifications
Symbol
Description
Frequency
Min
0.750
38
Typ
–
Max
12.6
5300
–
Units
MHz
ns
Notes
FOSCEXT
–
–
–
High period
–
Low period
38
–
ns
Power-up IMO to switch
150
–
–
µs
Table 23. 3.3 V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT
Frequency with CPU clock divide
by 1
0.750
–
12.6
MHz MaximumCPUfrequency is12 MHzat
3.3 V. With the CPU clock divider set
to 1, the external clock must adhere to
the maximum frequency and duty
cycle requirements.
–
–
–
Highperiod withCPUclockdivide
by 1
41.7
41.7
150
–
–
–
5300
ns
ns
µs
Low period with CPU clock divide
by 1
–
–
Power-up IMO to switch
Table 24. 2.7 V AC External Clock Specifications
Symbol Description
Min
Typ
Max
Units
Notes
FOSCEXT1A Frequency with CPU clock divide
by 1 (2.7 V nominal)
0.75
–
3.080
MHz 2.4 V < VDD < 3.0 V. Maximum CPU
frequency is 3 MHz at 2.7 V. With the
CPU clock divider set to 1, the external
clock must adhere to the maximum
frequency and duty cycle
requirements.
FOSCEXT1B Frequency with CPU clock divide
by 1 (2.7 V minimum)
0.75
1.5
–
–
6.30
6.35
MHz 2.7 V < VDD < 3.0 V. Maximum CPU
frequency is 3 MHz at 2.7 V. With the
CPU clock divider set to 1, the external
clock must adhere to the maximum
frequency and duty cycle
requirements.
FOSCEXT2A Frequency with CPU clock divide
by 2 or greater (2.7 V nominal)
MHz 2.4 V < VDD < 3.0 V. If the frequency of
the external clock is greater than
3 MHz, the CPU clock divider is set to
2 or greater. In this case, the CPU
clock divider ensures that the fifty
percent duty cycle requirement is met.
Document Number: 001-41947 Rev. *P
Page 22 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Table 24. 2.7 V AC External Clock Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
Notes
FOSCEXT2B Frequency with CPU clock divide
by 2 or greater (2.7 V minimum)
1.5
–
12.6
MHz 2.7 V < VDD < 3.0 V. If the frequency of
the external clock is greater than
3 MHz, the CPU clock divider is set to
2 or greater. In this case, the CPU
clock divider ensures that the fifty
percent duty cycle requirement is met.
–
–
–
Highperiod withCPUclockdivide
by 1
160
160
150
–
–
–
5300
ns
ns
µs
Low period with CPU clock divide
by 1
–
–
Power-up IMO to switch
AC Programming Specifications
Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 25. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
Description
Rise time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
Fall time of SCLK
1
–
ns
Data set up time to falling edge of
SCLK
40
–
ns
tHSCLK
Data hold time from falling edge
of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
–
–
–
10
40
–
8
–
MHz
ms
tERASEB
tWRITE
tDSCLK
Flash erase time (Block)
Flash block write time
–
ms
Data out delay from falling edge
of SCLK
45
ns 3.6 VDD
tDSCLK3
Data out delay from falling edge
of SCLK
–
–
–
–
–
–
–
50
70
ns 3.0 VDD 3.6
ns 2.4 VDD 3.0
tDSCLK2
Data out delay from falling edge
of SCLK
tERASEALL
tPROGRAM_HOT
Flash erase time (Bulk)
20
–
–
ms Erase all blocks and protection
fields at once
Flash block erase + Flash block
write time
100
200
ms 0 °C Tj 100 °C
tPROGRAM_COLD Flash block erase + Flash block
write time
–
ms –40 °C Tj 0 °C
Document Number: 001-41947 Rev. *P
Page 23 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
AC I2C Specifications
Table 26 and Table 27 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 26. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V
Standard Mode
Fast Mode
Symbol
FSCLI2C
Description
Units
Notes
Min
Max
Min
Max
SCL clock frequency
0
100
0
400
kHz
µs
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
tHDSTAI2C
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
µs
µs
µs
tLOWI2C
tHIGHI2C
tSUSTAI2C
Setup time for a repeated START
condition
Data hold time
0
–
–
–
–
0
100[19]
0.6
–
–
–
–
µs
ns
µs
µs
tHDDATI2C
tSUDATI2C
tSUSTOI2C
tBUFI2C
Data setup time
250
4.0
4.7
Setup time for STOP condition
Bus free time between a STOP
and START condition
1.3
Pulse width of spikes are
suppressed by the input filter
–
–
0
50
ns
tSPI2C
Table 27. 2.7 V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not supported)
Standard Mode
Fast Mode
Symbol
FSCLI2C
Description
Units
Notes
Min
Max
Min
Max
SCL clock frequency
0
100
–
–
–
kHz
µs
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
4.0
–
–
tHDSTAI2C
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
–
–
–
–
–
–
–
–
–
µs
µs
µs
tLOWI2C
tHIGHI2C
tSUSTAI2C
Setup time for a repeated START
condition
Data hold time
0
–
–
–
–
–
–
–
–
–
–
–
–
µs
ns
µs
µs
tHDDATI2C
tSUDATI2C
tSUSTOI2C
tBUFI2C
Data setup time
250
4.0
4.7
Setup time for STOP condition
Bus free time between a STOP
and START condition
Pulse width of spikes are
suppressed by the input filter.
–
–
–
–
ns
tSPI2C
Note
2
2
19. A Fast Mode I C bus device is used in a Standard Mode I C bus system but the requirement T
250 ns is met. This automatically is the case if the device does
SUDAT
not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax +
2
T
= 1000 + 250 = 1250 ns (according to the Standard Mode I C bus specification) before the SCL line is released.
SUDAT
Document Number: 001-41947 Rev. *P
Page 24 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Figure 10. Definition for Timing for Fast or Standard Mode on the I2C Bus
I2C_SDA
I2C_SCL
TSUDATI2C
THDSTAI2C
TSPI2C
TSUSTAI2C
TBUFI2C
THDDATI2C
THIGHI2C TLOWI2C
TSUSTOI2C
P
S
S
Sr
STOP Condition
START Condition
Repeated START Condition
AC SPI Specifications
Table 28. SPI Master AC Specifications
Symbol
FSCLK
Description
SCLK clock frequency
SCLK duty cycle
Conditions
Min
–
Typ
–
Max
Units
MHz
%
12
–
DC
–
50
–
tSETUP
tHOLD
tOUT_VAL
tOUT_H
MISO to SCLK setup time
SCLK to MISO hold time
SCLK to MOSI valid time
MOSI high time
40
40
–
–
ns
–
–
ns
–
40
–
ns
40
–
ns
Table 29. SPI Slave AC Specifications
Symbol
FSCLK
Description
SCLK clock frequency
SCLK low time
Conditions
Min
Typ
–
Max
4
Units
MHz
ns
–
41.67
41.67
30
tLOW
–
–
tHIGH
SCLK high time
–
–
ns
tSETUP
tHOLD
tSS_MISO
MOSI to SCLK setup time
SCLK to MOSI hold time
SS high to MISO valid
–
–
ns
50
–
–
ns
–
–
153
125
50
–
ns
tSCLK_MISO SCLK to MISO valid
–
–
ns
tSS_HIGH
tSS_CLK
tCLK_SS
SS high time
–
–
ns
Time from SS low to first SCLK
2/SCLK
2/SCLK
–
ns
Time from last SCLK to SS high
–
–
ns
Document Number: 001-41947 Rev. *P
Page 25 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Ordering Information
Table 30 lists the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC devices key package features and ordering codes.
Table 30. PSoC Device Key Features and Ordering Information
Maximum Maximum Maximum Configurable
Flash SRAM
(Bytes) (Bytes)
Proximity
Sensing
Package
Ordering Code
Numberof Numberof Numberof LED Behavior
Buttons
Sliders
LEDs
(Fade, Strobe)
16-pin (3 × 3 mm 0.60 CY8C20224-12LKXI
Max) COL
8K
8K
512
512
10
1
13
Yes
Yes
Yes
16-pin (3 × 3 mm 0.60 CY8C20224-12LKXIT
Max) COL (Tape and
Reel)
10
1
13
Yes
24-pin (4 × 4 mm 0.60 CY8C20324-12LQXI
Max) QFN
8K
8K
512
512
17
17
1
1
20
20
Yes
Yes
Yes
Yes
24-pin (4 × 4 mm 0.60 CY8C20324-12LQXIT
Max) QFN (Tape and
Reel)
28-pin (210-Mil) SSOP CY8C20524-12PVXI
8K
8K
512
512
21
21
1
1
24
24
Yes
Yes
Yes
Yes
28-pin (210-Mil) SSOP CY8C20524-12PVXIT
(Tape and Reel)
32-pin (5 × 5 mm 0.60 CY8C20424-12LQXI
Max) QFN (Sawn)
8K
8K
512
512
25
25
1
1
28
28
Yes
Yes
Yes
Yes
32-pin (5 × 5 mm 0.60 CY8C20424-12LQXIT
Max) QFN (Sawn)
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 20 xxx - 12 xx
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LKX/LQX = QFN Pb-free
AX = TQFP Pb-free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 12 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-41947 Rev. *P
Page 26 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Packaging Dimensions
This section illustrates the packaging specifications for the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC devices,
along with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 11. 16-pin Chip On-Lead (3 × 3 × 0.6 mm (Sawn)) Package Outline, 001-09116
001-09116 *J
Document Number: 001-41947 Rev. *P
Page 27 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Figure 12. 24-pin QFN ((4 × 4 × 0.6 mm) 2.65 × 2.65 E-Pad (Sawn)) Package Outline, 001-13937
001-13937 *G
Figure 13. 28-pin SSOP (210 Mils) Package Outline, 51-85079
51-85079 *F
Document Number: 001-41947 Rev. *P
Page 28 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Figure 14. 32-pin QFN ((5 × 5 × 0.6 mm) 1.3 × 2.7 E-Pad (Sawn Type)) Package Outline, 001-48913
001-48913 *E
Figure 15. 48-pin QFN ((7 × 7 × 1.0 mm) 5.1 × 5.1 E-Pad (Subcon Punch Type Package)) Package Outline, 001-12919
001-12919 *D
Important For information on the preferred dimensions for mounting the QFN packages, see the following application note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
It is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.
Document Number: 001-41947 Rev. *P
Page 29 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Thermal Impedances
Table 31. Thermal Impedances Per Package
[20]
Package
16-pin COL
24-pin QFN[21]
28-pin SSOP
32-pin QFN[21]
48-pin QFN[21]
Typical JA
46 °C/W
25 °C/W
96 °C/W
27 °C/W
28 °C/W
Solder Reflow Specifications
Table 32 lists the minimum solder reflow peak temperature to achieve good solderability.
Table 32. Solder Reflow Specifications
Package
16-pin COL
24-pin QFN
28-pin SSOP
32-pin QFN
48-pin QFN
Maximum Peak Temperature
Time at Maximum Peak Temperature
260 °C
260 °C
260 °C
260 °C
260 °C
30 s
30 s
30 s
30 s
30 s
Notes
20. T = T + Power x
J
A
JA.
21. To achieve the thermal impedance specified for the QFN package, the center thermal pad is soldered to the PCB ground plane.
Document Number: 001-41947 Rev. *P
Page 30 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Evaluation Tools
Development Tool Selection
Software
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
PSoC Designer
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for over half a
decade. PSoC Designer is available free of charge at
http://www.cypress.com.
■ MiniProg Programming Unit
■ MiniEval Socket Programming and Evaluation Board
■ 28-pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge
at http://www.cypress.com.
■ Getting Started Guide
■ USB 2.0 Cable
Development Kits
CY3210-PSoCEval1
All development kits are sold at the Cypress Online Store.
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ PSoC Designer Software CD
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ USB 2.0 Cable
CY3214-PSoCEvalUSB
■ Mini-Eval Programming Board
■ 110 ~ 240 V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration required)
■ ISSP Cable
The CY3214-PSoCEvalUSB evaluation kit features
a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■ USB 2.0 Cable and Blue Cat-5 Cable
■ Two CY8C29466-24PXI 28-PDIP Chip Samples
■ PSoCEvalUSB Board
■ LCD Module
■ MIniProg Programming Unit
■ Mini USB Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Document Number: 001-41947 Rev. *P
Page 31 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
CY3207ISSP In-System Serial Programmer (ISSP)
Device Programmers
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
All device programmers are purchased from the Cypress Online
Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ 110 ~ 240 V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ Modular Programmer Base
■ Three Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
Accessories (Emulation and Programming)
Table 33. Emulation and Programming Accessories
Prototyping
Part Number
Pin Package
16-pin COL Not available
24-pin QFN CY3250-20334QFN CY3250-24QFN-FK
Flex-Pod Kit [22]
Foot Kit [23]
Adapter [24]
Module
CY8C20224-12LKXI
CY8C20324-12LQXI
CY8C20524-12PVXI
Not available
CY3210-20X34
CY3210-20X34
–
AS-24-28-01ML-6
–
28-pin SSOP CY3250-20534
CY3250-28SSOP-FK CY3210-20X34
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools are specially designed by the following third party
vendors to accompany PSoC devices during development and
production. Specific details of each of these tools are found at
http://www.cypress.com under DESIGN RESOURCES >>
Evaluation Boards.
For details on emulating the circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, refer application note AN2323 “Build a PSoC Emulator
into Your Board”.
Notes
22. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
23. Foot kit includes surface mount feet that is soldered to the target PCB.
24. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at
http://www.emulation.com.
Document Number: 001-41947 Rev. *P
Page 32 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Acronyms
Acronyms Used
Table 34 lists the acronyms that are used in this document.
Table 34. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
MIPS
OCD
Description
alternating current
million instructions per second
ADC
analog-to-digital converter
on-chip debug
API
application programming interface
PCB
printed circuit board
programmable gain amplifier
power on reset
CMOS complementary metal oxide semiconductor
CPU central processing unit
PGA
POR
EEPROM electrically erasable programmable read-only
memory
PPOR
precision power on reset
GPIO
ICE
general purpose I/O
PSoC® Programmable System-on-Chip
in-circuit emulator
PWM
QFN
pulse width modulator
quad flat no leads
IDAC
IDE
current DAC
integrated development environment
internal low speed oscillator
internal main oscillator
input/output
SLIMO slow IMO
ILO
SPITM
SRAM
SROM
SSOP
USB
serial peripheral interface
IMO
I/O
static random access memory
supervisory read only memory
shrink small-outline package
universal serial bus
ISSP
LCD
LDO
LED
LVD
MCU
in-system serial programming
liquid crystal display
WDT
watchdog timer
light-emitting diode
low voltage detect
microcontroller unit
WLCSP wafer level chip scale package
XRES external reset
Reference Documents
PSoC® CY8C20x34 and PSoC® CY8C20x24 Technical Reference Manual (TRM) – 001-13033
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com.
Document Number: 001-41947 Rev. *P
Page 33 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Document Conventions
Units of Measure
Table 35 lists the units of measures.
Table 35. Units of Measure
Symbol
°C
Unit of Measure
Symbol
ms
ns
Unit of Measure
degree Celsius
picofarad
millisecond
nanosecond
picosecond
microvolts
millivolts
volts
pF
kHz
MHz
k
kilohertz
ps
megahertz
kilohm
µV
mV
V
ohm
µA
microampere
milliampere
nanoampere
microsecond
W
watt
mA
nA
mm
%
millimeter
percent
µs
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
(ADC)
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that
create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
Document Number: 001-41947 Rev. *P
Page 34 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Glossary (continued)
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
compiler
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
(DAC)
converter performs the reverse operation.
duty cycle
emulator
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
Document Number: 001-41947 Rev. *P
Page 35 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Glossary (continued)
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
gain
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with
resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
routine (ISR)
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage
detect (LVD)
A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
Document Number: 001-41947 Rev. *P
Page 36 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Glossary (continued)
modulator
noise
A device that imposes a signal on a carrier.
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
A circuit that may be crystal controlled and is used to generate a clock frequency.
oscillator
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoCDesigner™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
reset
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
shift register
slave device
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
Document Number: 001-41947 Rev. *P
Page 37 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Glossary (continued)
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning “voltage drain”. The most positive power supply signal. Usually 5 V or 3.3 V.
A name for a power net meaning “voltage source”. The most negative power supply signal.
VSS
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 001-41947 Rev. *P
Page 38 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Document History Page
Document Title: CY8C20224/CY8C20324/CY8C20424/CY8C20524, CapSense PSoC Programmable System-on-Chip
Document Number: 001-41947
Submission
Revision
ECN
Description of Change
Date
**
1734104
2542938
11/14/2007 New parts and document (Revision **).
*A
07/28/2008 Updated Packaging Dimensions:
spec 001-13937 – Changed revision from *A to *B.
Updated to new template.
*B
*C
2610469
2634376
11/20/2008 Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC GPIO Specifications:
Updated Table 9 (Updated details in “Min”, “Typ” and “Max” columns corresponding to VOH5
,
VOH7, and VOH9 parameters).
01/12/2009 Updated Document Title to read as “CY8C20224/CY8C20324/CY8C20424/CY8C20524,
CapSense™ Multimedia PSoC® Programmable System-on-Chip™”.
Changed status from Preliminary to Final.
Updated Development Tools:
Updated description; and also removed figure “PSoC Designer Subsystems”.
Updated PSoC Designer Software Subsystems:
Removed “Device Editor”.
Removed “Design Browser”.
Added “System-Level View”.
Added “Chip-Level View”.
Added “Hybrid Designs”.
Updated Code Generation Tools:
Replaced “Application Editor” with “Code Generation Tools” in heading; and also updated
description.
Removed “Designing with User Modules”.
Added “Designing with PSoC Designer”.
Updated Development Tool Selection:
Updated Software:
Removed “PSoC Express™”.
Updated C Compilers:
Replaced “CY3202-C iMAGEcraft C Compiler” with “C Compilers” in heading; and also
updated description.
Updated Accessories (Emulation and Programming):
Updated Table 33 (Updated details in “Pin Package”, “Flex-Pod Kit” and “Foot Kit” columns
corresponding to CY8C20224-12LKXI).
Updated Ordering Information:
Updated part numbers.
*D
2693024
04/16/2009 Updated Ordering Information:
Updated part numbers.
Updated Packaging Dimensions:
Added spec 001-48913 *A.
Document Number: 001-41947 Rev. *P
Page 39 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Document History Page (continued)
Document Title: CY8C20224/CY8C20324/CY8C20424/CY8C20524, CapSense PSoC Programmable System-on-Chip
Document Number: 001-41947
Submission
Revision
ECN
Description of Change
Date
*E
2717566
06/11/2009 Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC GPIO Specifications:
Updated Table 9 (Added IOH2, IOH4, IOL parameters and their corresponding details).
Updated DC Programming Specifications:
Updated Table 14 (Added Note 12 and referred the same note in description of FlashENPB
parameter).
Updated AC Electrical Characteristics:
Updated AC Chip Level Specifications:
Updated Table 16 (Updated details in “Min”, “Typ” and “Max” columns corresponding to
F
IMO6 parameter; added F32K_U, DCILO, TPOWERUP parameters and their corresponding
details).
Updated Table 17.
Updated AC Programming Specifications:
Updated Table 25 (Updated details in “Min”, “Typ” and “Max” columns corresponding to
T
WRITE parameter; added TERASEALL, TPROGRAM_HOT, TPROGRAM_COLD parameters and
their corresponding details).
Updated AC SPI Specifications:
Removed table “5V and 3.3V AC SPI Specifications”.
Removed table “2.7V AC SPI Specifications”.
Added Table 28.
Added Table 29.
*F
2899195
03/26/2010 Updated Packaging Dimensions:
spec 001-09116 – Changed revision from *D to *E.
spec 001-13937 – Changed revision from *B to *C.
spec 51-85079 – Changed revision from *C to *D.
Removed spec 001-06392 *A.
spec 001-48913 – Changed revision from *A to *B.
spec 001-12919 – Changed revision from *A to *B.
Updated Ordering Information:
Updated part numbers.
*G
*H
3037121
3049675
09/24/2010 Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC Comparator Specifications:
Replaced “AC Comparator Amplifier Specifications” with “AC Comparator Specifications” in
heading.
Updated Table 20 (updated table caption only to read as “AC Comparator Specifications”).
Minor edits across the document.
Updated to new template.
10/06/2010 Updated Development Tools:
Updated description.
Updated PSoC Designer Software Subsystems:
Removed “System-Level View”.
Removed “Chip-Level View”.
Removed “Hybrid Designs”.
Added “Design Entry”.
Document Number: 001-41947 Rev. *P
Page 40 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Document History Page (continued)
Document Title: CY8C20224/CY8C20324/CY8C20424/CY8C20524, CapSense PSoC Programmable System-on-Chip
Document Number: 001-41947
Submission
Revision
ECN
Description of Change
Date
*H (cont.)
3049675
10/06/2010 Updated Designing with PSoC Designer:
Updated description.
Updated Select User Modules:
Replaced “Select Components” with “Select User Modules” in heading; and also updated
description.
Updated Configure User Modules:
Replaced “Configure Components” with “Configure User Modules” in heading; and also
updated description.
Updated Organize and Connect:
Updated description.
Updated Generate, Verify, and Debug:
Updated description.
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Removed “AC Analog Mux Bus Specifications”.
*I
3072668
10/27/2010 Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Added “DC I2C Specifications”.
Updated AC Electrical Characteristics:
Updated AC Chip Level Specifications:
Updated Table 16 (Added value in “Max” column corresponding to F32K_U parameter; added
Tjit_IMO parameter and its corresponding details).
Updated Table 17 (Added Tjit_IMO parameter and its corresponding details).
Updated AC I2C Specifications:
Updated Figure 10 (for clearer understanding).
Updated Packaging Dimensions:
No change in revisions.
Updated Solder Reflow Specifications:
Updated Table 32 (Removed “Minimum Peak Temperature” column and added “Time at
Maximum Temperature” column).
Added Reference Documents.
Added Glossary.
Updated to new template.
*J
*K
*L
3112469
3182773
3638597
12/16/2010 Updated Ordering Information:
Updated part numbers.
03/01/2011 No technical updates.
Completing Sunset Review.
06/06/2012 Updated Getting Started:
Updated description.
Updated Application Notes:
Updated description.
Updated Development Kits:
Updated description.
Updated Training:
Updated description.
Updated CYPros Consultants:
Updated description.
Updated Solutions Library:
Updated description.
Updated Technical Support:
Updated description.
Document Number: 001-41947 Rev. *P
Page 41 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
Document History Page (continued)
Document Title: CY8C20224/CY8C20324/CY8C20424/CY8C20524, CapSense PSoC Programmable System-on-Chip
Document Number: 001-41947
Submission
Revision
ECN
Description of Change
Date
*L (cont.)
3638597
06/06/2012 Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC SPI Specifications:
Updated Table 28:
Renamed “tOUT_HIGH” as “tOUT_H” in “Symbol” column.
Updated Table 29:
Removed tSCLK parameter and its details.
Added FSCLK parameter and its details.
Updated Packaging Dimensions:
spec 001-09116 – Changed revision from *E to *F.
spec 001-13937 – Changed revision from *C to *D.
spec 51-85079 – Changed revision from *D to *E.
spec 001-12919 – Changed revision from *B to *C.
Updated Solder Reflow Specifications:
Updated Table 32:
Replaced “Time at Maximum Temperature” with “Time at Maximum Peak Temperature” in
column heading and updated details in that column.
Updated Development Tool Selection:
Updated Software:
Updated PSoC Designer:
Updated description.
Updated PSoC Designer:
Updated description.
Updated Reference Documents:
Removed spec 001-17397 and spec 001-14503 from the list as these specs are obsolete.
*M
*N
4311264
5625819
03/19/2014 Updated Designing with PSoC Designer:
Updated Configure User Modules:
Updated description (Replaced references of PWM User Module with EzI2Cs User Module).
Updated Packaging Dimensions:
spec 001-09116 – Changed revision from *F to *J.
spec 001-13937 – Changed revision from *D to *E.
spec 001-48913 – Changed revision from *B to *D.
spec 001-12919 – Changed revision from *C to *D.
02/09/2017 Updated Packaging Dimensions:
spec 001-13937 – Changed revision from *E to *F.
spec 51-85079 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*O
*P
5988009
6659978
12/08/2017 Updated Cypress Logo and Copyright.
08/22/2019 Updated Document Title to read as “CY8C20224/CY8C20324/CY8C20424/CY8C20524,
CapSense PSoC Programmable System-on-Chip”.
Updated Packaging Dimensions:
spec 001-13937 – Changed revision from *F to *G.
spec 001-48913 – Changed revision from *D to *E.
Updated to new template.
Document Number: 001-41947 Rev. *P
Page 42 of 43
CY8C20224/CY8C20324
CY8C20424/CY8C20524
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© Cypress Semiconductor Corporation, 2008–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
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OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-41947 Rev. *P
Revised August 22, 2019
Page 43 of 43
相关型号：
CY8C20334-12LKXI
Multifunction Peripheral, CMOS, 4 X 4 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16
CYPRESS
CY8C20334-12LKXIT
Multifunction Peripheral, CMOS, 4 X 4 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16
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CY8C20336-24LQXI
MULTIFUNCTION PERIPHERAL, QCC24, 4 X 4 MM, 0.60 MM HEIGHT, MO-248, QFN-24
ROCHESTER
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