CY8C4013SXI-410T [INFINEON]
32位PSoC™ 4 Arm® Cortex®-M0/M0+;
| 型号： | CY8C4013SXI-410T |
| 厂家： | 
Infineon |
| 描述： | 32位PSoC™ 4 Arm® Cortex®-M0/M0+ |
| 文件： | 总37页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PSoC® 4: PSoC 4000 Family
Datasheet
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a combination of a microcontroller with
standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, and
general-purpose analog. PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applica-
tions and design needs.
Features
32-bit MCU Subsystem
Timing and Pulse-Width Modulation
■ 16-MHz Arm Cortex-M0 CPU
■ Up to 16 KB of flash with Read Accelerator
■ Up to 2 KB of SRAM
■ One 16-bit timer/counter/pulse-width modulator (TCPWM)
block
■ Center-aligned, Edge, and Pseudo-Random modes
■ Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Programmable Analog
■ Two current DACs (IDACs) for general-purpose or capacitive
sensing applications
Up to 20 Programmable GPIO Pins
■ One low-power comparator with internal reference
■ 28-pin SSOP, 24-pin QFN, 16-pin SOIC, 16-pin QFN, 16 ball
■ Limited ADC function provided by capacitance sensing block
WLCSP, and 8-pin SOIC packages
■ GPIO pins on Ports 0, 1, and 2 can be CapSense or have other
functions
Low Power 1.71-V to 5.5-V operation
■ Deep Sleep mode with wake-up on interrupt and I2C address
■ Drive modes, strengths, and slew rates are programmable
detect
PSoC Creator Design Environment
Capacitive Sensing
■ Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) and water tolerance
■ Cypress-supplied software component makes capacitive
sensing design easy
■ Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
■ Automatic hardware tuning (SmartSense™) over a sensor
Industry-Standard Tool Compatibility
range of 5 pF to 45 pF
■ After schematic entry, development can be done with
Arm-based industry-standard development tools
Serial Communication
■ Multi-master I2C block with the ability to do address matching
during Deep Sleep and generate a wake-up on match
Cypress Semiconductor Corporation
Document Number: 001-89638 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 15, 2021
PSoC® 4: PSoC 4000 Family
Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
■ Overview: PSoC Portfolio, PSoC Roadmap
❐ AN73854: Introduction To Bootloaders
❐ AN89610: Arm Cortex Code Optimization
■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
■ Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PSoC 4 functional block.
❐ Registers TRM describes each of the PSoC 4 registers.
■ Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
■ Development Kits:
❐ CY8CKIT-040,PSoC4000PioneerKit, isaneasy-to-useand
inexpensivedevelopmentplatformwithdebuggingcapability.
ThiskitincludesconnectorsforArduino™compatibleshields
and Digilent® Pmod™ daughter cards.
❐ The MiniProg3 device provides an interface for flash
programming and debug.
❐ AN79953: Getting Started With PSoC 4
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN86439: Using PSoC 4 GPIO Pins
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN81623: Digital Design Best Practices
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
system design in the main design workspace
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Creator IDE C compiler
Figure 1. Example Project in PSoC Creator
Document Number: 001-89638 Rev. *K
Page 2 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem..................................... 5
System Resources ...................................................... 5
Analog Blocks.............................................................. 6
Fixed Function Digital.................................................. 6
GPIO ........................................................................... 6
Special Function Peripherals....................................... 6
Pinouts .............................................................................. 7
Power............................................................................... 12
Unregulated External Supply..................................... 12
Regulated External Supply........................................ 12
Development Support .................................................... 13
Documentation .......................................................... 13
Online........................................................................ 13
Tools.......................................................................... 13
Electrical Specifications ................................................ 14
Absolute Maximum Ratings....................................... 14
Device Level Specifications....................................... 14
Analog Peripherals.................................................... 17
Digital Peripherals ..................................................... 20
Memory ..................................................................... 21
System Resources.................................................... 21
Ordering Information...................................................... 24
Part Numbering Conventions .................................... 24
Packaging........................................................................ 26
Package Outline Drawings........................................ 27
Acronyms........................................................................ 32
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Revision History ............................................................. 35
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support....................... 36
Products.................................................................... 36
PSoC® Solutions ...................................................... 36
Cypress Developer Community................................. 36
Technical Support ..................................................... 36
Document Number: 001-89638 Rev. *K
Page 3 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure 2. Block Diagram
CPU Subsystem
PSoC 4000
SWD/TC
Cortex
M0
16 MHz
MUL
SPCIF
Flash
16KB
SRAM
2KB
ROM
4KB
32-bit
AHB-Lite
Read Accelerator
SRAM Controller
ROM Controller
NVIC, IRQMX
System Resources
Lite
System Interconnect (
)
Single/Multi Layer AHB
Power
Sleep Control
WIC
Peripherals
POR
PWRSYS
REF
PCLK
Peripheral Interconnect (MMIO)
Clock
Clock Control
WDT
IMO
ILO
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
Power Modes
Active/ Sleep
Deep Sleep
High Speed I/O Matrix
20 x GPIOs
I/O Subsystem
PSoC 4000 devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The debug circuits are enabled by default and can only be
disabled in firmware. If they are not enabled, the only way to
re-enable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables debugging.
The Arm Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000 allows the
customer to make.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000 devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000 family provides a level of security not
possible with multi-chip application solutions or with microcon-
trollers. It has the following advantages:
■ Allows disabling of debug features
■ Robust flash protection
■ Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 001-89638 Rev. *K
Page 4 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Clock System
Functional Definition
CPU and Memory Subsystem
CPU
The PSoC 4000 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that there are no metastable conditions.
The Cortex-M0 CPU in the PSoC 4000 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
the CPU executes a subset of the Thumb-2 instruction set. This
enables fully compatible, binary, upward migration of the code to
higher performance processors, such as the Cortex-M3 and M4.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from the
Deep Sleep mode, allowing power to be switched off to the main
processor when the chip is in the Deep Sleep mode. The CPU
subsystem also includes a 24-bit timer called SYSTICK, which
can generate an interrupt.
The clock system for the PSoC 4000 consists of the internal main
oscillator (IMO) and the internal low-frequency oscillator (ILO)
and provision for an external clock.
Figure 3. PSoC 4000 MCU Clocking Architecture
IMO
FCPU
Divide By
2,4, 8
External Clock
(connects to GPIO pin P 0.4)
LFCLK
ILO
WDT
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG. The debug
configuration used for PSoC 4000 has four breakpoint (address)
comparators and two watchpoint (data) comparators.
The FCPU signal can be divided down to generate synchronous
clocks for the analog and digital peripherals. There are four clock
dividers for the PSoC 4000, each with 16-bit divide capability The
16-bit capability allows flexible generation of fine-grained
frequency values and is fully supported in PSoC Creator.
Flash
The PSoC 4000 device has a flash module with a flash accel-
erator, tightly coupled to the CPU to improve average access
times from the flash block. The low-power flash block is designed
to deliver zero wait-state (WS) access time at 16 MHz.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4000. It is trimmed during testing to achieve the specified
accuracy. The IMO default frequency is 24 MHz. It can be
adjusted to 24 or 32 MHz. The IMO tolerance with
Cypress-provided calibration settings is ±2% (24 and 32 MHz).
SRAM
Two KB of SRAM are provided with zero wait-state access at
16 MHz.
ILO Clock Source
SROM
The ILO is a very low power, 40-kHz oscillator, which is primarily
used to generate clocks for the watchdog timer (WDT) and
peripheral operation in Deep Sleep mode. ILO-driven counters
can be calibrated to the IMO to improve accuracy.
Asupervisory ROM that contains boot and configuration routines
is provided.
System Resources
Watchdog Timer
Power System
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
The power system is described in detail in the section on Power
on page 12. It provides an assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000 operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000 provides Active,
Sleep, and Deep Sleep low-power modes.
Reset
The PSoC 4000 can be reset from a variety of sources including
a software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the reset. An XRES pin is reserved for
external reset on the 24-pin package. An internal POR is
provided on the 16-pin and 8-pin packages. The XRES pin has
an internal pull-up resistor that is always enabled. Reset is Active
Low.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with instan-
taneous wake-up on a wake-up event. In Deep Sleep mode, the
high-speed clock and associated circuitry is switched off;
wake-up from this mode takes 35 µS.
Voltage Reference
The PSoC 4000 reference system generates all internally
required references. A1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
Document Number: 001-89638 Rev. *K
Page 5 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
■ GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
■ Fast-mode minimum fall time is not met in Fast Strong mode;
Slow Strong mode can help meet this spec depending on the
Bus Load.
Analog Blocks
Low-power Comparators
The PSoC 4000 has a low-power comparator, which uses the
built-in voltage reference. Any one of up to 16 pins can be used
as a comparator input and the output of the comparator can be
brought out to a pin. The selected comparator input is connected
to the minus input of the comparator with the plus input always
connected to the 1.2-V voltage reference. This comparator is
also used for CapSense purposes and is not available during
CapSense operation.
GPIO
The PSoC 4000 has up to 20 GPIOs. The GPIO block imple-
ments the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
Current DACs
The PSoC 4000 has two IDACs, which can drive any of up to 16
pins on the chip and have programmable current ranges.
Analog Multiplexed Buses
The PSoC 4000 has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on Ports 0, 1, and 2.
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
■ Selectable slew rates for dV/dt related noise control to improve
The TCPWM block consists of
a
16-bit counter with
EMI
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention.
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (4 for PSoC 4000).
The 28-pin and 24-pin packages have 20 GPIOs. The 16-pin
SOIC has 13 GPIOs. The 16-pin QFN and the 16-ball WLCSP
have 12 GPIOs. The 8-pin SOIC has 5 GPIOs.
Serial Communication Block (SCB)
The PSoC 4000 has a serial communication block, which imple-
ments a multi-master I2C interface.
Special Function Peripherals
CapSense
I2C Mode: The hardware I2C block implements
a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4000 and effectively reduces I2C commu-
nication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
The PSoC 4000 is not completely compliant with the I2C spec in
the following respect:
CapSense is supported in the PSoC 4000 through a CSD block
that can be connected to up to 16 pins through an analog mux
bus via an analog switch (pins on Port 3 are not available for
CapSense purposes). CapSense function can thus be provided
on any available pin or group of pins in a system under software
control. A PSoC Creator component is provided for the
CapSense block to make it easy for the user.
Shield voltage can be driven on another mux bus to provide
water-tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block can also be re-purposed to implement a
limited ADC function, which is only available when not using the
block for capacitive sensing.
Document Number: 001-89638 Rev. *K
Page 6 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Pinouts
All port pins support GPIO. Ports 0, 1, and 2 support CSD CapSense and analog multiplexed bus connections. TCPWM functions and Alternate Functions are multiplexed
with port pins as follows for the five PSoC 4000 packages.
Table 1. Pin Descriptions
28-Pin SSOP
Name
24-Pin QFN
Name
16-Pin QFN
Name
16-Pin SOIC
Name
8-Pin SOIC
Name
Pin
20
Pin
Pin
Pin
Pin
TCPWM Signals Alternate Functions
VSS
21
P0.0/TRIN0
1
2
3
4
5
P0.0/TRIN0
TRIN0:TriggerInput
0
22 P0.1/TRIN1/CMPO
_0
P0.1/TRIN1/CMPO
_0
1
2
P0.1/TRIN1/CMPO
_0
3
4
P0.1/TRIN1/CMPO
_0
TRIN1:TriggerInput
1
CMPO_0: Sense
Comp Out
23
P0.2/TRIN2
P0.2/TRIN2
P0.2/TRIN2
P0.2/TRIN2
TRIN2:TriggerInput
2
24
P0.3/TRIN3
P0.3/TRIN3
TRIN3:TriggerInput
3
25 P0.4/TRIN4/CMPO
_0/EXT_CLK
P0.4/TRIN4/CMPO
_0/EXT_CLK
3
P0.4/TRIN4/CMPO
_0/EXT_CLK
5
P0.4/TRIN4/CMPO
_0/EXT_CLK
2
P0.4/TRIN4/CMPO TRIN4:TriggerInput
CMPO_0: Sense
Comp Out, External
Clock, CMOD Cap
_0/EXT_CLK
4
26
27
28
1
VCCD
VDD
6
7
VCCD
VDD
4
6
7
5
8
VCCD
VDD
6
7
VCCD
VDD
VSS
3
4
5
VCCD
VDD
VSS
VSS
8
VSS
VSS
8
P0.5
9
P0.5
VDDIO
P0.6
9
P0.5
P0.6
2
P0.6
10
11
12
13
14
15
16
P0.6
10
3
P0.7
P0.7
4
P1.0
P1.0
5
P1.1/OUT0
P1.2/SCL
P1.3/SDA
P1.4/UND0
P1.1/OUT0
P1.2/SCL
P1.3/SDA
P1.4/UND0
9
P1.1/OUT0
P1.2/SCL
P1.3/SDA
11
12
13
P1.1/OUT0
P1.2/SCL
P1.3/SDA
6
7
P1.1/OUT0
OUT0: PWM OUT 0
6
10
11
I2C Clock
I2C Data
7
8
UND0: Underflow
Out
9
P1.5/OVF0
17
P1.5/OVF0
OVF0: Overflow Out
10 P1.6/OVF0/UND0/n 18 P1.6/OVF0/UND0/n 12 P1.6/OVF0/UND0/n 14 P1.6/OVF0/UND0/n
P1.6/OVF0/UND0/n
OUT0/CMPO_0
nOUT0:
CMPO_0: Sense
OUT0
/CMPO_0
OUT0
/CMPO_0
OUT0/CMPO_0
OUT0/CMPO_0
Complement of
OUT0, UND0,
OVF0 as above
Comp Out, Internal
[1]
Reset function
Note
1. Must not have load to ground during POR (should be an output).
Document Number: 001-89638 Rev. *K
Page 7 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 1. Pin Descriptions (continued)
28-Pin SSOP
Name
24-Pin QFN
Name
16-Pin QFN
Name
16-Pin SOIC
Name
8-Pin SOIC
Name
Pin
Pin
Pin
Pin
Pin
TCPWM Signals Alternate Functions
11
VSS
[2]
12 No Connect (NC)
13 P1.7/MATCH/EXT_ 19 P1.7/MATCH/EXT_ 13 P1.7/MATCH/EXT_ 15 P1.7/MATCH/EXT_
MATCH: Match Out
External Clock
CLK
P2.0
VSS
CLK
P2.0
CLK
CLK
P2.0
14
15
20
16
16 P3.0/SDA/SWD_IO 21 P3.0/SDA/SWD_IO 14 P3.0/SDA/SWD_IO
1
2
P3.0/SDA/SWD_IO
8
1
P3.0/SDA/SWD_IO
I2C Data, SWD I/O
17 P3.1/SCL/SWD_CL 22 P3.1/SCL/SWD_CL 15 P3.1/SCL/SWD_CL
P3.1/SCL/SWD_CL
K
P3.1/SCL/SWD_CL
K
I2C Clock, SWD
Clock
K
K
K
18
19
P3.2
XRES
23
24
P3.2
XRES
16
P3.2
OUT0:PWM OUT 0
XRES: External
Reset
Descriptions of the Pin functions are as follows:
VDD: Power supply for both analog and digital sections.
VDDIO: Where available, this pin provides a separate voltage domain (see the Power section for details).
VSS: Ground pin.
VCCD: Regulated digital supply (1.8 V ±5%).
Pins belonging to Ports 0, 1, and 2 can all be used as CSD sense or shield pins connected to AMUXBUS A or B. They can also be used as GPIO pins that can be driven by
the firmware, in addition to their alternate functions listed in the Table 1.
Pins on Port 3 can be used as GPIO, in addition to their alternate functions listed above.
The following packages are provided: 28-pin SSOP, 24-pin QFN, 16-pin QFN, 16-pin SOIC, and 8-pin SOIC.
Note
2. This pin is not to be used; it must be left floating.
Document Number: 001-89638 Rev. *K
Page 8 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure 4. 28-Pin SSOP Pinout
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
VSS
27 VDD
26 VCCD
P0.4
P0.3
23 P0.2
22 P0.1
1
2
3
4
5
6
28
25
24
28 SSOP
(Top View)
7
8
9
21
20
P0.0
VSS
P1.6 10
VSS 11
NC 12
P1.7 13
P2.0 14
19 XRES
18 P3.2
17
16
P3.1
P3.0
15 VSS
Figure 5. 24-pin QFN Pinout
24
23
22
21
20
19
18
P0.0
P0.1
1
2
3
4
5
6
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
17
16
15
14
13
QFN
24
P0.2
Top
P0.3
View
P0.4
VCCD
7
8
9
10
11
12
Figure 6. 16-Pin QFN Pinout
16
15
14
13
12
P0.1
P0.2
1
2
3
4
P1.6
P1.3
P1.2
P1.1
QFN
Top
View
16
11
10
9
P0.4
VCCD
5
6
7
8
Document Number: 001-89638 Rev. *K
Page 9 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure 7. 16-Pin SOIC Pinout
P3.0
1
2
3
4
5
6
16
P2.0
P1.7
P1.6
P1.3
P1.2
P3.1
15
14
13
12
11
P0.1
P0.2
P0.4
16-SOIC
Top View
P1.1
VCCD
VDD
VSS
7
8
P0.6
P0.5
10
9
Figure 8. 8-Pin SOIC Pinout
8
P 3.1
P 0.4
1
2
3
4
P 3.0
P 1.6
P 1.1
V S S
-
7
6
5
8 S O IC
T o p V ie w
V C C D
V D D
Document Number: 001-89638 Rev. *K
Page 10 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 2. 16-ball WLCSP Pin Descriptions and Diagram
Alternate
Functions
Pin
Name
TCPWM Signal
Pin Diagram
B4
C3
C4
P3.2
OUT0:PWMOUT0
–
–
Bottom View
P0.2/TRIN2
TRIN2:Trigger Input 2
4
3
2
1
P0.4/TRIN4/CMPO_0/ TRIN4:Trigger Input 4 CMPO_0: Sense
EXT_CLK
Comp Out, Ext.
Clock, CMOD Cap
A
B
C
D
D4
D3
D2
C2
D1
C1
B1
A1
A2
VCCD
VDD
–
–
–
–
VSS
–
–
VDDIO
P0.6
–
–
–
–
P1.1/OUT0
P1.2/SCL
P1.3/SDA
OUT0:PWMOUT0
–
Top View
–
–
I2C Clock
I2C Data
1
2
3
4
P1.6/OVF0/UND0/nO nOUT0:Complement CMPO_0: Sense
A
B
C
D
UT0/CMPO_0
of OUT0, UND0,
OVF0
Comp Out, Internal
Reset function[3]
PIN 1 DOT
B2
P1.7/MATCH/
EXT_CLK
MATCH: Match Out
External Clock
A3
B3
A4
P2.0
–
–
–
–
P3.0/SDA/SWD_IO
P3.1/SCL/SWD_CLK
I2C Data, SWD I/O
I2C Clock, SWD
Clock
Note
3. Must not have load to ground during POR (should be an output).
Document Number: 001-89638 Rev. *K
Page 11 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure9. 16-pinQFNBypassSchemeExample-Unregulated
External Supply
Power
The following power system diagrams (Figure 9 and Figure 10)
show the set of power supply pins as implemented for the
PSoC 4000. The system has one regulator in Active mode for the
digital circuitry. There is no analog regulator; the analog circuits
run directly from the VDD input. There is a separate regulator for
the Deep Sleep mode. The supply voltage range is either 1.8 V
±5% (externally regulated) or 1.8 V to 5.5 V (unregulated exter-
nally; regulated internally) with all functions and circuits
operating over that range.
5. 5V
Power supply connections when 1.8 VDD
1.8 V to 5.5 V
PSoC4000
VDD
1 F
0. 1 F
The VDDIO pin, available in the 16-pin QFN package, provides a
separate voltage domain for the following pins: P3.0, P3.1, and
P3.2. P3.0 and P3.1 can be I2C pins and the chip can thus
communicate with an I2C system, running at a different voltage
(where VDDIO VDD). For example, VDD can be 3.3 V and VDDIO
can be 1.8 V.
VCCD
F
0. 1
1.71 V< VDDIO
VDD
VDDIO
The PSoC 4000 family allows two distinct modes of power supply
operation: Unregulated External Supply and Regulated External
Supply.
0.1
F
VSS
Unregulated External Supply
In this mode, the PSoC 4000 is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4000 supplies the internal logic and the
Regulated External Supply
In this mode, the PSoC 4000 is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator should be disabled in the
firmware. Note that in this mode VDD (VCCD) should never
exceed 1.89 in any condition, including flash programming.
VCCD output of the PSoC 4000 must be bypassed to ground via
an external capacitor (0.1 µF; X5R ceramic or better). The
bypass capacitor should be located as close as possible to the
VCCD pin.
Bypass capacitors must be used from VDD to ground. The typical
practice for systems in this frequency range is to use a capacitor
in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated to design and
obtain optimal bypassing.
An example of a bypass scheme follows (VDDIO is available on
the 16-QFN package).
Figure 10. 16-pin QFN Bypass Scheme Example - Regulated
External Supply
An example of a bypass scheme follows (VDDIO is available on
the 16-QFN package).
Power supply connections when 1.71 VDD 1.89 V
1.71 V to 1.89 V
PSoC 4000
VDD
VCCD
1 F
0.1 F
0.1 F
1.71 V < VDDIO < VDD
VDDIO
VSS
Document Number: 001-89638 Rev. *K
Page 12 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Development Support
The PSoC 4000 family has a rich set of documentation, devel-
opment tools, and online resources to assist you during your
development process. Visit www.cypress.com/go/psoc4 to find
out more.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Documentation
Online
A suite of documentation supports the PSoC 4000 family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4000 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 001-89638 Rev. *K
Page 13 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings[4]
Details/
Conditions
Spec ID#
SID1
Parameter
VDD_ABS
Description
Min
Typ
Max
Units
Digital supply relative to VSS
–0.5
–0.5
–
–
6
V
V
Direct digital core voltage input relative
to VSS
SID2
VCCD_ABS
1.95
SID3
SID4
VGPIO_ABS
IGPIO_ABS
GPIO voltage
–0.5
–25
–
–
VDD+0.5
25
V
Maximum current per GPIO
mA
GPIO injection current, Max for VIH
DD, and Min for VIL < VSS
>
Current injected
per pin
SID5
IGPIO_injection
ESD_HBM
–0.5
–
–
0.5
–
mA
V
V
Electrostatic discharge human body
model
BID44
2200
Electrostatic discharge charged device
model
BID45
BID46
ESD_CDM
LU
500
–
–
–
V
Pin current for latch-up
–140
140
mA
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 4. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Details/
Spec ID#
SID53
Parameter
VDD
Description
Min
Typ
Max
Units
Conditions
With regulator
enabled
Power supply input voltage
1.8
–
5.5
V
Internally
unregulated
supply
Power supply input voltage (VCCD
=
SID255
VDD
1.71
–
1.89
V
VDD
)
SID54
SID55
VDDIO
CEFC
VDDIO domain supply
1.71
–
–
VDD
–
V
External regulator voltage (VCCD
bypass
)
X5R ceramic or
better
0.1
µF
X5R ceramic or
better
SID56
CEXC
Power supply bypass capacitor
–
1
–
µF
Active Mode, VDD = 1.8 to 5.5 V
SID9
IDD5
IDD8
IDD11
Execute from flash; CPU at 6 MHz
–
–
–
2.0
3.2
4.0
2.85
3.75
4.5
mA
mA
mA
SID12
SID16
Execute from flash; CPU at 12 MHz
Execute from flash; CPU at 16 MHz
Sleep Mode, VDD = 1.71 to 5.5 V
SID25
IDD20
I2C wakeup, WDT on. 6 MHz
I2C wakeup, WDT on. 12 MHz
–
–
1.1
1.4
–
–
mA
mA
SID25A
IDD20A
Deep Sleep Mode, VDD = 1.8 to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
–
2.5
8.2
µA
Note
4. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-89638 Rev. *K
Page 14 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 4. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Details/
Conditions
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Deep Sleep Mode, VDD = 3.6 to 5.5 V (Regulator on)
SID34 IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 to 1.89 V (Regulator bypassed)
–
–
–
2.5
2.5
2
12
9.2
5
µA
µA
SID37
IDD32
I2C wakeup and WDT on
XRES Current
SID307
IDD_XR
Supply current while XRES asserted
mA
Table 5. AC Specifications
Details/
Spec ID#
SID48
SID49[5]
SID50[5]
Parameter
FCPU
Description
Min
Typ
Max
Units
Conditions
CPU frequency
DC
–
–
0
16
–
MHz 1.71 VDD 5.5
TSLEEP
Wakeup from Sleep mode
Wakeup from Deep Sleep mode
µs
µs
TDEEPSLEEP
–
35
–
GPIO
Table 6. GPIO DC Specifications (referenced to VDDIO for 16-Pin QFN VDDIO pins)
Details/
Units
Spec ID#
SID57
Parameter
Description
Min
Typ
Max
Conditions
[6]
VIH
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDD < 2.7 V
LVTTL input, VDD < 2.7 V
LVTTL input, VDD 2.7 V
LVTTL input, VDD 2.7 V
0.7 × VDD
–
–
–
–
–
–
–
V
V
V
V
V
V
CMOS Input
CMOS Input
SID58
VIL
VIH
VIL
VIH
VIL
–
0.3 × VDD
[6]
[6]
SID241
SID242
SID243
SID244
0.7× VDD
–
0.3 × VDD
–
–
2.0
–
0.8
I
OH = 4 mA at
SID59
SID60
SID61
SID62
SID62A
VOH
VOH
VOL
VOL
VOL
Output voltage high level
Output voltage high level
Output voltage low level
Output voltage low level
Output voltage low level
VDD –0.6
–
–
–
–
–
–
V
V
V
V
V
3 V VDD
I
OH = 1 mA at
VDD –0.5
–
1.8 V VDD
I
OL = 4 mA at
–
–
–
0.6
0.6
0.4
1.8 V VDD
I
OL = 10 mA at
3 V VDD
I
OL = 3 mA at 3 V
VDD
SID63
SID64
RPULLUP
Pull-up resistor
3.5
3.5
5.6
5.6
8.5
8.5
kΩ
kΩ
RPULLDOWN
Pull-down resistor
25 °C, VDD
3.0 V
=
SID65
SID66
IIL
Input leakage current (absolute value)
Input capacitance
–
–
–
3
2
7
nA
pF
CIN
Notes
5. Guaranteed by characterization.
6. must not exceed V + 0.2 V.
V
IH
DD
Document Number: 001-89638 Rev. *K
Page 15 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 6. GPIO DC Specifications (referenced to VDDIO for 16-Pin QFN VDDIO pins) (continued)
Details/
Spec ID#
SID67[7]
Parameter
VHYSTTL
Description
Input hysteresis LVTTL
Min
Typ
40
–
Max
–
Units
mV
mV
mV
µA
Conditions
15
VDD 2.7 V
VDD < 4.5 V
VDD > 4.5 V
0.05 ×
VDD
SID68[7]
VHYSCMOS
VHYSCMOS5V5
IDIODE
Input hysteresis CMOS
Input hysteresis CMOS
–
SID68A[7]
SID69[7]
200
–
–
Current through protection diode to
VDD/VSS
–
–
100
Maximum total source or sink chip
current
SID69A[7]
ITOT_GPIO
–
–
85
mA
Table 7. GPIO AC Specifications
(Guaranteed by Characterization)
Details/
Spec ID#
SID70
Parameter
TRISEF
Description
Rise time in fast strong mode
Fall time in fast strong mode
Rise time in slow strong mode
Fall time in slow strong mode
Min
2
Typ
–
Max
12
Units
ns
ns
–
Conditions
3.3 V VDD
,
Cload = 25 pF
3.3 V VDD
,
SID71
SID72
SID73
TFALLF
TRISES
TFALLS
2
–
12
Cload = 25 pF
3.3 V VDD
,
10
10
–
60
Cload = 25 pF
3.3 V VDD
,
–
60
–
Cload = 25 pF
90/10%, 25 pF
load, 60/40 duty
cycle
GPIO FOUT; 3.3 V VDD 5.5 V.
SID74
SID75
SID76
FGPIOUT1
FGPIOUT2
FGPIOUT3
–
–
–
–
–
–
16
16
7
MHz
MHz
MHz
Fast strong mode.
90/10%, 25 pF
load, 60/40 duty
cycle
GPIO FOUT; 1.71 VVDD3.3 V.
Fast strong mode.
90/10%, 25 pF
load, 60/40 duty
cycle
GPIO FOUT; 3.3 V VDD 5.5 V.
Slow strong mode.
90/10%, 25 pF
load, 60/40 duty
cycle
GPIO FOUT; 1.71 V VDD 3.3 V.
SID245
SID246
FGPIOUT4
–
–
–
–
3.5
16
MHz
MHz
Slow strong mode.
GPIO input operating frequency;
1.71 V VDD 5.5 V
FGPIOIN
90/10% VIO
Note
7. Guaranteed by characterization.
Document Number: 001-89638 Rev. *K
Page 16 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
XRES
Table 8. XRES DC Specifications
Details/
Spec ID#
SID77
Parameter
VIH
Description
Input voltage high threshold
Input voltage low threshold
Min
Typ
–
Max
Units
Conditions
0.7 ×
VDD
–
V
V
CMOS Input
0.3 ×
VDD
SID78
VIL
–
–
CMOS Input
SID79
SID80
RPULLUP
CIN
Pull-up resistor
3.5
–
5.6
3
8.5
7
kΩ
pF
Input capacitance
Typical hysteresis
is 200 mV for VDD
> 4.5V
0.05*
VDD
SID81[8]
VHYSXRES
Input voltage hysteresis
–
–
mV
Table 9. XRES AC Specifications
Details/
Conditions
Spec ID#
Parameter
TRESETWIDTH Reset pulse width
TRESETWAKE Wake-up time from reset release
Description
Min
Typ
Max
Units
SID83[8]
BID#194[8]
5
–
–
–
–
3
µs
ms
Analog Peripherals
Comparator
Table 10. Comparator DC Specifications
Details/
Conditions
Spec ID#
Parameter
ICMP1
Description
Min
Typ
Max
Units
SID330[8]
SID331[8]
Block current, High Bandwidth mode
Block current, Low Power mode
–
–
–
–
110
85
µA
µA
ICMP2
SID332[8]
SID333[8]
SID334[8]
VOFFSET1
VOFFSET2
ZCMP
Offset voltage, High Bandwidth mode
Offset voltage, Low Power mode
DC input impedance of comparator
–
–
10
10
–
30
30
–
mV
mV
MΩ
35
Max input voltage
is lower of 3.6 V or
VDD
SID338[8]
SID339
VINP_COMP Comparator input range
0
–
3.6
V
V
VREF_COMP Comparator internal voltage reference
1.188
1.2
1.212
Note
8. Guaranteed by characterization.
Document Number: 001-89638 Rev. *K
Page 17 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 11. Comparator AC Specifications (Guaranteed by Characterization)
Details/
Conditions
Spec ID#
Parameter
TCOMP1
TCOMP2
Description
Min
–
Typ
–
Max
90
Units
ns
Response Time High Bandwidth mode,
50-mV overdrive
SID336[8]
SID337[8]
Response Time Low Power mode,
50-mV overdrive
–
–
110
ns
CSD
Table 12. CSD and IDAC Block Specifications
Details/
Spec ID#
CSD and IDAC Specifications
SYS.PER#3 VDD_RIPPLE
Parameter
Description
Min
Typ
Max
Units
Conditions
VDD > 2V (with ripple),
25 °C TA,
Sensitivity = 0.1 pF
Maxallowedrippleonpowersupply,
DC to 10 MHz
–
–
–
–
±50
±25
mV
mV
VDD > 1.75V (with ripple),
25 C TA, Parasitic Capaci-
tance (CP) < 20 pF, Sensi-
tivity ≥ 0.4 pF
Maxallowedrippleonpowersupply,
DC to 10 MHz
SYS.PER#16 VDD_RIPPLE_1.8
SID.CSD#15
SID.CSD#16
SID.CSD#17
SID308
VREFHI
IDAC1IDD
IDAC2IDD
VCSD
Reference Buffer Output
IDAC1 (8-bits) block current
IDAC2 (7-bits) block current
Voltage range of operation
Voltage compliance range of IDAC
DNL for 8-bit resolution
1.1
–
1.2
–
1.3
1125
1125
5.5
V
µA
–
–
µA
1.71
0.8
–1
–3
–1
–3
–
V
1.8 V ±5% or 1.8 V to 5.5 V
SID308A
SID309
VCOMPIDAC
IDAC1DNL
IDAC1INL
IDAC2DNL
IDAC2INL
–
V
DD –0.8
V
–
1
3
1
3
LSB
LSB
LSB
LSB
SID310
INL for 8-bit resolution
–
SID311
DNL for 7-bit resolution
–
SID312
INL for 7-bit resolution
–
Ratio of counts of finger to noise.
Guaranteed by characterization
Capacitance range of 9 to
35 pF, 0.1 pF sensitivity
SID313
SID314
SID314A
SID315
SID315A
SNR
5
–
–
–
–
–
–
–
–
–
–
Ratio
µA
Output current of IDAC1 (8 bits) in
high range
IDAC1CRT1
IDAC1CRT2
IDAC2CRT1
IDAC2CRT2
612
Output current of IDAC1(8 bits) in
low range
306
µA
Output current of IDAC2 (7 bits) in
high range
304.8
152.4
µA
Output current of IDAC2 (7 bits) in
low range
µA
SID320
SID321
SID322
IDACOFFSET
IDACGAIN
All zeroes input
–
–
–
–
–
–
±1
±10
7
LSB
%
Full-scale error less offset
Mismatch between IDACs
IDACMISMATCH
LSB
Settling time to 0.5 LSB for 8-bit
IDAC
Full-scale transition. No
external load.
SID323
IDACSET8
–
–
10
µs
Settling time to 0.5 LSB for 7-bit
IDAC
Full-scale transition. No
external load.
SID324
SID325
IDACSET7
CMOD
–
–
–
10
–
µs
nF
External modulator capacitor.
2.2
5-V rating, X7R or NP0 cap.
Document Number: 001-89638 Rev. *K
Page 18 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
CSD ADC
All characterization is done with a 0.1% tolerance 1-MΩ input resistor (R_in), 0.1% tolerance 220-KΩ bleed resistor (R_bleed), and
2.2-nF C_mod capacitor. Refer to this page for more details on the circuit.
Table 13. CSD ADC DC Specifications
Symbol
ADCRes
Description
ADC resolution
Conditions
Min
1
Typ
–
Max
–
Units
mV
Yes
%
ADCMONO
ADCError
ADCOffset
ADC Monotonicity
ADC gain error
ADC offset error
Across PVT
–
–
–
For 0 to 5-V range, 0.1% accurate Rin /
Rbleed,1% accurate Internal Vref and
Temp range of 0 to 70 °C
–
–
1
–
–
50
mV
[9]
ADCINMAX
ADC input voltage range
0
–
5 / VDDIO
V
Note: Inputs applied directly to a pin must not exceed VDDIO, but voltages applied to an input resistor can exceed VDDIO
.
Table 14. CSD ADC AC Specifications
Symbol
ADCINL
Description
ADC integral non-linearity
ADC differential non-linearity
ADC Sample rate
Conditions
0 to 5-V input and 0 to 70 °C
0 to 5-V input and 0 to 70 °C
-
Min
–
Typ
–
Max
18
Units
mV
ADCDNL
–
–
12
mV
ADCSamp
–
–
58
sps
Note
9. Inputs applied directly to a pin must not exceed V
, but voltages applied to an input resistor can exceed V
.
DDIO
DDIO
Document Number: 001-89638 Rev. *K
Page 19 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 15. TCPWM Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.TCPWM.1
ITCPWM1
Block current consumption at 3 MHz
–
–
45
All modes (TCPWM)
μA
SID.TCPWM.2
ITCPWM2
Block current consumption at 8 MHz
Block current consumption at 16 MHz
–
–
–
–
145
160
All modes (TCPWM)
All modes (TCPWM)
μA
μA
SID.TCPWM.2A ITCPWM3
Fc max = CLK_SYS.
Maximum = 16 MHz
For all trigger
events[10]
TCPWMFREQ
TPWMENEXT
SID.TCPWM.3
SID.TCPWM.4
Operating frequency
–
–
–
Fc
–
MHz
ns
Input trigger pulse width
2/Fc
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
TPWMEXT
SID.TCPWM.5
Output trigger pulse widths
2/Fc
–
–
ns
Minimum time
between successive
counts
Minimum pulse width
of PWM Output
Minimum pulse width
between Quadrature
phase inputs.
TCRES
PWMRES
QRES
SID.TCPWM.5A
SID.TCPWM.5B
SID.TCPWM.5C
Resolution of counter
PWM resolution
1/Fc
1/Fc
1/Fc
–
–
–
–
–
–
ns
ns
ns
Quadrature inputs resolution
I2C
Table 16. Fixed I2C DC Specifications[11]
Spec ID Parameter
SID149 II2C1
SID150 II2C2
SID.PWR#5 ISBI2C
Description
Min
Typ
–
Max
Units Details/Conditions
Block current consumption at 100 kHz
Block current consumption at 400 kHz
I2C enabled in Deep Sleep mode
–
–
–
25
135
2.5
µA
µA
µA
–
–
Table 17. Fixed I2C AC Specifications[11]
Spec ID Parameter
SID153 FI2C1
Description
Min
Typ
Max
Units Details/Conditions
Bit rate
–
–
400
Kbps
Note
10. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
11. Guaranteed by characterization.
Document Number: 001-89638 Rev. *K
Page 20 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Memory
Table 18. Flash DC Specifications
Spec ID
Parameter
VPE
Description
Min
Typ
Max
Units
Details/Conditions
SID173
Erase and program voltage
1.71
–
5.5
V
Table 19. Flash AC Specifications
Spec ID
SID174
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Row (block) write time (erase and
program)
[12]
TROWWRITE
–
–
20
ms
Row (block) = 64 bytes
[12]
SID175
TROWERASE
Row erase time
–
–
–
–
–
–
13
7
ms
ms
[12]
SID176
TROWPROGRAM
Row program time after erase
Bulk erase time (16 KB)
Total device program time
Flash endurance
–
–
[12]
SID178
TBULKERASE
15
7.5
–
ms
SID180[13]
SID181[13]
TDEVPROG
–
seconds
cycles
[12]
FEND
100 K
Flash retention. TA 55 °C, 100 K
SID182[13]
FRET
20
10
–
–
–
–
years
years
P/E cycles
Flash retention. TA 85 °C, 10 K
P/E cycles
SID182A[13]
System Resources
Power-on Reset (POR)
Table 20. Power On Reset (PRES)
Spec ID Parameter
SID.CLK#6 SR_POWER_UP Power supply slew rate
Description
Min
Typ
Max
Units
Details/Conditions
At power-up and
power-down
1
–
67
V/ms
SID185[13] VRISEIPOR
SID186[13] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
–
1.5
1.4
V
V
Table 21. Brown-out Detect (BOD) for VCCD
Spec ID
Parameter
Description
Min
1.48
1.11
Typ
–
Max
1.62
1.5
Units
Details/Conditions
BOD trip voltage in active and
sleep modes
SID190[13] VFALLPPOR
SID192[13] VFALLDPSLP
V
V
BOD trip voltage in Deep Sleep
–
Notes
12. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
13. Guaranteed by characterization.
Document Number: 001-89638 Rev. *K
Page 21 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
SWD Interface
Table 22. SWD Interface Specifications
Spec ID
SID213
Parameter
Description
3.3 V VDD 5.5 V
Min
Typ
Max
Units
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
F_SWDCLK1
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
MHz
SID215[14] T_SWDI_SETUP T = 1/f SWDCLK
SID216[14] T_SWDI_HOLD T = 1/f SWDCLK
SID217[14] T_SWDO_VALID T = 1/f SWDCLK
SID217A[14] T_SWDO_HOLD T = 1/f SWDCLK
0.25*T
–
–
–
–
–
–
ns
ns
ns
ns
0.25*T
–
1
0.5*T
–
Internal Main Oscillator
Table 23. IMO DC Specifications
(Guaranteed by Design)
Spec ID
SID218
Parameter
IIMO1
IIMO2
Description
Min
–
Typ
Max
250
180
Units
µA
Details/Conditions
Details/Conditions
IMO operating current at 48 MHz
IMO operating current at 24 MHz
–
–
SID219
–
µA
Table 24. IMO AC Specifications
Spec ID
Parameter
FIMOTOL1
Description
Min
Typ
Max
Units
Frequency variation at 24 and
32 MHz (trimmed)
2 V VDD 5.5 V, and
–25 °C TA 85 °C
SID223
–
–
±2
%
Frequency variation at 24 and
32 MHz (trimmed)
SID223A FIMOTOLVCCD
–
–
±4
%
All other conditions
SID226
SID228
TSTARTIMO
IMO startup time
–
–
–
7
–
µs
ps
TJITRMSIMO2
RMS jitter at 24 MHz
145
Internal Low-Speed Oscillator
Table 25. ILO DC Specifications
(Guaranteed by Design)
Spec ID
SID231[14] IILO1
SID233[14] IILOLEAK
Parameter
Description
ILO operating current
ILO leakage current
Min
–
Typ
0.3
2
Max
1.05
15
Units
µA
Details/Conditions
Details/Conditions
–
nA
Table 26. ILO AC Specifications
Spec ID Parameter
SID234[14] TSTARTILO1
SID236[14] TILODUTY
Description
ILO startup time
Min
–
Typ
–
Max
2
Units
ms
ILO duty cycle
40
20
50
40
60
80
%
SID237
FILOTRIM1
ILO frequency range
kHz
Note
14. Guaranteed by characterization.
Document Number: 001-89638 Rev. *K
Page 22 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 27. External Clock Specifications
Spec ID Parameter
Description
Min
0
Typ
–
Max
16
Units
MHz
%
Details/Conditions
SID305[15] ExtClkFreq
SID306[15] ExtClkDuty
External clock input frequency
Duty cycle; measured at VDD/2
45
–
55
Table 28. Block Specs
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID262[15] TCLKSWITCH
System clock source switching time
3
–
4
Periods
Note
15. Guaranteed by characterization.
Document Number: 001-89638 Rev. *K
Page 23 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Ordering Information
The PSoC 4000 part numbers and features are listed in the following table. All package types are available in Tape and Reel.
Feature
Package
MPN
CY8C4013SXI-400
CY8C4013SXI-410
CY8C4013SXI-411
CY8C4013LQI-411
CY8C4014SXI-420
CY8C4014SXI-411
CY8C4014SXI-421
CY8C4014LQI-421
CY8C4014LQI-412
CY8C4014LQI-422
CY8C4014PVI-412
CY8C4014PVI-422
CY8C4014FNI-421
CY8C4014FNI-421A
CY8C4014LQI-SLT1
CY8C4014LQI-SLT2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
✔
–
–
✔
✔
–
–
✔
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
✔
✔
–
–
–
–
8
8
–
✔
–
–
–
8
–
✔
–
–
16
16
16
16
16
16
16
16
16
16
16
16
✔
–
–
–
✔
✔
–
–
–
✔
✔
–
–
–
✔
–
–
–
✔
✔
–
✔
–
–
–
–
–
✔
✔
✔
✔
✔
–
–
–
✔
–
–
–
–
–
–
–
–
–
–
✔
–
–
–
✔
Part Numbering Conventions
PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0,
1, 2, …, 9, A,B, …, Z) unless stated otherwise.
The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows.
x
x x
CY8C
4 A B C D E F -
Examples
Cypress Prefix
Architecture
4 : PSoC4
Family Group within Architecture
Speed Grade
0 : 4000 Family
1 : 16 MHz
Flash Capacity
4 : 16 KB
PV : SSOP
SX : SOIC
LQ : QFN
FN: WLCSP
Package Code
Temperature Range
Peripheral Set
I : Industrial
Document Number: 001-89638 Rev. *K
Page 24 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
The Field Values are listed in the following table:
Field
Description
Values
Meaning
CY8C
Cypress prefix
Architecture
Family
4
4
PSoC 4
A
0
4000 Family
1
16 MHz
B
C
CPU speed
4
48 MHz
3
8 KB
4
16 KB
Flash capacity
5
32 KB
6
64 KB
7
SX
128 KB
SOIC
LQ
QFN
DE
Package code
PV
SSOP
WLCSP
FN
F
Temperature range
Attributes code
I
Industrial
XYZ
000-999
Code of feature set in specific family
Document Number: 001-89638 Rev. *K
Page 25 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Packaging
Table 29. Package List
Spec ID#
BID#47A
BID#26
BID#33
BID#40
BID#47
Package
28-Pin SSOP
24-Pin QFN
16-Pin QFN
16-Pin SOIC
8-Pin SOIC
Description
28-pin 5 × 10 × 1.65mm SSOP with 0.65-mm pitch
24-pin 4 × 4 × 0.6 mm QFN with 0.5-mm pitch
16-pin 3 × 3 × 0.6 mm QFN with 0.5-mm pitch
16-pin (150 Mil) SOIC
8-pin (150 Mil) SOIC
16-Ball WLCSP (1.47 × 1.58mm) 16-Ball 1.47 × 1.58 × 0.4 mm
16-Ball WLCSP (1.45 × 1.56mm) 16-Ball 1.45 × 1.56 × 0.4 mm
BID#147A
Table 30. Package Characteristics
Parameter
TA
Description
Conditions
Min
Typ
Max
Units
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
Package θJA (28-pin SSOP)
Package θJC (28-pin SSOP)
Package θJA (24-pin QFN)
Package θJC (24-pin QFN)
Package θJA (16-pin QFN)
Package θJC (16-pin QFN)
Package θJA (16-pin SOIC)
Package θJC (16-pin SOIC)
Package θJA (16-ball WLCSP)
Package θJC (16-ball WLCSP)
Package θJA (8-pin SOIC)
Package θJC (8-pin SOIC)
–40
–
–
100
–
°C
TJA
TJC
TJA
TJC
TJA
TJC
TJA
TJC
TJA
TJC
TJA
TJC
66.6
34
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
–
–
–
38
–
–
5.6
–
–
49.6
5.9
–
–
–
–
142
49.8
90
–
–
–
–
–
–
0.9
–
–
198
56.9
–
–
–
Table 31. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 32. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
MSL 3
MSL1
All except WLCSP
16-ball WLCSP
Document Number: 001-89638 Rev. *K
Page 26 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Package Outline Drawings
Figure 11. 28-Pin SSOP Package Outline
51-85079 *F
Figure 12. 24-pin QFN EPAD (Sawn) Package Outline
001-13937 *G
Document Number: 001-89638 Rev. *K
Page 27 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Figure 13. 16-pin QFN Package EPAD (Sawn)
001-87187 *A
Figure 14. 16-pin (150-mil) SOIC Package Outline
51-85068 *F
Document Number: 001-89638 Rev. *K
Page 28 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure 15. 8-pin (150-mil) SOIC Package Outline
51-85066 *I
Document Number: 001-89638 Rev. *K
Page 29 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure 16. 16-Ball WLCSP 1.47 × 1.58 × 0.42 mm
5.
1
1
2
3
4
4
3
2
A
B
C
D
A
B
C
D
6.
7.
TOP VIEW
6.
SIDE VIEW
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
MIN.
MAX.
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
D
-
-
0.42
0.109
1.497
1.604
0.089
1.447
0.099
1.472
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
E
1.554
1.579
1.05 BSC
1.05 BSC
4
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
4
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
16
b
0.17
0.20
0.23
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
eD
eE
SD
SE
0.35 BSC
0.35 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
0.18 BSC
0.18 BSC
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF. : N/A.
002-18598 **
Document Number: 001-89638 Rev. *K
Page 30 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Figure 17. 16-Ball WLCSP 1.45 × 1.56 × 0.42 mm
5.
1
1
2
3
4
4
3
2
A
B
C
D
A
B
C
D
6.
7.
TOP VIEW
6.
SIDE VIEW
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
MIN.
MAX.
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
D
-
-
0.42
0.109
1.477
1.584
0.089
1.427
0.099
1.452
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
E
1.534
1.559
1.05 BSC
1.05 BSC
4
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
4
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
16
b
0.17
0.20
0.23
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
eD
eE
SD
SE
0.35 BSC
0.35 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
0.18 BSC
0.18 BSC
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF. : N/A.
001-95966 *C
Document Number: 001-89638 Rev. *K
Page 31 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Acronyms
Table 33. Acronyms Used in this Document (continued)
Table 33. Acronyms Used in this Document
Acronym
FIR
Description
finite impulse response, see also IIR
flash patch and breakpoint
full-speed
Acronym
abus
Description
analog local bus
FPB
ADC
analog-to-digital converter
analog global
FS
AG
general-purpose input/output, applies to a PSoC
pin
GPIO
AMBA(advanced microcontroller bus architecture)
high-performance bus, an Arm data transfer bus
AHB
HVI
IC
high-voltage interrupt, see also LVI, LVD
integrated circuit
ALU
arithmetic logic unit
AMUXBUS analog multiplexer bus
IDAC
current DAC, see also DAC, VDAC
API
application programming interface
IDE
integrated development environment
APSR
Arm®
ATM
BW
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
I2C, or IIC Inter-Integrated Circuit, a communications protocol
IIR
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
ILO
bandwidth
IMO
INL
Controller Area Network, a communications
protocol
CAN
I/O
CMRR
CPU
common-mode rejection ratio
central processing unit
IPOR
IPSR
IRQ
ITM
LCD
interrupt program status register
interrupt request
cyclic redundancy check, an error-checking
protocol
CRC
DAC
DFB
digital-to-analog converter, see also IDAC, VDAC
digital filter block
instrumentation trace macrocell
liquid crystal display
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
Local Interconnect Network, a communications
protocol.
DIO
LIN
DMIPS
DMA
DNL
DNU
DR
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
LR
link register
LUT
LVD
LVI
lookup table
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
port write data registers
LVTTL
MAC
MCU
MISO
NC
DSI
digital system interconnect
data watchpoint and trace
error correcting code
DWT
ECC
ECO
microcontroller unit
master-in slave-out
external crystal oscillator
no connect
electrically erasable programmable read-only
memory
NMI
nonmaskable interrupt
non-return-to-zero
EEPROM
NRZ
NVIC
NVL
opamp
PAL
EMI
electromagnetic interference
external memory interface
end of conversion
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
EMIF
EOC
EOF
EPSR
ESD
ETM
end of frame
programmable array logic, see also PLD
program counter
execution program status register
electrostatic discharge
embedded trace macrocell
PC
PCB
printed circuit board
Document Number: 001-89638 Rev. *K
Page 32 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Table 33. Acronyms Used in this Document (continued)
Table 33. Acronyms Used in this Document (continued)
Acronym
PGA
PHUB
PHY
Description
programmable gain amplifier
peripheral hub
Acronym
THD
TIA
Description
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
physical layer
TRM
TTL
PICU
PLA
port interrupt control unit
programmable logic array
programmable logic device, see also PAL
phase-locked loop
TX
PLD
Universal Asynchronous Transmitter Receiver, a
communications protocol
UART
PLL
UDB
USB
universal digital block
Universal Serial Bus
PMDD
POR
PRES
PRS
package material declaration data sheet
power-on reset
USB input/output, PSoC pins used to connect to a
USB port
precise power-on reset
pseudo random sequence
port read data register
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
USBIO
VDAC
WDT
voltage DAC, see also DAC, IDAC
watchdog timer
PS
PSoC®
PSRR
PWM
RAM
RISC
RMS
RTC
WOL
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
crystal
WRES
XRES
XTAL
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
RTL
register transfer language
remote transmission request
receive
RTR
RX
SAR
successive approximation register
switched capacitor/continuous time
I2C serial clock
SC/CT
SCL
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
special input/output, GPIO with advanced features.
See GPIO.
SIO
SOC
SOF
start of conversion
start of frame
Serial Peripheral Interface, a communications
protocol
SPI
SR
slew rate
SRAM
SRES
SWD
SWV
TD
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
Document Number: 001-89638 Rev. *K
Page 33 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Document Conventions
Table 34. Units of Measure (continued)
Symbol Unit of Measure
µH
Units of Measure
Table 34. Units of Measure
microhenry
microsecond
microvolt
Symbol
°C
Unit of Measure
µs
degrees Celsius
decibel
µV
µW
mA
ms
mV
nA
ns
dB
microwatt
milliampere
millisecond
millivolt
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
Khr
kHz
k
kilobits per second
kilohour
nanoampere
nanosecond
nanovolt
kilohertz
nV
kilo ohm
ohm
ksps
LSB
Mbps
MHz
M
Msps
µA
kilosamples per second
least significant bit
megabits per second
megahertz
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
mega-ohm
sps
sqrtHz
V
samples per second
square root of hertz
volt
megasamples per second
microampere
microfarad
µF
Document Number: 001-89638 Rev. *K
Page 34 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4000 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-89638
Submission
Revision
ECN
Description of Change
Date
*B
4348760 05/16/2014 New PSoC 4000 datasheet.
Added 28-pin SSOP pin and package details.
Updated VREF spec values.
4514139 10/27/2014 Updated conditions for SID174.
*C
Updated SID.CSD#15 values and description.
Added spec SID339.
Corrected Development Kits information and PSoC Creator Example Project figure.
4617283 01/09/2015 Corrected typo in the ordering information table.
*D
*E
*F
*G
*H
*I
Updated 28-pin SSOP package diagram.
4735762 05/26/2015 Added 16-ball WLCSP pin and package details.
Updated Table 32.
5466193 10/07/2016 Updated 8-pin SOIC package diagram.
Updated the template.
5685079 04/05/2017 Updated 16-ball WLCSP package details.
Added Figure 17 (spec 001-95966 *C) in Packaging.
5807014 07/24/2017 Updated Table 29.
Updated Ordering Information.
6189153 05/29/2018 Updated 8-pin SOIC and 24-pin QFN package drawings.
Corrected TRM links in More Information.
Updated clocking diagram.
Updated Pin 26 in 28-pin SSOP pinout.
*J
6604429 07/02/2019
Added CSD ADC DC Specifications and CSD ADC AC Specifications.
*K
7104675 03/15/2021 Updated conditions for SID.CLK#6.
Document Number: 001-89638 Rev. *K
Page 35 of 36
PSoC® 4: PSoC 4000 Family
Datasheet
Sales, Solutions, and Legal Information
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Document Number: 001-89638 Rev. *K
Revised March 15, 2021
Page 36 of 36
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