CY8C4747LQS-S453 [INFINEON]
Automotive PSoC™ 4700S Plus;
| 型号： | CY8C4747LQS-S453 |
| 厂家： | 
Infineon |
| 描述： | Automotive PSoC™ 4700S Plus |
| 文件： | 总64页 (文件大小：1452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Automotive PSoC™ MCU
Automotive PSoC™ 4 MCU: PSoC™ 4700S
Plus
General description
Automotive PSoC™ 4 MCU is a scalable and reconfigurable platform architecture for a family of programmable
embedded system controllers with an Arm® Cortex®-M0+ CPU while being AEC-Q100 compliant. It combines
programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC™ 4700S
Plus product family, based on this platform, is the industry’s first microcontroller with oscillator based inductive
sensing and capacitive sensing technology in a single chip. The inductive sensing technology enables sensing of
metal objects and industry’s leading capacitive sensing (CAPSENSE™) technology enables sensing of
non-metallic objects.
Features
• Automotive Electronics Council (AEC) AEC-Q100 qualified
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU
- Up to 128 KB of flash with read accelerator
- Up to 8 KB of SRAM
- 8-channel DMA engine
• Programmable analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and comparator
modes and ADC input buffering capability. Opamps can operate in deep sleep low-power mode.
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in deep sleep low-power mode
• Programmable digital
- Three smart IO ports (19 smart IO pins) allowing boolean operations to be performed on port inputs and
outputs
• Low-power 1.71 V to 5.5 V operation
- Deep sleep mode with operational analog and 2.5 A digital system current
• Oscillator based inductive sensing
- Infineon inductive sensing provides superior noise immunity
- Can reliably detect metal deflection under 190 nm
- Inductive sense software component automatically calibrates the solution to compensate for the
manufacturing variations
- Supports up to four sensors
• Capacitive sensing
- Infineon CAPSENSE™ sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (> 5:1) and water
tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Five independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI,
UART functionality, or LIN slave functionality
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Features
• Timing and Pulse-Width Modulation
- Eight 16-bit Timer/Counter/Pulse-Width Modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
• Clock sources
- 4 to 33 MHz External Crystal Oscillator (ECO)
- PLL to generate 48-MHz frequency
- 32-kHz Watch Crystal Oscillator (WCO)
- ±2% Internal Main Oscillator (IMO)
- 32-kHz Internal Low-Power Oscillator (ILO)
• True random number generator (TRNG)
- TRNG generates truly random number for secure key generation for cryptography applications
• Temperature range
- Grade-S: –40°C to +105°C
• Up to 34 programmable GPIO pins (19 of these can be configured as smart IO)
- 40-pin QFN package
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
• ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
More information
More information
Infineon provides a wealth of data at www.infineon.com to help you to select the right PSoC™ MCU device for
your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive
list of resources, see the knowledge base article How to design with PSoC™ 3, PSoC™ 4, and PSoC™ 5LP -
KBA86521. Following is an abbreviated list for PSoC™ 4 MCU:
• Application notes: Infineon offers a large number of PSoC™ device application notes covering a broad range of
topics, from basic to advanced level. Recommended application notes for getting started with PSoC™ 4 MCU are:
- AN79953: Getting started with PSoC™ 4
- AN86439: Using PSoC™ 4 GPIO pins
- AN57821: Mixed signal circuit board layout
- AN81623: Digital design best practices
- AN73854: Introduction to bootloaders
- AN89610: Arm® Cortex® code optimization
- AN85951: PSoC™ 4 and PSoC™ 6 MCU CAPSENSE™ design guide
• Online:
- In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ MCU users and experts
in PSoC™ MCU from around the world, 24 hours a day, 7 days a week.
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ModusToolbox™ software
ModusToolbox™ software
ModusToolbox™ software is Infineon comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub. This includes:
• Board support packages (BSPs) aligned with Infineon kits
• Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENE™, Bluetooth® Low Energy, and mesh networks
• An extensive set of thoroughly tested code example applications
Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Infineon
MCUs. It is a generic interface that can be used across multiple product families. For example, it wraps the
PSoC™ 4 MCU PDL with a simplified API, but the PDL exposes all low-level peripheral functionality. You can
leverage the HAL's simpler and more generic interface for most of an application, even if one portion requires
finer-grained control.
ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the
optional eclipse IDE for ModusToolbox™ software, as Figure 1 shows.
Figure 1
ModusToolbox™ software tools
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Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
More information ..............................................................................................................................3
ModusToolbox™ software...................................................................................................................4
Table of contents...............................................................................................................................5
Block diagram...................................................................................................................................7
1 Functional description ....................................................................................................................8
2 Functional definition.......................................................................................................................9
2.1 CPU and memory subsystem .................................................................................................................................9
2.1.1 CPU .......................................................................................................................................................................9
2.1.2 Flash .....................................................................................................................................................................9
2.1.3 SRAM.....................................................................................................................................................................9
2.1.4 SROM ....................................................................................................................................................................9
2.2 System resources....................................................................................................................................................9
2.2.1 Power system.......................................................................................................................................................9
2.2.2 Clock system ......................................................................................................................................................10
2.2.3 IMO clock source ................................................................................................................................................10
2.2.4 ILO clock source.................................................................................................................................................10
2.2.5 WCO ....................................................................................................................................................................10
2.2.6 ECO .....................................................................................................................................................................11
2.2.7 WDT.....................................................................................................................................................................11
2.2.8 Reset ...................................................................................................................................................................11
2.3 Analog blocks ........................................................................................................................................................11
2.3.1 12-bit SAR ADC ...................................................................................................................................................11
2.3.2 Two opamps (continuous-time block; CTB).....................................................................................................12
2.3.3 Low-power comparators (LPC) .........................................................................................................................12
2.3.4 Current DACs ......................................................................................................................................................12
2.3.5 Analog multiplexed buses .................................................................................................................................12
2.4 Programmable digital blocks...............................................................................................................................12
2.4.1 Smart I/O block ..................................................................................................................................................12
2.5 Fixed function digital blocks ................................................................................................................................12
2.5.1 Timer/counter/PWM (TCPWM) block ................................................................................................................12
2.5.2 Serial communication block (SCB) ...................................................................................................................13
2.6 GPIO.......................................................................................................................................................................13
2.7 Special function peripherals ................................................................................................................................14
2.7.1 CAPSENSE™........................................................................................................................................................14
2.7.2 LCD segment drive.............................................................................................................................................14
2.8 Inductive sensing ..................................................................................................................................................15
2.8.1 SNR vs target distance.......................................................................................................................................16
2.8.2 Distance delta (metal target displacement) when SNR = 5 .............................................................................16
2.8.3 Raw counts vs target distance...........................................................................................................................17
2.8.4 Noiseless precision ............................................................................................................................................17
2.8.5 Sensitivity...........................................................................................................................................................18
2.8.6 Noise floor (%)....................................................................................................................................................18
2.8.7 Effective number of bits (ENOB)........................................................................................................................19
2.8.8 Scan time............................................................................................................................................................19
2.8.9 Detection range..................................................................................................................................................20
3 Pinouts ........................................................................................................................................21
3.1 Alternate pin functions .........................................................................................................................................23
4 Power ..........................................................................................................................................26
4.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................26
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Table of contents
4.2 Mode 2: 1.8 V ± 5% external supply ......................................................................................................................26
5 Electrical specifications.................................................................................................................28
5.1 Absolute maximum ratings ..................................................................................................................................28
5.2 Device level specifications....................................................................................................................................29
5.2.1 GPIO....................................................................................................................................................................30
5.2.2 XRES....................................................................................................................................................................32
5.3 Analog peripherals................................................................................................................................................33
5.3.1 CTBm opamp .....................................................................................................................................................33
5.3.2 Comparator........................................................................................................................................................37
5.3.3 Temperature sensor ..........................................................................................................................................37
5.3.4 SAR ADC..............................................................................................................................................................38
5.3.5 CSD and IDAC .....................................................................................................................................................40
5.3.6 10-bit CAPSENSE™ ADC......................................................................................................................................42
5.3.7 Inductive sensing ...............................................................................................................................................43
5.4 Digital peripherals.................................................................................................................................................44
5.4.1 Timer counter pulse-width modulator (TCPWM) .............................................................................................44
5.4.2 I2C .......................................................................................................................................................................45
5.4.3 SPI.......................................................................................................................................................................46
5.4.4 UART ...................................................................................................................................................................47
5.4.5 LCD direct drive..................................................................................................................................................47
5.5 Memory..................................................................................................................................................................48
5.5.1 Flash ...................................................................................................................................................................48
5.6 System resources..................................................................................................................................................49
5.6.1 Power-on reset (POR) ........................................................................................................................................49
5.6.2 Brown-out detect (BOD) ....................................................................................................................................49
5.6.3 SWD interface.....................................................................................................................................................49
5.6.4 Internal Main Oscillator .....................................................................................................................................50
5.6.5 Internal low-speed oscillator ............................................................................................................................50
5.6.6 Watch crystal oscillator (WCO)..........................................................................................................................51
5.6.7 External clock.....................................................................................................................................................51
5.6.8 External Crystal Oscillator (ECO) and PLL ........................................................................................................52
5.6.9 System clock ......................................................................................................................................................52
5.6.10 Smart I/O ..........................................................................................................................................................52
6 Ordering information ....................................................................................................................53
7 Packaging ....................................................................................................................................55
7.1 Package diagram ..................................................................................................................................................56
8 Acronyms.....................................................................................................................................57
9 Document conventions..................................................................................................................61
9.1 Units of measure ...................................................................................................................................................61
Revision history ..............................................................................................................................62
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Block diagram
Block diagram
CPU Subsystem
PSoC™ 4700S
SWD/TC, MTB
SPCIF
Plus
Cortex
FLASH
DataWire/
DMA
SRAM
8 KB
ROM
8 KB
M0+
32-bit
128 KB
48 MHz
FAST MUL
NVIC, IRQMUX, MPU
Initiator/MMIO
AHB-Lite
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
Programmable
Analog
ILO
IMO
SAR ADC
(12-bit)
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
x1
Analog DFT
CTBm
2x OpAmp
SARMUX
High Speed I/O Matrix & Smart I/O
Power Modes
Active/Sleep
DeepSleep
Up to 34x GPIOs
I/O Subsystem
Figure 2
Block diagram
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Functional description
1
Functional description
PSoC™ 4700S Plus devices include extensive support for programming, testing, debugging, and tracing both
hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The SWD interface is fully compatible with industry-standard third-party tools. PSoC™ 4700S Plus provides a level
of security not possible with multi-chip application solutions or with microcontrollers. It has the following
advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4700S Plus, with device security enabled, may not be
returned for failure analysis. This is a trade-off the PSoC™ 4700S Plus allows the customer to make.
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Functional definition
2
Functional definition
CPU and memory subsystem
CPU
2.1
2.1.1
The Cortex®-M0+ CPU in the PSoC™ 4700S Plus is part of the 32-bit MCU subsystem, which is optimized for
low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a
subset of the thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight
interrupt inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from
deep sleep mode, allowing power to be switched off to the main processor when the chip is in deep sleep mode.
The CPU subsystem includes an 8-channel DMA engine and also includes a debug interface, the SWD interface,
which is a 2-wire form of JTAG. The debug configuration used for PSoC™ 4700S Plus has four breakpoint (address)
comparators and two watchpoint (data) comparators.
2.1.2
Flash
The PSoC™ 4700S Plus device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
2.1.3
SRAM
8 KB of SRAM are provided with zero wait-state access at 48 MHz.
2.1.4
SROM
An 8-KB supervisory ROM that contains boot and configuration routines is provided.
2.2
System resources
Power system
2.2.1
The power system is described in detail in the section “Power” on page 26. It provides assurance that voltage
levels are as required for each respective mode and either delays mode entry (for example, on power-on reset
(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brownout
detection). PSoC™ 4700S Plus operates with a single external supply over the range of either 1.8 V ± 5% (externally
regulated) or 1.8 V to 5.5 V (internally regulated) and has three different power modes, transitions between which
are managed by the power system. PSoC™ 4700S Plus provides active, sleep, and deep sleep low-power modes.
All subsystems are operational in active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs. The opamps can remain operational in deep sleep mode.
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Functional definition
2.2.2
Clock system
The PSoC™ 4700S Plus clock system is responsible for providing clocks to all subsystems that require clocks and
for switching between different clock sources without glitching. In addition, the clock system ensures that there
are no metastable conditions.
The clock system for the PSoC™ 4700S Plus consists of the IMO, ILO, a 32-kHz watch crystal oscillator (WCO), 4 to
33 MHz ECO and PLL, and provision for an external clock. The WCO block allows locking the IMO to the 32-kHz
oscillator.
External Clock
HLFK
Divide By
IMO
2,4,8
PLL
ECO
WDC 0
16-bits
WDC 1
16-bits
LFCLK
IMO
ECO
WDC 2
32-bits
WDT
Watchdog Counters (WDC)
Watchdog Timer (WDT)
Prescaler
SYSCLK
HFCLK
Integer
12× 16-bits
Dividers
Fractional
Dividers
5× 16.5-bit, 1× 24.5-bit
Figure 3
PSoC™ 4700S Plus MCU clocking architecture
The HFCLK signal can be divided down as shown to generate synchronous clocks for the analog and digital
peripherals. There are 18 clock dividers for the PSoC™ 4700S Plus (six with fractional divide capability, twelve with
integer divide only). The twelve 16-bit integer divide capability allows a lot of flexibility in generating fine-grained
frequency. In addition, there are five 16-bit fractional dividers and one 24-bit fractional divider.
2.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4700S Plus. It is trimmed during testing to achieve
the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2% over the entire voltage and
temperature range.
2.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in deep sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
2.2.5
WCO
The PSoC™ 4700S Plus clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that
can be used for precision timing applications.
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Functional definition
2.2.6
ECO
The PSoC™ 4700S Plus also implements a 4 to 33 MHz crystal oscillator.
2.2.7
WDT
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
deep sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a reset cause register, which is firmware readable.
2.2.8
Reset
PSoC™ 4700S Plus can be reset from a variety of sources including a software reset. Reset events are
asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky
through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset
by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.
2.3
Analog blocks
12-bit SAR ADC
2.3.1
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The sample-and-hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier
driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an
external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected
channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching
is effected through a state machine or through firmware driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying
source impedance and frequency, it is possible to have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast
detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed
and the CPU to read the values and check for out-of-range values in software.
The SAR is not available in deep sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating
range is 1.71 V to 5.5 V.
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
External
Reference and
Bypass
(optional )
Reference
Selection
VDDA
VREF
VDDA /2
Inputs from other Ports
Figure 4
SAR ADC
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Functional definition
2.3.2
Two opamps (continuous-time block; CTB)
PSoC™ 4700S Plus has two opamps with comparator modes which allow most common analog functions to be
performed on-chip eliminating external components; PGAs, voltage buffers, filters, trans-impedance amplifiers,
and other functions can be realized, in some cases with external passives. saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive the sample-and-hold circuit of the ADC without
requiring external buffering.
2.3.3
Low-power comparators (LPC)
PSoC™ 4700S Plus has a pair of low-power comparators, which can also operate in deep sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
2.3.4
Current DACs
PSoC™ 4700S Plus has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
2.3.5
Analog multiplexed buses
PSoC™ 4700S Plus has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal
resources (IDACs, comparator) to connect to any pin on the I/O ports.
2.4
Programmable digital blocks
Smart I/O block
2.4.1
The smart I/O block is a fabric of switches and LUTs that allows boolean functions to be performed in signals
being routed to the pins of a GPIO port. The smart I/O can perform logical operations on input pins to the chip
and on signals going out as outputs.
2.5
Fixed function digital blocks
2.5.1
Timer/counter/PWM (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. Each block also incorporates a quadrature decoder.
There are eight TCPWM blocks in PSoC™ 4700S Plus.
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Functional definition
2.5.2
Serial communication block (SCB)
PSoC™ 4700S Plus has five serial communication blocks (SCBs), which can be programmed to have SPI, I2C, UART,
or LIN slave functionality.
I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (fast mode plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates
a mailbox address range in the memory of PSoC™ 4700S Plus and effectively reduces I2C communication to
reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C standard-mode and fast-mode plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
PSoC™ 4700S Plus is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system.
UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
LIN slave mode: The LIN slave mode uses the SCB hardware block and implements a full LIN slave interface. This
LIN slave is compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE J2602-2 specification standards. It is certified
by C&S GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated
at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length.
2.6
GPIO
PSoC™ 4700S Plus has up to 33 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the
blocks are forced to the disabled state so as not to crowbar any inputs and/or cause excess turn-on current. A
multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.7
Special function peripherals
CAPSENSE™
2.7.1
CAPSENSE™ is supported in the PSoC™ 4700S Plus through a CAPSENSE™ sigma-delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator IDE
component is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield
capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit Slope ADC function which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references
and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It
has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise.
2.7.2
LCD segment drive
PSoC™ 4700S Plus has an LCD controller, which can drive up to 4 commons and up to 50 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays. LCD
operation is supported during deep sleep refreshing a small display buffer (4 bits; one 32-bit register per port).
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.8
Inductive sensing
The PSoC™ 4700S Plus devices support a low-cost and robust Oscillator based inductive sensing, which
integrates seamlessly with existing user interfaces and is used to detect the presence of metallic or conductive
objects. The Oscillator based inductive sensing provides best-in-class signal-to-noise ratio (SNR), Higher
operating frequency, better sensitivity and Parallel scanning.
The inductive sensing can be used for applications such as buttons (touch-over-metal), metal proximity
detection and measurement, rotary and linear encoders, spring-based position detection, and other applications
for detecting position or distance of the metal objects.
Oscillator based inductive sense block:
Figure 5
Oscillator based Inductive Sensing Architecture
As shown in the above Figure 5, off-chip components such as L1 (PCB coil), C1, C2, RS and RL needs to be
connected to GPIO pins and configure SmartIO block with inverter logic. This combination forms an oscillator
whose output frequency (FOUT) is modulated by the inductance changes of the PCB coil, caused by a metal target.
Internal timer and counter blocks convert the variations of FOUT into the digital domain.
Oscillator based inductive sense has the following features:
• Supports Inductive sensing for frequencies from 1 MHz to 12 MHz.
• Oscillator runs at high frequency reducing coil dimensions, current and scan.
• Lower temperature drift than other sensing methods
• High sensitivity, low noise, resulting in greater SNR
• Sensing distance up to 1.5 times the diameter of the coil (SNR = 5, 2 layers coil)
• Parallel scanning
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.8.1
SNR vs target distance
SNR for 1μm delta vs Target Distance
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
v2 16bit
v2 15bit
v2 14bit
v2 12bit
5
10
15
20
25
30
35
40
45
50
Target Distance - % of Dout
This graph shows the signal-to-noise ratio versus metal target position. In this case, the signal corresponds to the
raw counts delta provoked by a metal target displacement of 1 µm. The y-axis of the graph is scalable for
displacements different than 1 µm. For example, to obtain the SNR for a 10-µm displacement, the corresponding
y-axis SNR value must be multiplied by 10.
2.8.2
Distance delta (metal target displacement) when SNR = 5
Distance Delta vs Target Distance for SNR=5
2000
1900
Above Curve: SNR>5
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
v2 16bit
v2 15bit
v2 14bit
v2 12bit
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Target Distance - % of Dout
Each curve in this graph determines the metal target displacement needed to achieve a SNR value of 5. Therefore,
above the curve, SNR > 5, and below the curve SNR < 5. For example, if we have a metal target positioned at a
distance equivalent to 50% of the coil’s diameter (Dout), we need a minimum target displacement of
approximately 75 µm @ 16 bits, 150 µm @ 15 bits, and 300 µm @ 14 bits to obtain an SNR 5.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.8.3
Raw counts vs target distance
Raw Counts vs Target Distance (Dout=20mm)
70000
60000
50000
40000
30000
20000
10000
0
v2 16bit
v2 15bit
v2 14bit
v2 12bit
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Target Distance - % of Dout
This graph plots the unfiltered converted data (raw counts) versus the metal target distance for different scan
resolutions (bits).
2.8.4
Noiseless precision
Distance Delta vs Target Distance for 1 Raw Count Delta
(Noiseless Precision)
1200
1150
1100
1050
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
v2 16bit
v2 15bit
v2 14bit
v2 12bit
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100
Target Distance - % of Dout
This graph shows the metal target displacement that can be detected in the absence of noise. In this ideal
scenario, the plotted target displacement results in one raw count delta.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.8.5
Sensitivity
Sensitivity (RawC/um) vs Target Distance
5
4
3
2
1
v2 16bit
v2 15bit
v2 14bit
v2 12bit
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Target Distance - % of Dout
This graph shows the sensitivity of the system in raw counts per µm versus the target distance.
2.8.6
Noise floor (%)
Max Noise Floor (%) vs Scan Resolution
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
12
13
14
15
16
Scan Resolution - bits
Noise floor is the ratio between the peak-to-peak raw counts noise and the averaged (or DC) raw counts (1000
samples).
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.8.7
Effective number of bits (ENOB)
ENOB is the actual resolution of the system when intrinsic noise is considered. For example, a 16-bit scan has an
ENOB = 15 bits, and therefore has the same resolution of a noiseless 15-bit scan.
Resolution (% of Dout)
Target distance (mm)
ENOB (bits)
12.997
5
10
20
40
60
100
1
2
4
8
12
20
12.858
12.786
12.738
12.525
11.057
2.8.8
Scan time
Scan Time vs Resolution for Fout MAX (12MHz)
3000
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
10
11
12
13
14
15
16
Scan Resolution - bits
The plot in this graph shows an example of Fmax = 12 MHz; hence it shows the minimum scan time per sensor at
different scan resolutions.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Functional definition
2.8.9
Detection range
Detection Range (d/Dout for SNR=5)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
12
13
14
15
16
Scan Resolution - bits
This graph shows the maximum distance until which a metal target can be detected with a SNR value of 5. When
a metal target that was initially far away (i.e. > 2x Dout) is moved in closer, the raw counts begin to increase. The
point at which these raw counts increase is 5 times the peak-to-peak noise (SNR = 5) and that marks the detection
range. The measured peak-to-peak noise is the noise at the initial distance, d > 2x Dout.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Pinouts
3
Pinouts
Table 1
Pin list for PSoC™ 4700S Plus for the 40-pin QFN package
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSSD
VDD
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.7/VREF
P2.3
P2.4
P2.5
P2.6
P2.7
P6.0
P6.1
P6.2
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Pinouts
Table 1
Pin list for PSoC™ 4700S Plus for the 40-pin QFN package (continued)
Pin
19
Name
P4.1
20
P4.2
21
P4.3
Descriptions of the power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ± 5%)
VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply
GPIOs: 34
Datasheet
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3.1
Alternate pin functions
Each port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a Smart
IO pin. The pin assignments are shown in the following table.
Table 2
Pin assignments
Analog
Alternate Alternate Alternate Alternate
function 1 function 2 function 3 function 4
Pin Name
Smart I/O
Deep Sleep 1 Deep Sleep 2 Deep Sleep 3 Deep Sleep 4
22
P0.0
lpcomp.in_p[0]
–
–
tcpwm.tr_ pass.dsi_ scb[2].uart
lcd.com[0]
lcd.seg[0]
scb[2].i2c_scl: scb[0].spi_
in[0]
sar_data_
valid
_cts:0
0
select1:0
23
24
P0.1
P0.2
lpcomp.in_n[0]
lpcomp.in_p[1]
–
–
–
–
tcpwm.tr_ pass.tr_sar scb[2].uart
lcd.com[1]
lcd.com[2]
lcd.seg[1]
lcd.seg[2]
scb[2].i2c_
sda:0
scb[0].spi_
select2:0
in[1]
–
_out
_rts:0
–
pass.dsi_
sar_
–
scb[0].spi_
select3:0
sample_
done
25
26
27
28
P0.3
P0.4
P0.5
P0.6
lpcomp.in_n[1]
wco.wco_in
–
–
–
–
–
–
–
–
pass.dsi_
–
lcd.com[3]:0
lcd.com[4]
lcd.com[5]
lcd.com[6]
lcd.seg[3]
lcd.seg[4]
lcd.seg[5]
lcd.seg[6]
–
scb[2].spi_
select0:1
sar_data[2]
scb[1].uart pass.dsi_ scb[2].uart
_rx:0 sar_data[0] _rx:0
scb[1].i2c_scl: scb[1].spi_
0
mosi:1
wco.wco_out
scb[1].uart pass.dsi_ scb[2].uart
scb[1].i2c_
sda:0
scb[1].spi_
miso:1
_tx:0
sar_data[1]
–
_tx:0
srss.adft_por_pad_
hv
srss.ext_clk scb[1].uart
_cts:0
scb[2].uart
_tx:1
–
scb[1].spi_clk
:1
exco.eco_in
29
35
36
P0.7
P1.0
P1.1
exco.eco_out
–
tcpwm.line scb[1].uart
–
–
–
–
–
–
lcd.com[7]
lcd.com[8]
lcd.com[9]
lcd.seg[7]
lcd.seg[8]
lcd.seg[9]
–
scb[1].spi_
select0:1
[0]:3
_rts:0
pass.ctb0_pads[0] SmartIo[2]. tcpwm.line scb[0].uart
io[0] [2]:1 _rx:1
scb[0].i2c_scl: scb[0].spi_
0
mosi:1
pass.ctb0_pads[1] SmartIo[2]. tcpwm.line scb[0].uart
scb[0].i2c_
sda:0
scb[0].spi_
miso:1
io[1]
_compl[2]:
1
_tx:1
37
38
39
P1.2
P1.3
P1.4
pass.ctb0_pads[2] SmartIo[2]. tcpwm.line scb[0].uart pass.dsi_ tcpwm.tr_ lcd.com[10]
lcd.seg[10] scb[2].i2c_scl: scb[0].spi_clk
pass.ctb0_oa0_out_
10x
io[2]
[3]:1
_cts:1
sar_
in[2]
2
:1
data[3]:0
pass.ctb0_pads[3] SmartIo[2]. tcpwm.line scb[0].uart pass.dsi_ tcpwm.tr_ lcd.com[11]
lcd.seg[11]
scb[2].i2c_
sda:2
scb[0].spi_
select0:1
pass.ctb0_oa1_out_
10x
io[3]
_compl[3]:
1
_rts:1
sar_
in[3]
data[4]:0
pass.ctb0_pads[4] SmartIo[2]. tcpwm.line
io[4] [6]:1
–
–
–
lcd.com[12]
lcd.seg[12] scb[3].i2c_scl: scb[0].spi_
select1:1
0
Table 2
Pin assignments (continued)
Analog Smart I/O
Alternate Alternate Alternate Alternate
function 1 function 2 function 3 function 4
Pin Name
Deep Sleep 1 Deep Sleep 2 Deep Sleep 3 Deep Sleep 4
40
P1.7
pass.ctb0_pads[7] SmartIo[2]. tcpwm.line
–
–
–
lcd.com[15]
lcd.seg[15]
-
scb[2].spi_clk
:1
pass.sar_ext_vref0
pass.sar_ext_vref1
io[7]
_compl[7]:
1
pass.sarmux_pads[0]
–
–
tcpwm.line csd.comp
[4]:0
–
–
tcpwm.tr_ lcd.com[16]
in[4]
lcd.seg[16] scb[1].i2c_scl: scb[1].spi_
1
mosi:2
pass.sarmux_pads[1]
tcpwm.line
_compl[4]:
0
–
tcpwm.tr_ lcd.com[17]
in[5]
lcd.seg[17]
scb[1].i2c_
sda:1
scb[1].spi_
miso:2
pass.sarmux_pads[2]
–
tcpwm.line
[5]:1
–
–
–
–
–
–
lcd.com[18]
lcd.com[19]
lcd.seg[18]
lcd.seg[19]
–
–
scb[1].spi_clk
:2
1
P2.3 pass.sarmux_pads[3] SmartIo[0]. tcpwm.line
scb[1].spi_
select0:2
io[3]
_compl[5]:
1
2
3
P2.4 pass.sarmux_pads[4] SmartIo[0]. tcpwm.line scb[3].uart
io[4] [0]:1 _rx:1
–
–
–
–
lcd.com[20]
lcd.com[21]
lcd.seg[20]
lcd.seg[21]
–
–
scb[1].spi_
select1:1
P2.5 pass.sarmux_pads[5] SmartIo[0]. tcpwm.line scb[3].uart
scb[1].spi_
select2:1
io[5]
_compl[0]:
1
_tx:1
4
5
P2.6 pass.sarmux_pads[6] SmartIo[0]. tcpwm.line scb[3].uart pass.dsi_
–
–
lcd.com[22]
lcd.com[23]
lcd.com[48]
lcd.seg[22]
–
scb[1].spi_
select3:1
io[6]
[1]:1
_cts:1
sar_
data[5]:0
P2.7 pass.sarmux_pads[7] SmartIo[0]. tcpwm.line scb[3].uart pass.dsi_
lcd.seg[23] lpcomp.comp scb[2].spi_
[0]:0 mosi:1
io[7]
_compl[1]:
1
_rts:1
sar_
data[6]:0
6
7
P6.0
P6.1
–
–
–
–
tcpwm.line scb[3].uart
[4]:1 _rx:0
–
can.can_
lcd.seg[48] scb[3].i2c_scl: scb[3].spi_
tx_enb_n:0
1
mosi:0
tcpwm.line scb[3].uart
–
can.can_rx: lcd.com[49]
0
lcd.seg[49]
lcd.seg[50]
scb[3].i2c_
sda:1
scb[3].spi_
miso:0
_compl[4]:
1
_tx:0
8
P6.2
P3.0
–
–
–
tcpwm.line scb[3].uart
[5]:0 _cts:0
–
can.can_tx: lcd.com[50]
0
–
scb[3].spi_clk
:0
10
SmartIo[1]. tcpwm.line scb[1].uart pass.dsi_
–
lcd.com[24]
lcd.seg[24] scb[1].i2c_scl: scb[1].spi_
io[0]
[0]:0
_rx:1
sar_
2
mosi:0
data[7]:0
11
P3.1
–
SmartIo[1]. tcpwm.line scb[1].uart pass.dsi_
–
lcd.com[25]
lcd.seg[25]
scb[1].i2c_
sda:2
scb[1].spi_
miso:0
io[1]
_compl[0]:
0
_tx:1
sar_
data[8]:0
Table 2
Pin assignments (continued)
Alternate Alternate Alternate Alternate
function 1 function 2 function 3 function 4
Pin Name
Analog
Smart I/O
Deep Sleep 1 Deep Sleep 2 Deep Sleep 3 Deep Sleep 4
12
13
P3.2
P3.3
–
SmartIo[1]. tcpwm.line scb[1].uart
io[2] [1]:0 _cts:1
–
–
lcd.com[26]
lcd.com[27]
lcd.seg[26]
lcd.seg[27]
cpuss.swd_ scb[1].spi_clk
data
:0
–
SmartIo[1]. tcpwm.line scb[1].uart
–
–
cpuss.swd_
clk
scb[1].spi_
select0:0
io[3]
_compl[1]:
0
_rts:1
14
15
P3.4
P3.5
–
–
SmartIo[1]. tcpwm.line
io[4] [2]:0
–
–
–
–
tcpwm.tr_ lcd.com[28]
in[6]
lcd.seg[28]
lcd.seg[29]
–
–
scb[1].spi_
select1:0
SmartIo[1]. tcpwm.line
–
lcd.com[29]
scb[1].spi_
select2:0
io[5]
_compl[2]:
0
16
17
P3.6
P3.7
–
–
SmartIo[1]. tcpwm.line
io[6] [3]:0
–
–
pass.dsi_
ctb_cmp0
–
–
lcd.com[30]
lcd.com[31]
lcd.seg[30]
scb[4].spi_
select3
scb[1].spi_
select3:0
SmartIo[1]. tcpwm.line
pass.dsi_
ctb_cmp1
lcd.seg[31] lpcomp.comp scb[2].spi_
[1]:1 miso:1
io[7]
–
_compl[3]:
0
18
P4.0
csd.vref_ext
csd.vref_ext_h-
scomp
–
scb[0].uart pass.dsi_ can.can_rx: lcd.com[32]
lcd.seg[32] scb[0].i2c_scl: scb[0].spi_
_rx:0
sar_
1
1
mosi:0
data[9]:0
19
20
P4.1
P4.2
csd.cshieldpads
–
–
–
–
scb[0].uart
_tx:0
–
can.can_tx: lcd.com[33]
1
lcd.seg[33]
scb[0].i2c_
sda:1
scb[0].spi_
miso:0
csd.cmodpads
csd.cmodpadd
scb[0].uart pass.dsi_
can.can_
lcd.com[34]
lcd.seg[34] lpcomp.comp scb[0].spi_clk
[0]:1 :0
_cts:0
sar_
tx_enb_n:1
data[10]:0
21
–
P4.3
–
csd.csh_tankpads
csd.csh_tankpadd
–
–
–
scb[0].uart pass.dsi_
–
–
lcd.com[35]
lcd.seg[35] lpcomp.comp scb[0].spi_
_rts:0
sar_
[1]:2
select0:0
data[11]:0
–
tcpwm.line scb[3].uart
–
lcd.com[55]:0 lcd.seg[55]
scb[3].i2c_
sda:2
scb[3].spi_
miso:1
_compl[0]:
2
_tx:2
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Power
4
Power
The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4700S
Plus. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog
circuits run directly from the VDDA input.
VDDA
VDDD
VDDA
VSSA
VDDD
VSSD
Analog
Domain
Digital
Domain
VCCD
1.8 Volt
Regulator
Figure 6
Power supply connections
There are two distinct modes of operation. In mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In mode 2, the supply range is1.8 V ± 5% (externally regulated; 1.71 to
1.89, internal regulator bypassed).
4.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, PSoC™ 4700S Plus is powered by an external power supply that can be anywhere in the range of 1.8
to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from
a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of PSoC™ 4700S
Plus supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to
ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.
4.2
Mode 2: 1.8 V ± 5% external supply
In this mode, PSoC™ 4700S Plus is powered by an external power supply that must be within the range of 1.71 to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing. On some packages, VDDD and
VDDA pins are shorted inside the package and brought out as a generic VDD pin. In that case, only 0.1-µF and 1-µF
decoupling capacitors are required on the VDD pin.
An example of a bypass scheme is shown in the following diagram.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Power
Power supply bypass connections example
1.8 V to 5.5 V
0.1 µF
1.8 V to 5.5 V
0.1 µF
VDDA
VDDD
0.1 µF
1 µF
VCCD
PSoC™ 4700S Plus
0.1 µF
VSS
Figure 7
External supply range from 1.8 V to 5.5 V with internal regulator active
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5
Electrical specifications
5.1
Absolute maximum ratings
Absolute maximum ratings[1]
Table 3
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID1
VDDD_ABS
Digital supply relative
to VSS
–0.5
–
6
V
–
SID2
VCCD_ABS
Direct digital core
voltage input relative
to VSS
–0.5
–
1.95
–
SID3
SID4
VGPIO_ABS
IGPIO_ABS
GPIO voltage
Maximum current per
GPIO
–0.5
–25
–
–
VDD + 0.5
25
–
–
mA
SID5
IGPIO_injection GPIO injection current,
Max for VIH > VDDD, and
–0.5
–
0.5
Current injected per
pin
Min for VIL < VSS
BID44
BID45
BID46
ESD_HBM
ESD_CDM
LU
Electrostatic discharge
human body model
Electrostatic discharge
charged device model
2200
500
–
–
–
–
–
V
–
–
–
Pin current for latch-up
–140
140
mA
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device.
Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The
maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, high temperature
storage life. When used below absolute maximum conditions but above normal operating conditions, the
device may not operate to specification.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.2
Device level specifications
All specifications are valid for –40°C TA 85°C for grade-A devices, –40°C TA 105°C for grade-S devices, and
–40°C TA 125°C for grade-E devices. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 4
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID# Parameter Description
DC specifications
Min Typ Max Unit
Details/conditions
SID53
SID255
VDD
VDD
Power supply input voltage 1.8
Power supply input voltage 1.71
–
–
5.5
1.89
V
Internally regulated supply
Internally unregulated
supply
(VCCD = VDDD = VDDA
)
SID54
SID55
SID56
VCCD
CEFC
CEXC
Output voltage (for core
logic)
External regulator voltage
bypass
Power supply bypass
capacitor
–
–
–
1.8
0.1
1
–
–
–
–
µF X5R ceramic or better
X5R ceramic or better
Active mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10
SID16
SID19
IDD5
IDD8
IDD11
Execute from flash; CPU at
6 MHz
Execute from flash; CPU at
24 MHz
Execute from flash; CPU at
48 MHz
–
–
–
1.8
3.0
5.4
2.7
mA Max is at 125°C and 5.5 V
Max is at 125°C and 5.5 V
Max is at 125°C and 5.5 V
5
7.6
Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and
Comparators on
I2C wakeup, WDT, and
Comparators on
–
–
1.1
1.5
2.2
2.5
mA 6 MHZ. Max is at 125°C and
5.5 V
SID25
IDD20
12 MHZ. Max is at 125°C and
5.5 V
Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
Comparators on
I2C wakeup, WDT, and
Comparators on
–
1.1
1.5
1.8
2.1
mA 6 MHz. Max is at 125°C and
1.89 V.
SID28A
IDD23A
–
12 MHz. Max is at 125°C and
1.89 V.
Deep sleep mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
SID31
IDD25
IDD26
I2C wakeup and WDT on
I2C wakeup and WDT on
–
–
2.5
2.5
40
350
µA T = –40°C to 60°C
Max is at 3.6 V and 125°C
Deep sleep mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID33
SID34
IDD28
IDD29
I2C wakeup and WDT on
I2C wakeup and WDT on
–
–
2.5
2.5
40
350
µA T = –40°C to 60°C
Max is at 5.5 V and 125°C
Deep sleep mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID36
SID37
IDD31
IDD32
I2C wakeup and WDT on
I2C wakeup and WDT on
–
–
2.5
2.5
60
400
µA T = –40°C to 60°C
Max is at 125°C and 1.89 V.
XRES current
SID307
IDD_XR
Supply current while XRES
asserted
–
2
5
mA –
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 5
AC specifications
Spec ID# Parameter
Description
CPU frequency
Wakeup from sleep mode
Min
DC
–
Typ
–
0
Max Unit Details/conditions
SID48
SID49
SID50
FCPU
TSLEEP
48
–
MHz 1.71 VDD 5.5
µs
–
–
TDEEPSLEEP Wakeup from deep sleep mode
–
35
–
5.2.1
GPIO
Table 6
GPIO DC specifications
Spec ID# Parameter
Description
Input voltage high
threshold
Min
0.7 VDDD
Typ
–
Max
–
Unit Details/conditions
[2]
SID57
VIH
V
CMOS Input
SID58
VIL
Input voltage low
threshold
–
–
0.3 VDDD
CMOS Input
[2]
[2]
SID241
SID242
SID243
SID244
SID59
VIH
VIL
VIH
VIL
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD 2.7 V
LVTTL input, VDDD 2.7 V
Output voltage high level VDDD – 0.6
Output voltage high level VDDD – 0.5
0.7 VDDD
–
–
–
–
–
–
–
–
–
–
–
–
2.0
–
0.3 VDDD
–
0.8
–
VOH
VOH
IOH = 4 mA at 3 V VDDD
IOH = 1 mA at 1.8 V
VDDD
SID60
–
SID61
SID62
VOL
VOL
Output voltage low level
Output voltage low level
–
–
–
–
0.6
0.6
IOL = 4 mA at 1.8 V
VDDD
IOL = 10 mA at 3 V
VDDD
SID62A VOL
Output voltage low level
Pull-up resistor
–
–
0.4
8.5
8.5
2
IOL = 3 mA at 3 V VDDD
–
–
SID63
SID64
SID65
RPULLUP
RPULLDOWN Pull-down resistor
IIL
3.5
3.5
–
5.6
5.6
–
kΩ
Input leakage current
(absolute value)
nA 25°C, VDDD = 3.0 V
SID66
CIN
Input capacitance
–
25
–
40
–
7
–
–
–
pF
mV
–
V
SID67[3] VHYSTTL
Input hysteresis LVTTL
Input hysteresis CMOS
Input hysteresis CMOS
DDD 2.7 V
SID68[3] VHYSCMOS
0.05 × VDDD
200
VDD < 4.5 V
VDD > 4.5 V
SID68A[3] VHYSC-
MOS5V5
–
SID69[3] IDIODE
Current through
protection diode to
VDD/VSS
Maximum total source or
sink chip current
–
–
–
–
100
200
µA
–
–
SID69A[3] ITOT_GPIO
mA
Notes
2. VIH must not exceed VDDD + 0.2 V.
3. Guaranteed by characterization.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 7
GPIO AC specifications
(Guaranteed by characterization)
Spec ID# Parameter
Description
Min
Typ
Max Unit Details/conditions
SID70
SID71
SID72
SID73
SID74
TRISEF
Rise time in fast strong
mode
Fall time in fast strong mode
2
–
12
12
60
60
33
ns 3.3 V VDDD
,
Cload = 25 pF
TFALLF
TRISES
TFALLS
FGPIOUT1
2
10
10
–
–
–
–
–
3.3 V VDDD
Cload = 25 pF
,
Rise time in slow strong
mode
Fall time in slow strong
mode
–
–
3.3 V VDDD
,
Cload = 25 pF
3.3 V VDDD
Cload = 25 pF
,
GPIO FOUT
;
MHz 90/10%, 25 pF load,
60/40 duty cycle
3.3 V VDDD 5.5 V
fast strong mode
SID75
FGPIOUT2
FGPIOUT3
FGPIOUT4
FGPIOIN
GPIO FOUT
;
–
–
–
–
–
–
–
–
16.7
7
90/10%, 25 pF load,
60/40 duty cycle
1.71 V VDDD 3.3 V
fast strong mode
SID76
GPIO FOUT
;
90/10%, 25 pF load,
60/40 duty cycle
3.3 V VDDD 5.5 V
slow strong mode
SID245
SID246
GPIO FOUT
;
3.5
48
90/10%, 25 pF load,
60/40 duty cycle
1.71 V VDDD 3.3 V
slow strong mode.
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
90/10% VIO
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.2.2
XRES
Table 8
XRES DC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details/conditions
SID77
VIH
Input voltage high 0.7 × VDDD
threshold
–
–
V
CMOS Input
SID78
VIL
Input voltage low
threshold
–
–
0.3 VDDD
SID79
SID80
SID81[4]
RPULLUP
CIN
VHYSXRES
Pull-up resistor
Input capacitance
Input voltage
hysteresis
–
–
–
60
–
100
–
7
–
kΩ
pF
–
–
mV Typical hysteresis is
200 mV for VDD > 4.5 V
SID82
IDIODE
Current through
protection diode to
VDD/VSS
–
–
100
µA –
Table 9
XRES AC specifications
Description
Spec ID# Parameter
Min Typ Max Unit Details/conditions
SID83[4] TRESETWIDTH Reset pulse width
1
–
–
–
–
µs
–
–
BID194[4] TRESETWAKE Wake-up time from reset release
2.7 ms
Note
4. Guaranteed by characterization.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.3
Analog peripherals
5.3.1
CTBm opamp
Table 10
CTBm opamp specifications
Spec ID# Parameter
Description
Min Typ
Max
Unit Details/conditions
IDD
Opamp block current,
External load
SID269
SID270
SID271
IDD_HI
IDD_MED
IDD_LOW
GBW
power = hi
power = med
power = lo
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
–
–
–
1100
550
150
1850
950
350
µA
–
–
–
SID272
SID273
SID274
GBW_HI
power = hi
6
3
–
–
–
1
–
–
–
MHz Input and output are
0.2 V to VDDA – 0.2 V
GBW_MED
GBW_LO
IOUT_MAX
power = med
Input and output are
0.2 V to VDDA – 0.2 V
Input and output are
0.2 V to VDDA – 0.2 V
power = lo
VDDA = 2.7 V, 500 mV from rail
SID275
SID276
SID277
IOUT_MAX_HI power = hi
IOUT_MAX_MID power = mid
IOUT_MAX_LO power = lo
10
10
–
–
–
5
–
–
–
mA Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
IOUT
VDDA = 1.71 V, 500 mV from
rail
SID278
SID279
SID280
IOUT_MAX_HI power = hi
IOUT_MAX_MID power = mid
IOUT_MAX_LO power = lo
4
–
–
–
–
–
mA Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
4
–
2
IDD_Int
Opamp block current
Internal Load
power = hi
SID269_I
SID270_I
SID271_I
IDD_HI_Int
–
–
–
–
1500
700
–
1700
900
–
–
µA
IDD_MED_Int power = med
IDD_LOW_Int power = lo
–
–
–
GBW
VDDA = 2.7 V
–
–
SID272_I
GBW_HI_Int
power = hi
8
–
–
Output is 0.25 V to
MHz
VDDA – 0.25 V
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 10
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min Typ
Max
Unit Details/conditions
General opamp specs for
both internal and external
modes
SID281
SID282
VIN
Charge-pump on,
VDDA = 2.7 V
Charge-pump on,
VDDA = 2.7 V
–
–
–
V
DDA – 0.2
DDA – 0.2
V
V
–
–
0.05
VCM
–
0.05
V
VOUT
VDDA = 2.7 V
SID283
SID284
SID285
SID286
SID288
VOUT_1
VOUT_2
VOUT_3
VOUT_4
VOS_TR
power = hi, Iload = 10 mA
power = hi, Iload = 1 mA
power = med, Iload = 1 mA
power = lo, Iload = 0.1 mA
Offset voltage, trimmed
0.5
0.2
0.2
0.2
–
–
–
–
VDDA – 0.5
VDDA – 0.2
VDDA – 0.2
VDDA – 0.2
1.0
–
–
–
–
–1.0 0.5
mV Highmode,input0 Vto
DDA – 0.2 V
V
SID288A
SID288B
SID290
VOS_TR
Offset voltage, trimmed
Offset voltage, trimmed
–
–
1.4
2
–
–
Medium mode, input
0 V to VDDA – 0.2 V
Low mode, input 0 V to
VDDA – 0.2 V
VOS_TR
VOS_DR_TR
Offset voltage drift, trimmed –10 3
10
µV/ High mode
°C
SID290A
SID290B
SID291
VOS_DR_TR
VOS_DR_TR
CMRR
Offset voltage drift, trimmed
Offset voltage drift, trimmed
DC
–
–
70
10
10
80
–
–
–
µV/ Medium mode
Low mode
dB Input is 0 V to
°C
V
DDA – 0.2 V, Output is
0.2 V to VDDA – 0.2 V
SID292
PSRR
At 1 kHz, 10-mV ripple
70
85
–
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA – 0.2 V
Noise
VN2
–
72
–
nV/
–
SID294
SID295
SID296
SID297
SID298
SID299
SID299A
Input-referred, 1 kHz,
power = Hi
Input-referred, 10 kHz,
power = Hi
Input-referred, 100 kHz,
power = Hi
rtHz
VN3
–
–
–
6
–
–
28
15
–
–
–
Inputandoutputareat
0.2 V to VDDA – 0.2 V
Inputandoutputareat
0.2 V to VDDA – 0.2 V
VN4
CLOAD
Stable up to max. load.
Performance specs at 50 pF.
125
–
pF
–
SLEW_RATE Cload = 50 pF, Power = High,
DDA = 2.7 V
T_OP_WAKE From disable to enable, no
external RC dominating
–
V/µs –
V
–
25
–
µs
–
OL_GAIN
Open Loop Gain
90
dB
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 10
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min Typ
Max
Unit Details/conditions
COMP_
MODE
Comparator mode; 50 mV
drive, Trise = Tfall (approx.)
SID300
SID301
SID302
TPD1
TPD2
TPD3
Response time; power = hi
–
–
–
150
500
–
–
–
ns Input is 0.2 V to
V
DDA – 0.2 V
Response time; power =
med
Response time; power = lo
Input is 0.2 V to
DDA – 0.2 V
V
2500
Input is 0.2 V to
V
–
–
DDA – 0.2 V
SID303
SID304
VHYST_OP
WUP_CTB
Hysteresis
Wake-up time from Enabled
to Usable
–
–
10
–
–
25
mV
µs
Deep sleep Mode 2 is lowest current
mode
range. Mode 1 has higher
GBW.
SID_DS_1 IDD_HI_M1
SID_DS_2 IDD_MED_M1 Mode 1, medium current
SID_DS_3 IDD_LOW_M1 Mode 1, low current
SID_DS_4 IDD_HI_M2
SID_DS_5 IDD_MED_M2 Mode 2, medium current
SID_DS_6 IDD_LOW_M2 Mode 2, low current
Mode 1, high current
–
–
–
–
–
–
–
1400
700
200
120
60
–
–
–
–
–
–
–
µA 25°C
25°C
25°C
25°C
25°C
25°C
Mode 2, high current
15
4
SID_DS_7 GBW_HI_M1
Mode 1, high current
MHz 20-pF load, no DC load
0.2 V to VDDA – 0.2 V
SID_DS_8 GBW_MED_M1 Mode 1, medium current
SID_DS_9 GBW_LOW_M1 Mode 1, low current
–
–
–
–
–
–
–
–
–
–
–
2
0.5
0.5
0.2
0.1
5
–
–
–
–
–
–
–
–
–
–
–
20-pF load, no DC load
0.2 V to VDDA – 0.2 V
20-pF load, no DC load
0.2 V to VDDA – 0.2 V
20-pF load, no DC load
0.2 V to VDDA – 0.2 V
20-pF load, no DC load
0.2 V to VDDA – 0.2 V
SID_DS_10 GBW_HI_M2
Mode 2, high current
SID_DS_11 GBW_MED_M2 Mode 2, medium current
SID_DS_12 GBW_Low_M2 Mode 2, low current
20-pF load, no DC load
0.2 V to VDDA – 0.2 V
SID_DS_13 VOS_HI_M1
Mode 1, high current
mV With trim 25 °C, 0.2 V to
VDDA – 0.2 V
SID_DS_14 VOS_MED_M1 Mode 1, medium current
SID_DS_15 VOS_LOW_M2 Mode 1, low current
5
With trim 25°C, 0.2 V to
VDDA – 0.2 V
With trim 25°C, 0.2 V to
VDDA – 0.2 V
With trim 25°C, 0.2V to
VDDA – 0.2 V
With trim 25°C, 0.2 V to
VDDA – 0.2 V
5
SID_DS_16 VOS_HI_M2
Mode 2, high current
5
SID_DS_17 VOS_MED_M2 Mode 2, medium current
SID_DS_18 VOS_LOW_M2 Mode 2, low current
5
5
With trim 25°C, 0.2 V to
VDDA – 0.2 V
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 10
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min Typ
Max
Unit Details/conditions
SID_DS_19 IOUT_HI_M1
Mode 1, high current
–
–
–
10
10
4
–
mA Output is 0.5 V to
VDDA – 0.5 V
SID_DS_20 IOUT_MED_M1 Mode 1, medium current
SID_DS_21 IOUT_LOW_M1 Mode 1, low current
–
–
Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
SID_DS_22 IOUT_HI_M2
SID_DS_23 IOU_MED_M2 Mode 2, medium current
SID_DS_24 IOU_LOW_M2 Mode 2, low current
Mode 2, high current
–
–
–
1
1
0.5
–
–
–
–
–
–
Datasheet
36
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.3.2
Comparator
Table 11
Comparator DC specifications
Spec ID# Parameter
Description
Min Typ
Max Unit Details/conditions
SID84
VOFFSET1
Input offset voltage, factory
trim
–
–
±10
mV
–
SID85
VOFFSET2
Input offset voltage, custom
trim
–
–
±4
–
SID86
SID87
VHYST
VICM1
Hysteresis when enabled
Input common mode voltage
in normal mode
–
0
10
–
35
VDDD-0.
1
–
V
Modes 1 and 2
SID247
SID247A
SID88
VICM2
VICM3
CMRR
CMRR
Input common mode voltage
in low power mode
Input common mode voltage
in ultra low power mode
Common mode rejection
ratio
Common mode rejection
ratio
0
0
–
–
–
–
VDDD
–
VDDD-1.
15
VDDD ≥ 2.2 V at –40°C
50
42
–
dB VDDD ≥ 2.7 V
VDDD ≤ 2.7 V
SID88A
–
SID89
SID248
ICMP1
ICMP2
Block current, normal mode
Block current, low power
mode
–
–
–
–
400
100
µA
–
–
SID259
SID90
ICMP3
ZCMP
Block current in ultra
low-power mode
DC Input impedance of
comparator
–
–
–
6
–
VDDD ≥ 2.2 V at –40°C
35
MΩ
–
Table 12
Comparator AC specifications
Spec ID# Parameter
Description
Min
Typ
Max Unit Details/conditions
SID91
SID258
SID92
TRESP1
TRESP2
TRESP3
Response time, normal
mode, 50 mV overdrive
Response time, low power
mode, 50 mV overdrive
Response time, ultra-low
power mode, 200 mV
overdrive
–
38
110
200
15
ns
–
–
–
70
–
2.3
µs VDDD ≥ 2.2 V at –40°C
5.3.3
Temperature sensor
Table 13
Temperature sensor specifications
Spec ID# Parameter
Description
Min
Typ
Max Unit Details/conditions
SID93
TSENSACC
Temperature sensor
accuracy
–5
±1
5
°C –40 to +85°C
SID93A
TSENSACC
Temperature sensor
accuracy
–15
±1
+15
°C +85 to +150°C
Datasheet
37
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.3.4
SAR ADC
Table 14
SAR ADC specifications
Spec ID# Parameter
Description
Min
Typ
Max Unit Details/conditions
SAR ADC DC specifications
SID94
SID95
A_RES
Resolution
–
–
–
–
12
16
bits
–
–
A_CHNLS_S Number of channels - single
ended
SID96
A-CHNKS_D Number of channels -
differential
–
–
4
Diff inputs use
neighboring I/O
SID97
SID98
A-MONO
A_GAINERR Gain error
Monotonicity
–
–
–
–
–
±0.1
Yes
%
With external
reference
SID99
A_OFFSET
Input offset voltage
–
–
2
mV Measured with 1 V
reference
SID100
SID101
A_ISAR
A_VINS
Current consumption
Input voltage range - single
ended
–
VSS
–
–
1
VDDA
mA
V
–
–
SID102
A_VIND
Input voltage range -
differential
VSS
–
VDDA
V
–
SID103
SID104
SID260
A_INRES
A_INCAP
VREFSAR
Input resistance
Input capacitance
Trimmed internal reference
to SAR
–
–
–
–
1.2
2.2
10
1.212
KΩ
pF
V
–
–
–
1.188
Datasheet
38
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 14
SAR ADC specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max Unit Details/conditions
SAR ADC AC specifications
SID106
SID107
A_PSRR
A_CMRR
Power supply rejection ratio
Common mode rejection
ratio
70
66
–
–
–
–
dB
–
dB Measured at 1 V
SID108
SID109
A_SAMP
A_SNR
Sample rate
Signal-to-noise and
distortion ratio (SINAD)
–
65
–
–
1
–
Msps –
dB
F
IN = 10 kHz
SID110
SID111
A_BW
A_INL
Input bandwidth without
aliasing
Integral non linearity. VDD
1.71 to 5.5, 1 Msps
Integral non linearity. VDDD
1.71 to 3.6, 1 Msps
Integral non linearity. VDD
1.71 to 5.5, 500 ksps
Differential non linearity.
VDD = 1.71 to 5.5, 1 Msps
Differential non linearity.
VDD = 1.71 to 3.6, 1 Msps
Differential non linearity.
VDD = 1.71 to 5.5, 500 ksps
–
–
–
–
A_sam kHz
p/2
–
=
–1.7
–1.5
–1.5
–1
2
LSB VREF = 1 to VDD
LSB VREF = 1.71 to VDD
LSB VREF = 1 to VDD
SID111A A_INL
SID111B A_INL
=
1.7
1.7
2.2
2
=
–
–
SID112
A_DNL
LSB
LSB
LSB
V
V
V
REF = 1 to VDD
REF = 1.71 to VDD
REF = 1 to VDD
–
–
SID112A A_DNL
SID112B A_DNL
–1
–1
2.2
–
–
–
–
SID113
SID261
A_THD
Total harmonic distortion
–65
100
dB Fin = 10 kHz
ksps 12-bit resolution
FSARINTREF SAR operating speed without
external reference bypass
Datasheet
39
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.3.5
CSD and IDAC
Table 15
CSD and IDAC specifications
Spec ID#
SYS.PER#3
Parameter
VDD_RIPPLE Max allowed ripple on
power supply,
Description
Min Typ
Max
±50
Unit
mV
Details/conditions
–
–
V
DD > 2 V (with ripple),
25°C TA,
DC to 10 MHz
sensitivity = 0.1 pF
SYS.PER#16 VDD_RIPPLE Max allowed ripple on
–
–
±25
mV
VDD > 1.75 V (with
_1.8
power supply,
DC to 10 MHz
ripple), 25°C TA,
parasitic capacitance
(CP) < 20 pF,
sensitivity ≥ 0.4 pF
SID.CSD.BLK ICSD
Maximum block current
–
–
4000
µA Maximum block current
for both IDACs in
dynamic (switching)
mode including
comparators, buffer,
and reference
generator
SID.CSD#15 VREF
Voltage reference for
CSD and comparator
External voltage
reference for CSD and
comparator
0.6 1.2 VDDA –0.6
V
V
VDDA – 0.06 or 4.4,
whichever is lower
VDDA – 0.06 or 4.4,
whichever is lower
SID.CSD#15A VREF_EXT
0.6
V
DDA – 0.6
SID.CSD#16 IDAC1IDD
SID.CSD#17 IDAC2IDD
IDAC1 (7-bits) block
current
IDAC2 (7-bits) block
current
Voltage range of
operation
–
–
–
–
–
–
1750
1750
µA
µA
V
–
–
SID308
VCSD
1.71
0.6
5.5
1.8 V ± 5% or 1.8 V to
5.5 V
VDDA – 0.06 or 4.4,
whichever is lower
SID308A
VCOMPIDAC Voltage compliance
range of IDAC
V
DDA – 0.6
V
SID309
SID310
IDAC1DNL
IDAC1INL
DNL
INL
–1
–2
–
–
1
2
LSB
–
LSB INL is ±5.5 LSB for
V
DDA < 2 V
SID311
SID312
IDAC2DNL
IDAC2INL
DNL
INL
–1
–2
–
–
1
2
LSB
–
LSB INL is ±5.5 LSB for
DDA < 2 V
V
SID313
SNR
Ratio of counts of finger
to noise. Guaranteed by
characterization
5
–
–
Ratio Capacitance range of 5
to 35 pF, 0.1-pF
sensitivity. Allusecases.
VDDA > 2 V.
SID314
IDAC1CRT1 Output current of IDAC1 4.2
(7 bits) in low range
IDAC1CRT2 Output current of IDAC1 34
(7 bits) in medium range
IDAC1CRT3 Output current of IDAC1 275
(7 bits) in high range
–
–
–
–
5.4
41
µA LSB = 37.5 nA typ
µA LSB = 300 nA typ
µA LSB = 2.4 µA typ
µA LSB = 75 nA typ
SID314A
SID314B
SID314C
330
10.5
IDAC1CRT12 Output current of IDAC1
(7 bits) in low range, 2X
mode
8
Datasheet
40
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
Table 15
Spec ID#
CSD and IDAC specifications (continued)
Parameter Description
Min Typ
Max
Unit
Details/conditions
SID314D
IDAC1CRT22 Output current of IDAC1 69
(7 bits) in medium
–
82
µA LSB = 600 nA typ.
range, 2X mode
SID314E
IDAC1CRT32 Output current of IDAC1 540
(7 bits) in high range, 2X
mode
–
660
µA LSB = 4.8 µA typ
SID315
IDAC2CRT1 Output current of IDAC2 4.2
(7 bits) in low range
IDAC2CRT2 Output current of IDAC2 34
(7 bits) in medium range
IDAC2CRT3 Output current of IDAC2 275
(7 bits) in high range
–
–
–
–
5.4
41
µA LSB = 37.5 nA typ
µA LSB = 300 nA typ
µA LSB = 2.4 µA typ
µA LSB = 75 nA typ
SID315A
SID315B
SID315C
330
10.5
IDAC2CRT12 Output current of IDAC2
(7 bits) in low range, 2X
mode
8
SID315D
SID315E
SID315F
SID315G
SID315H
SID320
IDAC2CRT22 Output current of IDAC2 69
(7 bits) in medium
–
–
–
–
–
–
82
660
10.5
82
µA LSB = 600 nA typ
µA LSB = 4.8 µA typ
µA LSB = 37.5 nA typ
µA LSB = 300 nA typ
µA LSB = 2.4 µA typ
range, 2X mode
IDAC2CRT32 Output current of IDAC2 540
(7 bits) in high range, 2X
mode
IDAC3CRT13 Output current of IDAC
in 8-bit mode in low
range
8
IDAC3CRT23 Output current of IDAC
in 8-bit mode in
69
medium range
IDAC3CRT33 Output current of IDAC 540
660
1
in 8-bit mode in high
range
IDACOFFSET All zeroes input
–
LSB Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
SID321
SID322
IDACGAIN
Full-scale error less
offset
Mismatch between
IDAC1 and IDAC2 in Low
mode
Mismatch between
IDAC1 and IDAC2 in
Medium mode
Mismatch between
IDAC1 and IDAC2 in High
mode
–
–
–
–
±10
9.2
%
–
IDACMIS-
MATCH1
LSB LSB = 37.5 nA typ
LSB LSB = 300 nA typ
LSB LSB = 2.4 µA typ
SID322A
SID322B
IDACMIS-
MATCH2
–
–
–
–
5.6
6.8
IDACMIS-
MATCH3
SID323
SID324
SID325
IDACSET8
IDACSET7
CMOD
Settling time to 0.5 LSB
for 8-bit IDAC
Settling time to 0.5 LSB
for 7-bit IDAC
External modulator
capacitor.
–
–
–
–
–
5
5
–
µs Full-scale transition. No
external load
µs Full-scale transition. No
external load
nF 5-V rating, X7R or NP0
cap
2.2
Datasheet
41
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.3.6
10-bit CAPSENSE™ ADC
Table 16
10-bit CAPSENSE™ ADC specifications
Spec ID# Parameter
Description
Resolution
Min
–
Typ
–
Max Unit
Details/conditions
SIDA94
A_RES
10
bits Auto-zeroing is required
every millisecond
SIDA95
A_CHNLS_S Number of channels - single
ended
–
–
16
Defined by AMUX Bus
SIDA97
SIDA98
A-MONO
A_GAINERR Gain error
Monotonicity
–
–
–
–
–
±3
Yes
%
–
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA99
A_OFFSET Input offset voltage
–
–
–
±18
mV In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA101 A_VINS
Input voltage range - single
ended
VSSA
VDDA
V
–
SIDA103 A_INRES
SIDA104 A_INCAP
SIDA106 A_PSRR
Input resistance
Input capacitance
Power supply rejection ratio
–
–
–
2.2
20
60
–
–
–
KΩ
pF
–
–
dB In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA107 A_TACQ
SIDA108 A_CONV8
Sample acquisition time
–
–
1
–
–
21.3
µs
–
Conversion time for 8-bit
resolution at conversion
rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
µs Does not include
acquisition time.
Equivalent to 44.8 ksps
including acquisition
time.
SIDA108A A_CONV10 Conversion time for 10-bit
resolution at conversion
–
–
–
85.3
–
µs Does not include
acquisition time.
Equivalent to 11.6 ksps
including acquisition
time.
dB With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
SIDA109 A_SND
Signal-to-noise and
Distortion ratio (SINAD)
61
SIDA110 A_BW
SIDA111 A_INL
SIDA112 A_DNL
Input bandwidth without
aliasing
Integral Non Linearity.
1 ksps
Differential Non Linearity.
1 ksps
–
–
–
–
–
–
22.4 KHz 8-bit resolution
2
1
LSB VREF = 2.4 V or greater
–
Datasheet
42
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.3.7
Inductive sensing
Table 17
Spec ID#
SID500
Inductive sense specifications (Preliminary data; unless otherwise mentioned VDD > 2.7 V)
Parameter
Nsense
Description
Number of sensors
Sample rate
Min
–
Typ
4
Max Unit Details/conditions
–
–
–
SID501
Lsamp
–
–
12
ksps Measured at below
conditions:
Resolution = 11bits,
sensor operating
frequency
(Fout) = 12 MHz
refer sec 2.8.8
SID502
SID503
Lres
Lfreq
Resolution
Sensor excitation
frequency
–
1
–
–
16
12
bits
MHz –
–
SID505
SID506
Lval
Lprox
Inductance range
Proximity detection
range
1
–
–
10000 µH
–
–
0.75 ×
coil
diameter
–
–
–
1.5 × coil
diameter
–
–
If ECO is used
SID507
Rp
Tank impedance
500
–
10000
–
Datasheet
43
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.4
Digital peripherals
5.4.1
Timer counter pulse-width modulator (TCPWM)
Table 18
TCPWM specifications
Spec ID
Parameter
Description
Block current
consumption at 3 MHz
Block current
consumption at 12 MHz
Block current
consumption at 48 MHz
Min
–
Typ
–
Max Unit Details/conditions
SID.TCPWM.1 ITCPWM1
SID.TCPWM.2 ITCPWM2
SID.TCPWM.2A ITCPWM3
45
155
650
Fc
A
All modes (TCPWM)
All modes (TCPWM)
All modes (TCPWM)
–
–
–
–
–
–
SID.TCPWM.3 TCPWMFREQ Operating frequency
MHz
ns
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.4 TPWMENEXT Input trigger pulse
width
SID.TCPWM.5 TPWMEXT
2/Fc
2/Fc
–
–
–
–
For all trigger
events[5]
Output trigger pulse
widths
Minimum possible
width of overflow,
underflow, and CC
(counter equals
compare value)
outputs
SID.TCPWM.5A TCRES
Resolution of counter
PWM resolution
1/Fc
–
–
Minimum time
between successive
counts
Minimum pulse width
of PWM Output
Minimum pulse width
between Quadrature
phase inputs
SID.TCPWM.5B PWMRES
SID.TCPWM.5C QRES
1/Fc
1/Fc
–
–
–
–
Quadrature inputs
resolution
Note
5. Guaranteed by characterization.
Datasheet
44
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.4.2
I2C
Table 19
Fixed I2C DC specifications[6]
Spec ID# Parameter
Description
Min
Typ
Max Unit
Details/conditions
–
–
–
–
SID149
SID150
SID151
SID152
II2C1
II2C2
II2C3
II2C4
Block current consumption
at 100 kHz
Block current consumption
at 400 kHz
Block current consumption
at 1 Mbps
I2C enabled in deep sleep
mode
–
–
50
135
310
–
µA
–
–
–
–
–
1
Table 20
Fixed I2C AC specifications[6]
Description
Spec ID# Parameter
Min
Typ
Max Unit
Details/conditions
–
SID153
FI2C1
Bit rate
–
–
1
Msps
Note
6. Guaranteed by characterization.
Datasheet
45
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.4.3
SPI
Table 21
SPI DC specifications[7]
Spec ID# Parameter
Description
Min
Typ
Max Unit
Details/Conditions
SID163
SID164
SID165
ISPI1
ISPI2
ISPI3
Block current consumption
at 1 Mbps
Block current consumption
at 4 Mbps
Block current consumption
at 8 Mbps
–
–
360
560
600
µA
–
–
–
–
–
–
–
Table 22
SPI AC specifications[8]
Spec ID# Parameter
SID166 FSPI
Description
SPI Operating frequency
(Master; 6X Oversampling)
Min
–
Typ
–
Max Unit
Details/conditions
8
MHz
–
–
Fixed SPI master mode AC specifications
SID167
SID168
SID169
TDMO
MOSI Valid after Sclock
driving edge
MISO Valid before Sclock
capturing edge
Previous MOSI data hold
time
–
20
0
–
–
–
15
–
ns
TDSI
Full clock, late MISO
sampling
Referred to slave
capturing edge
THMO
–
Fixed SPI slave mode AC specifications
SID170
TDMI
MOSI valid before Sclock
capturing edge
MISO valid after Sclock
driving edge
40
–
–
–
–
ns
–
SID171
TDSO
42 + (3
×
Tcpu)
T
CPU = 1/FCPU
SID171A
TDSO_EXT MISO valid after Sclock
driving edge in Ext. Clk
mode
–
–
48
–
SID172
THSO
Previous MISO data hold
time
0
–
–
–
–
–
–
SID172A
TSSELSSCK SSEL Valid to first SCK valid
edge
100
ns
Note
7. Guaranteed by characterization.
Datasheet
46
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.4.4
UART
UART DC specifications[8]
Table 23
Spec ID# Parameter
Description
Block current consumption
at 100 Kbps
Block current consumption
at 1000 Kbps
Min
–
Typ
–
Max Unit
Details/conditions
Details/conditions
SID160
IUART1
55
µA
–
–
SID161
IUART2
–
–
312
µA
Table 24
UART AC specifications[8]
Description
Spec ID# Parameter
Min
–
Typ
–
Max Unit
Mbps –
SID162
FUART
Bit rate
1
5.4.5
LCD direct drive
LCD direct drive DC specifications[8]
Table 25
Spec ID# Parameter
Description
Min
Typ
Max Unit Details/conditions
SID154
ILCDLOW
Operating current in low
power mode
–
5
–
µA 16 4 small segment
disp. at 50 Hz
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
500
5000
pF
–
SID156
SID157
LCDOFFSET Long-term segment offset
–
–
20
2
–
–
mV
–
ILCDOP1
LCD system operating
current Vbias = 5 V
mA 32 4 segments at
50 Hz, 25°C
SID158
ILCDOP2
LCD system operating
current Vbias = 3.3 V
–
2
–
32 4 segments at
50 Hz, 25°C
Table 26
LCD direct drive AC specifications[8]
Description
LCD frame rate
Spec ID# Parameter
SID159
Min
10
Typ
50
Max Unit Details/conditions
150 Hz
FLCD
–
Note
8. Guaranteed by characterization.
Datasheet
47
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.5
Memory
5.5.1
Flash
Table 27
Flash DC specifications
Spec ID#
SID173
Parameter
VPE
Description
Erase and program voltage 1.71
Min Typ Max
5.5
Unit Details/conditions
–
V
–
Table 28
Flash AC specifications
Parameter
Spec ID#
SID174
Description
Min Typ Max
Unit Details/conditions
[9]
TROWWRITE
Row (block) write time
(erase and program)
Row erase time
Row program time after
erase
Bulk erase time (64KB)
Total device program time
Flash endurance
–
–
20
ms
Row (block) =
256 bytes
[9]
SID175
SID176
TROWERASE
TROWPROGRAM
–
–
–
–
16
4
–
–
[9]
[9]
SID178
TBULKERASE
–
–
–
–
–
–
35
7
–
–
[9]
SID180[10] TDEVPROG
SID181[10] FEND
SID182[10] FRET
Seconds –
100K
20
Cycles
Years
–
–
Flash retention. TA 55°C,
100K P/E cycles
Flash retention. TA 85°C,
10K P/E cycles
–
SID182A[1 FRET
10
–
–
–
–
–
0]
SID182B
FRETQ
Flash retention. TA 105°C, 10
10K P/E cycles with no more
than 3 years at TA 85°C
Guaranteed by
design
SID256
SID257
TWS48
TWS24
Number of Wait states at
48 MHz
Number of Wait states at
24 MHz
2
–
–
–
–
CPU execution
from Flash
CPU execution
from Flash
1
Notes
9. It can take as much as 20 milliseconds to write to flash. During this time the device should not be reset, or
flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the
XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and
watchdogs. Make certain that these are not inadvertently activated.
10.Guaranteed by characterization.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.6
System resources
5.6.1
Power-on reset (POR)
Table 29
Power-on reset (PRES)
Spec ID#
SID.CLK#6 SR_POWER
Parameter
Description
Power supply slew
rate
Min
1[11]
Typ
–
Max
67
Unit Details/conditions
V/ms On power-up and
power-down
SID185[12] VRISEIPOR
SID186[12] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
–
1.5
1.4
V
–
–
5.6.2
Brown-out detect (BOD)
Table 30
Brown-out detect (BOD) for VCCD
Spec ID#
Parameter
Description
Min
1.48
Typ
–
Max
1.62
Unit Details/conditions
SID190[12] VFALLPPOR
BOD trip voltage in
active and sleep
modes
BOD trip voltage in
Deep Sleep
V
–
SID192[12] VFALLDPSLP
1.11
–
1.5
–
5.6.3
SWD interface
Table 31
SWD interface specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[12] T_SWDI_SETUP T = 1/f SWDCLK
SID216[12] T_SWDI_HOLD T = 1/f SWDCLK
SID217[12] T_SWDO_VALID T = 1/f SWDCLK
SID217A[12] T_SWDO_HOLD T = 1/f SWDCLK
0.25 × T
0.25 × T
–
–
–
–
–
ns
–
–
–
–
–
0.5 × T
–
–
1
Notes
11.If the minimum ramp rate cannot be met, XRES should be asserted during the voltage ramp
(1.5 V > VDDD > 1.0 V for ramp-down or until the voltage is stable for ramp-up). Note that a glitch on the I2C
bus could occur during the voltage ramp in this case.
12.Guaranteed by characterization.
Datasheet
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Electrical specifications
5.6.4
Internal Main Oscillator
Table 32
IMO DC specifications
(Guaranteed by design)
Spec ID#
SID218
Parameter
IIMO1
Description
IMO operating current
at 48 MHz
Min
–
Typ
–
Max
250
Unit Details/conditions
µA
–
SID219
IIMO2
IMO operating current
at 24 MHz
–
–
180
µA
–
Table 33
IMO AC specifications
Spec ID# Parameter
Description
Min
Typ
Max Unit
Details/conditions
SID223
SID223A
SID333
FIMOTOL1
FIMOTOL1A
IMOWCO
Frequency variation at 24,
32, and 48 MHz (trimmed)
Frequency variation at 24,
32, and 48 MHz (trimmed)
–
–
–
–
–
–
±2
%
%
%
–40°C ≤ TA ≤ 105°C
±2.5
±0.25
–40°C ≤ TA ≤ 125°C
All IMO settings
IMO variation in
WCO-locked DPLL
mode
SID226
SID228
TSTARTIMO
TJITRMSIMO2 RMS jitter at 24 MHz
IMO startup time
–
–
–
145
7
–
µs
ps
–
–
5.6.5
Internal low-speed oscillator
Table 34
ILO DC specifications
(Guaranteed by design)
Spec ID# Parameter
Description
ILO operating current
Min
–
Typ
0.3
Max Unit
1.05 µA
Details/conditions
SID231
IILO1
–
Table 35
ILO AC specifications
Description
SID234[13] TSTARTILO1 ILO startup time
Spec ID# Parameter
Min
–
40
20
Typ
–
50
40
Max Unit
Details/conditions
2
60
80
ms
%
–
–
–
SID236[13] TILODUTY
ILO duty cycle
SID237
FILOTRIM1
ILO frequency range
kHz
Notes
13.Guaranteed by characterization.
Datasheet
50
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.6.6
Watch crystal oscillator (WCO)
Table 36
WCO specifications
Spec ID# Parameter
Description
Crystal frequency
Frequency tolerance
Equivalent series resistance
Drive level
Startup time
Crystal load capacitance
Crystal shunt capacitance
Min
–
–
–
–
–
6
–
–
Typ
32.768
50
50
–
–
–
1.35
–
Max Unit Details/conditions
kHz –
250 ppm With 20-ppm crystal
SID398
SID399
SID400
SID401
SID402
SID403
SID404
SID405
FWCO
FTOL
ESR
PD
TSTART
CL
–
–
1
kΩ
µW
ms
pF
–
–
–
–
–
–
500
12.5
–
C0
IWCO1
pF
Operating current (high
power mode)
8
µA
5.6.7
External clock
Table 37
External clock specifications
Spec ID# Parameter
Description
Min
0
Typ
–
Max Unit Details/conditions
SID305[14] ExtClkFreq External clock input
frequency
48
MHz –40°C ≤ TA ≤ 85°C
SID306[14] ExtClkDuty Duty cycle; measured at
VDD/2
45
–
55
%
–40°C ≤ TA ≤ 85°C
Notes
14.Guaranteed by design.
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Electrical specifications
5.6.8
External Crystal Oscillator (ECO) and PLL
Table 38
ECO specifications
Spec ID# Parameter
Description
External clock input
frequency
Min
–
Typ
–
Max Unit Details/conditions
SID316[15] IECO1
1.5
mA
–
SID317[15] FECO
Crystal frequency range
4
–
33
MHz –
Table 39
PLL specifications
Spec ID# Parameter
Description
Min
–
–
1
1
Typ
530
300
–
Max Unit Details/conditions
SID410
SID411
SID412
SID413
IDD_PLL_48 In = 3 MHz, Out = 48 MHz
IDD_PLL_24 In = 3 MHz, Out = 24 MHz
Fpllin
610
405
48
µA
µA
MHz –
MHz –
–
–
PLL input frequency
PLL intermediate
frequency; prescaler out
Fpllint
–
3
SID414
SID415
Fpllvco
Divvco
VCO output frequency
before post-divide
VCO Output post-divider
range; PLL output
frequency is Fpplvco/Divvco
22.5
1
–
–
104
8
MHz –
–
SID416
SID417
Plllocktime Lock time at startup
–
–
–
–
250
150
µs
–
Jperiod_1
Period jitter for
VCO ≥ 67 MHz
ps Guaranteed by
design
–40°C ≤ TA ≤ 85°C
SID416A
Jperiod_2
Period jitter for
VCO ≤ 67 MHz
–
–
200
ps Guaranteed by
design
–40°C ≤ TA ≤ 85°C
5.6.9
System clock
Table 40
Block specs
Spec ID# Parameter
Description
Min
3
Typ
–
Max
4
Unit Details/conditions
Periods –
SID262[15] TCLKSWITCH System clock source
switching time
5.6.10
Smart I/O
Table 41
Smart I/O pass-through time (delay in bypass mode)
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID252
PRG_BYPASS Max delay added by smart
I/O in bypass mode
–
–
1.6
ns
–
Notes
15.Guaranteed by design.
Datasheet
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6
Ordering information
Table 42 lists the marketing part numbers (MPNs) for the PSoC™ 4700S Plus devices.
Table 42 Ordering information
4700S Plus CY8C4746LQS-S263 48 64
4700S Plus CY8C4747LQS-S453 48 128
8
8
–
–
–
2
X
X
X
X
–
X
1000 Ksps
1000 Ksps
2
2
8
8
4
4
X
X
X
X
19
19
–
–
34
34
X
X
–
–
X
X
–
–
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C
4
A
B
Description
Infineon prefix
Architecture
Family
Values
Meaning
4
7
2
PSoC™ 4
4700S family
CPU speed
24 MHz
4
48 MHz
C
Flash capacity
4
16 KB
5
32 KB
6
7
64 KB
128 KB
DE
F
S
Package code
Temperature range
Silicon family
LQ
S
S
QFN
Automotive (AEC-Q100: –40°C to +105°C)
PSoC™ 4 S-series
M
L
PSoC™ 4 M-series
PSoC™ 4 L-series
XYZ
Attributes code
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY8C
4
A
B
C
DE
F
S
XYZ
T
T = Tape and reel
Attributes code
Silicon family
Temperature range
Package code
Flash capacity
CPU speed
Family within architecture
Architecture
Infineon prefix
Example
4: PSoC™ 4
1: 4700S Plus family
4: 48 MHz
6: 64 KB
LQ: QFN
S: Automotive
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Packaging
7
Packaging
The PSoC™ 4700S Plus will be offered in 40-QFN package.
Table 43 provides the package dimensions and drawing numbers.
Table 43
Spec ID#
BID27A
Package list
Package
Description
Package dwg
002-25105
40-pin QFN
6 × 6 × 0.6-mm height with 0.5-mm pitch with wettable
flanks
Table 44
Package thermal characteristics
Parameter
Description
Package
Conditions
Min
Typ
Max Unit
TA
Operating ambient
temperature
Operating junction
temperature
For S-grade devices
–40
25
105
–
–
TJ
For S-grade devices
–40
–
115
TJA
TJC
Package θJA
40-pin QFN
40-pin QFN
–
–
–
–
25
3
–
–
°C/W
°C/W
Package θJC
Table 45
Solder reflow peak temperature
Package Maximum peak temperature
All 260 °C
Maximum time at peak temperature
30 seconds
Table 46
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
All
MSL
MSL 3
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Packaging
7.1
Package diagram
002-25105 *A
Figure 8
40-pin QFN (6 × 6 × 0.6 mm (4.6 × 4.6 mm E-Pad (Sawn))) package outline
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Acronyms
8
Acronyms
Table 47
Acronyms used in this document
Acronym
Description
abus
ADC
AG
analog local bus
analog-to-digital converter
analog global
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
AHB
ALU
arithmetic logic unit
AMUXBUS
API
APSR
ARM®
ATM
BW
analog multiplexer bus
application programming interface
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
bandwidth
CAN
CMRR
CPU
CRC
DAC
DFB
Controller Area Network, a communications protocol
common-mode rejection ratio
central processing unit
cyclic redundancy check, an error-checking protocol
digital-to-analog converter, see also IDAC, VDAC
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
DMIPS
DMA
DNL
DNU
DR
port write data registers
DSI
digital system interconnect
DWT
ECC
data watchpoint and trace
error correcting code
ECO
EEPROM
EMI
EMIF
EOC
EOF
external crystal oscillator
electrically erasable programmable read-only memory
electromagnetic interference
external memory interface
end of conversion
end of frame
EPSR
ESD
execution program status register
electrostatic discharge
ETM
FIR
FPB
embedded trace macrocell
finite impulse response, see also IIR
flash patch and breakpoint
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Acronyms
Table 47
Acronyms used in this document (continued)
Description
Acronym
FS
full-speed
GPIO
HVI
IC
general-purpose input/output, applies to a PSoC™ pin
high-voltage interrupt, see also LVI, LVD
integrated circuit
IDAC
IDE
I2C, or IIC
IIR
ILO
IMO
INL
current DAC, see also DAC, VDAC
integrated development environment
Inter-Integrated Circuit, a communications protocol
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
I/O
IPOR
IPSR
IRQ
interrupt program status register
interrupt request
ITM
LCD
LIN
instrumentation trace macrocell
liquid crystal display
Local Interconnect Network, a communications protocol.
link register
LR
LUT
LVD
LVI
LVTTL
MAC
MCU
MISO
NC
lookup table
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
master-in slave-out
no connect
NMI
NRZ
NVIC
NVL
opamp
PAL
nonmaskable interrupt
non-return-to-zero
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
programmable array logic, see also PLD
program counter
PC
PCB
PGA
PHUB
PHY
PICU
PLA
printed circuit board
programmable gain amplifier
peripheral hub
physical layer
port interrupt control unit
programmable logic array
Datasheet
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Acronyms
Table 47
Acronyms used in this document (continued)
Description
Acronym
PLD
PLL
programmable logic device, see also PAL
phase-locked loop
PMDD
POR
PRES
PRS
PS
package material declaration data sheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
PSoC™
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
Programmable system-on-chip
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
register transfer language
remote transmission request
receive
RTR
RX
SAR
SC/CT
SCL
SDA
S/H
successive approximation register
switched capacitor/continuous time
I2C serial clock
I2C serial data
sample and hold
SINAD
SIO
SOC
SOF
SPI
signal to noise and distortion ratio
special input/output, GPIO with advanced features. See GPIO.
start of conversion
start of frame
Serial Peripheral Interface, a communications protocol
slew rate
SR
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
TX
UART
UDB
Universal Asynchronous Transmitter Receiver, a communications protocol
universal digital block
Datasheet
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Acronyms
Table 47
Acronyms used in this document (continued)
Description
Acronym
USB
Universal Serial Bus
USBIO
VDAC
WDT
USB input/output, PSoC™ pins used to connect to a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
WRES
XRES
XTAL
crystal
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Document conventions
9
Document conventions
9.1
Units of measure
Table 48
Units of measure
Symbol
Unit of measure
°C
dB
degrees celsius
decibel
fF
Hz
femto farad
hertz
KB
1024 bytes
kbps
Khr
kHz
k
ksps
LSB
Mbps
MHz
M
Msps
µA
kilobits per second
kilohour
kilohertz
kilo ohm
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
µs
µV
microhenry
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
sqrtHz
V
samples per second
square root of hertz
volt
Datasheet
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Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Revision history
Revision history
Document
Date
Description of changes
revision
**
2021-12-16
Initial release.
Changed the datasheet status from Target datasheet to Datasheet (Final).
Updated Electrical specifications:
Updated Analog peripherals:
Updated Inductive sensing:
Updated Table 17.
Updated System resources:
*A
2022-03-21
Updated Power-on reset (POR):
Added Note 11 and referred the same note in minimum value of SR_POWER
parameter in Table 29.
Updated Packaging:
Updated Table 44.
Updated Block diagram:
Updated Figure 2.
Updated Functional definition:
Updated Inductive sensing:
Added SNR vs target distance.
Added Distance delta (metal target displacement) when SNR = 5.
Added Raw counts vs target distance.
Added Noiseless precision.
Added Sensitivity.
*B
2022-09-19
Added Noise floor (%).
Added Effective number of bits (ENOB).
Added Scan time.
Added Detection range.
Updated Electrical specifications:
Updated Analog peripherals:
Updated Inductive sensing:
Updated Table 17.
Completing Sunset Review.
Updated General description:
Updated description.
Updated Features:
Updated description.
Updated Block diagram:
Updated Figure 2.
Updated Functional definition:
Updated Inductive sensing:
Updated description.
*C
2023-03-17
Added Figure 5.
Updated Pinouts:
Updated description.
Updated Alternate pin functions:
Updated description.
Updated Table 2.
Updated Power:
Updated Mode 2: 1.8 V ± 5% external supply:
Updated Figure 7.
Datasheet
62
002-34139 Rev. *C
2023-03-17
Automotive PSoC™ 4 MCU: PSoC™ 4700S Plus
Revision history
Document
Date
Description of changes
revision
Updated Electrical specifications:
Updated Analog peripherals:
Updated Inductive sensing:
Updated Table 17.
*C
2023-03-17
Updated Ordering information:
Updated Table 42 (No change in part numbers; updated details under
“Smart IOs” column).
Updated to new template.
Datasheet
63
002-34139 Rev. *C
2023-03-17
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Edition 2023-03-17
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