CY8C6144AZI-S4F82 [INFINEON]
32-位PSoC™ 6 Arm® Cortex®-M4 / M0+;型号: | CY8C6144AZI-S4F82 |
厂家: | Infineon |
描述: | 32-位PSoC™ 6 Arm® Cortex®-M4 / M0+ |
文件: | 总74页 (文件大小:1248K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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PSoC 6 MCU: CY8C61x4
Datasheet
PSoC 61 MCU
General Description
PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C61x4
product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology,
digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.
Features
Note: In PSoC 61 the Cortex M0+ is reserved for system
functions, and is not available for applications.
Segment LCD Drive
■ Supports up to 61 segments and up to 8 commons
■ Operates in System Deep Sleep mode
32-bit Dual CPU Subsystem
■ 150-MHz Arm® Cortex®-M4F (CM4) with single-cycle multiply
(Floating Point and Memory Protection Unit)
Serial Communication
■ Six run-time configurable serial communication blocks (SCBs)
❐ Five SCBs: configurable as SPI, I2C, or UART
❐ One Deep Sleep SCB: configurable as SPI or I2C
■ USB Full-Speed device interface
■ 100-MHz Cortex-M0+ (CM0+) with single-cycle multiply and
MPU
■ User-selectable core logic operation at either 1.1 V or 0.9 V
■ Active CPU current slope with 1.1-V core operation
❐ Cortex-M4: 40 µA/MHz
■ One CAN FD block
❐ Cortex-M0+: 20 µA/MHz
Timing and Pulse-Width Modulation
■ Active CPU current slope with 0.9-V core operation
❐ Cortex-M4: 22 µA/MHz
❐ Cortex-M0+: 15 µA/MHz
■ Twelve timer/counter pulse-width modulators (TCPWMs)
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals
■ Three DMA controllers
Programmable Analog
Memory Subsystem
■ Two 12-bit 2-Msps SAR ADCs with synchronized sampling,
differential and single-ended modes, 16-channel sequencer
with result averaging, and Deep Sleep operation
■ 256-KB application flash and 32-KB supervisory flash (SFlash);
read-while-write (RWW) support. Two 8-KB flash caches, one
for each CPU.
■ One12-bitvoltage-modedigital-to-analogconverter(DAC)with
< 2-μs settling time
■ 128-KB SRAM with programmable power control and retention
granularity
■ Two low-power comparators available in Deep Sleep and
Hibernate modes
■ One-time-programmable (OTP) 1-Kb eFuse array
Low-Power 1.7-V to 3.6-V Operation
■ Two opamps with low-power operation modes
■ Always-on low frequency Deep Sleep operation
■ Built-in temperature sensor connected to ADC
■ Six power modes for fine-grained power management
■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention
■ On-chip DC-DC Buck converter, <1-µA quiescent current
■ Backup domain with 64 bytes of memory and real-time clock
Up to 62 Programmable GPIOs
■ One Smart I/O™ port (6 I/Os) enables Boolean operations on
GPIO pins; available during system Deep Sleep
Flexible Clocking Options
■ 8-MHz internal main oscillator (IMO) with ±2% accuracy
■ Ultra-low-power 32-kHz internal low-speed oscillator (ILO)
■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
■ Phase-locked loop (PLL) for multiplying clock frequency
■ Frequency-locked loop (FLL) for multiplying IMO frequency
■ Programmable drive modes, strengths, and slew rates
■ Two overvoltage-tolerant (OVT) pins
Quad-SPI (QSPI)/Serial Memory Interface (SMIF)
■ Execute-In-Place (XIP) from external Quad SPI Flash
■ On-the-fly encryption and decryption
■ 4-KB cache for greater XIP performance with lower power
■ Supports single, dual, and quad interfaces with throughput up
to 320 Mbps
Cypress Semiconductor Corporation
Document Number: 002-33480 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 18, 2022
PSoC 6 MCU: CY8C61x4
Datasheet
Capacitive Sensing
Device Identification and Revisions
■ Cypress CapSense® Sigma-Delta (CSD) provides
■ Product line ID (12-bit): 0x10E
■ Major/Minor die revision ID: 1/3
best-in-class SNR, liquid tolerance, and proximity sensing
■ Enables dynamic usage of both self and mutual sensing
■ Automatic hardware tuning (SmartSense™)
■ Firmware Revisions: ROM Boot: 8.1, Flash Boot: 3.1.0.528
(see Boot Code section)
Security Built into Platform Architecture
■ Authentication during boot using hardware hashing
■ All debug and test ingress paths can be disabled
■ Up to eight protection contexts
This product line has a JTAG ID which is available through the
SWJ interface. It is a 32-bit ID, where:
■ The most significant digit is the device revision, based on the
Major Die Revision
Cryptography Accelerators
■ The next four digits correspond to the part number, for example
■ Hardware acceleration for symmetric and asymmetric
"E4B0" as a hexadecimal number
cryptographic methods and hash functions
■ The three least significant digits are the manufacturer ID, in this
case "069" as a hexadecimal number
■ True random number generation (TRNG) function
The Silicon ID system call can be used by firmware to get Silicon
ID and ROM Boot data. For more information, see the technical
reference manual (TRM).
Packages
■ 80-TQFP, 64-TQFP, 68-QFN
The Flash Boot version can be read directly from designated
addresses 0x1600 2004 and 0x1600 2018. For more
information, see the technical reference manual (TRM).
Document Number: 002-33480 Rev. *E
Page 2 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Contents
Development Ecosystem................................................. 4
PSoC 6 MCU Resources .............................................4
ModusToolbox Software ..............................................5
Blocks and Functionality................................................. 6
Functional Description..................................................... 8
CPU and Memory Subsystem .....................................8
System Resources ....................................................11
Programmable Analog Subsystems ..........................14
Programmable Digital ................................................16
Fixed-Function Digital ................................................16
GPIO .........................................................................17
CapSense Subsystem ...............................................18
Pinouts ............................................................................ 21
Power Supply Considerations....................................... 31
Electrical Specifications ................................................ 36
Absolute Maximum Ratings .......................................36
Device-Level Specifications ......................................36
Analog Peripherals ....................................................44
Digital Peripherals .....................................................54
Memory .....................................................................57
System Resources ....................................................58
Ordering Information...................................................... 63
PSoC 6 MPN Decoder ..............................................63
Packaging........................................................................ 65
Acronyms........................................................................ 69
Document Conventions ................................................. 71
Units of Measure .......................................................71
Revision History ............................................................. 72
Sales, Solutions, and Legal Information ...................... 73
Worldwide Sales and Design Support .......................73
Products ....................................................................73
PSoC® Solutions ......................................................73
Cypress Developer Community .................................73
Technical Support .....................................................73
Document Number: 002-33480 Rev. *E
Page 3 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Development Ecosystem
PSoC 6 MCU Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated list of resources for PSoC 6 MCU:
■ Overview: PSoC Portfolio, PSoC Roadmap
■ Product Selectors: PSoC 6 MCU
■ PSoC 6 MCU Programming Specification provides the infor-
mation necessary to program PSoC 6 MCU nonvolatile
memory
■ Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
❐ AN221774: Getting Started with PSoC 6 MCU
■ Development Tools
❐ The ModusToolbox® software enables cross platform code
developmentwitharobustsuiteoftoolsandsoftwarelibraries
❐ AN218241: PSoC 6 MCU Hardware Design Guide
❐ AN213924: PSoC 6 MCU Device Firmware Update Guide
❐ AN215656: PSoC 6 MCU Dual-CPU System Design
❐ AN219528: PSoC 6 MCU Power Reduction Techniques
❐ AN221111: PSoC 6 MCU Creating a Secured System
❐ AN85951: PSoC 4, PSoC 6 MCU CapSense Design Guide
❐ There is no kit available for the PSoC 61 product line. How-
ever, the CY8CKIT-062S4 PSoC 62S4 Pioneer Kit is avail-
able: a low-cost hardware platform that enables design and
debug of the PSoC 62 CY8C62x5 product line.
❐ PSoC 6 CAD libraries provide footprint and schematic sup-
port for common tools. BSDL files and IBIS models are also
available.
■ CodeExamplesdemonstrateproductfeaturesandusage,and
are also available on Cypress GitHub repositories.
■ Training Videos are available on a wide range of topics
including the PSoC 6 MCU 101 series
■ Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 6 MCU architecture and registers.
■ Cypress Developer Community enables connection with
fellow PSoC developers around the world, 24 hours a day, 7
days a week, and hosts a dedicated PSoC 6 MCU Community
Document Number: 002-33480 Rev. *E
Page 4 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
ModusToolbox Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive
development experience for creating converged MCU and wireless systems. It is:
■ Comprehensive - it has the resources you need
■ Flexible - you can use the resources in your own workflow
■ Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub. This includes:
■ Board Support Packages (BSPs) aligned with Cypress kits
■ Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL)
■ Middleware enabling industry-leading features such as CapSense®, Bluetooth Low Energy, and mesh networks
■ An extensive set of thoroughly tested code example applications
Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Cypress MCUs. It is a generic
interface that can be used across multiple product families. For example, it wraps the PSoC 6 PDL with a simplified API, but the PDL
exposes all low-level peripheral functionality. You can leverage the HAL's simpler and more generic interface for most of an application,
even if one portion requires finer-grained control.
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a
project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox. For
information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and AN228571: Getting Started
with PSoC 6 MCU on ModusToolbox.
Figure 1. ModusToolbox Software Tools
Document Number: 002-33480 Rev. *E
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PSoC 6 MCU: CY8C61x4
Datasheet
Blocks and Functionality
Figure 2 shows the major subsystems and a simplified view of their interconnections. The color coding shows the lowest power mode
where a block is still functional. For example, the SRAM is functional down to Sleep Mode.
Figure 2. Block Diagram
Color Key:
Power Modes and
Domains
PSoC 61 MCU
CY8C61x4
Programmable Analog
2x SAR ADC 12-bit
System LP/ULP Mode
CPUs Active/Sleep
System Resources
DAC 12-bit
Power
Clocks
OVP
POR
LVD
IMO
FLL
ECO
PLL
2x Opamp
System
DeepSleep Mode
BOD
Temperature Sensor
Buck Regulator
XRES Reset
Backup Regs
2x MCWDT
ILO
RTC
WDT
WCO
System
Hibernate Mode
CapSense
LCD
PMIC Control
Backup
Domain
LP Comparator
CPU Subsystem
12x TCPWM
SCB
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
5x I2C, SPI,
UART, or LIN
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
I2C or SPI
eFuse: 1024 bits
CAN FD
3x DMA
Controller
QSPI (SMIF)
with OTF Encryption/Decryption
Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator
USB
PHY
USB -FS
Flash
256 KB + 32 KB
8 KB cache for each CPU
SRAM
128 KB
ROM
64 KB
Document Number: 002-33480 Rev. *E
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PSoC 6 MCU: CY8C61x4
Datasheet
There are three debug access ports, one each for CM4 and CM0+, and a system port.
PSoC 6 MCU devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All
device interfaces can be permanently disabled (device security) for applications concerned about attacks due to a maliciously
reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming,
debug, and test interfaces are disabled when maximum device security is enabled. The security level is settable by the user.
Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does
not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required
to fully support debug.
The Eclipse IDE for ModusToolbox provides fully integrated programming and debug support for these devices. The SWJ (SWD and
JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust
flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks,
PSoC 6 MCU provides multiple levels of security.
Document Number: 002-33480 Rev. *E
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PSoC 6 MCU: CY8C61x4
Datasheet
CPU and Memory Subsystem
Functional Description
PSoC 6 has multiple bus masters, as Figure 2 shows. They are:
CPUs, DMA controllers, QSPI,USB, and a Crypto block.
Generally, all memory and peripherals can be accessed and
shared by all bus masters through multi-layer Arm AMBA
high-performance bus (AHB) arbitration. Accesses between
CPUs can be synchronized using an inter-processor
communication (IPC) block.
The following sections provide an overview of the features,
capabilities and operation of each functional block identified in
the block diagram in Figure 2. For more detailed information,
refer to the following documentation:
■ Board Support Package (BSP) Documentation
BSPs are available on GitHub. They are aligned with Cypress
kits and provide files for basic device functionality such as
hardware configuration files, startup code, and linker files.
The BSP also includes other libraries that are required to sup-
port a kit. Each BSP has its own documentation, but typically
includes an API reference such as the example here. This
search link finds all currently available BSPs on the Cypress
GitHub site.
CPUs
There are two Arm Cortex CPUs:
The Cortex-M4 (CM4) has single-cycle multiply, a floating-point
unit (FPU), and a memory protection unit (MPU). It can run at up
to 150 MHz. This is the main CPU, designed for a short interrupt
response time, high code density, and high throughput.
CM4 implements a version of the Thumb instruction set based
on Thumb-2 technology (defined in the Armv7-M Architecture
Reference Manual).
■ Hardware Abstraction Layer API Reference Manual
The Cypress Hardware Abstraction Layer (HAL) provides a
high-level interface to configure and use hardware blocks on
Cypress MCUs. It is a generic interface that can be used
across multiple product families. You can leverage the HAL's
simpler and more generic interface for most of an application,
even if one portion requires finer-grained control. The HAL
API Reference provides complete details. Example applica-
tions that use the HAL download it automatically from the
GitHub repository.
The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU.
It can run at up to 100 MHz; however, for CM4 speeds above
100 MHz, CM0+ and bus peripherals are limited to half the speed
of CM4. Thus, for CM4 running at 150 MHz, CM0+ and
peripherals are limited to 75 MHz.
CM0+ is the secondary CPU; it is used to implement system calls
and device-level security, safety, and protection features.
■ Peripheral Driver Library (PDL) Application Programming
Interface (API) Reference Manual
CM0+ implements the Armv6-M Thumb instruction set (defined
in the Armv6-M Architecture Reference Manual).
The Peripheral Driver Library (PDL) integrates device header
files and peripheral drivers into a single package and supports
all PSoC 6 MCU product lines. The drivers abstract the hard-
ware functions into a set of easy-to-use APIs. These are fully
documented in the PDLAPI Reference. Example applications
that use the PSoC 6 PDL download it automatically from the
GitHub repository.
The CPUs have the following power draw, at VDDD = 3.3 V and
using the internal buck regulator:
Table 1. Active Current Slope at VDDD = 3.3 V Using the
Internal Buck Regulator
System Power Mode
ULP
LP
■ Architecture Technical Reference Manual (TRM)
Cortex-M0+
Cortex-M4
15 A/MHz
22 A/MHz
20 A/MHz
40 A/MHz
CPU
The architecture TRM provides a detailed description of each
resource in the device. This is the next reference to use if it is
necessary to understand the operation of the hardware below
the software provided by PDL. It describes the architecture
and functionality of each resource and explains the operation
of each resource in all modes. It provides specific guidance
regarding the use of associated registers.
The CPUs can be selectively placed in their Sleep and Deep
Sleep power modes as defined by Arm.
Both CPUs have nested vectored interrupt controllers (NVIC) for
rapid and deterministic interrupt response, and wakeup interrupt
controllers (WIC) for CPU wakeup from Deep Sleep power
mode.
■ Register Technical Reference Manual
The CPUs have extensive debug support. PSoC 6 has a debug
access port (DAP) that acts as the interface for device
programming and debug. An external programmer or debugger
(the “host”) communicates with the DAP through the device
serial wire debug (SWD) or Joint Test Action Group (JTAG)
interface pins. Through the DAP (and subject to device security
restrictions), the host can access the device memory and
peripherals as well as the registers in both CPUs.
The register TRM provides a complete list of all registers in
the device. It includes the breakdown of all register fields,
their possible settings, read/write accessibility, and default
states. All registers that have a reasonable use in typical ap-
plications have functions to access them from within PDL.
Note that ModusToolbox and PDL may provide software de-
fault conditions for some registers that are different from and
override the hardware defaults.
Each CPU offers debug and trace features as follows:
■ CM4 supports six hardware breakpoints and four watchpoints,
4-bit embedded trace macrocell (ETM), serial wire viewer
(SWV), and printf()-style debugging through the single wire
output (SWO) pin.
Document Number: 002-33480 Rev. *E
Page 8 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
■ CM0+ supports four hardware breakpoints and two watch-
points, and a micro trace buffer (MTB) with 4 KB dedicated
RAM.
source and destination. The size of data transfer per descriptor
varies based on the type of DMA channel. Refer to the technical
reference manual for details.
PSoC 6 also has an Embedded Cross Trigger for synchronized
debugging and tracing of both CPUs.
Cryptography Accelerator (Crypto)
This subsystem consists of hardware implementation and
acceleration of cryptographic functions and random number
generators.
Interrupts
This product line has 175system and peripheral interrupt
sources and supports interrupts and system exception on both
CPUs. CM4 has 175 interrupt request lines (IRQ), with the
interrupt source ‘n’ directly connected to IRQn. CM0+ has eight
interrupts IRQ[7:0] with configurable mapping of one or more
interrupt sources to any of the IRQ[7:0]. CM0+ also supports
eight internal (software only) interrupts.
The Crypto subsystem supports the following:
■ Encryption/Decryption Functions
❐ Data Encryption Standard (DES)
❐ Triple DES (3DES)
❐ Advanced Encryption Standard (AES) (128-, 192-, 256-bit)
❐ Elliptic Curve Cryptography (ECC)
❐ RSA cryptography functions
Each interrupt supports configurable priority levels (eight levels
for CM4 and four levels for CM0+). Up to four system interrupts
can be mapped to each of the CPUs' non-maskable interrupts
(NMI). Up to 45 interrupt sources are capable of waking the
device from Deep Sleep power mode using the WIC. Refer to the
technical reference manual for details.
■ Hashing functions
❐ Secure Hash Algorithm (SHA)
❐ SHA-1
❐ SHA-224/-256/-384/-512
InterProcessor Communication (IPC)
■ Message authentication functions (MAC)
In addition to the Arm SEV and WFE instructions, a hardware
InterProcessor Communication (IPC) block is included. It
includes 16 IPC channels and 16 IPC interrupt structures. The
IPC channels can be used to implement data communication
between the processors. Each IPC channel also implements a
locking scheme which can be used to manage shared resources.
The IPC interrupts let one processor interrupt the other, signaling
an event. This is used to trigger events such as notify and release
of the corresponding IPC channels. Some IPC channels and
other resources are reserved, as Table 2 shows:
❐ Hashed message authentication code (HMAC)
❐ Cipher-based message authentication code (CMAC)
■ 32-bit cyclic redundancy code (CRC) generator
■ Random number generators
❐ Pseudo random number generator (PRNG)
❐ True random number generator (TRNG)
Protection Units
This product line has multiple types of protection units to control
erroneous or unauthorized access to memory and peripheral
registers. CM4 and CM0+ have Arm MPUs for protection at the
bus master level. Other bus masters use additional MPUs.
Shared memory protection units (SMPUs) help implement
memory protection for memory/ resources that are shared
among multiple bus masters. Peripheral protection units (PPU)
are similar to SMPUs but are designed for protecting the
peripheral register space.
Table 2. Distribution of IPC Channels and Other Resources
Resources Available
Resources Consumed
IPC channels,
16 available
8 reserved
IPC interrupts,
16 available
8 reserved
Protection units support memory and peripheral access
attributes including address range, read/write, code/data,
privilege level, secured/non-secured, and protection context.
Some protection unit resources are reserved for system usage;
see the technical reference manual (TRM) for details.
Other interrupts
CM0+ NMI
1 reserved
Reserved
Other resources:
clock dividers, DMA
channels, etc.
1 CM0+ interrupt mux
Direct Memory Access (DMA) Controllers
This product line has three DMA controllers, with 32, 30, and 2
channels, which support CPU-independent accesses to memory
and peripherals. The descriptors for DMA channels can be in
SRAM or flash. Therefore, the number of descriptors are limited
only by the size of the memory. Each descriptor can transfer data
in two nested loops with configurable address increments to the
Document Number: 002-33480 Rev. *E
Page 9 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Memory
Boot Code
PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks.
Two blocks of code, ROM Boot and Flash Boot, are
pre-programmed into the device and work together to provide
device startup and configuration, basic security features,
life-cycle stage management and other system functions.
■ Flash
There is up to 256 KB of application flash, organized in
128 KB sectors. There is also a 32 KB supervisory flash
(SFlash) sector.
■ ROM Boot
On a device reset, the boot code in ROM is the first code to
execute. This code performs the following:
❐ Integrity checks of flash boot code
❐ Device trim setting (calibration)
❐ Setting the device protection units
Data stored in SFlash includes device trim values, Flash Boot
code, and encryption keys. After the device transitions into
the “Secure” lifecycle stage, SFlash can no longer be
changed.
The flash has 128-bit-wide accesses to reduce power. This
enables flash updates during code execution. Write opera-
tions can be performed at the row level. A row is 512 bytes.
Read operations are supported in both System Low Power
and Ultra-Low Power modes, however write operations may
not be performed in System Ultra-Low Power mode.
❐ Setting device access restrictions for lifecycle states
ROM cannot be changed and acts as the root of trust in a
secured system.
■ Flash Boot
Flash boot is firmware stored in SFlash that ensures that only
a validated application may run on the device. It also ensures
that the firmware image has not been modified, such as by a
malicious third party.
The flash controller has two caches, one for each CPU. Each
cache is 8 KB, with 4-way set associativity.
■ SRAM
Flash boot:
Up to 128 KB of SRAM is provided. Power control and reten-
tion granularity is implemented in 32 KB blocks allowing the
user to control the amount of memory retained in Deep Sleep.
Memory is not retained in Hibernate mode.
❐ Is validated by ROM Boot
❐ Runs after ROM Boot and before the user application
❐ Enables system calls
❐ Configures the Debug Access Port
❐ Launches the user application
■ ROM
If the user application cannot be validated, then flash boot
ensures that the device is transitioned into a safe state.
The 64-KB ROM, also referred to as the supervisory ROM
(SROM), provides code (ROM Boot) for several system func-
tions. The ROM contains device initialization, flash write, se-
curity, eFuse programming, and other system-level routines.
ROM code is executed only by the CM0+ CPU, in protection
context 0. A system function can be initiated by either CPU,
or through the DAP. This causes an NMI in CM0+, which
causes CM0+ to execute the system function.
■ eFuse
A one-time-programmable (OTP) eFuse array consists of
1024 bits, of which 648 are reserved for system use such as
die ID, device ID, initial trim settings, device life cycle, and
security settings. The remaining bits are available for storing
security key information, hash values, unique IDs or similar
custom content.
Each fuse is individually programmed; once programmed (or
“blown”), its state cannot be changed. Blowing a fuse transi-
tions it from the default state of 0 to 1. To program an eFuse,
VDDIO0 must be at 2.5 V ±5%, at 14 mA.
Because blowing an eFuse is an irreversible process, pro-
gramming is recommended only in mass production program-
ming under controlled factory conditions. For more informa-
tion, see PSoC 6 MCU Programming Specifications.
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PSoC 6 MCU: CY8C61x4
Datasheet
Memory Map
System Resources
Both CPUs have a fixed address map, with shared access to
memory and peripherals. The 32-bit (4 GB) address space is
divided into Arm-defined regions shown in Table 3. Note that
Code can be executed from the code and External RAM regions.
Power System
The power system provides assurance that voltage levels are as
required for each respective mode and will either delay mode
entry (on power-on reset (POR), for example) until voltage levels
are as required for proper function or generate resets (brown-out
detect (BOD)) when the power supply drops below specified
levels. The design guarantees safe chip operation between
power supply voltage dropping below specified levels (for
example, below 1.7 V) and the reset occurring. There are no
voltage sequencing requirements. The VDDD supply (1.7 to
3.6 V) powers an on-chip buck regulator or a low-dropout
regulator (LDO), selectable by the user. In addition, both the buck
and the LDO offer a selectable (0.9 or
Table 3. Address Map for CM4 and CM0+
Address Range
Name
Use
Program code region.
Datacanalsobeplaced
here. It includes the
exception vector table,
which starts at address
0.
0x0000 0000 – 0x1FFF FFFF
Code
Data region. This
region is not supported
in PSoC 6.
0x2000 0000 – 0x3FFF FFFF
SRAM
1.1 V) core operating voltage (VCCD).The selection lets users
choose between two system power modes:
All peripheral registers.
Code cannot be
■ System Low Power (LP) operates VCCD at 1.1 V and offers high
performance, with no restrictions on device configuration.
executed from this
region. CM4 bit-band in
this region is not
0x4000 0000 – 0x5FFF FFFF Peripheral
■ System Ultra Low Power (ULP) operates VCCD at 0.9 V for
exceptional low power, but imposes limitations on maximum
clock speeds.
supported in PSoC 6.
SMIF or Quad SPI, (see
the Quad-SPI/Serial
External Memory Interface
In addition, a backup domain adds an “always on” functionality
using a separate power domain supplied by a backup supply
(VBACKUP) such as a battery or supercapacitor. It includes a
real-time clock (RTC) with alarm feature, supported by a
0x6000 0000 – 0x9FFF FFFF
0xA000 0000 – 0xDFFF FFFF
RAM
(SMIF) section). Code
can be executed from
this region.
External
Device
Not used.
32.768-kHz
watch
crystal
oscillator
(WCO),
and
power-management IC (PMIC) control. Pin 5 of Port 0 (P0.5) can
be assigned as an enable signal for an external PMIC.
Private
Provides access to
0xE000 0000 – 0xE00F FFFF Peripheral peripheral registers
Bus
within the CPU core.
RTC alarms can be used as a trigger for the PMIC enable signal.
The backup domain can generate a wake-up interrupt to the chip
via the RTC timers or an external input.
Device-specific system
registers.
0xE010 A000 – 0xFFFF FFFF
Device
The device memory map shown in Table 4 applies to both CPUs.
That is, the CPUs share access to all PSoC 6 MCU memory and
peripheral registers.
Power Modes
PSoC 6 MCUcan operate in four system and three CPU power
modes. These modes are intended to minimize the average
power consumption in an application. For more details on power
modes and other power-saving configuration options, see the
application note, AN219528: PSoC 6 MCU Low-Power Modes
and Power Reduction Techniques and the Architecture TRM,
Power Modes chapter.
Table 4. Internal Memory Address Map for CM4 and CM0+
Address Range
Memory Type
Size
0x0000 0000 – 0x0000 FFFF
ROM
64 KB
Up to
0x0800 0000 –0x0801 FFFF
0x1000 0000 –0x1003 FFFF
SRAM
128 KB
Power modes supported by PSoC 6 MCUs, in the order of
decreasing power consumption, are:
Up to
256 KB
Application flash
■ System Low Power (LP) – All peripherals and CPU power
modes are available at maximum speed
0x1600 0000 – 0x1600 7FFF Supervisory flash 32 KB
■ System Ultra Low Power (ULP) – All peripherals and CPU
power modes are available, but with limited speed
Note that the PSoC 6 SRAM is located in the Arm Code region
for both CPUs (see Table 3). There is no physical memory
located in the CPUs’ Arm SRAM regions.
■ CPUActive – CPU is executing code in system LPor ULPmode
■ CPU Sleep – CPU code execution is halted in system LP or
ULP mode
■ CPU Deep Sleep – CPU code execution is halted and system
Deep Sleep is requested in system LP or ULP mode
■ System Deep Sleep – Only low-frequency peripherals are
available after both CPUs enter CPU Deep Sleep mode
■ System Hibernate – Device and I/O states are frozen and the
device resets on wakeup
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Page 11 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
CPU Active, Sleep, and Deep Sleep are standard Arm-defined
power modes supported by the Arm CPU instruction set
architecture (ISA). LP, ULP, Deep Sleep and Hibernate modes
are additional low-power modes supported by PSoC 6 MCU.
Clocks may be buffered and brought out to a pin on a smart I/O
port.
The default clocking when the application starts is CLK_HF[0]
being driven by the IMO and the FLL. CLK_HF[0], clk_fast,
clk_peri, and clk_slow are all either 50 MHz (LP mode) or 25 MHz
(ULP mode). All other clocks, including all peripheral clocks, are
off.
Clock System
Figure 3 shows that the clock system of this product line consists
of the following:
Internal Main Oscillator (IMO)
■ Internal main oscillator (IMO)
■ Internal low-speed oscillator (ILO)
■ Watch crystal oscillator (WCO)
■ External MHz crystal oscillator (ECO)
■ External clock input
The IMO is the primary source of internal clocking. It is trimmed
at the factory to achieve the specified accuracy. The IMO
frequency is 8 MHz and tolerance is ±2%.
Internal Low-speed Oscillator (ILO)
The ILO is a very low power oscillator, nominally 32 kHz, which
operates in all power modes. The ILO can be calibrated against
a higher accuracy clock for better accuracy.
■ One phase-locked loop (PLL)
■ One frequency locked loop (FLL)
Figure 3. Clocking Diagram
Yellow multiplexers
are glitch safe
Path Mux
Root mux
(FLL/PLL)
FLL
clk_fast
Divider
Divider
CM4
CLK_HF[0]
CLK_HF[1]
Predivider
(1/2/4/8)
Peripheral
clocks
IMO
clk_peri
Divider
Peripheral
Clock Dividers
TCPWM
SCB
EXTCLK
clk_slow
Predivider
(1/2/4/8)
PLL
clk_ext
CM0+
AHB
ECO
CapSense
CLK_PATH2
CLK_HF[2]
CLK_HF[3]
Analog
Subsystem
Predivider
(1/2/4/8)
QSPI/SMIF
USB
DMA
CLK_PATH3
CLK_PATH4
Smart I/O
eFuse
MMIO
PPU
Predivider
(1/2/4/8)
System LP/ULP Domain
System Deep Sleep /
Hibernate Domain
Crypto
ILO
clk_peri
CLK_LF
CLK_LF
clk_mf
LCD
Predivider
(1/2/3...256)
WCO
IMO/4
Document Number: 002-33480 Rev. *E
Page 12 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
External Crystal Oscillators
The crystal oscillator can be sensitive to GPIO switching noise
and requires the following constraints for reliable operation with
a broad range of crystals over the range of 16 to 35 MHz:
Figure 4 shows all of the external crystal oscillator circuits for this
product line. The component values shown are typical; check the
ECO Specifications for the crystal values, and the crystal
datasheet for the load capacitor values. The ECO and WCO
require balanced external load capacitors. For more information,
see the TRM and AN218241, PSoC 6 MCU Hardware Design
Considerations.
1. Port 12 must be used in low slew rate (slow) mode which limits
switching frequency to 2.5 MHz.
2. Port 11, which includes the QSPI interface, must be limited to
60-MHz operation with the QSPI and in Drive Mode 2; please
see the TRM for details.
For more information, see Table 5 and the GPIO section.
Figure 4. Oscillator Circuits
PSoC 6 MCU
MHz XTAL
32.768 kHz XTAL
CL / 2
CL / 2
CL / 2
CL / 2
Watchdog Timers (WDT, MCWDT)
Reset
PSoC 6 MCU has one WDT and two multi-counter WDTs
(MCWDT). The WDT has a 16-bit free-running counter. Each
MCWDT has two 16-bit counters and one 32-bit counter, with
multiple operating modes. All of the 16-bit counters can generate
a watchdog device reset. All of the counters can generate an
interrupt on a match event.
PSoC 6 MCU can be reset from a variety of sources:
■ Power-on reset (POR) to hold the device in reset while the
power supply ramps up to the level required for the device to
function properly. POR activates automatically at power-up.
■ Brown-out detect (BOD) reset to monitor the digital voltage
supply VDDD and generate a reset if VDDD falls below the
minimum required logic operating voltage.
The WDT is clocked by the ILO. It can do interrupt/wakeup
generation in LP/ULP, Deep Sleep, and Hibernate power modes.
The MCWDTs are clocked by LFCLK (ILO or WCO). It can do
periodic interrupt / wakeup generation in LP/ULP and Deep
Sleep power modes.
■ External reset dedicated pin (XRES) to reset the device using
an external source. The XRES pin is active low. It can be
connected either to a pull-up resistor to VDDD, or to an active
drive circuit, as Figure 5 shows. If a pull-up resistor is used,
select its value to minimize current draw when the pin is pulled
low; 4.7 kΩ to 100 kΩ is typical.
Clock Dividers
Integer and fractional clock dividers are provided for peripheral
use and timing purposes. There are:
Figure 5. XRES Connection Diagram
■ Four 8-bit clock dividers
1.7 to 3.6 V
PSoC 6
■ Eight 16-bit integer clock dividers
■ Two 16.5-bit fractional clock dividers
■ One 24.5-bit fractional clock divider
VDDD
Trigger Routing
4.7 kΩ typ.
PSoC 6 MCU contains a trigger multiplexer block. This is a
collection of digital multiplexers and switches that are used for
routing trigger signals between peripheral blocks and between
GPIOs and peripheral blocks.
XRES
XRES
drive
■ Watchdog timer (WDT or MCWDT) to reset the device if
firmware fails to service it within a specified timeout period.
■ Software-initiated reset to reset the device on demand using
firmware.
There are two types of trigger routing. Trigger multiplexers have
reconfigurability in the source and destination. There are also
hardwired switches called “one-to-one triggers”, which connect
a specific source to a destination. The user can enable or disable
the route.
Document Number: 002-33480 Rev. *E
Page 13 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
■ Logic-protectionfaultcantrigger aninterruptorresetthedevice
if unauthorized operating conditions occur; for example,
reaching a debug breakpoint while executing privileged code.
The ADCs have synchronous sampling, for applications such as
power supply monitoring and motor control. A SAR ADC may be
operated in Deep Sleep mode using a clock of either 2 MHz or
8 MHz (LPOSC).
■ Hibernate wakeup reset to bring the device out of the system
Hibernate low-power mode.
Temperature Sensor
Reset events are asynchronous and guarantee reversion to a
known state. Some of the reset sources are recorded in a
register, which is retained through reset and allows software to
determine the cause of the reset.
Each SAR ADC block contains a temperature sensor. The
sensor consists of a diode biased by a current source. It can be
disabled to save power. The temperature sensor may be
connected directly to a SAR ADC as one of the measurement
channels. The ADC digitizes the temperature sensor’s output,
and a Cypress-supplied software function may be used to
convert the reading to a temperature, with calibration and
linearization.
Programmable Analog Subsystems
12-bit SAR ADC
The two 12-bit, 2-Msps SAR ADCs can operate at a maximum
clock rate of 36 MHz and require a minimum of 18 clocks at that
frequency to do a 12-bit conversion. One of three internal
12-bit Digital-Analog Converter
There is a 12-bit voltage mode DAC on the chip, which can settle
in less than 2 µs. The DAC may be driven by the DMA controllers
to generate user-defined waveforms. The DAC output from the
chip can either be the resistive ladder output (highly linear near
ground) or a buffered output using an opamp in the CTBm block.
references may be used for an ADC reference voltage: VDDA
,
V
DDA/2, and an analog reference (AREF). AREF is nominally
1.2 V, trimmed to ±1%; see Table 22). An external reference may
also be used, by driving a VREF pin. When using VDDA/2 or AREF
as a reference, an external bypass capacitor may be connected
to a VREF pin to improve performance in noisy conditions. These
reference options allow ratio-metric readings or absolute
readings at the accuracy of the reference used. The input range
of the ADCs is the full supply voltage between VSS and
Continuous Time Block mini (CTBm) with Two Opamps
This block consists of two opamps, which have their inputs and
outputs connected to pins and other analog blocks, as Figure 6
shows. They have three power modes (high, medium, and low)
and a comparator mode. The opamps can be used to buffer SAR
inputs and DAC outputs. The non-inverting inputs of these
opamps can be connected to either of two pins, thus allowing
independent sensors to be used at different times. The pin
selection can be made via firmware.
V
DDA/VDDIOA. The ADCs may be configured with a mix of single
ended and differential signals in the same configuration.
The ADCs' sample-and-hold (S/H) aperture is programmable to
allow sufficient time for signals with a high impedance to settle,
if required. System performance is 65 dB for true 12-bit precision
provided appropriate references are used and system noise
levels permit it.
The opamps also support operation in system Deep Sleep mode,
with lower performance and reduced power consumption.
The ADCs are connected to fixed sets of pins through input
sequencers. A sequencer cycles through the selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, the aggregate sampling bandwidth is equal to
2 Msps whether it is for a single channel or distributed over
several channels). The result of each channel is buffered, so that
an interrupt may be triggered only when a full scan of all channels
is complete. Also, a pair of range registers can be set to detect
and cause an interrupt if an input exceeds a minimum and/or
maximum value. This allows fast detection of out-of-range
values without having to wait for a sequencer scan to be
completed and the CPU to read the values and check for
out-of-range values in software. An ADC can also be connected,
under firmware control, to most other GPIO pins via the analog
multiplexer bus (AMUXBUS). The ADCs are not available in
Hibernate mode. The ADC operating range is 1.71 to 3.6 V.
Low-Power Comparators
Two low-power comparators are provided, which can operate in
all power modes. This allows other analog system resources to
be disabled while retaining the ability to monitor external voltage
levels during system Deep Sleep and Hibernate modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator-switch event.
Document Number: 002-33480 Rev. *E
Page 14 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 6 shows an overview of the analog subsystem. This diagram is a high-level abstraction. See the TRM for detailed connectivity
information.
Figure 6. Analog Subsystem
AMUXBUSA
AMUXBUSB
CSD
shield_pad
LPCOMP0
vref_ext
inp
inn
csh
cmod
P6.2
P6.3
amuxbusa
amuxbusb
LPCOMP1
P5.6
P5.7
inp
inn
CTDAC
VDDA
vref vout
S/H
Red dots indicate
AMUXBUS splitter
switches
P9.3
P9.5
P9.4
OA1
10x
Bold lines indicate
+
-
comp out
direct connections
from the opamp 10x
ouputs to port pins.
1x
OA0
P9.0
P9.1
10x
+
-
comp out
1x
P9.2
AREF, 1.2 V
(2)
This product line has two
SAR ADCs; each includes
a SARMUX, SARREF,
temperature sensor, and
multiplexers.
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
SAR ADC
vplus
vminus
vref
SARREF
VDDA
VDDA / 2
TEMP (2)
temp
VSS
To VREF pins, for bypass capacitors
Document Number: 002-33480 Rev. *E
Page 15 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
■ Selectable start, reload, stop, count, and capture event signals
for each TCPWM; with rising edge, falling edge, both edges,
and level trigger options. The TCPWM has a Kill input to force
outputs to a predetermined state.
Programmable Digital
Smart I/O
Smart I/O™ is a programmable logic fabric that enables Boolean
operations on signals traveling from device internal resources to
the GPIO pins or on signals traveling into the device from
external sources. The Smart I/O block sits between the GPIO
pins and the high-speed I/O matrix (HSIOM) and is dedicated to
a single port.
In this device there are:
■ Four 32-bit TCPWMs
■ Eight 16-bit TCPWMs
Serial Communication Blocks (SCB)
This product line has six SCBs:
■ Five can implement either I2C, UART, or SPI.
This product line has one Smart I/O block, on Port 9.When the
Smart I/O is not enabled, all signals on Port 9 bypass the Smart
I/O hardware.
■ One SCB (SCB #6) can operate in Deep Sleep mode with an
Smart I/O supports:
external clock, this SCB can be either SPI slave or I2C slave.
■ System Deep Sleep operation
I2C Mode: The SCB can implement a full multi-master and slave
interface (it is capable of multimaster arbitration). This block can
operate at speeds of up to 1 Mbps (Fast Mode Plus). It also
supports EZI2C, which creates a mailbox address range and
effectively reduces I2C communication to reading from and
writing to an array in memory. The SCB supports a 256-byte
FIFO for receive and transmit.
■ Boolean operations without CPU intervention
■ Asynchronous or synchronous (clocked) operation
The Smart I/O block contains a data unit (DU) and eight look up
tables (LUTs).
The DU:
The SCB is compatible with I2C standard-mode, Fast Mode, and
Fast Mode Plus devices as defined in the NXP I2C-bus
specification and user manual (UM10204). The I2C bus I/O is
implemented with GPIOs in open-drain mode.
■ Performs unique functions based on a selectable opcode.
■ Can source input signals from internal resources, the GPIO
port, or a value in the DU register.
Each LUT:
UART Mode: This is a full-feature UART operating at up to
8 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows the
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. A 256-byte FIFO allows
much greater CPU service latencies to be tolerated.
■ Has four selectable input sources. The input signals may be
sourced from another LUT, an internal resource, an external
signal from a GPIO pin, or from the DU.
■ Acts as a programmable Boolean logic table.
■ Can be synchronous or asynchronous.
Fixed-Function Digital
Timer/Counter/Pulse-width Modulator (TCPWM)
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure
Simple Pairing (SSP) (essentially adds a start pulse that is used
to synchronize SPI Codecs), and National Microwire (half-duplex
form of SPI). The SPI block supports an EZSPI mode in which
the data interchange is reduced to reading and writing an array
in device SRAM. The SPI interface operates with a 25-MHz
clock.
■ The TCPWM supports the following operational modes:
❐ Timer-counter with compare
❐ Timer-counter with capture
❐ Quadrature decoding
❐ Pulse width modulation (PWM)
❐ Pseudo-random PWM
USB Full-Speed Device Interface
❐ PWM with dead time
PSoC 6 has a full-speed USB device interface. The device can
have up to eight endpoints. A 512-byte SRAM buffer is provided
and DMA is supported.
■ Up, down, and up/down counting modes.
■ Clock prescaling (division by 1, 2, 4, ... 64, 128)
■ Double buffering of compare/capture and period values
■ Underflow, overflow, and capture/compare output signals
■ Supports interrupt on:
Note: In this product line USB is available only in the 68-QFN
package.
Note: If the USB pins are not used, connect VDDUSB to ground
and leave the P14.0/USBDP and P14.1/USBDM pins
unconnected.
❐ Terminal count – Depends on the mode; typically occurs on
overflow or underflow
❐ Capture/compare – The count is captured to the capture reg-
ister or the counter value equals the value in the compare
register
CAN FD Block
This device has one CAN FD block, for industrial and automotive
applications. The block includes time-stamp support and has a
4-KB message RAM. FD Data rates of up to 5 Mbps are
supported. DMA transfers are supported.
■ Complementary output for PWMs
Document Number: 002-33480 Rev. *E
Page 16 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Quad-SPI/Serial Memory Interface (SMIF)
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
A serial memory interface is provided, running at up to 80 MHz.
It supports single, dual, and quad SPI configurations, and
supports up to four external memory devices. It supports two
modes of operation:
■ Input threshold select (CMOS or LVTTL)
■ Memory-mapped I/O (MMIO), a command mode interface that
provides data access via the SMIF registers and FIFOs
■ Hold mode for latching previous state (used for retaining the
I/O state in system Hibernate mode)
■ Execute in Place (XIP), in which AHB reads and writes are
directly translated to SPI read and write transfers.
■ Selectable slew rates for dV/dt-related noise control to improve
EMI
In XIP mode, the external memory is mapped into the CPU
internal address space, enabling code execution directly from
the external memory. To improve performance, a 4-KB cache is
included. XIP mode also supports AES-128 on-the-fly encryption
and decryption, enabling secured storage and access of code
and data in the external memory.
The pins are organized in logical entities called ports, which are
up to 8 pins in width. Data output and pin state registers store,
respectively, the values to be driven on the pins and the input
states of the pins.
Every pin can generate an interrupt if enabled; each port has an
interrupt request (IRQ) associated with it.
LCD
The port 3 pins are capable of overvoltage-tolerant (OVT)
This block drives LCD commons and segments; routing is
available to most of the GPIOs. One to eight of the GPIOs must
be used for commons, the rest can be used for segments.
operation, where the input voltage may be higher than VDDD.
OVT pins are commonly used with I2C, to allow powering the
chip OFF while maintaining a physical connection to an
operating I2C bus without affecting its functionality.
The LCD block has two modes of operation: high speed (8 MHz)
and low speed (32 kHz). Both modes operate in system LP, ULP,
and Deep Sleep modes, however the low-speed mode operates
with reduced contrast in system Deep Sleep mode. The 8-MHz
IMO is available in system Deep Sleep mode, and can be used
to generate a clock for the LCD block. Review the number of
common and segment lines, viewing angle requirements, and
prototype performance, and then select the appropriate LCD
clock frequency before using system Deep Sleep mode.
GPIO pins can be ganged to source or sink higher values of
current. GPIO pins, including OVT pins, may not be pulled up
higher than the absolute maximum; see Electrical Specifications.
During power-on and reset, the pins are forced to the analog
input drive mode, with input and output buffers disabled, so as
not to crowbar any inputs and/or cause excess turn-on current.
A multiplexing network known as the high-speed I/O matrix
(HSIOM) is used to multiplex between various peripheral and
analog signals that may connect to an I/O pin.
GPIO
Analog performance is affected by GPIO switching noise. In
order to get the best Analog performance, the following
frequency and drive mode constraints must be applied. The
DRIVE_SEL values (see Table 5) represent drive strengths
(please see the CY8C61x4 Architecture and Register TRMs for
further detail).
This device has up to 62 GPIOs. The GPIO block implements the
following:
■ Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
Table 5. DRIVE_SEL Values
Ports
Ports 0, 1
Max Frequency
8 MHz
Drive Strength for VDDD ≤ 2.7 V Drive Strength for VDDD > 2.7 V
DRIVE_SEL 2
DRIVE_SEL 1
DRIVE_SEL 2
DRIVE_SEL 1
No restrictions
DRIVE_SEL 3
DRIVE_SEL 2
DRIVE_SEL 3
DRIVE_SEL 2
No restrictions
Port 2
50 MHz
Ports 3 to 10
Ports 11 to 12
Ports 9 and 10
16 MHz; 25 MHz for SPI
80 MHz for SMIF (QSPI)
Slow slew rate setting for TQFP
Packages for ADC performance
Document Number: 002-33480 Rev. *E
Page 17 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
IDAC
CapSense Subsystem
The CSD block has two programmable current sources, which
offer the following features:
CapSense is supported in PSoC 6 MCU through a CapSense
sigma-delta (CSD) hardware block. It is designed for
high-sensitivity self-capacitance and mutual-capacitance
measurements, and is specifically built for user interface
solutions.
■ 7-bit resolution
■ Sink and source current modes
■ A current source programmable from 37.5 nA to 609 A
In addition to CapSense, the CSD hardware block supports three
general-purpose functions. These are available when CapSense
is not being used. Alternatively, two or more functions can be
time-multiplexed in an application under firmware control. The
four functions supported by the CSD hardware block are:
■ Two IDACs that can be used in parallel to form one 8-bit IDAC
Comparator
The CapSense subsystem comparator operates in the system
Low Power and Ultra-Low Power modes. The inverting input is
connected to an internal programmable reference voltage and
the non-inverting input can be connected to any GPIO via the
AMUXBUS.
■ CapSense
■ 10-bit ADC
■ Programmable current sources (IDAC)
CapSense Hardware Subsystem
■ Comparator
Figure 7 shows the high-level hardware overview of the
CapSense subsystem, which includes a delta sigma converter,
internal clock dividers, a shield driver, and two programmable
current sources.
CapSense
Capacitive touch sensors are designed for user interfaces that
rely on human body capacitance to detect the presence of a
finger on or near a sensor. Cypress CapSense solutions bring
elegant, reliable, and simple capacitive touch sensing functions
to applications including IoT, industrial, automotive, and home
appliances.
The inputs are managed through analog multiplexed buses
(AMUXBUS A/B). The input and output of all functions offered by
the CSD block can be provided on any GPIO or on a group of
GPIOs under software control, with the exception of the
comparator output and external capacitors that use dedicated
GPIOs.
The Cypress-proprietary CapSense technology offers the
following features:
■ Best-in-class signal-to-noise ratio (SNR) and robust sensing
under harsh and noisy conditions
Self-capacitance is supported by the CSD block using
AMUXBUS A, an external modulator capacitor, and a GPIO for
each sensor. There is a shield electrode (optional) for
self-capacitance sensing. This is supported using AMUXBUS B
and an optional external shield tank capacitor (to increase the
drive capability of the shield driver) should this be required.
Mutual-capacitance is supported by the CSD block using
AMUXBUS A, two external integrated capacitors, and a GPIO for
transmit and receive electrodes.
■ Self-capacitance (CSD) and mutual-capacitance (CSX)
sensing methods
■ Support for various widgets, including buttons, matrix buttons,
sliders, touchpads, and proximity sensors
■ High-performance sensing across a variety of materials
■ Best-in-class liquid tolerance
The ADC does not require an external component. Any GPIO
that can be connected to AMUXBUS A can be an input to the
ADC under software control. The ADC can accept VDDA as an
input without needing GPIOs (for applications such as battery
voltage measurement).
■ SmartSense auto-tuning technology that helps avoid complex
manual tuning processes
■ Superior immunity against external noise
■ Spread-spectrum clocks for low radiated emissions
■ Gesture and built-in self-test libraries
■ Ultra-low power consumption
The two programmable current sources (IDACs) in
general-purpose mode can be connected to AMUXBUS A or B.
They can therefore connect to any GPIO pin. The comparator
resides in the delta-sigma converter. The comparator inverting
input can be connected to the reference. Both comparator inputs
can be connected to any GPIO using AMUXBUS B; see
Figure 6. The reference has a direct connection to a dedicated
GPIO; see Table 8.
■ An integrated graphical CapSense tuner for real-time tuning,
testing, and debugging
ADC
The CSD block can operate in active and sleep CPU power
modes, and seamlessly transition between LP and ULP system
modes. It can be powered down in system Deep Sleep and
Hibernate modes. Upon wakeup from Hibernate mode, the CSD
block requires re-initialization. However, operation can be
resumed without re-initialization upon exit from Deep Sleep
mode, under firmware control.
The CapSense subsystem slope ADC offers the following
features:
■ Selectable 8- or 10-bit resolution
■ Selectable input range: GND to VREF and GND to VDDA on any
GPIO input
■ MeasurementofVDDA against aninternal referencewithoutthe
use of GPIO or external components
Document Number: 002-33480 Rev. *E
Page 18 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 7. CapSense Hardware Subsystem
AMUXBUS
A
B
GPIO Pin
GPIO
Cell
CSD Sensor 1
CS1
Clock Input
GPIO Pin
CMOD Pin
GPIO
Cell
CSD Sensor 2
CS2
CSD Hardware Block
CMOD
Sense clock
Clock
Generator
CSH_TANK
(optional)
GPIO Pin
GPIO Pin
Shield Drive
Circuit
Modulator
Clock
GPIO
Cell
Compensation
IDAC
CSHIELD
Shield Electrode
Modulator
IDAC
GPIO Pin
IDAC control
Tx
GPIO
Cell
CSX Sensor 3
CS3
Raw
Count
Sigma Delta
Converter
GPIO Pin
Rx
GPIO
Cell
VREF
CINTA Pin
GPIO
Cell
CINTA
CINTB
CINTB Pin
GPIO
Cell
ADC Input
IDAC Outputs
Comp Input
Document Number: 002-33480 Rev. *E
Page 19 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 8 shows the high-level software overview. Cypress
provides middleware libraries for CapSense, ADC, and IDAC on
GitHub to enable quick integration. The Board Support Package
for any kit with CapSense capabilities automatically includes the
CapSense library in any application that uses the BSP.
CapSense and ADC middleware use the CSD interrupt to
implement non-blocking sensing and A-to-D conversion.
Therefore, interrupt service routines are a defined part of the
middleware, which must be initialized by the application.
Middleware and drivers can operate on either CPU. Cypress
recommends using the middleware only in one CPU. If both
CPUs must access the CSD driver, memory access should be
managed in the application.
User applications interact only with middleware to implement
functions of the CSD block. The middleware interacts with
underlying drivers to access hardware as necessary. The CSD
driver facilitates time-multiplexing of the CSD hardware if more
than one piece of CSD-related middleware is present in a project.
It prevents access conflicts in this case.
Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design
Guide for more details on CSX sensing, CSD sensing, shield
electrode usage and its benefits, and capacitive system design
guidelines.
ModusToolbox Software provides a CapSense configurator to
enable fast library configuration. It also provides a tuner for
performance evaluation and real-time tuning of the system. The
tuner requires an EZI2C communication interface in the
application to enable real-time tuning capability. The tuner can
update configuration parameters directly in the device as well as
in the configurator.
Refer to theAPI reference guides for CapSense, ADC, and IDAC
available on GitHub.
Figure 8. CapSense Software/Firmware Subsystem
Application Program
Middleware
Software
Configurator
Tuner
SCB Driver (EZI2C)
SCB
CSD Driver
GPIO / Clock Drivers
CSD Block
GPIOs/ Clock
Hardware and Drivers
Document Number: 002-33480 Rev. *E
Page 20 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Pinouts
GPIO ports are powered by VDDx pins as follows:
■ P0: VBACKUP
■ P1, P2, P3: VDDIO2. Port 3 pins are overvoltage tolerant (OVT).
■ P5, P6, P7, P8: VDDIO1
■ P9, P10: VDDIOA, VDDA (VDDIOA, when present, and VDDA must be connected together on the PCB)
■ P11, P12: VDDIO0
■ P14: VDDUSB
Table 6. Packages and Pin Information
Package
Pin
80-TQFP
64-TQFP
68-QFN
VDDD
VCCD
VDDA
VDDIOA
VDDIO0
VDDIO1
VDDIO2
VBACKUP
VDDUSB
VSS
1
2
68
80
1
67
59
46
48
40
-
36
76
62
64
39
32
35
23
19
22
3
3
1
-
-
11
2, 11, 24, 38, 41, 58, 77
GND PAD
GND PAD
VDD_NS
VIND1
XRES
VREF
P0.0
-
-
-
-
9
10
8
10
57, 60
4
10
45, 47
4
49
2
P0.1
5
5
3
P0.2
6
6
4
P0.3
7
7
5
P0.4
8
8
6
P0.5
9
9
7
P1.0
12
13
14
15
16
17
18
19
20
21
22
-
-
P1.1
-
-
P1.2
-
-
P2.0
11
12
13
14
15
16
17
18
14
15
16
17
18
19
20
21
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Document Number: 002-33480 Rev. *E
Page 21 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 6. Packages and Pin Information (continued)
Package
64-TQFP
Pin
80-TQFP
68-QFN
P3.0
P3.1
P5.0
P5.1
P5.2
P5.6
P5.7
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.7
P8.0
P8.1
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
25
26
27
28
29
30
31
32
33
34
35
36
37
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
61
62
63
64
65
66
67
68
69
70
71
72
73
74
20
21
22
23
-
23
24
25
26
-
24
25
26
27
28
29
30
31
33
34
35
36
-
27
28
29
30
31
32
33
34
37
38
39
40
-
-
-
-
41
42
43
44
45
46
47
-
37
38
39
40
41
42
43
44
48
49
50
51
52
53
54
55
-
-
50
51
52
53
54
55
56
57
-
56
57
58
59
60
58
59
60
61
62
Document Number: 002-33480 Rev. *E
Page 22 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 6. Packages and Pin Information (continued)
Package
64-TQFP
Pin
80-TQFP
68-QFN
P11.7
P12.6
75
78
79
–
61
63
64
–
63
65
66
13
12
P12.7
P14.0 / USBDP
P14.1 / USBDM
–
–
Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.
Figure 9. Device Pinout for 80-TQFP Package
VDDD
VSS
VBACKUP
P0.0
1
2
3
4
5
6
60
59
VREF 0
VDDA
58
57
56
55
VSS
VREF 1
P9.5
P9.4
P0.1
P0.2
P0.3
P0.4
P0.5
XRES
VSS
54
53
52
51
50
49
P9.3
P9.2
7
8
9
10
11
12
13
14
15
P9.1
P9.0
P8.1
P8.0
TQFP
P1.0
P1.1
P1.2
P2.0
P2.1
P2.2
48
47
P7.7
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
46
45
44
43
16
17
P2.3
P2.4
P2.5
18
19
20
42
41
VSS
Document Number: 002-33480 Rev. *E
Page 23 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 10. Device Pinout for 64-TQFP Package
VCCD
VDDD
VBACKUP
P0.0
1
2
48
47
46
45
44
43
42
P10.0
VREF 0
VDDA
VREF 1
P9.5
P9.4
P9.3
3
4
5
6
P0.1
P0.2
P0.3
P0.4
P0.5
7
8
9
41
40
39
P9.2
P9.1
TQFP
10
XRES
P2.0
P2.1
P2.2
P9.0
P8.1
P8.0
P7.3
P7.2
11
12
13
14
15
16
38
37
36
35
34
33
P2.3
P2.4
P2.5
P7.1
P7.0
Figure 11. Device Pinout for 68-QFN Package
VBACKUP
P10.1
51
1
2
3
4
5
6
P0.0
P0.1
50
P10.0
VREF 0
VDDA
49
48
47
P0.2
P0.3
P0.4
P9.3
P9.2
46
P0.5
XRES
45
44
43
42
P9.1
P9.0
P8.1
7
8
9
QFN
(TOP VIEW)
VDD_NS
P8.0
10
VIND1
VDDUSB
P14.1 / USBDM
P7.7
P7.3
11
12
13
41
40
39
P14.0 / USBDP
P7.2
P7.1
P2.0 14
38
37
36
35
P2.1
P2.2
P2.3
15
16
17
P7.0
VDDIOA
VDDIO 1
Document Number: 002-33480 Rev. *E
Page 24 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Each port pin has multiple alternate functions. These are defined in Table 7. The columns ACT #x and DS #y denote active (System LP/ULP) and Deep Sleep mode signals
respectively.
The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there is more than one signal for
a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the
fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize use of on-chip resources.
Table 7. Multiple Alternate Functions
Port/
Pin
ACT ACT ACT
ACT
#7
ACT ACT
ACT
#10
ACT
#12
ACT
#13
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
DS #5 DS #6
#4
#5
#6
#8
#9
P0.0
tcpwm[0].l
ine[0]:0
tcpwm[25
6].line[0]:
0
csd.csd
_tx:0
csd.csd_
tx_n:0
srss.e
xt_clk:
0
scb[0].
spi_se
lect1:0
peri.tr
_io_in
put[0]:
0
P0.1
tcpwm[0].l
ine_comp
l[0]:0
tcpwm[25
6].line_co
mpl[0]:0
csd.csd
_tx:1
csd.csd_
tx_n:1
scb[0].
spi_se
lect2:0
peri.tr
_io_in
put[1]:
0
cpuss.
swj_tr
stn
P0.2
P0.3
P0.4
tcpwm[25
7].line[1]:
0
tcpwm[25
7].line[1]:
0
csd.csd
_tx:2
csd.csd_
tx_n:2
scb[0]
.uart_r
x:0
scb[0].
i2c_scl
:0
scb[0].
spi_m
osi:0
tcpwm[0].l
ine_comp
l[1]:0
tcpwm[25
7].line_co
mpl[1]:0
csd.csd
_tx:3
csd.csd_
tx_n:3
scb[0]
.uart_t
x:0
scb[0].
i2c_sd
a:0
scb[0].
spi_mi
so:0
tcpwm[0].l
ine[2]:0
tcpwm[25
8].line[2]:
0
csd.csd
_tx:4
csd.csd_
tx_n:4
scb[0]
.uart_r
ts:0
scb[0].
spi_cl
k:0
peri.tr
_io_in
put[2]:
0
peri.tr_io
_output[
0]:2
P0.5
tcpwm[0].l
ine_comp
l[2]:0
tcpwm[25
8].line_co
mpl[2]:0
csd.csd
_tx:5
csd.csd_
tx_n:5
srss.e
xt_clk:
1
scb[0]
.uart_
cts:0
scb[0].
spi_se
lect0:0
peri.tr
_io_in
put[3]:
0
peri.tr_io
_output[
1]:2
P1.0
P1.1
P1.2
P2.0
csd.csd
_tx:6
csd.csd_
tx_n:6
csd.csd
_tx:7
csd.csd_
tx_n:7
csd.csd
_tx:8
csd.csd_
tx_n:8
tcpwm[0].l
ine[3]:0
tcpwm[0].l
ine[259]:0
csd.csd
_tx:9
csd.csd_
tx_n:9
scb[1]
.uart_r
x:1
scb[1].
i2c_scl
:1
scb[1].
spi_m
osi:1
peri.tr
_io_in
put[4]:
0
Document Number: 002-33480 Rev. *E
Page 25 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 7. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT
ACT
#7
ACT ACT
ACT
#10
ACT
#12
ACT
#13
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
DS #5 DS #6
#4
#5
#6
#8
#9
P2.1
tcpwm[0].l
ine_comp
l[3]:0
tcpwm[0].l
ine_compl
[259]:0
csd.csd
_tx:10
csd.csd_
tx_n:10
scb[1]
.uart_t
x:1
scb[1].
i2c_sd
a:1
scb[1].
spi_mi
so:1
peri.tr
_io_in
put[5]:
0
P2.2
P2.3
P2.4
P2.5
P2.6
tcpwm[0].l
ine[0]:1
tcpwm[0].l
ine[260]:0
csd.csd
_tx:11
csd.csd_
tx_n:11
scb[1]
.uart_r
ts:1
scb[1].
spi_cl
k:1
tcpwm[0].l
ine_comp
l[0]:1
tcpwm[0].l
ine_compl
[260]:0
csd.csd
_tx:12
csd.csd_
tx_n:12
scb[1]
.uart_
cts:1
scb[1].
spi_se
lect0:1
tcpwm[0].l
ine[1]:1
tcpwm[0].l
ine[261]:0
csd.csd
_tx:13
csd.csd_
tx_n:13
scb[1].
spi_se
lect1:1
tcpwm[0].l
ine_comp
l[1]:1
tcpwm[0].l
ine_compl
[261]:0
csd.csd
_tx:14
csd.csd_
tx_n:14
scb[1].
spi_se
lect2:1
tcpwm[0].l
ine[1]:5
tcpwm[1].l
ine[262]:1
csd.csd
_tx:15
csd.csd_
tx_n:15
lpcom
p.dsi_
comp
0:0
scb[1].
spi_se
lect3:1
peri.tr
_io_in
put[8]:
0
P2.7
P3.0
tcpwm[0].l
ine_comp
l[2]:1
tcpwm[0].l
ine_compl
[262]:0
csd.csd
_tx:16
csd.csd_
tx_n:16
lpco
mp.ds
i_com
p1:0
peri.tr
_io_in
put[9]:
0
tcpwm[0].l
ine[3]:1
tcpwm[0].l
ine[263]:0
csd.csd
_tx:17
csd.csd_
tx_n:17
scb[2]
.uart_r
x:1
scb[2].
i2c_scl
:1
peri.tr
_io_in
put[6]:
0
P3.1
P5.0
P5.1
tcpwm[0].l
ine_comp
l[3]:1
tcpwm[0].l
ine_compl
[263]:0
csd.csd
_tx:18
csd.csd_
tx_n:18
scb[2]
.uart_t
x:1
scb[2].
i2c_sd
a:1
peri.tr
_io_in
put[7]:
0
tcpwm[0].l
ine[0]:2
tcpwm[0].l
ine[256]:1
csd.csd
_tx:19
csd.csd_
tx_n:19
scb[5]
.uart_r
x:0
scb[5].
i2c_scl
:0
scb[5].
spi_m
osi:0
peri.tr
_io_in
put[10
]:0
canfd[0]
.ttcan_r
x[0]
tcpwm[0].l
ine_comp
l[0]:2
tcpwm[0].l
ine_compl
[256]:1
csd.csd
_tx:20
csd.csd_
tx_n:20
scb[5]
.uart_t
x:0
scb[5].
i2c_sd
a:0
scb[5].
spi_mi
so:0
peri.tr
_io_in
put[11
]:0
canfd[0]
.ttcan_t
x[0]
P5.2
P5.6
P5.7
csd.csd
_tx:21
csd.csd_
tx_n:21
tcpwm[0].l
ine[1]:2
tcpwm[0].l
ine[257]:1
csd.csd
_tx:22
csd.csd_
tx_n:22
tcpwm[0].l
ine_comp
l[1]:2
tcpwm[0].l
ine_compl
[257]:1
csd.csd
_tx:23
csd.csd_
tx_n:23
Document Number: 002-33480 Rev. *E
Page 26 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 7. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT
ACT
#7
ACT ACT
ACT
#10
ACT
#12
ACT
#13
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
DS #5 DS #6
#4
#5
#6
#8
#9
P6.2
P6.3
P6.4
tcpwm[0].l
ine[3]:2
tcpwm[0].l
ine[259]:1
csd.csd
_tx:24
csd.csd_
tx_n:24
cpuss.f
ault_out[
0]
tcpwm[0].l
ine_comp
l[3]:2
tcpwm[0].l
ine_compl
[259]:1
csd.csd
_tx:25
csd.csd_
tx_n:25
cpuss.f
ault_out[
1]
tcpwm[0].l
ine[0]:3
tcpwm[0].l
ine[260]:1
csd.csd
_tx:26
csd.csd_
tx_n:26
scb[6].
i2c_scl
:0
peri.tr
_io_in
put[12
]:0
peri.tr_io
_output[
0]:1
cpuss.
swj_s
wo_td
o
scb[6]
.spi_
mosi:
0
P6.5
P6.6
P6.7
P7.0
P7.1
tcpwm[0].l
ine_comp
l[0]:3
tcpwm[1].l
ine_compl
[260]:1
csd.csd
_tx:27
csd.csd_
tx_n:27
scb[6].
i2c_sd
a:0
peri.tr
_io_in
put[13
]:0
peri.tr_io
_output[
1]:1
cpuss.
swj_s
wdoe_
tdi
scb[6]
.spi_
miso:
0
tcpwm[0].l
ine[1]:3
tcpwm[0].l
ine[261]:1
csd.csd
_tx:28
csd.csd_
tx_n:28
cpuss.
swj_s
wdio_t
ms
scb[6]
.spi_c
lk:0
tcpwm[0].l
ine_comp
l[1]:3
tcpwm[0].l
ine_compl
[261]:1
csd.csd
_tx:29
csd.csd_
tx_n:29
cpuss.
swj_s
wclk_t
clk
scb[6]
.spi_s
elect0
:0
tcpwm[0].l
ine[2]:2
tcpwm[0].l
ine[262]:1
csd.csd
_tx:30
csd.csd_
tx_n:30
scb[4]
.uart_r
x:0
scb[4].
i2c_scl
:0
scb[4].
spi_m
osi:0
peri.tr
_io_in
put[14
]:0
cpuss.tr
ace_clo
ck
tcpwm[0].l
ine_comp
l[2]:2
tcpwm[0].l
ine_compl
[262]:1
csd.csd
_tx:31
csd.csd_
tx_n:31
scb[4]
.uart_t
x:0
scb[4].
i2c_sd
a:0
scb[4].
spi_mi
so:0
peri.tr
_io_in
put[15
]:0
P7.2
P7.3
P7.4
P7.5
P7.7
tcpwm[0].l
ine[3]:3
tcpwm[0].l
ine[263]:1
csd.csd
_tx:32
csd.csd_
tx_n:32
scb[4]
.uart_r
ts:0
scb[4].
spi_cl
k:0
tcpwm[0].l
ine_comp
l[3]:3
tcpwm[0].l
ine_compl
[263]:1
csd.csd
_tx:33
csd.csd_
tx_n:33
scb[4]
.uart_
cts:0
scb[4].
spi_se
lect0:0
csd.csd
_tx:34
csd.csd_
tx_n:34
scb[4].
spi_se
lect1:0
csd.csd
_tx:35
csd.csd_
tx_n:35
scb[4].
spi_se
lect2:0
csd.csd
_tx:36
csd.csd_
tx_n:36
cpuss.
clk_fm
_pum
p
Document Number: 002-33480 Rev. *E
Page 27 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 7. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT
ACT
#7
ACT ACT
ACT
#10
ACT
#12
ACT
#13
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
DS #5 DS #6
#4
#5
#6
#8
#9
P8.0
P8.1
P9.0
P9.1
tcpwm[0].l
ine[2]:3
tcpwm[0].l
ine[258]:1
csd.csd
_tx:37
csd.csd_
tx_n:37
scb[4]
.uart_r
x:1
scb[4].
i2c_scl
:1
scb[4].
spi_m
osi:1
peri.tr
_io_in
put[16
]:0
tcpwm[0].l
ine_comp
l[2]:3
tcpwm[0].l
ine_compl
[258]:1
csd.csd
_tx:38
csd.csd_
tx_n:38
scb[4]
.uart_t
x:1
scb[4].
i2c_sd
a:1
scb[4].
spi_mi
so:1
peri.tr
_io_in
put[17
]:0
tcpwm[0].l
ine[0]:4
tcpwm[0].l
ine[260]:2
csd.csd
_tx:39
csd.csd_
tx_n:39
scb[2]
.uart_r
x:0
scb[2].
i2c_scl
:0
scb[2].
spi_m
osi:0
peri.tr
_io_in
put[18
]:0
cpuss.tr
ace_da
ta[3]:1
tcpwm[0].l
ine_comp
l[0]:4
tcpwm[0].l
ine_compl
[260]:2
csd.csd
_tx:40
csd.csd_
tx_n:40
scb[2]
.uart_t
x:0
scb[2].
i2c_sd
a:0
scb[2].
spi_mi
so:0
peri.tr
_io_in
put[19
]:0
cpuss.tr
ace_da
ta[2]:1
P9.2
P9.3
P9.4
P9.5
P10.0
tcpwm[0].l
ine[1]:4
tcpwm[0].l
ine[261]:2
csd.csd
_tx:41
csd.csd_
tx_n:41
scb[2]
.uart_r
ts:0
scb[2].
spi_cl
k:0
cpuss.tr
ace_da
ta[1]:1
pass.ds
i_ctb_c
mp0:1
tcpwm[0].l
ine_comp
l[1]:4
tcpwm[0].l
ine_compl
[261]:3
csd.csd
_tx:42
csd.csd_
tx_n:42
scb[2]
.uart_
cts:0
scb[2].
spi_se
lect0:0
cpuss.tr
ace_da
ta[0]:1
pass.ds
i_ctb_c
mp1:1
csd.csd
_tx:43
csd.csd_
tx_n:43
scb[2].
spi_se
lect1:0
csd.csd
_tx:44
csd.csd_
tx_n:44
scb[2].
spi_se
lect2:0
tcpwm[0].l
ine[2]:4
tcpwm[0].l
ine[262]:2
csd.csd
_tx:45
csd.csd_
tx_n:45
scb[1]
.uart_r
x:0
scb[1].
i2c_scl
:0
scb[1].
spi_m
osi:0
peri.tr
_io_in
put[20
]:0
cpuss.tr
ace_da
ta[3]:0
P10.1
tcpwm[0].l
ine_comp
l[2]:4
tcpwm[0].l
ine_compl
[262]:2
csd.csd
_tx:46
csd.csd_
tx_n:46
scb[1]
.uart_t
x:0
scb[1].
i2c_sd
a:0
scb[1].
spi_mi
so:0
peri.tr
_io_in
put[21
]:0
cpuss.tr
ace_da
ta[2]:0
P10.2
P10.3
tcpwm[0].l
ine[3]:4
tcpwm[0].l
ine[263]:2
csd.csd
_tx:47
csd.csd_
tx_n:47
scb[1]
.uart_r
ts:0
scb[1].
spi_cl
k:0
cpuss.tr
ace_da
ta[1]:0
tcpwm[0].l
ine_comp
l[3]:4
tcpwm[0].l
ine_compl
[263]:2
csd.csd
_tx:48
csd.csd_
tx_n:48
scb[1]
.uart_
cts:0
scb[1].
spi_se
lect0:0
cpuss.tr
ace_da
ta[0]:0
Document Number: 002-33480 Rev. *E
Page 28 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 7. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT
ACT
#7
ACT ACT
ACT
#10
ACT
#12
ACT
#13
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
DS #5 DS #6
#4
#5
#6
#8
#9
P10.4
tcpwm[0].l
ine[0]:5
tcpwm[0].l
ine[256]:2
csd.csd
_tx:49
csd.csd_
tx_n:49
scb[1].
spi_se
lect1:0
audios
s[0].p
dm_cl
k:0
P10.5
tcpwm[0].l
ine_comp
l[0]:5
tcpwm[0].l
ine_compl
[256]:2
csd.csd
_tx:50
csd.csd_
tx_n:50
scb[1].
spi_se
lect2:0
audios
s[0].p
dm_d
ata:0
P10.6
P10.7
tcpwm[0].l
ine[1]:5
tcpwm[0].l
ine[257]:2
csd.csd
_tx:51
csd.csd_
tx_n:51
scb[1].
spi_se
lect3:0
peri.tr
_io_in
put[22
]:0
tcpwm[0].l
ine_comp
l[1]:5
tcpwm[0].l
ine_compl
[257]:2
csd.csd
_tx:52
csd.csd_
tx_n:52
smif.
spi_s
elect
2
peri.tr
_io_in
put[23
]:0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
csd.csd
_tx:53
csd.csd_
tx_n:53
smif.s
pi_sel
ect1
tcpwm[0].l
ine[3]:5
tcpwm[0].l
ine[259]:2
csd.csd
_tx:54
csd.csd_
tx_n:54
smif.s
pi_sel
ect0
scb[5]
.uart_r
ts:0
scb[5].
spi_cl
k:0
tcpwm[0].l
ine_comp
l[3]:5
tcpwm[0].l
ine_compl
[259]:2
csd.csd
_tx:55
csd.csd_
tx_n:55
smif.s
pi_da
ta3
scb[5]
.uart_
cts:0
scb[5].
spi_se
lect0:0
peri.tr_io
_output[
0]:0
tcpwm[0].l
ine[0]:6
tcpwm[0].l
ine[260]:3
csd.csd
_tx:56
csd.csd_
tx_n:56
smif.s
pi_da
ta2
scb[5].
spi_se
lect1:0
peri.tr_io
_output[
1]:0
tcpwm[0].l
ine_comp
l[0]:6
tcpwm[0].l
ine_compl
[260]:3
csd.csd
_tx:57
csd.csd_
tx_n:57
smif.s
pi_da
ta1
scb[5].
spi_se
lect2:0
tcpwm[0]
.line[1]:6
tcpwm[0].
line[261]:
3
csd.csd
_tx:58
csd.csd_
tx_n:58
smif.s
pi_da
ta0
scb[5].
spi_se
lect3:0
tcpwm[0]
.line_com
pl[1]:6
tcpwm[0].
line_comp
l[261]:2
csd.csd
_tx:59
csd.csd_
tx_n:59
smif.s
pi_clk
P12.6
P12.7
tcpwm[0].l
ine[3]:6
tcpwm[0].l
ine[263]:3
csd.csd
_tx:60
csd.csd_
tx_n:60
tcpwm[0].l
ine_comp
l[3]:6
tcpwm[0].l
ine_compl
[263]:3
csd.csd
_tx:61
csd.csd_
tx_n:61
Document Number: 002-33480 Rev. *E
Page 29 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Analog and Smart I/O alternate port pin functionality is provided in Table 8.
Table 8. Port Pin Analog, Digital, and Smart I/O Functions
Table 8. Port Pin Analog, Digital, and Smart I/O Functions
Port/Pin
Analog
Port/Pin
P0.0
Analog
P10.6
P10.7
P12.6
sarmux_pads[6]
sarmux_pads[7]
eco_in
wco_in
P0.1
wco_out
P5.6
lpcomp.inp_comp0
lpcomp.inn_comp0
lpcomp.inp_comp1
lpcomp.inn_comp1
P12.7
eco_out
P5.7
Port/Pin
Digital
P6.2
P0.4
pmic_wakeup_in
hibernate_wakeup[1]
pmic_wakeup_out
hibernate_wakeup[0]
SMARTIO
P6.3
P6.6
P6.7
P7.2
P7.3
P7.7
swd_data
swd_clk
csd.csh_tank
csd.vref_ext
P0.5
P8.1
Port/Pin
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
smartio[9].io[0]
smartio[9].io[1]
smartio[9].io[2]
smartio[9].io[3]
smartio[9].io[4]
smartio[9].io[5]
csd.shield
P9.5
aref_ext_vref
sarmux_pads[0]
sarmux_pads[1]
sarmux_pads[2]
sarmux_pads[3]
sarmux_pads[4]
sarmux_pads[5]
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
Document Number: 002-33480 Rev. *E
Page 30 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Power Supply Considerations
The following power system diagrams show typical connections for power pins for all supported packages, and with and without usage
of the buck regulator.
In these diagrams, the package pin is shown with the pin name, for example "VDDA, 59". For VDDx pins, the I/O port that is powered
by that pin is also shown, for example “VBACKUP, 3; I/O port P0”.
Figure 12. 80-TQFP Power Connection Diagram
1.7 to 3.6 V
CY8C61x4, 80-TQFP package
1 KΩ at
100 MHz
VCCD, 80
VDDD, 1
BACKUP, 3; I/O port P0
4.7 µF
10 µF
1 µF
1 µF
1 µF
1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
V
VDDIO0, 76; I/O ports P11, P12
VDDIO1, 39; I/O ports P5, P6, P7, P8
VDDIO2, 23; I/O ports P1, P2, P3
1 KΩ at
100 MHz
VDDA, 59
10 µF
0.1 µF
VDDIOA, 40; I/O ports P9, P10
2, 11, 24, 38, 41, 58, 77
VSS
Document Number: 002-33480 Rev. *E
Page 31 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 13. 64-TQFP Power Connection Diagram
1.7 to 3.6 V
CY8C61x4, 64-TQFP package
1 KΩ at
100 MHz
VCCD, 1
VDDD, 2
VBACKUP, 3; I/O port P0
4.7 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1 µF
V
V
DDIO0, 62; I/O ports P11, P12
1 µF
1 µF
1 µF
DDIO1, 32; I/O ports P5, P6, P7, P8
VDDIO2, 19; I/O ports P2, P3
VDDA, 46; I/O ports P9, P10
1 KΩ at
100 MHz
10 µF
0.1 µF
GND PAD
VSS
Document Number: 002-33480 Rev. *E
Page 32 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 14. 68-QFN Power Connection Diagram
1.7 to 3.6 V
CY8C61x4, 68-QFN package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
VDDD, 68
VDD_NS, 9
10 µF
1 µF
1 µF
1 µF
1 µF
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
10 µF
VBACKUP, 1; I/O port P0
VDDIO0, 64; I/O ports P11, P12
VDDIO1, 35; I/O ports P5, P6, P7, P8
VDDIO2, 22; I/O ports P2, P3
VDDUSB, 11; I/O port P14
VIND1, 10
VCCD, 67
2.2 µH
4.7 µF
1 KΩ at
100 MHz
VDDA, 48
VDDIOA, 36; I/O ports P9, P10
GND PAD
VSS
Document Number: 002-33480 Rev. *E
Page 33 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 15. 68-QFN (No Buck) Power Connection Diagram
1.7 to 3.6 V
CY8C61x4, 68-QFN package
1 KΩ at
100 MHz
VDDD, 68
VDD_NS, 9
VIND1, 10
10 µF
1 µF
1 µF
1 µF
1 µF
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VBACKUP, 1; I/O port P0
VDDIO0, 64; I/O ports P11, P12
VDDIO1, 35; I/O ports P5, P6, P7, P8
VCCD, 67
4.7 µF
VDDIO2, 22; I/O ports P2, P3
VDDUSB, 11; I/O port P14
VDDA, 48
1 KΩ at
100 MHz
VDDIOA, 36; I/O ports P9, P10
GND PAD
VSS
There are as many as eight VDDx supply pins, depending on the
package, and multiple VSS ground pins. The power pins are:
■ VBACKUP: the supply for the backup domain, which includes the
32-kHz WCO and the RTC. It can be a separate supply as low
as 1.4 V, for battery or supercapacitor backup, as Figure 16
shows. otherwise it is connected to VDDD. It powers I/O port 0.
■ VDDD: the main digital supply.
■ VCCD: the main LDO output. It requires a 4.7-µF capacitor for
regulation. The LDO can be turned off when VCCD is driven
from the switching regulator (see below). For more information,
see the power system block diagram in the device technical
reference manual (TRM).
Figure 16. Separate Battery Connection to VBACKUP
1.7 to 3.6 V
■ VDDA: the supply for the analog peripherals. Voltage must be
applied to this pin for correct device initialization and boot up.
VDDD
10 µF
1 µF
0.1 µF
0.1 µF
■ VDDIOA: the supply for I/O ports 9 and 10. If it is present in the
device package, it must be connected to VDDA
■ VDDIO0: the supply for I/O ports 11 and 12.
■ VDDIO1: the supply for I/O ports 5, 6, 7, and 8.
■ VDDIO2: the supply for I/O ports 1, 2, and 3.
.
VBACKUP
1.4 to 3.6 V
Document Number: 002-33480 Rev. *E
Page 34 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
■ VDDUSB: the supply for the USB peripheral and the USBDPand
USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If
USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can
be used as limited-capability GPIOs on I/O port 14.
There are no power pin sequencing requirements; power
supplies may be brought up in any order. The power
management system holds the device in reset until all power pins
are at the voltage levels required for proper operation.
Table 9 shows a summary of the I/O port supplies:
Note: If a battery is installed on the PCB first, VDDD must be
cycled for at least 50 µs. This prevents premature drain of the
battery during product manufacture and storage.
Table 9. I/O Port Supplies
Port
0
Supply
VBACKUP
VDDIO2
VDDIO1
VDDIOA
VDDIO0
VDDUSB
Alternate Supply
Bypass capacitors must be connected to a common ground from
the VDDx and other pins, as indicated in the diagrams. Typical
practice for systems in this frequency range is to use a 10-µF or
1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated for optimal
bypassing.
VDDD
1,2, 3
5, 6, 7, 8
9, 10
11, 12
14
-
-
VDDA
-
-
All capacitors and inductors should be ±20% or better. The
recommended inductor value is 2.2 µH ±20% (for example, TDK
MLP2012H2R2MT0S1).
Note: If the USB pins are not used, connect VDDUSB to ground
and leave the P14.0/USBDP and P14.1/USBDM pins unconnect-
ed.
It is good practice to check the datasheets for your bypass
capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can
decrease considerably when the applied voltage is a significant
percentage of the rated working voltage.
Voltage must be applied to the VDDD pin, and the VDDA pin as
noted above, for correct device initialization and operation. If an
I/O port is not being used, applying voltage to the corresponding
V
DDx pin is optional.
For more information on pad layout, refer to PSoC 6 CAD
libraries.
■ VSS: ground pins for the above supplies.All ground pins should
be connected together to a common ground.
In addition to the LDO regulator, a switching regulator is
included. The regulator pins are:
■ VDD_NS: the regulator supply.
■ VIND1: the regulator output. It is typically used to drive VCCD
through an inductor.
The VDD power pins are not connected together on chip. They
can be connected off chip, in one or more separate nets. If
separate power nets are used, they can be isolated from noise
from the other nets using optional ferrite beads, as indicated in
the diagrams.
No external load should be placed on VCCD, or VIND1, whether
or not these pins are used.
Document Number: 002-33480 Rev. *E
Page 35 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Electrical Specifications
All specifications are valid for –40 °C TA 85 °C and for 1.71 V to 3.6 V except where noted.
Note: These are preliminary and subject to change.
Absolute Maximum Ratings
Table 10. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Analog or digital supply relative to Vss
SID1
V
V
–0.5
–
4
V
DD_ABS
(V
= V
)
SSD
SSA
Direct digital core voltage input relative
to Vssd
SID2
–0.5
–
1.2
V
CCD_ABS
GPIO_ABS
SID3
SID4
SID5
V
I
GPIO voltage; V
or V
–0.5
–25
–
–
–
VDD+0.5
25
V
DDD
DDA
Current per GPIO
mA
mA
GPIO_ABS
I
GPIO injection current per pin
–0.5
0.5
GPIO_injection
Electrostatic discharge Human Body
Model
SID3A
ESD_HBM
2200
–
–
V
Electrostatic discharge Charged
Device Model
SID4A
SID5A
ESD_CDM
LU
500
–
–
–
V
Pin current for latchup-free operation
–100
100
mA
Device-Level Specifications
Table 13 provides detailed specifications of CPU current. Table 11 summarizes these specifications, for rapid review of CPU currents
under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to
generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz.
Table 11. CPU Current Specifications Summary
Condition
= 3.3 V, V
Range
Typ Range
Max Range
LP Mode, V
= 1.1 V, with buck regulator
CCD
DDD
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
0.9–6.9 mA
0.8–3.8 mA
0.7–1.5 mA
0.7–1.3 mA
0.6–0.7 mA
1.5–8.6 mA
1.3–4.5 mA
1.3–2.2 mA
1.3–2 mA
Across CPUs clock ranges: 8–150/100 MHz; Dhrystone
with flash cache enabled
Minimum regulator current mode
ULP Mode, V = 3.3 V, V
Across CM4/CM0+ CPU active/sleep modes
1.1–1.1 mA
= 0.9 V, with buck regulator
CCD
DDD
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
0.65–1.6 mA
0.51–0.91 mA
0.42–0.76 mA
0.41–0.62 mA
0.39–0.54 mA
7–9 µA
0.8–2.2mA
0.72–1.25 mA
0.65–1.1 mA
0.6–0.9 mA
0.6–0.76 mA
-
Across CPUs clock ranges: 8 – 50/25 MHz; Dhrystone
with flash cache enabled
Minimum regulator current mode
Deep Sleep
Across CM4/CM0+ CPU active/sleep modes
Across SRAM retention
Hibernate
Across V
300–800 nA
-
DDD
Note
1. Usage above the absolute maximum conditions listed in Table 10 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-33480 Rev. *E
Page 36 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 17. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode[2]
8
CM4 Active, CM0+ Sleep 1/2 CM4
CM4 Active, CM0+ Sleep same as CM4
CM0+ Active, CM4 Sleep
7
6
5
4
3
2
1
0
0
25
50
75
100
125
150
CPU Clock, MHz
Power Supplies
Table 12. Power Supply DC Specifications
Spec ID#
Parameter
Description
Internal regulator
Analog power supply voltage. Shorted to
on PCB
Min
Typ
Max
Units
Details / Conditions
SID6
V
V
1.7
–
3.6
V
DDD
SID7
1.7
–
3.6
V
DDA
V
DDIOA
Must be ≥ VDDA if the
CapSense (CSD) block is
used in the application
GPIO supply for Ports 5 to 8 when
present
SID7A
V
1.7
–
3.6
V
DDIO1
SID7B
SID7E
SID7EI
V
V
I
GPIO supply for Ports 11 and 12
Supply when programming E-Fuse
eFuse programming current
eFuse programming time
1.7
2.38
–
–
2.5
–
3.6
2.62
14
V
V
DDIO0
DDIO0
eFuse programming voltage
mA
µs
DDEFUSE
SID7EP EFUSETIME
–
–
5
GPIO supply for Ports 1 to 3 when
present
SID7C
SID7D
SID7F
V
V
V
1.7
1.7
1.7
–
–
–
3.6
3.6
3.6
V
V
V
DDIO2
GPIO supply for Ports 9 and 10 when
present. Must be connected to V
PCB.
on
DDIOA
DDA
Supply for Port 14 (USB or GPIO) when
present
Min supply is 2.85 V for USB
DDUSB
SID6B
SID8
V
V
Backup Power; normally shorted to V
1.7
–
–
3.6
–
V
V
Min is 1.4 V in Backup mode
System LP mode
BACKUP
DDD
(LP)
Output voltage (for core logic bypass)
1.1
CCD
CCD
ULP mode. Valid for –20 to
85 °C.
SID9
V
(ULP)
Output voltage (for core logic bypass)
–
0.9
–
External Regulator voltage (V
bypass
)
X5R ceramic or better. Value
for 0.8 to 1.2 V.
CCD
SID10
SID11
C
C
3.8
–
4.7
10
5.6
–
µF
µF
EFC
EXC
Power supply decoupling capacitor
X5R ceramic or better
Note
2. CM4 Active, CM0+ Sleep 1/2 CM4 trace values are higher because above 100 MHz, the PLL must be used instead of the FLL.
Document Number: 002-33480 Rev. *E
Page 37 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
CPU Current and Transition Times
Table 13. CPU Current and Transition Specifications
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
LP Range Power Specifications (for VCCD = 1.1 Vwith Buck and LDO)
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
2.3
3.2
3.6
VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Flash; CM4 Active
50 MHz, CM0+ Sleep 25 MHz. With
IMO & FLL. While(1).
3.1
VDDD = 1.8 V, Buck ON, Max at 60 °C
SIDF1
SIDF2
IDD1
–
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
5.7
6.5
0.9
1.2
1.5
1.6
VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Flash; CM4 Active
8 MHz, CM0+ Sleep 8 MHz.With
IMO. While(1)
V
DDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 1.8 to 3.3 V, LDO, max at
IDD2
V
2.8
3.5
85 °C
Execute with Cache Enabled
Execute from Cache;CM4 Active
6.9
8.6
VDDD = 3.3 V, Buck ON, Max at 60 °C
10.9
13.7
V
DDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 1.8 to 3.3 V, LDO, max at
SIDC1
SIDC2
SIDC3
SIDC4
IDD3
IDD4
IDD5
IDD6
150 MHz, CM0+ Sleep 75 MHz. IMO
& PLL. Dhrystone.
–
–
–
–
mA
mA
mA
mA
V
13.7
15.5
85 °C
4.8
7.4
5.8
8.4
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Cache;CM4
Active100 MHz, CM0+ Sleep
100 MHz. IMO & FLL. Dhrystone.
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
11.3
12
2.4
3.7
3.4
4.1
VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Cache;CM4 Active
50 MHz, CM0+ Sleep 25MHz. IMO &
FLL. Dhrystone
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 1.8 to 3.3 V, LDO, max at
6.3
7.2
85 °C
0.9
1.3
1.5
1.8
VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Cache;CM4 Active
8 MHz, CM0+ Sleep 8 MHz. IMO.
Dhrystone
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
3
3.8
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
2.4
3.2
3.3
3.7
V
V
V
DDD = 3.3 V, Buck ON, max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 1.8 to 3.3 V, LDO, max at
Execute from Flash;CM4 Off, CM0+
Active 50 MHz. With IMO & FLL.
While (1).
SIDF3
SIDF4
IDD7
IDD8
–
–
mA
mA
5.6
6.3
85 °C
0.8
1.1
1.5
1.6
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Flash;CM4 Off, CM0+
Active 8 MHz. With IMO. While (1)
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.6
3.4
Document Number: 002-33480 Rev. *E
Page 38 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 13. CPU Current and Transition Specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
Execute with Cache Enabled
3.8
5.9
4.5
6.5
V
DDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Cache;CM4 Off, CM0+
Active 100 MHz. With IMO & FLL.
Dhrystone.
VDDD = 1.8 V, Buck ON, Max at 60 °C
SIDC5
SIDC6
IDD9
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
9
9.7
0.8
1.2
1.3
1.7
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Cache;CM4 Off, CM0+
Active 8 MHz. With IMO. Dhrystone
V
IDD10
–
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.60
3.4
Cortex M4. Sleep Mode
1.5
2.2
2.2
2.7
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD =1.8 V, Buck ON, Max at 60 °C
CM4 Sleep 100 MHz, CM0+ Sleep
25 MHz. With IMO & FLL.
V
SIDS1
SIDS2
SIDS3
IDD11
IDD12
IDD13
–
–
–
mA
mA
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
4
4.6
1.2
1.7
1.9
2.2
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 1.8 to 3.3 V, LDO, max at
CM4 Sleep 50 MHz, CM0+ Sleep
25 MHz. With IMO & FLL
3.4
4.3
85 °C
0.7
1
1.3
1.5
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
CM4 Sleep 8 MHz, CM0+ Sleep
8 MHz. With IMO.
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.4
3.3
Cortex M0+. Sleep Mode
1.30
1.9
2
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
CM4 Off, CM0+ Sleep 50 MHz. With
IMO & FLL.
2.4
V
SIDS4
SIDS5
IDD14
IDD15
–
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
3.8
4.6
0.70
1
1.3
1.5
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 1.8 to 3.3 V, LDO, max at
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
2.4
3.3
85 °C
Cortex M4. Minimum Regulator Current Mode
Execute from Flash; CM4 Active
0.9
1.2
1.5
1.7
V
V
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
SIDLPA1 IDD16
8 MHz, CM0+ Sleep 8 MHz. With
IMO. While (1).
–
–
mA
mA
DDD = 1.8 to 3.3 V, LDO, max at
2.8
3.5
85 °C
0.9
1.3
1.5
1.8
VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Cache; CM4 Active
8 MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.
VDDD = 1.8 V, Buck ON, Max at 60 °C
SIDLPA2 IDD17
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.9
3.7
Document Number: 002-33480 Rev. *E
Page 39 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 13. CPU Current and Transition Specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
Cortex M0+. Minimum Regulator Current Mode
0.8
1.1
1.4
1.6
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Flash; CM4 Off, CM0+
Active 8 MHz. With IMO. While (1)
SIDLPA3 IDD18
SIDLPA4 IDD19
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.7
3.6
0.8
1.2
1.4
1.7
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
ExecutefromCache;CM4Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
V
–
–
–
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.7
3.6
Cortex M4. Minimum Regulator Current Mode
0.7
1
1.1
1.5
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
CM4 Sleep 8 MHz, CM0+ Sleep
8 MHz. With IMO.
V
SIDLPS1 IDD20
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.4
3.3
Cortex M0+. Minimum Regulator Current Mode
0.6
0.9
1.1
1.5
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
V
SIDLPS3 IDD22
mA
VDDD = 1.8 to 3.3 V, LDO, max at
85 °C
2.4
3.3
ULP Range Power Specifications (for VCCD = 0.9 V using the Buck). ULP mode is valid from -20 to +85 °C.
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
Execute from Flash; CM4 Active
50 MHz, CM0+ Sleep 25 MHz. With
IMO & FLL. While(1).
1.7
2.1
2.2
2.4
0.8
1
VDDD = 3.3V, Buck ON, Max at 60 °C
SIDF5
SIDF6
IDD3
IDD4
–
–
mA
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Flash; CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With IMO.
While (1)
0.56
0.75
Execute with Cache Enabled
Execute from Cache; CM4 Active
50 MHz, CM0+ Sleep 25 MHz. With
IMO & FLL. Dhrystone.
1.6
2.4
2.2
2.7
0.8
1.1
V
DDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
SIDC8
SIDC9
IDD10
IDD11
–
–
mA
mA
Execute from Cache; CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With IMO.
Dhrystone.
0.65
0.8
V
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
Execute from Flash; CM4 Off, CM0+
Active 25 MHz. With IMO & FLL.
While(1).
1
1.4
1.6
V
DDD = 3.3 V, Buck ON, Max at 60 °C
SIDF7
SIDF8
IDD16
IDD17
–
–
mA
mA
1.34
VDDD = 1.8 V, Buck ON, Max at 60 °C
0.54
0.73
0.75
1
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Flash; CM4 Off, CM0+
Active 8 MHz. With IMO. While(1)
V
Document Number: 002-33480 Rev. *E
Page 40 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 13. CPU Current and Transition Specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
Execute with Cache Enabled
ExecutefromCache;CM4Off, CM0+
Active 25 MHz. With IMO & FLL.
Dhrystone.
0.91
1.34
1.25
1.6
V
DDD = 3.3 V, Buck ON, Max at 60 °C
SIDC10
SIDC11
IDD18
IDD19
–
–
mA
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 3.3 V, Buck ON, Max at 60 °C
0.51
0.73
0.72
0.95
ExecutefromCache;CM4Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
V
DDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M4. Sleep Mode
0.76
1.1
1.1
1.4
VDDD = 3.3 V, Buck ON, Max at 60 °C
CM4 Sleep 50 MHz, CM0+ Sleep
25 MHz. With IMO & FLL
SIDS7
SIDS8
IDD21
IDD22
–
–
mA
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
VDDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
0.42
0.59
0.65
0.8
CM4 Sleep 8 MHz, CM0+ Sleep
8 MHz. With IMO
Cortex M0+. Sleep Mode
0.62
0.88
0.41
0.58
0.9
1.1
0.6
0.8
V
V
V
DDD = 3.3 V, Buck ON, Max at 60 °C
DDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 3.3 V, Buck ON, Max at 60 °C
CM4 Off, CM0+ Sleep 25 MHz. With
IMO & FLL.
SIDS9
IDD23
IDD24
–
–
mA
mA
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
SIDS10
VDDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M4. Minimum Regulator Current Mode
Execute from Flash. CM4 Active
0.52
0.76
0.54
0.78
0.75
1
V
DDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 3.3 V, Buck ON, Max at 60 °C
VDDD = 1.8 V, Buck ON, Max at 60 °C
SIDLPA5 IDD25
8 MHz, CM0+ Sleep 8 MHz. With
IMO. While(1).
–
–
mA
mA
Execute from Cache. CM4 Active
8 MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.
0.76
1
V
SIDLPA6 IDD26
Cortex M0+. Minimum Regulator Current Mode
0.51
0.75
0.48
0.7
0.75
1
mA VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute from Flash. CM4 Off, CM0+
Active 8 MHz. With IMO. While (1).
SIDLPA7 IDD27
SIDLPA8 IDD28
–
–
V
DDD = 1.8 V, Buck ON, Max at 60 °C
DDD = 3.3 V, Buck ON, Max at 60 °C
0.7
0.95
V
ExecutefromCache. CM4Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
mA
mA
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M4. Minimum Regulator Current Mode
0.4
0.6
0.8
VDDD = 3.3 V, Buck ON, Max at 60 °C
CM4 Sleep 8 MHz, CM0 Sleep
SIDLPS5 IDD29
–
–
8 MHz. With IMO.
0.57
VDDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M0+. Minimum Regulator Current Mode
0.39
0.56
0.6
0.8
VDDD = 3.3 V, Buck ON, Max at 60 °C
CM4 Off, CM0+ Sleep 8 MHz. With
SIDLPS7 IDD31
IMO.
VDDD = 1.8 V, Buck ON, Max at 60 °C
Deep Sleep Mode
With internal Buck enabled and 64K
SRAM retention
SIDDS1
IDD33A
–
–
–
–
7
7
9
9
–
–
–
–
µA
µA
µA
µA
Max value is at 85 °C
Max value is at 60 °C
Max value is at 85 °C
Max value is at 60 °C
With internal Buck enabled and 64K
SRAM retention
SIDDS1_B IDD33A_B
With internal Buck enabled and 128K
SRAM retention
SIDDS2
IDD33B
With internal Buck enabled and 128K
SRAM retention
SIDDS2_B IDD33B_B
Document Number: 002-33480 Rev. *E
Page 41 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 13. CPU Current and Transition Specifications (continued)
Spec ID# Parameter
Hibernate Mode
Description
Min
Typ
Max Units
Details / Conditions
SIDHIB1 IDD34
SIDHIB2 IDD34A
V
DDD = 1.8 V
–
–
300
–
–
nA
nA
No clocks running
VDDD = 3.3 V
1400
No clocks running
Power Mode Transition Times
Minimum Regulator Current to LP
transition time
SID12
SID13
SID14
TLPACT_ACT
–
–
–
–
–
35
17
–
µs
µs
µs
Including PLL lock time
Guaranteed by Design
Including PLL lock time
TDS_LPACT Deep Sleep to LP transition time.
Hibernate to Active transition time
THIB_ACT
900
including Boot process.
XRES
Table 14. XRES DC Specifications
Spec ID# Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID17
SID17A
SID77
SID78
SID80
SID81
T
T
I
I
when XRES asserted
when XRES asserted
–
300
–
nA VDDD = 1.8 V
nA VDDD = 3.3 V
XRES_IDD
DD
DD
–
1400
–
XRES_IDD_1
V
V
Input voltage HIGH threshold
Input voltage LOW threshold
Input capacitance
0.7 * VDD
–
–
–
V
V
CMOS input
IH
IL
–
–
–
–
0.3 * VDD
CMOS input
C
V
3
–
–
pF
mV
µA
–
–
IN
Input voltage hysteresis
100
–
HYSXRES
DIODE
Current through protection diode to
V
100
SID82
I
–
/V
DD SS
Table 15. XRES AC Specifications
Spec ID# Parameter
Description
Min
Typ
900
Max
Units
Details / Conditions
–
–
µs Not minimum regulator current
mode; Cortex-M0+ executing at
50 MHz
Time from XRES release to Active
mode including Boot process
SID15
TXRES_ACT
TXRES_PW
SID16
XRES pulse width
5
–
–
µs
–
GPIO
Table 16. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
V
Details / Conditions
CMOS Input
SID57
V
Input voltage HIGH threshold
0.7 * VDD
–
–
–
–
IH
Input current when Pad > V
OVT inputs
for
10
µA
2
DDIO
SID57A
I
Per I C Spec
IHS
SID58
V
V
V
V
V
V
V
Input voltage LOW threshold
–
–
–
0.3 * VDD
V
V
CMOS Input
IL
SID241
SID242
SID243
SID244
SID59
LVTTL input, V < 2.7 V
0.7 * VDD
–
–
–
–
–
IH
IL
DD
LVTTL input, V < 2.7 V
–
–
0.3 * VDD
V
DD
LVTTL input, V ≥ 2.7 V
2.0
–
–
V
IH
IL
DD
LVTTL input, V ≥ 2.7 V
–
VDD – 0.5
–
–
0.8
–
V
DD
Output voltage HIGH level
Output voltage LOW level
Pull-up resistor
–
V
I
I
= 8 mA
= 8 mA
OH
OL
OH
OL
SID62A
SID63
–
0.4
8.5
V
R
3.5
5.6
kΩ
–
PULLUP
Document Number: 002-33480 Rev. *E
Page 42 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 16. GPIO DC Specifications (continued)
Spec ID#
Parameter
Description
Pull-down resistor
Min
3.5
–
Typ
5.6
–
Max
8.5
2
Units
kΩ
Details / Conditions
SID64
R
–
PULLDOWN
Input leakage current (absolute
value)
nA
SID65
I
I
25 °C, V = 3.0 V
IL
DD
SID65A
SID66
SID67
SID68
Input leakage on CTBm input pins
Input capacitance
–
–
–
0
–
–
4
5
nA
pF
IL_CTBM
C
V
–
100
–
–
–
IN
Input hysteresis LVTTL V > 2.7 V
–
mV
mV
µA
HYSTTL
DD
V
Input hysteresis CMOS
0.05*VDD
–
–
HYSCMOS
Current through protection diode to
100
SID69
I
I
–
–
DIODE
V
/V
DD SS
Maximum total source or sink chip
current
–
–
200
mA
SID69A
TOT_GPIO
Table 17. GPIO AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Rise time in Fast Strong Mode. 10%
Cload = 15 pF, 8-mA drive
strength
–
–
2.5
2.5
142
102
211
93
ns
SID70
T
T
T
T
T
T
T
F
F
F
F
F
RISEF
to 90% of V
.
DD
Fall time in Fast Strong Mode. 10%
to 90% of V
Cload = 15 pF, 8-mA drive
strength
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
SID71
FALLF
.
DD
RisetimeinSlowStrongMode. 10%
to 90% of V
Cload = 15 pF, 8-mA drive
52
48
44
42
SID72
RISES_1
RISES_2
FALLS_1
FALLS_2
FALL_I2C
GPIOUT1
GPIOUT2
GPIOUT3
GPIOUT4
GPIOIN
.
strength, V 2.7 V
DD
DD
RisetimeinSlowStrongMode. 10%
to 90% of V
Cload = 15 pF, 8-mA drive
ns
SID72A
SID73
.
strength, 2.7 V < V 3.6 V
DD
DD
Fall time in Slow Strong Mode. 10%
to 90% of V
Cload = 15 pF, 8-mA drive
ns
.
strength, V 2.7 V
DD
DD
Fall time in Slow Strong Mode. 10%
to 90% of V
Cload = 15 pF, 8-mA drive
ns
SID73A
SID73G
SID74
.
strength, 2.7 V < V 3.6 V
DD
DD
Fall time (30% to 70% of V ) in
Cload = 10 pF to 400 pF, 8-mA
drive strength
20 * VDDIO
/ 5.5
250
100
16.7
7
ns
DD
Slow Strong mode.
90/10%, 15-pF load, 60/40 duty
cycle
–
–
–
–
–
MHz
MHz
MHz
MHz
MHz
GPIO Fout. Fast Strong mode.
90/10%, 15-pF load, 60/40 duty
cycle
SID75
GPIO Fout; Slow Strong mode.
GPIO Fout; Fast Strong mode.
90/10%, 25-pF load, 60/40 duty
cycle
SID76
90/10%, 25-pF load, 60/40 duty
cycle
3.5
100
SID245
SID246
GPIO Fout; Slow Strong mode.
GPIO input operating frequency;
90/10% V
IO
1.71 V V 3.6 V
DD
Document Number: 002-33480 Rev. *E
Page 43 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Analog Peripherals
Opamp
Table 18. Opamp Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Overvoltage and temp
(–40/105 °C) unless
stated otherwise
I
Opamp block current. No load.
–
–
–
–
DD
SID269
I
I
I
power = hi
power = med
power = lo
–
–
1300
1500
uA
uA
uA
DD_HI
SID270
SID271
450
250
–
600
350
–
DD_MED
DD_LOW
–
GBW
Load = 20 pF, 0.1mA. V
power = hi
= 2.7 V
–
DDA
SID272
SID273
SID274
GBW_HI
GBW_MED
GBW_LO
6
–
–
MHz
MHz
MHz
power = med
2
–
–
power = lo
–
1
–
I
V
≥ 2.7 V, 500 mV from rail
–
–
–
OUT_MAX
DDA
SID275
SID276
SID277
I
power = hi
power = med
power = lo
10
10
–
–
–
mA
mA
mA
OUT_MAX_HI
I
–
–
OUT_MAX_MID
I
5
–
OUT_MAX_LO
I
I
I
I
V
= 1.7 V, 500 mV from rail
OUT
DDA
SID278
SID279
SID280
SID281
power = hi
4
4
–
0
–
–
2
–
–
mA
mA
mA
V
OUT_MAX_HI
OUT_MAX_MID
OUT_MAX_LO
power = med
power = lo
–
–
V
Input voltage range
VDDA-0.2
Charge pump ON
Charge pump OFF,
IN
SID282
V
Input common mode voltage
0
–
VDDA-0.2
V
CM
V
≥ 2.7 V
DDA
V
V
V
V
V
V
≥ 2.7 V
OUT
DDA
SID283
SID284
SID285
SID286
power = hi, Iload = 10 mA
power = hi, Iload = 1 mA
power = med, Iload = 1 mA
power = lo, Iload = 0.1 mA
0.5
0.2
0.2
0.2
–
–
–
–
VDDA -0.5
VDDA -0.2
VDDA -0.2
VDDA -0.2
V
V
V
V
OUT_1
OUT_2
OUT_3
OUT_4
Offset voltage. Closed loop configu-
ration.
High mode, 0.2 to
DDA – 0.2
SID288
V
-1
+/-0.5
1
mV
OS
V
SID288A
SID288B
V
V
Offset voltage
Offset voltage
-
-
+/-1
+/-2
-
-
mV Medium mode
mV Low mode
OS
OS
High mode, 0.2 to
µV/°C
SID290
V
Offset voltage drift
-10
+/-3
10
OS_DR
V
-0.2
DDA
SID290A
SID290B
V
V
Offset voltage drift
Offset voltage drift
-
-
+/10
–
–
µV/°C Medium mode
µV/C Low mode
OS_DR
OS_DR
+/-10
V
V
= 3.3 V. Vin = 0.2 to
DDA – 0.2.
DDD
SID291
SID292
CMRR
PSRR
DC Common mode rejection ratio
67
70
80
85
–
–
dB
dB
Power supply rejection ratio at 1 kHz,
10mV ripple
V = 3.3 V. Vin =
DDD
V
.
DDA/2
Noise
SID293
VN1
VN2
Input-referred, 1 Hz - 1 GHz, power = hi
Input-referred, 1 kHz, power = hi
–
–
100
180
–
–
µVrms Guaranteed by design
nV/
SID294
Guaranteed by design
rtHz
Document Number: 002-33480 Rev. *E
Page 44 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 18. Opamp Specifications (continued)
Spec ID#
SID295
Parameter
VN3
Description
Min
Typ
Max
Units
Details/Conditions
nV/
rtHz
Input-referred, 10 kHz, power = hi
–
70
–
Guaranteed by design
nV/
rtHz
SID296
SID297
VN4
Input-referred, 100 kHz, power = hi
–
–
38
–
–
Guaranteed by design
Stable up to max load. Performance
specs at 50 pF.
CLOAD
125
pF High and m
Cload = 50pF,
Power = High, V
V
≥ 2.7
DDA
SID298
SID299
SLEW_RATE
T_OP_WAKE
Output slew rate
4
–
–
–
–
V/µs
Refer to Figure 18 and
Figure 19
From disable to enable, no external RC
dominating
10
µs For V
≥ 2.7 V
DDA
COMP_MODE Comparator mode; 50mV overdrive.
SID300
SID301
SID302
SID303
TPD1
TPD2
TPD3
V
Response time; power = hi
Response time; power = med
Response time; power = lo
Hysteresis
–
–
–
–
150
400
2000
10
–
–
–
–
ns
ns
ns
mV
HYST_OP
Deep Sleep mode
operation: V ≥ 2.7 V.
Mode 2 is lowest current range. Mode 1
has higher GBW.
Deep Sleep Mode
DDA
V
is 0.2 to V
- 1.5 V
IN
DDA
SID_DS_1
SID_DS_2
SID_DS_3
SID_DS_4
SID_DS_5
SID_DS_6
SID_DS_7
SID_DS_8
SID_DS_9
IDD_HI_M1
Mode 1, High current
–
–
–
–
–
–
–
–
–
1300
460
230
100
40
1500
600
350
–
µA Typ at 25 °C
µA Typ at 25 °C
µA Typ at 25 °C
µA 25 °C
IDD_MED_M1 Mode 1, Medium current
IDD_LOW_M1 Mode 1, Low current
IDD_HI_M2 Mode 2, High current
IDD_MED_M2 Mode 2, Medium current
IDD_LOW_M2 Mode 2, Low current
–
µA 25 °C
15
–
µA 25 °C
GBW_HI_M1
Mode 1, High current
4
–
MHz 25 °C
GBW_MED_M1 Mode 1, Medium current
GBW_LOW_M1 Mode 1, Low current
2
–
MHz 25 °C
0.5
–
MHz 25 °C
20-pF load, no DC load
SID_DS_10
SID_DS_11
SID_DS_12
GBW_HI_M2
Mode 2, High current
–
–
–
0.5
0.2
0.1
–
–
–
MHz
MHz
MHz
0.2V to V
-1.5 V
DDA
20-pF load, no DC load
0.2 V to V -1.5 V
GBW_MED_M2 Mode 2, Medium current
GBW_LOW_M2 Mode 2, Low current
DDA
20-pF load, no DC load
0.2 V to V
-1.5 V
-1.5 V
-1.5 V
-1.5 V
-1.5 V
-1.5 V
-1.5 V
DDA
DDA
DDA
DDA
DDA
DDA
DDA
SID_DS_13
SID_DS_14
SID_DS_15
SID_DS_16
SID_DS_17
SID_DS_18
VOS_HI_M1
Mode 1, High current
–
–
–
–
–
–
5
5
5
5
5
5
–
–
–
–
–
–
mV 0.2 V to V
mV 0.2 V to V
mV 0.2 V to V
mV 0.2 V to V
mV 0.2 V to V
mV 0.2 V to V
VOS_MED_M1 Mode 1, Medium current
VOS_LOW_M1 Mode 1, Low current
VOS_HI_M2
Mode 2, High current
VOS_MED_M2 Mode 2, Medium current
VOS_LOW_M2 Mode 2, Low current
Output is 0.5 V to
-0.5 V
SID_DS_19
SID_DS_20
IOUT_HI_M1
Mode 1, High current
–
–
10
10
–
–
mA
mA
V
DDA
Output is 0.5 V to
-0.5 V
IOUT_MED_M1 Mode 1, Medium current
V
DDA
Document Number: 002-33480 Rev. *E
Page 45 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 18. Opamp Specifications (continued)
Spec ID#
Parameter
IOUT_LOW_M1 Mode 1, Low current
IOUT_HI_M2 Mode 2, High current
Description
Min
Typ
Max
Units
Details/Conditions
Output is 0.5 V to
SID_DS_21
–
4
–
mA
V
-0.5 V
DDA
Output is 0.5 V to
-0.5 V
SID_DS_22
SID_DS_23
SID_DS_24
–
–
–
1
1
–
–
–
mA
mA
mA
V
DDA
Output is 0.5 V to
-0.5 V
IOU_MED_M2 Mode 2, Medium current
IOU_LOW_M2 Mode 2, Low current
V
DDA
Output is 0.5 V to
-0.5 V
0.5
V
DDA
Figure 18. Opamp Step Response, Rising
Figure 19. Opamp Step Response, Falling
1.4
1.4
Input
Output, Power = Hi
Output, Power = Med
1.2
1
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
Input
Output, Power = Hi
Output, Power = Med
0.4
0.2
0
-0.25
0
0.25
Time, µs
0.5
0.75
1
-0.25
0
0.25
0.5
0.75
1
Time. µs
Low-Power (LP) Comparator
Table 19. LP Comparator DC Specifications
Spec ID#
Parameter
Description
Min Typ
–10
Max
Units
Details/Conditions
Input offset voltage for COMP.
Normal power mode.
SID84
V
V
V
V
V
V
V
V
–
10
mV
–
–
–
–
–
–
–
–
–
OFFSET1
Input offset voltage. Low-power
mode.
SID85A
SID85B
SID86
–25 ±12
–25 ±12
25
mV
mV
mV
mV
V
OFFSET2
OFFSET3
HYST1
HYST2
ICM1
Input offset voltage. Ultra
low-power mode.
25
Hysteresis when enabled in
Normal mode
–
–
–
–
–
–
–
–
60
80
Hysteresis when enabled in
Low-power mode
SID86A
SID87
Input common mode voltage in
Normal mode
0
VDDIO1 – 0.1
VDDIO1 – 0.1
VDDIO1 – 0.1
–
InputcommonmodevoltageinLow
power mode
SID247
SID247A
SID88
0
V
ICM2
Input common mode voltage in
Ultra low power mode
0
V
ICM3
Common mode rejection ratio in
Normal power mode
CMRR
50
dB
SID89
I
Block current, Normal mode
–
–
–
–
150
10
µA
µA
–
–
CMP1
SID248
I
Block current, Low-power mode
CMP2
Document Number: 002-33480 Rev. *E
Page 46 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 19. LP Comparator DC Specifications (continued)
Spec ID#
SID259
Parameter
Description
Min Typ
Max
0.85
–
Units
µA
Details/Conditions
Block current in Ultra low-power
mode
I
–
0.3
–
–
–
CMP3
SID90
ZCMP
DC input impedance of comparator 35
MΩ
Table 20. LP Comparator AC Specifications
Spec ID#
Parameter
Description
Min Typ
Max
Units
Details/Conditions
Response time, Normal mode, 100
mV overdrive
SID91
T
T
T
–
–
–
–
–
–
100
ns
–
–
–
RESP1
Response time, Low power mode,
100 mV overdrive
SID258
SID92
1000
20
ns
µs
RESP2
RESP3
Response time, Ultra-low power
mode, 100 mV overdrive
SID92E
SID92F
T_CMP_EN1
T_CMP_EN2
Time from Enabling to operation
Time from Enabling to operation
–
–
–
–
10
50
µs Normal and low-power modes
µs Ultra-low-power mode
Temperature Sensor
Table 21. Temperature Sensor Specifications
Spec ID
SID93
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T
Temperature sensor accuracy
–5
±1
5
°C –40 to +105 °C
SENSACC
Internal Reference
Table 22. Internal Reference Specification
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID93R
V
–
1.188
1.2
1.212
V
–
REFBG
SAR ADC
Table 23. SAR ADC DC Specifications
Spec ID# Parameter Description
SAR ADC resolution
Min Typ Max Units
Details / Conditions
SID94
SID95
SID96
SID97
SID98
SID99
A_RES
–
–
–
–
–
–
–
–
–
–
–
–
12
16
8
bits
A_CHNLS_S Number of channels - single-ended
A-CHNKS_D Number of channels - differential
8 full speed.
Diff inputs use neighboring I/O
Yes
A-MONO
A_GAINERR Gain error
A_OFFSET Input offset voltage
Monotonicity
-
±0.2
2
%
With external reference.
mV Measured with 1-V reference
At 1 Msps. External reference
mode
SID100 A_ISAR_1
SID100A A_ISAR_2
SID1002 A_ISAR_3
Current consumption at 1 Msps
Current consumption at 1 Msps
Current consumption at 2 Msps
–
–
–
–
–
–
1.05 mA
1.3
mA At 1 Msps. Internal reference mode
At 2 Msps. External reference
mode
2.15 mA At 2 Msps. Internal reference mode
1.65 mA
SID1003 A_ISAR_4
SID101 A_VINS
SID102 A_VIND
SID103 A_INRES
SID104 A_INCAP
Current consumption at 2 Msps
Input voltage range - single-ended
Input voltage range - differential
Input resistance
–
VSS
VSS
–
–
–
–
1
5
VDDA
VDDA
–
V
V
kΩ
pF
Input capacitance
–
–
Document Number: 002-33480 Rev. *E
Page 47 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 23. SAR ADC DC Specifications (continued)
SAR in Deep Sleep Mode VDDA = 2.7 V. 2-MHz LPOSC and duty-cycled.
Chip current consumption for 12 bits,
100 ksps Deep Sleep Mode
SIDP121 IDD_CHIP_1
SIDP122 IDD_CHIP_2
–
–
320
16
–
–
µA
µA
Chip current consumption for 12 bits,
500 sps, duty cycle in Deep Sleep Mode
Chip Current Consumption for 10Bits
SIDP123 IDD_CHIP_3 (10% power mode), 16 ksps Deep Sleep
Mode
–
150
–
µA
Integral non-linearity for 10 bits (10%
SIDP124 INL_10bits
–2
–1
–2
–
–
–
2
1
2
LSB
LSB
LSB
power mode) mode (VDDA ≥ 2.7 V)
Differential non-linearity for 10Bits (10%
SIDP125 DNL_10bits
power mode) mode (VDDA ≥ 2.7 V)
Offset for 10 bits (10% power mode)
SIDP126 Vos_10bits
mode (VDDA ≥ 2.7 V)
Gain Error for 10 bits (10% power mode)
SIDP127 GE_10bits
mode (VDDA ≥ 2.7 V, VREF = 1.2 V
bypassed with external cap)
–1
–
1
LSB
Table 24. SAR ADC AC Specifications
Spec ID# Parameter
Description
Min Typ Max Units
Details / Conditions
SID106
SID107
A_PSRR
A_CMRR
Power supply rejection ratio
Common mode rejection ratio
70
66
1
–
–
–
–
–
dB
dB Measured at 1 V
–
SID107A EXT_REF_1 External reference range
VDDA
VDDA
V
V
1 Msps sample rate and below
SDI107B Ext_REF_2
External reference range
Sample rate with external reference
With bypass cap
2
>1 and up to 2 Msps sample rates
SID1081 A_SAMP_1
–
–
–
–
–
–
–
–
–
–
2
1
2
1
1
Msps VDDA 2.7–3.6 V
Msps VDDA 1.7–3.6 V
Msps VDDA 2.7–3.6 V
Msps VDDA 1.7–3.6 V
Msps
Sample rate with external reference
With bypass cap
SID1082 A_SAMP_1
SID108A1 A_SAMP_2
SID108A2 A_SAMP_2
SID108B A_SAMP_3
SID108C A_SAMP_4
Sample rate with VDD Reference;
No bypass cap
–
Sample rate with VDD Reference;
No bypass cap
–
Sample rate with Internal reference;
With bypass cap
–
Sample rate with internal reference.
No bypass cap
–
200 ksps
Signal-to-noise and distortion ratio
(SINAD).
SID109
A_SINAD
64
– 2
–
2
dB Fin = 10 kHz
Integral non-linearity.
Up to 1 Msps
SID111A A_INL
SID111B A_INL
SID112A A_DNL
LSB All reference mode
External reference or VDDA
LSB Reference Mode, VREF ≥ 2 V.
VDDA = 2.7–3.6 V
Integral non-linearity.
2 Msps.
–2.5
– 1
–
–
2.5
1.5
Differential non-linearity.
Up to 1 Msps
LSB All Reference Mode
Document Number: 002-33480 Rev. *E
Page 48 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 24. SAR ADC AC Specifications (continued)
Spec ID# Parameter
Description
Min Typ Max Units
Details / Conditions
External Reference or VDDA
Reference Mode, VREF ≥ 2 V.
LSB
Differential non-linearity.
2 Msps.
SID112B A_DNL
–1
–
1.6
VDDA = 2.7–3.6 V
SID113
A_THD
Total harmonic distortion. 1 Msps.
–
–
–65
dB Fin = 10 kHz. VDDA = 2.7–3.6 V.
Both SARs with simultaneous sampling. Fclk = 18 MHz, Data Rate = 1 Msps; VDDA ≥ 2.7 V; Internal Ref. with Bypass Cap.
Simultaneous sampling spec assume the same clock source is used for both SAR ADCs.
SIDP131 INL
SIDP132 DNL
SIDP133 Vos
Integral Non Linearity (VDDA ≥ 2.7 V)
–2
–
–
–
2
1
2
LSB
LSB
LSB
Differential Non Linearity (VDDA ≥ 2.7V) –1
Offset (VDDA ≥ 2.7V)
–2
-1
Gain Error (VDDA ≥ 2.7V, VREF = 1.2V
bypassed with external Cap)
SIDP134 GE
–
1
LSB
Both SARs internal op amp buffered with simultaneous sampling VDDA reference. Fclk = 18 MHz, Data Rate = 1 Msps;
VDDA ≥ 2.7 V; VREF ≥ 2 V. Simultaneous sampling spec assume the same clock source is used for both SAR ADCs.
SIDP141 INL
SIDP142 DNL
SIDP143 Vos
Integral Non Linearity (VDDA ≥ 2.7 V)
–3
–
–
–
3
2
3
LSB
LSB
LSB
Differential Non Linearity (VDDA ≥ 2.7 V) –1
Offset (VDDA ≥ 2.7 V)
–3
–1
Gain Error (VDDA ≥ 2.7V, VREF = 1.2 V
bypassed with external Cap)
SIDP144 GE
–
1
LSB
Document Number: 002-33480 Rev. *E
Page 49 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
DAC
Table 25. 12-bit DAC DC Specifications
Spec ID#
SID108D
Parameter
DAC_RES
Description
DAC resolution
Min
–
Typ
–
Max
12
4
Units
bits
LSB
LSB
mV
kΩ
Details / Conditions
SID111D
SID112D
SID99D
DAC_INL
Integral Non-Linearity
–4
–2
–10
–
–
DAC_DNL
Differential Non Linearity
Output Voltage zero offset error
–
2
Monotonic to 11 bits.
For 000 (hex)
DAC_OFFSET
–
10
–
SID103D
SID100D
SID101D
DAC_OUT_RES DAC Output Resistance
15
–
DAC_IDD
DAC Current
–
125
1
µA
DAC_QIDD
DAC Current when DAC stopped
–
–
µA
Table 26. 12-bit DAC AC Specifications
Spec ID#
SID109D
Parameter
Description
DAC Settling time
Min
Typ
Max
Units
Details / Conditions
Driving through CTBM buffer;
25 pF load
DAC_CONV
–
–
2
µs
Time from Enabling to ready for
conversion
SID110D
DAC_Wakeup
–
–
10
µs
CSD
Table 27. CSD V2 Specifications
Spec ID# Parameter
CSD V2 Specifications
Description
Min
Typ
Max
Units
Details / Conditions
V
> 2 V (with ripple),
DDA
Maxallowedrippleonpowersupply,
DC to 10 MHz
25 °C T ,
SYS.PER#3
V
–
–
–
±50
±25
mV
mV
A
DD_RIPPLE
Sensitivity = 0.1 pF
V
> 1.75 V (with ripple),
DDA
25 ° C T ,
Maxallowedrippleonpowersupply,
DC to 10 MHz
A
SYS.PER#16
V
I
–
DD_RIPPLE_1.8
Parasitic Capacitance (C )
P
< 20 pF, Sensitivity ≥ 0.4 pF
SID.CSD.BLK
SID.CSD#15
Maximum block current
–
–
4500
µA
V
–
CSD
Voltage reference for CSD and
Comparator
V
0.6
1.2
VDDA – 0.6
V
V
– VREF ≥ 0.6 V
REF
DDA
DDA
External Voltage reference for CSD
and Comparator
SID.CSD#15A
V
I
0.6
VDDA – 0.6
V
– V
≥ 0.6 V
REF_EXT
REF
SID.CSD#16
SID.CSD#17
SID308
IDAC1 (7-bits) block current
IDAC2 (7-bits) block current
Voltage range of operation
Voltage compliance range of IDAC
DNL
–
–
–
–
–
–
1900
1900
3.6
µA
µA
V
–
–
DAC1IDD
DAC2IDD
I
–
V
V
I
1.7
0.6
–1
1.71 to 3.6 V
CSD
SID308A
VDDA –0.6
1
V
V
–
– V
DDA REF
≥ 0.6 V
COMPIDAC
SID309
LSB
DAC1DNL
DAC1INL
DAC2DNL
DAC2INL
If V
< 2 V then for LSB
DDA
SID310
SID311
SID312
I
I
I
INL
DNL
INL
–3
–1
–3
–
–
–
3
1
3
LSB
LSB
LSB
of 2.4 µA or less
–
If V
< 2 V then for LSB
DDA
of 2.4 µA or less
SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization.
SRSS Reference. IMO + FLL Clock
Source. 0.1-pF sensitivity.
SID313_1A
SNRC_1
5
–
–
Ratio 9.5-pF max. capacitance
Page 50 of 73
Document Number: 002-33480 Rev. *E
PSoC 6 MCU: CY8C61x4
Datasheet
Table 27. CSD V2 Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SRSS Reference. IMO + FLL Clock
Source. 0.3-pF sensitivity.
SID313_1B
SNRC_2
5
–
–
Ratio 31-pF max. capacitance
Ratio 61-pF max. capacitance
Ratio 12-pF max. capacitance
Ratio 47-pF max. capacitance
Ratio 86-pF max. capacitance
Ratio 25-pF max. capacitance
Ratio 86-pF max. capacitance
Ratio 168-pF Max. capacitance
SRSS Reference. IMO + FLL Clock
Source. 0.6-pF sensitivity.
SID313_1C
SID313_2A
SID313_2B
SID313_2C
SID313_3A
SID313_3B
SID313_3C
SID314
SNRC_3
SNRC_4
SNRC_5
SNRC_6
SNRC_7
SNRC_8
SNRC_9
5
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PASS Reference. IMO + FLL Clock
Source. 0.1-pF sensitivity.
PASS Reference. IMO + FLL Clock
Source. 0.3-pF sensitivity.
5
–
PASS Reference. IMO + FLL Clock
Source. 0.6-pF sensitivity.
5
–
PASS Reference. IMO + PLL Clock
Source. 0.1-pF sensitivity.
5
–
PASS Reference. IMO + PLL Clock
Source. 0.3-pF sensitivity.
5
–
PASS Reference. IMO + PLL Clock
Source. 0.6-pF sensitivity.
5
–
Output current of IDAC1 (7 bits) in
low range
IDAC
4.2
33.7
270
8
5.7
45.6
365
11.4
91
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
LSB
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB = 2.4-µA typ.
1CRT1
Output current of IDAC1 (7 bits) in
medium range
SID314A
SID314B
SID314C
SID314D
SID314E
SID315
IDAC
1CRT2
Output current of IDAC1 (7 bits) in
high range
IDAC
1CRT3
Output current of IDAC1 (7 bits) in
low range, 2X mode
LSB = 37.5-nA typ. 2X
output stage
IDAC
1CRT12
Output current of IDAC1 (7 bits) in
medium range, 2X mode
LSB = 300-nA typ. 2X
output stage
IDAC
67
540
4.2
33.7
270
8
1CRT22
Output current of IDAC1 (7 bits) in
LSB = 2.4-µAtyp. 2X output
stage
IDAC
730
5.7
45.6
365
11.4
91
1CRT32
high range, 2X mode. V
> 2 V
DDA
Output current of IDAC2 (7 bits) in
low range
IDAC
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB = 2.4-µA typ.
2CRT1
Output current of IDAC2 (7 bits) in
medium range
SID315A
SID315B
SID315C
SID315D
SID315E
SID315F
SID315G
SID315H
SID320
IDAC
2CRT2
Output current of IDAC2 (7 bits) in
high range
IDAC
2CRT3
Output current of IDAC2 (7 bits) in
low range, 2X mode
LSB = 37.5-nA typ. 2X
output stage
IDAC
2CRT12
Output current of IDAC2 (7 bits) in
medium range, 2X mode
LSB = 300-nA typ. 2X
output stage
IDAC
67
540
8
2CRT22
Output current of IDAC2 (7 bits) in
LSB = 2.4-µAtyp. 2X output
stage
IDAC
730
11.4
91
2CRT32
high range, 2X mode. V
> 2V
DDA
Output current of IDAC in 8-bit
mode in low range
IDAC
LSB = 37.5-nA typ.
LSB = 300-nA typ.
LSB = 2.4-µA typ.
3CRT13
Output current of IDAC in 8-bit
mode in medium range
IDAC
67
540
–
3CRT23
Output current of IDAC in 8-bit
IDAC
730
1
3CRT33
mode in high range. V
> 2V
DDA
Polarity set by Source or
Sink
IDAC
All zeroes input
OFFSET
Document Number: 002-33480 Rev. *E
Page 51 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 27. CSD V2 Specifications (continued)
Spec ID#
SID321
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
IDAC
Full-scale error less offset
–
–
±15
%
LSB = 2.4-µA typ.
GAIN
IDAC
Mismatch between IDAC1 and
IDAC2 in Low mode
MIS-
SID322
–
–
–
–
–
–
–
–
9.2
6
LSB LSB = 37.5-nA typ.
LSB LSB = 300-nA typ.
LSB LSB = 2.4-µA typ.
MATCH1
IDAC
Mismatch between IDAC1 and
IDAC2 in Medium mode
MIS-
MATCH2
SID322A
SID322B
SID323
IDAC
Mismatch between IDAC1 and
IDAC2 in High mode
MIS-
5.8
10
MATCH3
Settling time to 0.5 LSB for 8-bit
IDAC
Full-scale transition. No
IDAC
µs
SET8
external load.
Settling time to 0.5 LSB for 7-bit
IDAC
Full-scale transition. No
external load.
SID324
SID325
IDAC
–
–
–
10
–
µs
SET7
CMOD
External modulator capacitor.
2.2
nF
5-V rating, X7R or NP0 cap.
Table 28. CSDv2 ADC Specifications
Spec ID# Parameter
CSDv2 ADC Specifications
Description
Min Typ Max Units
Details / Conditions
Auto-zeroing is required every milli-
second
–
–
10
bits
SIDA94
A_RES
Resolution
SID95
A_CHNLS_S
A-MONO
Number of channels - single ended
Monotonicity
–
–
–
–
–
–
Yes
–
16
–
–
SIDA97
V
mode
REF
Reference Source: SRSS
0.6
%
(V
(V
= 1.20 V, V
= 1.6 V, 2.2 V < V
< 2.2 V),
DDA
REF
SIDA98
A_GAINERR_VREF Gain error
< 2.7
REF
DDA
V), (V
= 2.13 V, V
> 2.7 V)
REF
DDA
Reference Source: SRSS
–
–
0.2
0.5
–
–
%
(V
(V
= 1.20 V, V
= 1.6 V,
< 2.2V),
DDA
REF
SIDA98A A_GAINERR_VDDA Gain error
REF
2.2 V < V
< 2.7 V),
DDA
(V
= 2.13 V, V
> 2.7 V)
REF
DDA
After ADC calibration, Ref. Src =
LSB
SRSS, (V
2.2 V),
= 1.20 V, V
<
REF
DDA
SIDA99
A_OFFSET_VREF
Input offset voltage
Input offset voltage
(V
= 1.6 V, 2.2 V < V
<
DDA
REF
2.7 V),
(V = 2.13 V, V
> 2.7 V)
DDA
REF
After ADC calibration, Ref. Src =
SRSS, (V
2.2 V),
–
0.5
–
LSB
= 1.20 V, V
<
REF
DDA
SIDA99A A_OFFSET_VDDA
(V
= 1.6 V, 2.2 V < V
<
DDA
REF
2.7 V),
(V = 2.13 V, V
> 2.7 V)
DDA
REF
SIDA100 A_ISAR_VREF
SIDA100A A_ISAR_VDDA
Current consumption
Current consumption
–
–
0.3
0.3
–
–
–
mA CSD ADC Block current
mA CSD ADC Block current
(V
(V
= 1.20 V, V
< 2.2 V),
DDA
VSSA
VREF
V
REF
= 1.6 V, 2.2 V < V
<
REF
DDA
SIDA101 A_VINS_VREF
Input voltage range - single ended
2.7 V),
(V = 2.13 V, V
> 2.7 V)
DDA
REF
Document Number: 002-33480 Rev. *E
Page 52 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 28. CSDv2 ADC Specifications (continued)
Spec ID#
Parameter
Description
Min Typ Max Units
Details / Conditions
= 1.20 V, V < 2.2 V),
(V
(V
VSSA
–
VDDA
V
REF
DDA
= 1.6 V, 2.2 V < V
<
DDA
RE F
SIDA101A A_VINS_VDDA
Input voltage range - single ended
2.7 V),
(V
= 2.13 V, V
> 2.7 V)
DDA
REF
SIDA103 A_INRES
SIDA104 A_INCAP
SIDA106 A_PSRR
Input charging resistance
Input capacitance
–
–
–
–
15
41
60
10
–
–
–
–
kΩ
pF
dB
µs
–
–
Power supply rejection ratio (DC)
–
Measured with 50-Ω source
impedance. 10 µs is default
software driver acquisition time
setting. Settling to within 0.05%.
SIDA107 A_TACQ
Sample acquisition time
Conversion time for 8-bit resolution at
conversion rate = Fhclk / (2"(N + 2)).
Clock frequency = 50 MHz.
–
–
25
60
–
–
µs
µs
SIDA108 A_CONV8
SIDA108A A_CONV10
Does not include acquisition time.
Does not include acquisition time.
Conversion time for 10-bit resolution at
conversion rate = Fhclk / (2"(N + 2)).
Clock frequency = 50 MHz.
Signal-to-noise and Distortion ratio
(SINAD)
Measured with 50-Ω source
impedance
–
–
–
–
–
–
57
52
–
–
–
2
2
1
1
dB
SIDA109 A_SND_VRE
SIDA109A A_SND_VDDA
Signal-to-noise and Distortion ratio
(SINAD)
Measured with 50-Ω source
impedance
dB
Measured with 50-Ω source
impedance
LSB
LSB
LSB
LSB
SIDA111
SIDA111A A_INL_VDDA
SIDA112 A_DNL_VREF
SIDA112A A_DNL_VDDA
A_INL_VREF
Integral non-linearity. 11.6 ksps
Integral non-linearity. 11.6 ksps
Differential non-linearity. 11.6 ksps
Differential non-linearity. 11.6 ksps
Measured with 50-Ω source
impedance
–
Measured with 50-Ω source
impedance
–
Measured with 50-Ω source
impedance
–
Document Number: 002-33480 Rev. *E
Page 53 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Digital Peripherals
Timer/Counter/PWM (TCPWM)
Table 29. TCPWM Specifications
Spec ID#
SID.TCPWM.1
SID.TCPWM.2
SID.TCPWM.2A
Parameter
Description
Min Typ Max Units
Details/Conditions
µA All modes (TCPWM)
µA All modes (TCPWM)
µA All modes (TCPWM)
I
I
I
Block current consumption at 8 MHz
Block current consumption at 24 MHz
Block current consumption at 50 MHz
–
–
–
–
–
–
70
TCPWM1
TCPWM2
TCPWM3
180
270
SID.TCPWM.2B
SID.TCPWM.3
I
Block current consumption at 100 MHz
Operating frequency
–
–
–
–
540
µA All modes (TCPWM)
TCPWM4
TCPWM
100 MHz Maximum = 100 MHz
FREQ
Trigger Events can be Stop,
Start, Reload, Count, Capture,
or Kill depending on which
mode of operation is selected.
FC is counter operating
frequency.
Input trigger pulse width for all trigger
events
SID.TCPWM.4
SID.TCPWM.5
TPWM
2/Fc
–
–
–
–
ns
ENEXT
Minimum possible width of
Overflow, Underflow, and CC
ns (Counter equals Compare
value) trigger outputs. FC is
counter operating frequency.
TPWM
Output trigger pulse widths
1.5/Fc
EXT
Minimum time between
ns successive counts. FC is
counter operating frequency.
SID.TCPWM.5A TC
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
RES
Minimum pulse width of PWM
ns output. FCiscounteroperating
frequency.
SID.TCPWM.5B PWM
RES
Minimum pulse width between
Quadrature phase inputs.
ns Delays from pins should be
similar. FC is counter
SID.TCPWM.5C
Q
Quadrature inputs resolution
2/Fc
–
–
RES
operating frequency.
Document Number: 002-33480 Rev. *E
Page 54 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Serial Communication Block (SCB)
Table 30. Serial Communication Block (SCB) Specifications
Spec ID#
Parameter
Description
Min Typ
Max
Units
Details / Conditions
2
Fixed I C DC Specifications
SID149
SID150
SID151
SID152
I
I
I
I
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
–
–
–
–
–
–
–
–
30
80
µA
µA
µA
–
–
–
I2C1
I2C2
I2C3
I2C4
180
1.7
2
I C enabled in Deep Sleep mode
µA At 60 °C.
2
Fixed I C AC Specifications
SID153
Fixed UART DC Specifications
F
Bit Rate
–
–
1
Mbps –
I2C1
Block current consumption at
100 kbps
–
–
–
–
30
µA
SID160
SID161
I
–
UART1
UART2
Block current consumption at
1000 kbps
180
µA
I
–
Fixed UART AC Specifications
SID162A
SID162B
F
F
–
–
–
–
3
8
Mbps ULP Mode
LP Mode
UART1
UART2
Bit Rate
Fixed SPI DC Specifications
SID163
SID164
SID165
SID165A
I
I
I
I
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
Block current consumption at 25 Mbps
–
–
–
–
–
–
–
–
220
340
360
800
µA
µA
µA
µA
–
–
–
–
SPI1
SPI2
SPI3
SP14
Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SPI Operating frequency externally
clocked slave
6.25-MHz max for ULP
(0.9 V) mode
–
–
–
25
MHz
MHz
SID166
F
F
F
SPI
F
max is 100 MHz in LP
–
Fscb/4
scb
SPI operating frequency master (F
is SPI clock).
scb
SID166B
(1.1 V) mode, 25 MHz in ULP
mode.
SPI_EXT
5 MHz max for ULP (0.9 V)
mode
–
–
15
MHz
SID166A
SPI slave internally clocked
SPI_IC
Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
20 ns max for ULP (0.9 V)
mode
–
–
–
–
–
–
12
–
ns
ns
ns
ns
ns
SID167
SID168
SID169
SID169A
SID169B
T
T
T
T
T
MOSI valid after SClock driving edge
DMO
MISO valid before SClock capturing
edge
Full clock, late MISO
sampling
5
DSI
Referred to Slave capturing
edge
0
–
MOSI data hold time
HMO
Referred to Master clock
edge
18
18
–
Valid to first SCK Valid edge
Hold after last SCK Valid edge
SSELMSCK1SSEL
SSELMCK2SSEL
Referred to Master clock
edge
–
Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
MOSI valid before Sclock capturing
edge
5
–
–
ns
SID170
T
–
DMI
Document Number: 002-33480 Rev. *E
Page 55 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 30. Serial Communication Block (SCB) Specifications (continued)
Spec ID#
SID171A
Parameter
Description
Min Typ
Max
Units
Details / Conditions
MISO valid after Sclock driving edge
in Ext. Clk. mode
35 ns max. for ULP (0.9 V)
mode
–
–
–
–
–
–
20
ns
T
T
DSO_EXT
MISO valid after Sclock driving edge
in Internally Clk. mode
Tscb is Serial Comm. Block
clock period.
TDSO_EXT ns
+ 3 * Tscb
SID171
DSO
MISO Valid after Sclock driving edge
in Internally Clk. Mode with median
filter enabled.
TDSO_EXT ns
+ 4 * Tscb
Tscb is Serial Comm. Block
clock period.
SID171B
T
T
DSO
SID172
Previous MISO data hold time
5
–
–
–
–
–
–
ns
ns
ns
–
–
–
HSO
SID172A
SID172B
TSSEL
TSSEL
SSEL Valid to first SCK valid edge
65
SCK1
SCK2
SSEL Hold after Last SCK valid edge 65
LCD Specifications
Table 31. LCD Direct Drive DC Specifications
Spec ID# Parameter
Description
Min
Typ Max Units
Details / Conditions
32X4 small display. 30 Hz.
µA PWM mode. Slow slew rate.
Operating current with 100 kHz LCD block
clock in ULP mode in Deep Sleep
SID154
I
I
–
–
–
90
50
LCDLOW1
460 k series resistors
Operating current with 32 kHz LCD block
clock in ULP mode in Deep Sleep
SID154A
–
µA
–
LCDLOW2
LCD capacitance per segment/common
driver
SID155
SID156
SID157
C
–
–
–
500 5000 pF
–
–
LCDCAP
LCD
I
Long-term segment offset
20
–
–
mV
mA
OFFSET
PWM Mode current.
32 × 4 segments
50 Hz
0.6
LCDOP1
LCDOP2
3.3 V bias. 8 MHz IMO. 25°C.
PWM Mode current.
32 × 4 segments
50 Hz
SID158
I
–
0.5
–
mA
3.3 V bias. 8 MHz IMO. 25°C.
Table 32. LCD Direct Drive AC Specifications
Spec ID Parameter Description
SID159 LCD frame rate
Min
Typ Max Units
50 150 Hz
Details/Conditions
F
10
–
LCD
Document Number: 002-33480 Rev. *E
Page 56 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Memory
Table 33. Flash DC Specifications[3]
Spec ID
SID173
SID173A
Parameter
VPE
IPE
Description
Erase and program voltage
Erase and program current
Min Typ Max
Units
V
Details/Conditions
Details/Conditions
1.71
–
–
–
3.6
6
–
–
mA
Table 34. Flash AC Specifications[3]
Spec ID
SID174
Parameter
Description
Row write time (erase and program)
Row erase time
Min Typ Max
Units
ms
T
T
T
T
T
T
–
–
–
–
–
–
–
–
–
–
–
–
16
11
5
Row = 512 bytes
ROWWRITE
ROWERASE
ROWPROGRAM
BULKERASE
SECTORERASE
SSERIAE
SID175
SID176
SID178
SID179
SID178S
ms
–
Row program time after erase
Bulk erase time (256 KB)
Sector erase time (128 KB)
Subsector erase time
ms
–
11
11
11
ms
–
ms
256 rows per sector
8 rows per subsector
ms
Subsector write time; 1 erase plus 8
program times
SID179S
SID180S
T
T
–
–
–
–
51
ms
–
[4]
SSWRITE
SWRITE
Sector write time; 1 erase plus 256 program
times
1.3 seconds –
2.6 seconds –
SID180
SID181
T
F
Total device write time
Flash endurance
–
–
–
DEVPROG
END
100K
–
cycles
–
Flash retention. T 25 °C, 100K P/E
cycles
A
SID182
F
10
–
–
years
–
RET1
SID182A
SID182B
SID256
F
F
T
T
Flash retention. T 85 °C, 10K P/E cycles 10
–
–
–
–
–
–
–
–
years
years
–
RET2
RET3
WS100
WS50
A
Flash retention. T 55 °C, 20K P/E cycles 20
–
A
Number of Wait states at 100 MHz
Number of Wait states at 50 MHz
3
2
LP mode (1.1 V)
ULP mode (0.9 V)
SID257
Notes
3. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
4. Subsector, sector, and device write times do not include data transfer overhead.
Document Number: 002-33480 Rev. *E
Page 57 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
System Resources
Power-on Reset
Table 35. Power-On-Reset (POR) with Brown-out Detect (BOD) DC Specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
BOD trip voltage in system LP and ULP
modes.
SID190
V
V
1.54
1.54
–
–
–
–
V
V
FALLPPOR
ResetguaranteedforV
below 1.54 V
levels
DDD
BOD trip voltage in system Deep Sleep
mode.
SID192
FALLDPSLP
Table 36. POR with BOD AC Specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
100 mV/µs System LP mode
10 mV/µs BOD operation guaranteed
Maximum power supply ramp rate (any
supply)
SID192A
V
V
–
–
–
–
DDRAMP
Maximum power supply ramp rate (any
supply) in system Deep Sleep mode
SID194A
DDRAMP_DS
Voltage Monitors
Table 37. Voltage Monitors DC Specifications
Parameter Description
Spec ID
SID195R
SID195
SID196
SID197
SID198
SID199
SID200
SID201
SID202
SID203
SID204
SID205
SID206
SID207
SID208
SID209
SID211
Min Typ Max Units
Details/Conditions
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
–
1.18 1.23 1.27
1.38 1.43 1.47
1.57 1.63 1.68
1.76 1.83 1.89
1.95 2.03 2.1
2.05 2.13 2.2
2.15 2.23 2.3
2.24 2.33 2.41
2.34 2.43 2.51
2.44 2.53 2.61
2.53 2.63 2.72
2.63 2.73 2.82
2.73 2.83 2.92
2.82 2.93 3.03
2.92 3.03 3.13
3.02 3.13 3.23
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
HVD0
–
HVDI1
HVDI2
HVDI3
HVDI4
HVDI5
HVDI6
HVDI7
HVDI8
HVDI9
HVDI10
HVDI11
HVDI12
HVDI13
HVDI14
HVDI15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
LVI_IDD
Block current
–
5
15
Table 38. Voltage Monitors AC Specification
Spec ID
Parameter
Description
Min Typ Max Units
170 ns
Details/Conditions
SID212
T
Voltage monitor trip time
–
–
–
MONTRIP
Document Number: 002-33480 Rev. *E
Page 58 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
SWD Interface
Table 39. SWD and Trace Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details / Conditions
SWD and Trace Interface
LP Mode.
MHz
SID214
F_SWDCLK2
F_SWDCLK2L
1.7 V V
1.7 V V
3.6 V
–
–
–
–
25
12
DDD
V
= 1.1 V.
CCD
ULP Mode.
SID214L
3.6 V
MHz
DDD
V
–
–
–
–
= 0.9 V.
CCD
SID215
SID216
SID217
SID217A
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
0.25 * T
–
–
–
–
–
ns
ns
ns
ns
0.25 * T
–
0.5 * T
–
–
1
With Trace Data setup/hold times of
2/1 ns respectively
SID214T
SID215T
SID216T
F_TRCLK_LP1
F_TRCLK_LP2
F_TRCLK_ULP
–
–
–
–
–
–
50
50
20
MHz LP Mode. V = 1.1 V.
DD
With Trace Data setup/hold times of
3/2 ns respectively
MHz LP Mode. V = 1.1 V.
DD
With Trace Data setup/hold times of
3/2 ns respectively
MHz ULP Mode. V = 0.9 V.
DD
Internal Main Oscillator
Table 40. IMO DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID218
I
IMO operating current at 8 MHz
–
9
15
µA
–
IMO1
Table 41. IMO AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–40 to + 85 °C
–
–
±1
%
Frequency variation centered on
8 MHz
–40 to + 105 °C
SID223
F
T
IMOTOL1
–
–
–
±1.5
–
%
For extended industrial
temp MPNs
SID227
Cycle-to-Cycle and Period jitter
250
ps
–
JITR
Internal Low-Speed Oscillator
Table 42. ILO DC Specification
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID231
I
ILO operating current at 32 kHz
–
0.3
0.7
µA
–
ILO2
Table 43. ILO AC Specifications
Spec ID
Parameter
Description
ILO startup time
Min
Typ
Max
Units
Details/Conditions
Startup time to 95% of
final frequency
SID234
T
–
–
7
µs
STARTILO1
SID236
SID237
TLIODUTY
ILO Duty cycle
ILO frequency
45
50
32
55
%
–
F
28.8
35.2
kHz
Factory trimmed
ILOTRIM1
Document Number: 002-33480 Rev. *E
Page 59 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
FLL Specifications
Table 44. Frequency Locked Loop (FLL) Specifications
Spec ID#
Parameter
Description
Input frequency range.
Output frequency range.
Min
Typ
Max
Units
Details / Conditions
Lower limit allows lock to
USB SOF signal (1 kHz).
Upper limit is for External
input.
0.001
–
100
MHz
SID450
FLL_RANGE
Output range of FLL
divided-by-2 output
24.00
24.00
–
–
100.00
50.00
MHz
MHz
SID451
FLL_OUT_DIV2
V
= 1.1 V
CCD
Output frequency range.
= 0.9 V
Output range of FLL
divided-by-2 output
SID451A
SID452
FLL_OUT_DIV2
FLL_DUTY_DIV2
V
CCD
Divided-by-2 output; High or Low
47.00
–
–
–
53.00
7.50
%
–
With IMO input, less than
10 °C change in
temperature while in Deep
Sleep, and Fout ≥ 50 MHz.
µs
Time from stable input clock to 1% of
final value on Deep Sleep wakeup
SID454
FLL_WAKEUP
50 ps at 48 MHz, 35 ps at
100 MHz
–
–
–
–
35.00
5.50
ps
SID455
SID456
FLL_JITTER
Period jitter (1 sigma) at 100 MHz
CCO + Logic current
FLL_CURRENT
µA/MHz –
Crystal Oscillator Specifications
Table 45. ECO Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
MHz ECO DC Specifications
Max at 35 MHz.
Typ at 16 MHz.
Block operating current with Cload up to
18 pF
SID316
MHz ECO AC Specifications
SID317 F_MHz
I
–
800
–
1600
35
µA
DD_MHz
Some restrictions apply.
Refer to the device TRM
Crystal frequency range
16
MHz
kHz ECO DC Specifications
SID318
I
Block operating current with 32-kHz crystal
Equivalent series resistance
Drive level
–
–
–
0.38
80
–
1
–
1
µA
kΩ
–
–
–
DD_kHz
SID321E ESR32K
SID322E PD32K
µW
kHz ECO AC Specifications
SID319
SID320
F_kHz
32-kHz frequency
Startup time
–
–
32.77
–
–
kHz
ms
–
–
Ton_kHz
1000
May be calibrated to
sub-10 ppm levels
SID320E
F
Frequency tolerance
–
50
250
ppm
TOL32K
External Clock Specifications
Table 46. External Clock Specifications
Spec ID
SID305
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Min 200 kHz for 32 kHz
clock operation
0
–
100
MHz
EXTCLK
External clock input frequency
FREQ
DUTY
SID306
EXTCLK
Duty cycle; measured at V /2
45
–
55
%
–
DD
Document Number: 002-33480 Rev. *E
Page 60 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
PLL Specifications
Table 47. PLL Specifications
Spec ID
Parameter
Description
Input frequency to PLL block
Time to achieve PLL lock
Output frequency from PLL block
PLL current
Min
Typ
–
Max
64
Units
MHz
µs
Details/Conditions
SID304P PLL_IN
4
SID305P PLL_LOCK
SID306P PLL_OUT
SID307P PLL_IDD
–
16
–
35
–
–
10.625
150
1.1
150
MHz
–
–
0.55
–
mA Typ at 100 MHz out.
ps
100-MHz output
frequency
SID308P PLL_JTR
Period jitter
Clock Source Switching Times
Table 48. Clock Source Switching Time Specifications
Spec ID
Parameter
TCLK
Description
Min
Typ
Max
Units
Details/Conditions
Clock switching from clk1 to clk2 in clock
4 clk1 +
3 clk2
SID262
–
–
periods –
[5]
SWITCH
periods
USB
Table 49. USB Specifications (USB requires LP Mode 1.1-V internal supply)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
USB Block Specifications
USB Configured, USB
Reg. bypassed
SID322U
Vusb_3.3
Device supply for USB operation
3.15
–
3.6
V
Device supply for USB operation
(functional operation only)
USB Configured, USB
Reg. bypassed
SID323U
SID325U
SID328
Vusb_3
2.85
–
–
8
3.6
–
V
Iusb_config
Iusb_suspend
Block supply current in Active mode
mA
mA
V
V
= 3.3 V
DDD
= 3.3 V, Device
DDD
Block supply current in suspend mode
–
0.5
–
connected
V
= 3.3 V, Device
DDD
SID329
Iusb_suspend
Block supply current in suspend mode
–
0.3
–
mA
disconnected
Series resistors are on
chip
SID330U
SID332U
SID333U
USB_Drive_Res
USB_Pullup_Idle
USB_Pullup
USB driver impedance
Idle mode range
Active mode
28
–
–
–
44
Ω
Ω
Ω
900
1575
3090
Bus idle
Upstream device trans-
mitting
1425
QSPI
Table 50. QSPI Specifications
Spec ID# Parameter
Description
Min
Typ
Max
Units Details / Conditions
SMIF QSPI Specifications. All specs with 15-pF load.
SID390Q
SID390QU
SID399Q
SID397Q
SID398Q
Fsmifclock
Fsmifclocku
Clk_dutycycle
Idd_qspi
SMIF QSPI output clock frequency
SMIF QSPI output clock frequency
Clock duty cycle (high or low time)
Block current in LP mode (1.1 V)
Block current in ULP mode (0.9 V)
–
–
–
–
–
–
–
80
50
MHz LP mode (1.1 V)
MHz ULP mode (0.9 V)
%
45
–
55
1900
590
µA
µA
LP mode (1.1 V)
ULP mode (0.9 V)
Idd_qspi_u
–
Note
5. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 4) then clk1 is the IMO and clk2 is the FLL.
Document Number: 002-33480 Rev. *E
Page 61 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Table 50. QSPI Specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Units Details / Conditions
Input data set-up time with respect to
clock capturing edge
SID391Q
Tsetup
4.5
–
–
ns
Input data hold time with respect to clock
capturing edge
SID392Q
SID393Q
SID394Q
SID395Q
SID396Q
Tdatahold
0
–
–
–
–
–
–
–
3.7
–
ns
ns
ns
ns
ns
–
Output data valid time with respect to
clock falling edge
7.5-ns max for ULP
mode (0.9 V)
Tdataoutvalid
Tholdtime
Output data hold time with respect to
clock rising edge
3
–
Output Select valid time with respect to
clock rising edge
15-ns max for ULP
mode (0.9 V)
Tseloutvalid
Tselouthold
–
7.5
–
Tsclk = Fsmifclk cycle
time
Output Select hold time with respect to
clock rising edge
Tsclk
Smart I/O
Table 51. Smart I/O Subsystem Specifications
Spec ID#
SID420
SID421
Parameter
SMIO_BYP
SMIO_LUT
Description
Smart I/O bypass delay
Min
–
Typ
–
Max
2
Units
ns
Details/Conditions
–
–
Smart I/O LUT prop delay
–
8
–
ns
JTAG Boundary Scan
Table 52. JTAG Boundary Scan
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:
SID468
SID469
SID470
SID471
SID472
T
TCK LOW
52
10
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
–
CKLOW
TCKHIGH
TCK_TDO
TSU_TCK
TCk_THD
TCK HIGH
–
–
–
–
TCK falling edge to output valid
Input valid to TCK rising edge
Input hold time to TCK rising edge
40
–
12
10
40
–
TCK falling edge to output valid (High-Z
to Active).
–
SID473
SID474
TCK_TDOV
TCK_TDOZ
–
–
TCK falling edge to output valid (Active to
High-Z).
40
–
–
ns
JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:
SID468A
SID469A
SID470A
SID471A
SID472A
TCKLOW
TCKHIGH
TCK_TDO
TSU_TCK
TCk_THD
TCK low
102
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
–
–
–
–
–
TCK high
TCK falling edge to output valid
Input valid to TCK rising edge
Input hold time to TCK rising edge
80
–
22
20
80
–
TCK falling edge to output valid (high-Z to
active).
–
SID473A
SID474A
TCK_TDOV
TCK_TDOZ
–
–
TCK falling edge to output valid (active to
high-Z).
80
–
–
ns
Document Number: 002-33480 Rev. *E
Page 62 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Ordering Information
Table 53 lists the CY8C61x4 part numbers and features. All devices include dual CPU, DMA, DC-DC converter, QSPI SMIF, DAC,
LPCOMP, 6 SCBs, and 12 TCPWMs. See also the product selector guide.
Table 53. Ordering Information
Arm CM4,
5x SCBs, 1x
DS-SCB, 1x
FS-USB, 1x
Q-SPI, 2x
CY8C6144AZI-S4F92
CY8C6144LQI-S4F92
CY8C6144AZI-S4F93
CY8C6144AZI-S4F82
CY8C6144LQI-S4F82
CY8C6144AZI-S4F83
CY8C6144AZI-S4F62
CY8C6144LQI-S4F62
CY8C6144AZI-S4F12
CY8C6144LQI-S4F12
CY8C6144AZQ-S4F92
CY8C6144LQQ-S4F92
CY8C6144AZQ-S4F93
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 1x 12-bit
150/50 FLEX 256 128 1x 12-bit
150/50 FLEX 256 128 1x 12-bit
150/50 FLEX 256 128 1x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
150/50 FLEX 256 128 2x 12-bit
2
2
2
2
2
2
-
Y
Y
Y
Y
Y
Y
-
-
Y
-
1
1
1
-
Y 54 64-TQFP A2
Y 52 68-QFN A2
Y 62 80-TQFP A2
Y 54 64-TQFP A2
Y 52 68-QFN A2
Y 62 80-TQFP A2
- 54 64-TQFP A2
- 52 68-QFN A2
- 54 64-TQFP A2
- 52 68-QFN A2
Y 54 64-TQFP A2
Y 52 68-QFN A2
Y 62 80-TQFP A2
-
Comp, LCD
Y
-
-
-
-
1
1
-
-
-
Y
-
-
Y
Y
Y
Y
Y
-
Y
-
-
2
2
2
1
1
1
Y
-
Note: In PSoC 61 the Cortex M0+ is reserved for system functions, and is not available for applications. In LP and ULP modes, the
maximum CM0+ CPU operating frequency is restricted to 100 MHz and 25 MHz respectively.
PSoC 6 MPN Decoder
CY XX 6 A B C DD E - FF G H I JJ K L
Field
Description
Values
Meaning
CY
Cypress
CY
8C
B0
S0
6
Cypress
Standard
XX
6
Firmware
“Secure Boot” v1
“Standard Secure” - AWS
PSoC 6
Architecture
0
Value
1
Programmable
Performance
Connectivity
Security
A
Line
2
3
4
Document Number: 002-33480 Rev. *E
Page 63 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Field
Description
Values
Meaning
2
100 MHz
150 MHz
150/50 MHz
RFU
B
Speed
3
4
0-3
4
256K/128K
512K/256K
512K/128K
1024K/288K
1024K/512K
RFU
5
6
7
Memory Size
(Flash/SRAM)
C
8
9
A
2048K/1024K
TQFP
AZ, AX
LQ
BZ
FM
QFN
DD
Package
BGA
M-CSP
FN, FD, FT WLCSP
C
I
Consumer
Industrial
E
Temperature Range
Feature Code
Q
Extended Industrial
Cypress internal
FF
S2-S6
BL
F
Integrated Bluetooth Low Energy
Single Core
Dual Core
Feature set
31-50
G
H
CPU Core
D
Attributes Code
0–9
1
2
51-70
I
GPIO count
3
71-90
4
91-110
Engineering sample
(optional)
JJ
K
ES
Engineering samples or not
Base
Die Revision (optional)
A1-A9
T
Die revision
Tape/Reel Shipment
(optional)
L
Tape and Reel shipment
Document Number: 002-33480 Rev. *E
Page 64 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Packaging
This product line is offered in 80-TQFP, 64-E-TQFP, and 68-QFN packages.
Table 54. Package Dimensions
Spec ID#
PKG_1
PKG_2
PKG_3
Package
Description
Package Dwg #
002-29467
80-TQFP
80-TQFP, 12 × 12 × 1.6 mm
64-E-TQFP 64-E-TQFP, 10 × 10 × 1.6 mm
68-QFN
68 QFN 8 × 8 × 1 mm
002-29202
001-96836
Table 55. Package Characteristics
Parameter Description
Conditions
Min
–40
–40
–40
–40
–
Typ
25
25
–
Max
85
105
100
120
–
Units
°C
T
T
T
T
T
T
T
T
T
T
Operating ambient temperature
Extended Industrial temperature
Operating junction temperature
Extended Industrial temperature
–
–
–
–
–
–
–
–
–
–
A
°C
A
°C
J
–
°C
J
Package (80-TQFP)
35
6
°C/watt
°C/watt
°C/watt
°C/watt
°C/watt
°C/watt
JA
JC
JA
JC
JA
JC
JA
Package (80-TQFP)
–
–
JC
Package (64-E-TQFP)
–
26
7
–
JA
Package (64-E-TQFP)
–
–
JC
Package (68-QFN)
–
21
6
–
JA
Package (68-QFN)
–
–
JC
Table 56. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All packages
260 °C
30 seconds
Table 57. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
All packages
MSL3
Document Number: 002-33480 Rev. *E
Page 65 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 20. 68 QFN 8 × 8 × 1 mm
001-96836 *A
Document Number: 002-33480 Rev. *E
Page 66 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 21. 80-TQFP 12.0 × 12.0 × 1.6 mm
002-29467 **
Document Number: 002-33480 Rev. *E
Page 67 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Figure 22. 64-TQFP 10.0 × 10.0 × 1.6 mm
002-29202 **
Document Number: 002-33480 Rev. *E
Page 68 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Acronyms
Acronym
EMI
Description
electromagnetic interference
embedded MultiMediaCard
electrostatic discharge
embedded trace macrocell
first-in, first-out
Acronym
3DES
Description
triple DES (data encryption standard)
analog-to-digital converter
eMMC
ESD
ETM
FIFO
FLL
ADC
advanced DMA version 3, a Secured Digital data
transfer mode
ADMA3
AES
advanced encryption standard
frequency locked loop
floating-point unit
AMBA(advanced microcontroller bus architecture)
high-performance bus, an Arm data transfer bus
AHB
FPU
FS
full-speed
AMUX
AMUXBUS
API
analog multiplexer
GND
Ground
analog multiplexer bus
general-purpose input/output, applies to a PSoC
pin
application programming interface
advanced RISC machine, a CPU architecture
ball grid array
GPIO
®
Arm
HMAC
HSIOM
I/O
Hash-based message authentication code
high-speed I/O matrix
BGA
BOD
brown-out detect
input/output, see also GPIO, DIO, SIO, USBIO
Inter-Integrated Circuit, a communications protocol
inter-IC sound
BREG
BWC
CAD
backup registers
2
I C, or IIC
backward compatibility (eMMC data transfer mode)
computer aided design
2
I S
IC
integrated circuit
CCO
current controlled oscillator
a stream cipher
IDAC
IDE
ILO
current DAC, see also DAC, VDAC
integrated development environment
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input output subsystem
ChaCha
CM0+
CM4
Cortex-M0+, an Arm CPU
Cortex-M4, an Arm CPU
IMO
INL
CMAC
cypher-based message authentication code
complementary metal-oxide-semiconductor, a
process technology for IC fabrication
CMOS
IOSS
IoT
internet of things
CMRR
CPU
common-mode rejection ratio
central processing unit
IPC
IRQ
ISR
ITM
JTAG
LCD
inter-processor communication
interrupt request
cyclic redundancy check, an error-checking
protocol
CRC
interrupt service routine
CSD
CSV
CapSense Sigma-Delta
clock supervisor
instrumentation trace macrocell
Joint Test Action Group
Cypress mutual capacitance sensing method. See
also CSD
liquid crystal display
CSX
Local Interconnect Network, a communications
protocol
LIN
CTI
cross trigger interface
DAC
DAP
DDR
DES
DFT
DMA
DNL
DSI
digital-to-analog converter, see also IDAC, VDAC
debug access port
LP
low power
LS
low-speed
double data rate
LUT
lookup table
data encryption standard
design for test
LVD
low-voltage detect, see also LVI
low-voltage interrupt
low-voltage transistor-transistor logic
multiply-accumulate
LVI
direct memory access, see also TD
differential nonlinearity, see also INL
digital system interconnect
data unit
LVTTL
MAC
MCU
MCWDT
MISO
MMIO
MOSI
MPU
MSL
Msps
microcontroller unit
DU
multi-counter watchdog timer
master-in slave-out
DW
data wire, a DMA implementation
error correcting code
ECC
ECC
ECO
memory-mapped input output
master-out slave-in
elliptic curve cryptography
external crystal oscillator
memory protection unit
moisture sensitivity level
million samples per second
electrically erasable programmable read-only
memory
EEPROM
Document Number: 002-33480 Rev. *E
Page 69 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Acronym
MTB
Description
Acronym
SMPU
Description
shared memory protection unit
signal-to-noise ration
micro trace buffer
multiplier
MUL
NC
SNR
SOF
no connect
start of frame
silicon-oxide-nitride-oxide-silicon, a flash memory
technology
NMI
nonmaskable interrupt
SONOS
SPI
NVIC
NVL
nested vectored interrupt controller
nonvolatile latch, see also WOL
one-time programmable
over voltage protection
overvoltage tolerant
Serial Peripheral Interface, a communications
protocol
OTP
OVP
OVT
PASS
PCB
PCM
PDM
PHY
PICU
PLL
SRAM
SROM
SRSS
SWD
SWJ
static random access memory
supervisory read-only memory
system resources subsystem
serial wire debug, a test protocol
serial wire JTAG
programmable analog subsystem
printed circuit board
pulse code modulation
SWO
SWV
TCPWM
TDM
single wire output
pulse density modulation
physical layer
single-wire viewer
timer, counter, pulse-width modulator
time division multiplexed
total harmonic distortion
thin quad flat package
port interrupt control unit
phase-locked loop
THD
PMIC
POR
PPU
PRNG
power management integrated circuit
power-on reset
TQFP
TRM
technical reference manual
true random number generator
transmit
peripheral protection unit
pseudo random number generator
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
TRNG
TX
®
PSoC
PSRR
PWM
QD
universal asynchronous transmitter receiver, a
communications protocol
UART
UDB
ULP
universal digital block
ultra-low power
quadrature decoder
QSPI
RAM
RISC
RMS
ROM
quad serial peripheral interface
random-access memory
reduced-instruction-set computing
root-mean-square
USB
Universal Serial Bus
watch crystal oscillator
watchdog timer
WCO
WDT
WIC
wakeup interrupt controller
wafer level chip scale package
execute-in-place
read-only memory
WLCSP
XIP
Rivest–Shamir–Adleman, a public-key cryptog-
raphy algorithm
RSA
XRES
external reset input pin
RTC
real-time clock
RWW
RX
read-while-write
receive
S/H
sample and hold
SAR
successive approximation register
SAR ADC multiplexer bus
switched capacitor/continuous time
serial communication block
SARMUX
SC/CT
SCB
2
SCL
I C serial clock
SD
Secured Digital
2
SDA
I C serial data
SDHC
SDR
Secured Digital host controller
single data rate
Sflash
SHA
supervisory flash
secure hash algorithm
signal to noise and distortion ratio
SINAD
Document Number: 002-33480 Rev. *E
Page 70 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Document Conventions
Table 58. Units of Measure (continued)
Symbol Unit of Measure
µH
Units of Measure
Table 58. Units of Measure
microhenry
microsecond
microvolt
Symbol
°C
Unit of Measure
µs
degrees Celsius
decibel
µV
µW
mA
ms
mV
nA
ns
dB
microwatt
milliampere
millisecond
millivolt
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
khr
kilobits per second
kilohour
nanoampere
nanosecond
nanovolt
kHz
k
kilohertz
nV
W
kilo ohm
ohm
ksps
LSB
Mbps
MHz
M
Msps
µA
kilosamples per second
least significant bit
megabits per second
megahertz
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
mega-ohm
sps
sqrtHz
V
samples per second
square root of hertz
volt
megasamples per second
microampere
microfarad
µF
Document Number: 002-33480 Rev. *E
Page 71 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Revision History
Description Title: PSoC 6 MCU: CY8C61x4 Datasheet
Document Number: 002-33480
Submission
Revision
ECN
Description of Change
Date
**
7167054
06/22/2021 New datasheet.
Removed the errata section.
*A
*B
7209916
7269159
08/04/2021 Updated values for SIDHIB2, SID13, SID14, SID17A, SID15, SIDP122, SIDP123, and
SID313_3A.
Added extended industrial temperature specs in Opamp Specifications, Temperature
Sensor Specifications, and IMO AC Specifications.
Added extended industrial temperature MPNs in Ordering Information
Updated the analog subsystem diagram.
09/01/2021
11/26/2021
Updated CPU current values in Features.
Added note regarding unused USB pins in USB Full-Speed Device Interface, Power Supply
Considerations, and Pinouts.
*C
7452981
Updated SIDC1 description.
Updated details/conditions for SID7A.
Updated SID325U, SID328, and SID329 description.
Updated Figure 17.
*D
*E
7750278
7789060
04/12/2022 Updated eFuse description in the Memory section.
Added device identification and revision information in Features.
Added spec SID304P.
10/18/2022
Updated PLL Specifications and Clock System.
Updated Protection Units.
Document Number: 002-33480 Rev. *E
Page 72 of 73
PSoC 6 MCU: CY8C61x4
Datasheet
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation,2021-2022. This document is the property of Cypress Semiconductor Corporation, an Infineon Technologies company, and its affiliates ("Cypress"). This
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Document Number: 002-33480 Rev. *E
Revised October 18, 2022
Page 73 of 73
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