CY8C9520A-24PVXI [INFINEON]
CY8C95xx;
| 型号： | CY8C9520A-24PVXI |
| 厂家： | 
Infineon |
| 描述： | CY8C95xx |
| 文件： | 总32页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C9520A
CY8C9540A
CY8C9560A
20-, 40-, and 60-Bit I/O Expander
with EEPROM
Features
Overview
■ I2C interface logic electrically compatible with SMBus
The CY8C95xxA is a multi-port I/O expander with on board user
available EEPROM and several PWM outputs. All devices in this
family operate identically but differ in I/O pins, number of PWMs,
and internal EEPROM size.
The CY8C95xxA operates as two I2C slave devices. The first
device is a multi port I/O expander (single I2C address to access
all ports through registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to
disable the EEPROM. The EEPROM uses 2-byte addressing to
support the 28 Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
■ Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)
I/O data pins independently configurable as inputs, outputs,
Bi-directional input/outputs, or PWM outputs
■ 4/8/16 PWM sources with 8-bit resolution
■ Extendable soft addressing algorithm allowing flexible I2C
address configuration
■ Internal 3-/11-/27-Kbyte EEPROM
■ User default storage, I/O port settings in internal EEPROM
■ Optional EEPROM write disable (WD) input
The I/O expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.
The individual data pins can be configured as open drain or
collector, strong drive (10 mA source, 25 mA sink), resistively
pulled up or down, or high impedance. The factory default
configuration is pulled up internally.
■ Interrupt output indicates input pin level changes and pulse
width modulator (PWM) state changes
■ Internal power on reset (POR)
■ Internal configurable watchdog timer
The system master writes to the I/O configuration registers
through the I2C bus. Configuration and output register settings
are storable as user defaults in a dedicated section of the
EEPROM. If user defaults were stored in EEPROM, they are
restored to the ports at power up. While this device can share the
bus with SMBus devices, it can only communicate with I2C
masters. The I2C slave in this device requires that the I2C master
supports clock stretching.
Top Level Block Diagram
WD
EEPROM
User
Settings
Area
User
Available
Area
There is one dedicated pin that is configured as an interrupt
output (INT) and can be connected to the interrupt logic of the
system master. This signal can inform the system master that
there is incoming data on its ports or that the PWM output state
was changed.
Clocks
32 kHz
24 MHz
GPort 0
GPort 1
GPort 2
GPort 3
8 Bit IO
5 Bit IO
1.5 MHz
The EEPROM is byte readable and supports byte-by-byte
writing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The
configuration registers can also disable EEPROM operations.
3 Bit IO
or A4-A6
93.75 kHz
4 Bit IO
or A1-A3, WD6
Divider (1-255)
The CY8C95xxA has one fixed address pin (A0) and up to six
additional pins (A1-A6), which allow up to 128 devices to share
a common two wire I2C data bus. The Extendable Soft
Addressing algorithm provides the option to choose the number
of pins needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
Control
Unit
PWM 0
8 Bit IO
8 Bit IO
PWM 15
GPort 7
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)
independently configurable 8-bit PWMs. These PWMs are listed
as PWM0-PWM15. Each PWM can be clocked by one of six
available clock sources.
SCL
SDA
INT
A0
Vdd
Vss
Power-on-Reset
Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-12036 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 1, 2015
CY8C9520A
CY8C9540A
CY8C9560A
Contents
Architecture ......................................................................3
Applications .................................................................3
Device Access Addressing ..............................................4
Serial EEPROM Device ...............................................4
Multi Port I/O Device ...................................................4
Pinouts ..............................................................................5
28-Pin Part Pinout .......................................................5
48-Pin Part Pinout .......................................................6
100-Pin Part Pinout .....................................................7
Pin Descriptions ...............................................................9
Extendable Soft Addressing ........................................9
Interrupt Pin (INT) ........................................................9
Write Disable Pin (WD) ...............................................9
External Reset Pin (XRES) .........................................9
Working with PWMs ....................................................9
Register Mapping Table .................................................11
Register Descriptions ....................................................11
Input Port Registers (00h–07h) .................................11
Output Port Registers (08h–0Fh) ..............................11
Int. Status Port Registers (10h–17h) .........................12
Port Select Register (18h) .........................................12
Interrupt Mask Port Register (19h) ............................12
Select PWM Register (1Ah) ......................................12
Inversion Register (1Bh) ............................................12
Port Direction Register (1Ch) ....................................12
Drive Mode Registers (1Dh–23h) ..............................12
PWM Select Register (28h) .......................................12
Config (29h) ...............................................................13
Period Register (2Ah) ................................................13
Pulse Width Register (2Bh) .......................................13
Divider Register (2Ch) ...............................................13
Enable Register (2Dh) ...............................................13
Device ID/Status Register (2Eh) ...............................13
Watchdog Register (2Fh) ..........................................14
Command Register (30h) ..........................................14
Commands Description .................................................14
Store Config to E2 POR Defaults Cmd (01h) ............14
Restore Factory Defaults Cmd (02h) .........................14
Write E2 POR Defaults Cmd (03h) ............................14
Read E2 POR Defaults Cmd (04h) ...........................15
Write Device Config Cmd (05h) .................................15
Read Device Config Cmd (06h) ................................15
Reconfigure Device Cmd (07h) .................................15
Electrical Specifications ................................................16
Absolute Maximum Ratings .......................................16
Operating Temperature .............................................16
DC Electrical Characteristics .....................................17
AC Electrical Characteristics .....................................19
Packaging Dimensions ..................................................21
Thermal Impedances .................................................23
Solder Reflow Specifications .....................................23
Features and Ordering Information ..............................24
Ordering Code Definitions .........................................24
Acronyms ........................................................................25
Reference Documents ....................................................25
Document Conventions .................................................25
Units of Measure .......................................................25
Numeric Conventions ....................................................25
Numeric Naming ........................................................25
Glossary ..........................................................................26
Errata ...............................................................................30
Part Numbers Affected ..............................................30
Qualification Status ...................................................30
Errata Summary ........................................................30
Document History Page .................................................31
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products ....................................................................32
PSoC® Solutions ......................................................32
Cypress Developer Community .................................32
Technical Support .....................................................32
Document Number: 38-12036 Rev. *I
Page 2 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Figure 1. Logical Structure of the I/O Port
Architecture
The Top Level Block Diagram on page 1 illustrates the device
block diagram. The main blocks include the control unit, PWMs,
EEPROM, and I/O ports. The control unit executes commands
received from the I2C bus and transfers data between other bus
devices and the master device.
GPortx
7 Drive Mode
Registers
The on chip EEPROM can be separated conventionally into two
regions. The first region is designed to store data and is available
for byte wide read/writes through the I2C bus. It is possible to
prevent write operations by setting the WD pin to high. All
EEPROM operations can be blocked by configuration register
settings. The second region allows the user to store the port and
PWM default settings using special commands. These defaults
are automatically reloaded and processed after device power on.
Output
Register
DriveMode
Pull-Up
Data
DriveMode
High Z
PWMs
Select PWM
The number of I/O lines and PWM sources are listed in the
following table.
Interrupt
Status
Table 1. GPIO Availability
Input Register
8 Bit IO
Port
CY8C9520A CY8C9540A CY8C9560A
Interrupt
Mask
GPort 0
GPort 1
GPort 2
GPort 3
GPort 4
GPort 5
GPort 6
GPort 7
PWMs
8 bit
5-8 bit[1]
0-4 bit[1]
8 bit
5-8bit[1]
0-4it[1]
8 bit
8 bit
4 bit
–
8 bit
5-8 bit[1]
0-4 bit[1]
8 bit
Pin Direction
Inversion
–
–
–
–
–
4
8 bit
8 bit
The Port Input and Output registers are separated. When the
Output register is written, the data is sent to the external pins.
When the Input register is read, the external pin logic levels are
captured and transferred. As a result, the read data can be
different from written Output register data. This enables imple-
mentation of a quasi-bidirectional input-output mode, when the
corresponding binary digit is configured as pulled up/down
output.
8 bit
–
8 bit
8
16
There are four pins on GPort 2 and three on GPort 1 that can be
used as general purpose I/O or EEPROM Write Disable (WD)
and I2C-address input (A1-A6), depending on configuration
settings.
Each port has an Interrupt Mask register and an Interrupt Status
register. Each high bit in the Interrupt Status register signals that
there has been a change in the corresponding input line since
the last read of that Interrupt Status register. The Interrupt Status
register is cleared after each read. The Interrupt Mask register
enables/disables activation of the INT line when input levels are
changed. Each high in the Interrupt Mask register masks
(disables) an interrupt generated from the corresponding input
line.
Figure 1 shows the single port logical structure. The Port Drive
Mode register gives the option to select one of seven available
modes for each pin separately: pulled up/down, open drain
high/low, strong drive fast/slow, or high impedance. By default
these configuration registers store values setting I/O pins to be
pulled up. The Invert register enables inversion of the logic of the
Input registers separately for each pin. The Select PWM register
assigns pins as PWM outputs. All of these configuration registers
are read/writable using corresponding commands in the
multi-port device.
Applications
Each GPIO pin can be used to monitor and control various board
level devices, including LEDs and system intrusion detection
devices.
The on board EEPROM can be used to store information such
as error codes or board manufacturing data for read-back by
application software for diagnostic purposes.
Note
1. This port contains configuration-dependant GPIO lines or A1-A6 and WD lines.
Document Number: 38-12036 Rev. *I
Page 3 of 32
CY8C9520A
CY8C9540A
CY8C9560A
To read one or more bytes, the master device addresses the unit
with a write cycle (= 0) to send AHI followed by ALO, readdresses
the unit with a read cycle (= 1), and reads one or more data bytes.
Each data byte read increments the internal address counter by
one up to the end of the EEPROM address space. A read or write
beyond the end of the EEPROM address space must result in a
NAK response by the Port Expander.
Device Access Addressing
Following a start condition, the I2C master device sends a byte
to address an I2C slave. This address accesses the device in the
CY8C95xx. By default there are two possible address formats in
binary representation: 010000A0X and 101000A0X. The first is
used to access the multi port device and the second to access
the EEPROM. If additional address lines (A1-A6) are used then
the Device Addressing. Table 2 defines the device addresses.
This addressing method uses a technique called Extendable Soft
Addressing, described in the section Extendable Soft
Addressing on page 9.
To write data to the EEPROM, the master device performs one
write cycle, with the first two bytes being AHI followed by ALO.
This is followed by one or more data bytes. In the case of block
writing it is advisable to set the starting address on the beginning
of the 64-byte boundary, for example 01C0h or 0080h, but this is
not mandatory. When a 64-byte boundary is crossed in the
EEPROM, the I2C clock is stretched while the device performs
an EEPROM write sequence. If the end of available EEPROM
space is reached, then further writes are responded to with a
NAK.
Table 2. Device Addressing
Multi-Port Device
EEPROM Device
01
0
0
0
0
0
0
0
0
0
0
0
A
A
A
A
A
A
A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
A
A
A
A
A
A
A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
A
A
1
1
1
1
1
1
1
1
1
1
1
1
Refer to Figure 6 on page 10, which illustrates memory reading
and writing procedures for the EEPROM device.
0
A
A
A
A
A
A
A
A
A
A
A
A
2
2
2
2
2
2
2
2
2
2
0
A
A
A
A
A
A
A
A
A
A
3
3
3
3
3
3
3
3
Multi Port I/O Device
0
A
A
A
A
A
A
A
A
4
4
4
4
4
4
0
A
A
A
A
A
A
This device allows the user to set configurations and I/O
operations through internal registers.
5
5
5
5
A
6
A
A
A
6
Each data transfer is preceded by the command byte. This byte
is used as a pointer to a register that receives or transmits data.
Available registers are listed in Table 6 on page 11.
When all address lines A1-A6 are used, the device being
accessed is defined by the first byte following the address in the
write transaction. If the most significant bit (MSb) of this byte is
‘0’, this byte is treated as a command (register address) byte of
the multi-port device. If the MSb is ‘1’, this byte is the first of a
2-byte EEPROM address. In this case, the device masks the
MSb to determine the EEPROM address.
Serial EEPROM Device
EEPROM reading and writing operations require 2 bytes, AHI
and ALO, which indicate the memory address to use.
Document Number: 38-12036 Rev. *I
Page 4 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Pinouts
The CY8C95xxA device is available in a variety of packages, which are listed and illustrated in the following tables.
28-Pin Part Pinout
Table 3. 28-Pin Part Pinout (SSOP)
Pin
No.
Figure 2. CY8C9520A 28-Pin Device
Pin Name
Description
1
GPort0_Bit0_PWM3
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
Port 0, Bit 0, PWM 3.
GPort0_Bit0_PWM3
Vdd
2
Port 0, Bit 1, PWM 1.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 3.
Port 0, Bit 5, PWM 1.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Ground connection.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
Vss
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
GPort1_Bit0_PWM2
GPort1_Bit1_PWM0
GPort1_Bit2_PWM2
GPort1_Bit3_PWM0
GPort1_Bit4_PWM2
GPort1_Bit5_PWM0/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
XRES
3
4
5
6
7
8
SSOP
9
V
SS
2
2
10 I C Serial Clock (SCL)
2
I C Clock.
2
11
I C Serial Data (SDA)
I C Data.
GPort2_Bit0_PWM2/A3
GPort2_Bit1_PWM0/A2
INT
12 GPort2_Bit3_PWM3/A1
13 A0
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
14
V
Ground connection.
SS
Vss
GPort2_Bit2_PWM0/WD
2
15 GPort2_Bit2_PWM0/WD
16 INT
Port 2, Bit 2, PWM 0, E Write Disable.
17 GPort2_Bit1_PWM0/A2
18 GPort2_Bit0_PWM2/A3
Port 2, Bit 1, PWM 0, Address 2.
Port 2, Bit 0, PWM 2, Address 3.
19 XRES
Active high external reset with internal pull
down.
20 GPort1_Bit7_PWM0/A4
21 GPort1_Bit6_PWM2/A5
22 GPort1_Bit5_PWM0/A6
23 GPort1_Bit4_PWM2
24 GPort1_Bit3_PWM0
25 GPort1_Bit2_PWM2
26 GPort1_Bit1_PWM0
27 GPort1_Bit0_PWM2
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 0, Address 6.
Port 1, Bit 4, PWM 2.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 0.
Port 1, Bit 0, PWM 2.
28
V
Supply voltage.
dd
Document Number: 38-12036 Rev. *I
Page 5 of 32
CY8C9520A
CY8C9540A
CY8C9560A
48-Pin Part Pinout
Table 4. 48-Pin Part Pinout (SSOP)
Pin
Figure 3. CY8C9540A 48-Pin Device
Pin Name
No.
Description
1
GPort0_Bit0_PWM7
GPort0_Bit1_PWM5
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
Port 0, Bit 0, PWM 7.
2
Port 0, Bit 1, PWM 5.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 7.
Port 0, Bit 5, PWM 5.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Port 3, Bit 0, PWM 7.
Port 3, Bit 1, PWM 5.
Port 3, Bit 2, PWM 3.
Port 3, Bit 3, PWM 1.
Ground connection.
Port 3, Bit 4, PWM 7.
Port 3, Bit 5, PWM 5.
Port 3, Bit 6, PWM 3.
Port 3, Bit 7, PWM 1.
Port 5, Bit 2, PWM 3.
Port 5, Bit 3, PWM 1.
GPort0_Bit0_PWM7
1
2
Vdd
48
47
46
45
44
43
42
41
40
39
38
37
36
3
GPort0_Bit1_PWM5
GPort0_Bit2_PWM3
GPort1_Bit0_PWM6
GPort1_Bit1_PWM4
GPort1_Bit2_PWM2
4
3
4
5
6
7
5
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
Vss
6
GPort1_Bit3_PWM0
GPort1_Bit4_PWM6
GPort1_Bit5_PWM4/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
GPort4_Bit0_PWM6
GPort4_Bit1_PWM4
GPort4_Bit2_PWM2
GPort4_Bit3_PWM0
XRES
7
8
9
8
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
11
12
13
14
15
16
V
SS
SSOP
GPort3_Bit4_PWM7
GPort3_Bit5_PWM5
GPort3_Bit6_PWM3
GPort3_Bit7_PWM1
GPort5_Bit2_PWM3
GPort5_Bit3_PWM1
GPort3_Bit4_PWM7
GPort3_Bit5_PWM5
35
34
GPort4_Bit4_PWM6
GPort4_Bit5_PWM4
GPort4_Bit6_PWM2
GPort4_Bit7_PWM0
GPort5_Bit0_PWM2
GPort5_Bit1_PWM0
GPort2_Bit0_PWM6/A3
GPort2_Bit1_PWM4/A2
INT
GPort3_Bit6_PWM3
GPort3_Bit7_PWM1
33
32
31
30
29
28
27
26
25
17
18
19
20
21
GPort5_Bit2_PWM3
GPort5_Bit3_PWM1
I2C Serial Clock (SCL)
2
2
I C Serial Clock (SCL)
I C Clock.
2
2
I C Serial Data (SDA)
I C Data.
I2C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
GPort2_Bit3_PWM3/A1
22
23
24
A0
V
Ground connection.
SS
2
Vss
GPort2_Bit2_PWM0/WD
GPort2_Bit2_PWM0/WD
INT
Port 2, Bit 2, PWM 0, E Write Disable.
GPort2_Bit1_PWM4/A2
GPort2_Bit0_PWM6/A3
GPort5_Bit1_PWM0
GPort5_Bit0_PWM2
GPort4_Bit7_PWM0
GPort4_Bit6_PWM2
GPort4_Bit5_PWM4
GPort4_Bit4_PWM6
XRES
Port 2, Bit 1, PWM 4, Address 2.
Port 2, Bit 0, PWM 6, Address 3.
Port 5, Bit 1, PWM 0.
Port 5, Bit 0, PWM 2.
Port 4, Bit 7, PWM 0.
Port 4, Bit 6, PWM 2.
Port 4, Bit 5, PWM 4.
Port 4, Bit 4, PWM 6.
Active high external reset with internal pull
down.
36
37
38
39
40
41
42
43
44
45
46
47
48
GPort4_Bit3_PWM0
GPort4_Bit2_PWM2
GPort4_Bit1_PWM4
GPort4_Bit0_PWM6
GPort1_Bit7_PWM0/A4
GPort1_Bit6_PWM2/A5
GPort1_Bit5_PWM4/A6
GPort1_Bit4_PWM6
GPort1_Bit3_PWM0
GPort1_Bit2_PWM2
GPort1_Bit1_PWM4
GPort1_Bit0_PWM6
Port 4, Bit 3, PWM 0.
Port 4, Bit 2, PWM 2.
Port 4, Bit 1, PWM 4.
Port 4, Bit 0, PWM 6.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 4, Address 6.
Port 1, Bit 4, PWM 6.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 4.
Port 1, Bit 0, PWM 6.
V
Supply voltage.
dd
Document Number: 38-12036 Rev. *I
Page 6 of 32
CY8C9520A
CY8C9540A
CY8C9560A
100-Pin Part Pinout
Table 5. 100-Pin Part Pinout (TQFP)
Pin
Pin
No.
Name
No.
Description
Name
Description
1
DNU
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Port 0, Bit 3, PWM 1.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DNU
DNU = Do Not Use; leave floating.
Port 5, Bit 1, PWM 8.
2
DNU
GPort5_Bit1_PWM8
GPort5_Bit0_PWM10
GPort5_Bit4_PWM12
GPort5_Bit5_PWM14
GPort4_Bit7_PWM8
GPort4_Bit6_PWM10
GPort4_Bit5_PWM12
GPort4_Bit4_PWM14
DNU
3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
DNU
Port 5, Bit 0, PWM 10.
4
Port 0, Bit 4, PWM 7.
Port 5, Bit 4, PWM 12.
5
Port 0, Bit 5, PWM 5.
Port 5, Bit 5, PWM 14.
6
Port 0, Bit 6, PWM 3.
Port 4, Bit 7, PWM 8.
7
Port 0, Bit 7, PWM 1.
Port 4, Bit 6, PWM 10.
8
Port 3, Bit 0, PWM 7.
Port 4, Bit 5, PWM 12.
9
Port 3, Bit 1, PWM 5.
Port 4, Bit 4, PWM 14.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Port 3, Bit 2, PWM 3.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Active high external reset with internal pull down.
Port 4, Bit 3, PWM 0.
Port 3, Bit 3, PWM 1.
DNU
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Ground connection.
XRES
DNU
GPort4_Bit3_PWM0
GPort4_Bit2_PWM2
VSS
DNU
Port 4, Bit 2, PWM 2.
VSS
Ground connection.
GPort3_Bit4_PWM15
GPort3_Bit5_PWM13
GPort3_Bit6_PWM11
GPort3_Bit7_PWM9
GPort5_Bit7_PWM15
GPort5_Bit6_PWM13
GPort5_Bit2_PWM11
GPort5_Bit3_PWM9
I2C Serial Clock (SCL)
DNU
Port 3, Bit 4, PWM 15.
Port 3, Bit 5, PWM 13.
Port 3, Bit 6, PWM 11.
GPort4_Bit1_PWM4
GPort4_Bit0_PWM6
Port 4, Bit 1, PWM 4.
Port 4, Bit 0, PWM 6.
GPort1_Bit7_PWM0/A4 Port 1, Bit 7, PWM 0, Address 4.
GPort1_Bit6_PWM2/A5 Port 1, Bit 6, PWM 2, Address 5.
GPort1_Bit5_PWM4/A6 Port 1, Bit 5, PWM 4, Address 6.
Port 3, Bit 7, PWM 9.
Port 5, Bit 7, PWM 15.
Port 5, Bit 6, PWM 13.
Port 5, Bit 2, PWM 11.
DNU
DNU = Do Not Use; leave floating.
Port 1, Bit 4, PWM 6.
GPort1_Bit4_PWM6
DNU
Port 5, Bit 3, PWM 9.
I2C Clock.
DNU = Do Not Use; leave floating.
Port 1, Bit 3, PWM 0.
GPort1_Bit3_PWM0
DNU
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
I2C Data.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Port 1, Bit 2, PWM 2.
DNU
DNU
DNU
GPort1_Bit2_PWM2
DNU
I2C Serial Data (SDA)
GPort2_Bit3_PWM11/A1
A0
DNU = Do Not Use; leave floating.
Port 1, Bit 1, PWM 4.
Port 2, Bit 3, PWM 11, Address 1.
Address 0.
GPort1_Bit1_PWM4
DNU
DNU = Do Not Use; leave floating.
Port 1, Bit 0, PWM 6.
DNU
DNU = Do Not Use; leave floating.
Supply voltage.
GPort1_Bit0_PWM6
Vdd
Vdd
Supply voltage.
DNU
DNU = Do Not Use; leave floating.
Ground connection.
Vdd
Supply voltage.
VSS
VSS
Ground connection.
DNU
DNU = Do Not Use; leave floating.
Port 7, Bit 7, PWM 15.
Port 7, Bit 6, PWM 14.
Port 7, Bit 5, PWM 13.
Port 7, Bit 4, PWM 12.
Port 7, Bit 3, PWM 11.
VSS
Ground connection.
GPort7_Bit7_PWM15
GPort7_Bit6_PWM14
GPort7_Bit5_PWM13
GPort7_Bit4_PWM12
GPort7_Bit3_PWM11
GPort7_Bit2_PWM10
GPort7_Bit1_PWM9
GPort7_Bit0_PWM8
GPort2_Bit2_PWM8/WD
INT
GPort6_Bit0_PWM0
GPort6_Bit1_PWM1
GPort6_Bit2_PWM2
GPort6_Bit3_PWM3
GPort6_Bit4_PWM4
GPort6_Bit5_PWM5
GPort6_Bit6_PWM6
GPort6_Bit7_PWM7
DNU
Port 6, Bit 0, PWM 0.
Port 6, Bit 1, PWM 1.
Port 6, Bit 2, PWM 2.
Port 6, Bit 3, PWM 3.
Port 6, Bit 4, PWM 4.
Port 7, Bit 2, PWM 10.
Port 7, Bit 1, PWM 9.
Port 6, Bit 5, PWM 5.
Port 6, Bit 6, PWM 6.
Port 7, Bit 0, PWM 8.
Port 2, Bit 2, PWM 8, E2 Write Disable.
Port 6, Bit 7, PWM 7.
DNU = Do Not Use; leave floating.
Port 0, Bit 0, PWM 7.
GPort0_Bit0_PWM7
DNU
GPort2_Bit1_PWM12/A2
GPort2_Bit0_PWM14/A3
DNU
Port 2, Bit 7, PWM 0, Address 4.
Port 2, Bit 6, PWM 2, Address 5.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Port 0, Bit 1, PWM 5.
GPort0_Bit1_PWM5
DNU
DNU = Do Not Use; leave floating.
Port 0, Bit 2, PWM 3.
DNU
GPort0_Bit2_PWM3
DNU
100 DNU
DNU = Do Not Use; leave floating.
Document Number: 38-12036 Rev. *I
Page 7 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Figure 4. CY8C9560A 100-Pin Device[2]
DNUa
DNU
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
DNU
1
2
3
4
5
6
75
74
GPort1_Bit3_PWM0
DNU
73
72
71
GPort1_Bit4_PWM6
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
DNU
70
69
GPort1_Bit5_PWM4/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
GPort4_Bit0_PWM6
GPort4_Bit1_PWM4
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
7
8
9
68
67
10
66
65
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
DNU
Vss
11
12
13
14
15
16
17
GPort4_Bit2_PWM2
64
63
DNU
GPort4_Bit3_PWM0
XRES
TQFP
DNU
Vss
62
61
60
DNU
DNU
GPort3_Bit4_PWM15
GPort3_Bit5_PWM13
GPort4_Bit4_PWM14
GPort4_Bit5_PWM12
GPort4_Bit6_PWM10
GPort4_Bit7_PWM8
GPort5_Bit5_PWM14
59
58
57
56
55
GPort3_Bit6_PWM11
GPort3_Bit7_PWM9
GPort5_Bit7_PWM15
18
19
20
21
22
GPort5_Bit6_PWM13
GPort5_Bit2_PWM11
GPort5_Bit3_PWM9
GPort5_Bit4_PWM12
GPort5_Bit0_PWM10
GPort5_Bit1_PWM8
54
53
23
52
51
I2C Serial Clock (SCL)
DNU
24
25
DNU
Note
2. DNU = Do Not Use; leave floating.
Document Number: 38-12036 Rev. *I
Page 8 of 32
CY8C9520A
CY8C9540A
CY8C9560A
POR. When the part is held in reset, all In and Out pins are held
at their default High-Z State.
Pin Descriptions
Extendable Soft Addressing
Working with PWMs
The A0 line defines the corresponding bit of the I2C address. This
pin must be pulled up or down. If A0 is a strong pull up or a strong
pull down (wired through 330 or less resistor to Vdd or Vss), then
that is the only address line being specified and the A1-A6 lines
are used as GPIO. If A0 is a weak pull up or a weak pull down
(connected to Vdd or Vss through 75K- 200K ohm resistor), then
A0 is not the only externally defined address bit. There is a pin
assigned to be A1 if it is needed. This pin can be pulled up or
pulled down strong or weak with a resistor. As with A0, the type
of pull determines whether the address bit is the last externally
defined address bit. Differently from A0, A1 is not dedicated as
an address pin. It is only used if A0 is not the only address bit
externally defined. There are also predefined pins for A2, A3, A4,
A5, and A6 that is only used for addressing if needed. The last
address bit in the chain is pulled strong. That way, only the
number of pins needed to assign the address desired for the part
are allocated as address pins, any pins not used for address bits
can be used as GPIO pins. The Table 2 on page 4 defines the
resulting device I2C address.
There are four independent PWMs in the CY8C9520A, eight in
the CY8C9540A and sixteen in the CY8C9560A. Each I/O pin
can be configured as a PWM output by writing ‘1’ to the
corresponding bit of the Select PWM register (see Table 7 on
page 12).
The next step of PWM configuration is clock source selection
using the Config PWM registers. There are six available clock
sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6
Hz or previous PWM output. (see Figure 5)
Figure 5. Clock Sources
32 kHz
24mHz
1.5mHz
93.75 kHz
Note: It is not recommended to share pull up/down resistors
between multiple devices.
367.6 Hz -
Divider (1-255)
93.75 kHz
Interrupt Pin (INT)
The interrupt output (if enabled) is activated if one of these
events occurs:
By default, 32 kHz is selected as the PWM clock.
■ Oneofthe GPIOport pins changesstate andthecorresponding
bit in the Interrupt Mask register is set low.
PWM Period registers are used to set the output period:
■ When a PWM driven by the slowest clock source (367.6 Hz)
and assigned to a pin changes state and the pin’s
corresponding bit in the Interrupt Mask register is set low.
tOUT = Period tCLK
Allowed values are between 1 and FFh.
The interrupt line is deactivated when the master device
performs a read from the corresponding Interrupt Status register.
The INT output is active high output and the drive mode of this
pin is strong drive mode.
The PWM Pulse Width register sets the duration of the PWM
output pulse. Allowed values are between zero and the
(Period-1) value. The duty cycle ratio is computed using thsi
equation:
Write Disable Pin (WD)
If this feature is enabled, ‘0’ allows writes to the EEPROM and
‘1’ blocks any memory writes. This pin is checked immediately
before performing any write to memory. If the EEE bit in the
Enable register is not set (EEPROM disabled) or bit EERO is set
(EEPROM is read-only) then WD line level is ignored.
PulseWidth
------------------------------
DutyCycle =
Period
Note that ‘1’ on this line blocks all commands that perform
operations with EEPROM (see Table 14 on page 14).
This line may be enabled/disabled by bit 1 of the Enable register
(2Dh): ‘1’ enables WD function, ‘0’ disables.
External Reset Pin (XRES)
A full device reset is caused by pulling the XRES pin high. The
XRES pin has an always-on pull down resistor, so it does not
require an external pull down for operation. It can be tied
directly to ground or left open. Behavior after XRES is similar to
Document Number: 38-12036 Rev. *I
Page 9 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Figure 6. Memory Reading and Writing
Memory Address
Slave Address
R/W
0
R/W
Stop
S
A6 A5 A4 A3 A2 A1 A0
A
High(Addr)
A
Low(Addr)
A
S
A6 A5 A4 A3 A2 A1 A0
1
A
data(Addr)
A
data(Addr+1)
A
...
N
P
Start
ACK from
Slave
ACK from
Slave
ACK from
Slave
ACK from
Slave
ACK from
Master
ACK from
Master
No ACK
from Master
Reading from EEPROM
Up to the End of Address Space
Slave Address
Memory Address
R/W
Stop
S
A6 A5 A4 A3 A2 A1 A0
0
A
High(Addr)
A
Low(Addr)
A
data 1
A
data 2
A
...
A
P
Start
ACK from
Slave
ACK from
Slave
ACK from
Slave
If current address crosses
64-byte block boundary,
then device performs real
writing to EEPROM
Writing to EEPROM
Figure 7. Port Reading and Writing in Multi-Port Device
Slave Address
Register Address = 1
Reading from GPort 2
At this moment, device
performs reading from GPort 1
R/W
R/W
Stop
S
A6 A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
0
0
0
1
A
S
A6 A5 A4 A3 A2 A1 A0
1
A
data from GPort1
A
data from GPort 2
A
...
N
P
Start
ACK from
Slave
ACK from
Slave
No ACK
from Master
ACK from
Master
Reading from GPort 1
Slave Address
Register Address = 09h
Output to GPort 2
Output to GPort 3
At this moment, device
performs output to GPort 1
R/W
Stop
P
S
A6 A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
1
0
0
1
A
data from GPort1
A
data from GPort 2
A
data from GPort 3
A
...
Start
ACK from
Slave
ACK from
Slave
ACK from
Slave
ACK from
Slave
Writing from GPort 1
Document Number: 38-12036 Rev. *I
Page 10 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Table 6. The Device Register Address Map (continued)
Register Mapping Table
Default
The register address is auto-incrementing. If the master device
writes or reads data to or from one register and then continues
data transfer in the same I2C transaction, sequential bytes are
written or read to or from the following registers. For example, if
the first byte is sent to the Output Port 1 register, then the next
bytes are written to Output Port 2, Output Port 3, Output Port 4
etc. The first byte of each write transaction is treated as the
register address.
Address
1Ah
Register
Register Value
Select PWM for Port Output 00h
Inversion 00h
Pin Direction - Input/Output 00h
1Bh
1Ch
1Dh
1Eh
1Fh
Drive Mode - Pull Up
FFh
00h
00h
Drive Mode - Pull Down
To read data from a seires of registers, the master device must
write the starting register address byte then perform a start and
series of read transactions. If no address was sent, reads start
from address 0.
Drive Mode - Open Drain
High
20h
Drive Mode - Open Drain
Low
00h
To read a specific register address, the master device must write
the register address byte, then perform a start and read trans-
action.
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
Drive Mode - Strong
Drive Mode - Slow Strong
Drive Mode - High-Z
Reserved
00h
00h
See Figure 7 on page 10.
00h
The device’s register mapping is listed in Table 6.
None
None
None
None
00h
Reserved
Table 6. The Device Register Address Map
Default
Reserved
Address
Register
Reserved
Register Value
None
None
None
None
None
None
None
None
FFh
PWM Select
00h
Input Port 0
Config PWM
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
Input Port 1
Period PWM
FFh
80h
Input Port 2
Pulse Width PWM
Programmable Divider
Input Port 3
FFh
Input Port 4
Enable WDE, EEE, EERO 00h
Input Port 5
Device ID/Status
Watchdog
20h/40h/60h
Input Port 6
00h
00h
Input Port 7
Command
Output Port 0
Output Port 1
FFh
Output Port 2
FFh
Register Descriptions
Output Port 3
FFh
The registers for the CY8C95xx are described in the sections
that follow. Note that the PWM registers are located at addresses
28h to 2Bh.
Output Port 4
FFh
Output Port 5
FFh
Output Port 6
FFh
Input Port Registers (00h–07h)
Output Port 7
FFh
These registers represent actual logical levels on the pins and
are used for I/O port reading operations. They are read only. The
Inversion registers changes the state of reads to these ports.
Interrupt Status Port 0
Interrupt Status Port 1
Interrupt Status Port 2
Interrupt Status Port 3
Interrupt Status Port 4
Interrupt Status Port 5
Interrupt Status Port 6
Interrupt Status Port 7
Port Select
00h
00h
00h
Output Port Registers (08h–0Fh)
00h
These registers are used for writing data to GPIO ports. By
default, all ports are in the pull up mode allowing
quasi-bidirectional I/O. To allow input operations without
reconfiguration, these registers have to store ’1’s.
00h
00h
00h
Output register data also affects pin states when PWMs are
enabled. See Table 7 on page 12 for details.
00h
00h
See Figure 7 on page 10 illustrates port read/write procedures.
The Inversion registers have no effect on these ports.
Interrupt Mask
FFh
Document Number: 38-12036 Rev. *I
Page 11 of 32
CY8C9520A
CY8C9540A
CY8C9560A
The Input registers' logic is presented in Table 8. These registers
have no effect on outputs or PWMs.
Int. Status Port Registers (10h–17h)
Each ’1’ bit in these registers signals that there was a change in
the corresponding input line since the last read of that Interrupt
Status register. Each Interrupt (Int.) Status register is cleared
only after a read of that register.
Table 8. Inversion Register Logic
Pin State
Invert
Input
If a PWM is assigned to a pin, then all state changes of the PWM
sets the corresponding bit in the Interrupt Status register. If the
pin's interrupt mask is cleared and the PWM is set to the slowest
possible rate allowed (driven by the programmable clock source
with divide register 2Dh set to FFh), then the INT line also drives
on the PWM state change.
0
1
0
1
0
0
1
1
0
1
1
0
Port Select Register (18h)
Port Direction Register (1Ch)
This register configures the GPort. Write a value of 0–7 to this
register to select the port to program with registers 19h–23h.
Each bit in a port is configurable as either an input or an output.
To perform this configuration, the Port Direction register (1Ch) is
used for the GPort selected by the Port Select register (18h). If
a bit in this register is set (written with '1'), the corresponding port
pin is enabled as an input. If a bit in this register is cleared (written
with '0'), the corresponding port pin is enabled as an output.
Interrupt Mask Port Register (19h)
The Interrupt Mask register enables or disables activation of the
INT line when GPIO input levels are changed. Each ’1’ in the
Interrupt Mask register masks (disables) interrupts generated
from the corresponding input line of the GPort selected by the
Port Select register (18h).
Drive Mode Registers (1Dh–23h)
Each port's data pins can be set separately to one of seven
available modes: pull up or down, open drain high/low, strong
drive fast/slow, or high-impedance input. To perform this
configuration, the seven drive mode registers are used for the
GPort selected by the Port Select register (18h). Each ’1’ written
to this register changes the corresponding line drive mode.
Registers 1Dh through 23h have last register priority meaning
that the bit set to high in which the last register was written
overrides those that came before. Reading these registers
reflects the actual setting, not what was originally written.
Select PWM Register (1Ah)
This register allows each port to act as a PWM output. By default,
all ports are configured as GPIO lines. Each ’1’ in this register
connects the corresponding pin of the GPort selected by the Port
Select register (18h) to the PWM output. Output register data
also affects the pin state when a PWM is enabled. See Table 7.
Note that a pin used as PWM output must be configured to the
appropriate drive mode. See Table 9 for more information.
Table 7 describes the logic of the Output and Select PWM
registers.
Table 9. Drive Mode Register Settings
Reg.
1Dh
Pin State
Description
Table 7. Output and Select PWM Registers Logic
Resistive Pull Up
Resistive High, Strong Low
(default)
Output
Select PWM
Pin State
1Eh
1Fh
20h
21h
Resistive Pull Down Strong High, Resistive Low
0
1
0
1
0
0
1
1
0
Open Drain High
Open Drain Low
Strong Drive
Slow Strong High, High Z Low
Slow Strong Low, High Z High
1
0
Strong High, Strong Low, Fast
Output Mode
Current PWM
22h
23h
Slow Strong Drive Strong High, Strong Low,
Slow Output Mode
Inversion Register (1Bh)
This register can invert the logic of the input ports. Each ’1’
written to this register inverts the logic of the corresponding bit in
the Input register of the GPort selected by the Port Select register
(18h).
High Impedance
High Z
PWM Select Register (28h)
This register is configures the PWM. Write a value of 00h-0Fh to
this register to select the PWM to program with registers
29h-2Bh.
Document Number: 38-12036 Rev. *I
Page 12 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Config (29h)
Divider Register (2Ch)
This register selects the clock source for the PWM selected by
the PWM Select register (28h) and interrupt logic.
This register sets the frequency on the output of the
programmable divider:
There are six available clock sources: 32 kHz (default), 24 MHz,
1.5 MHz, 93.75 kHz, 367.6 Hz, or previous PWM output. The
367.6 Hz clock is user programmable. It divides the 93.75 kHz
clock source by the divisor stored in the Divider register (2Ch).
The default divide ratio is 255. (see Table 10 for details). By
default, all PWMs are clocked from 32 kHz.
93.75 kHz
Frequency
.
Divider
Allowed values are between 1 and 255.
Enable Register (2Dh)
Table 10. PWM Clock Sources
The WDE bit configures the write disable pin to operate either as
a GPIO or as WD. It also enables/disables EEPROM operations
(EEE bit) or makes the EEPROM read-only (EERO bit). Bit
assignments are shown in Table 12 on page 13.
Config PWM
xxxxx000b
xxxxx001b
xxxxx010b
xxxxx011b
xxxxx100b
xxxxx101b
PWM Clock Source
32 kHz (default)
24 MHz
1.5 MHz
Table 12. Enable Register
93.75 kHz
Bit
7
6
5
4
3
2
1
0
367.6 Hz (programmable)
Previous PWM
Function
Default
Reserved
Reserved
EERO EEE WDE
0
0
0
Each PWM can generate an interrupt at the rising or falling edge
of the output pulse. There is a limitation on the clock source for
a PWM to generate an interrupt. Only the slowest speed source
(programmed to 367.6 Hz) with the divider equal to 255 allows
interrupt generation. Consequently, to create a PWM interrupt, it
is necessary to choose the programmable divider output as the
clock source (write xxxxx100b to Config register (29h)), write 255
to the Divide register (2Ch), and select PWM for pin output (1Ah).
Each ’1’ enables the corresponding feature, ’0’ disables.
Writes to this register differ from other registers. The write
sequence to modify the Enable register is as follows:
1. Send device I2C address with bit 0.
2. Send register address 2Dh.
3. Send unlock key - the sequence of three bytes: 43h, 4Dh, 53h;
('C', 'M', 'S' in ASCII bytes).
Interrupt status is reflected in the Interrupt Status registers
(10h-17h) and can cause INT line activation if enabled by the
corresponding mask bit in the Interrupt Mask register:
4. Send new Enable register value.
This write sequence secures the register from accidental
changes. The register can be read without the use of the unlock
key.
Period Register (2Ah)
Table 11. Period Register
By default, EERO and EEPROM (EEE bit) are disabled and WD
line (WDE bit) is set to GPIO (WD disabled).
When performing a burst write operation that crosses this
register, the data written to this register is ignored and the
address increments to 2Eh.
Config PWM
xxxx0xxxb
PWM Interrupt on
Falling pulse edge (default)
Rising pulse edge
xxxx1xxxb
Device ID/Status Register (2Eh)
This register sets the period of the PWM counter. Allowed values
are between 1 and FFh. The effective output waveform period of
the PWM is:
This register stores device identifiers (2xh/4xh/6xh) and reflects
which settings were loaded during startup, either factory defaults
(FD) or user defaults (UD). By default during startup, the device
attempts to load the user default block. If it is corrupted then
factory defaults are loaded and the low nibble of this register is
set high to inform which set is active. The high nibble is always
equal to 2 for CY8C9520A, 4 for CY8C9540A, and 6 for
CY8C9560A.
tOUT Period tCLK
Pulse Width Register (2Bh)
This register is read-only.
This register sets the pulse width of the PWM output. Allowed
values are between zero and the (Period - 1) value. The duty
cycle ratio can be computed using the following equation:
Table 13. Device ID Status Register
Bit
7
6
5
4
3
2
1
0
Function Device Family (2, 4,or 6)
Reserved
FD/UD
PulseWidth
DutyCycle
.
Period
Document Number: 38-12036 Rev. *I
Page 13 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Watchdog Register (2Fh)
Write E2 POR Defaults Cmd (03h)
This register controls the internal Watchdog timer. This timer can
trigger a device reset if the device is not responding to I2C
requests due to misconfiguration. Device operation is not
affected when the Watchdog register = 0. If the I2C master writes
any non zero value to the Watchdog register, the countdown
mechanism is activated and each second the register is
decremented. Upon transition from 1 to 0, the device is rebooted,
which restores user defaults. After reboot, the Watchdog register
value is reset to zero. Any I2C transaction (addressing the
Expander) resets the Watchdog register to the previously stored
value. Any device reboot (caused by a POR or Watchdog) sets
the Watchdog register to zero (turns off the Watchdog feature).
The Watchdog timer can be disabled by writing zero to the
Watchdog register (2Fh) or by using the Reconfigure Device
Cmd (07h).
This command sends new power up defaults to the CY8C95xx
without changing current settings unless the 07h command is
issued afterwards. This command is followed by 147 data bytes
according to Table 15. The CRC is calculated as the XOR of the
146 data bytes (00h-91h). If the CRC check fails or an
incomplete block is sent, then the slave responds with a NAK and
the data does not get saved to EEPROM.
To define new POR defaults the user must:
■ Write command 03h
■ Write 146 data bytes with new values of registers
■ Write 1 CRC byte calculated as XOR of previous 146 data
bytes.
Content of the data block is described in Table 15.
Note The Watchdog timer is not intended to track precise time
intervals. The timer's frequency can vary in range between –50%
on up to +100%. This variation must be taken into account when
selecting the appropriate value for the Watchdog register.
Table 15. POR Defaults Data Structure
Offset
00h–07h
Value
Output Port 0–7
Command Register (30h)
08h–0Fh
10h–17h
18h–1Fh
20h–27h
28h
Interrupt mask Port 0–7
Select PWM Port 0–7
Inversion Port 0–7
This register sends commands to the device, including current
configuration as new POR defaults, restore factory defaults,
define POR defaults, read POR defaults, write device
configuration, read device configuration, and reconfigure device
with stored POR defaults. The command set is presented in
Table 14.
Pin Direction Port 0–7
Resistive pull up Drive Mode Port 0
Resistive pull down Drive Mode Port 0
Open drain high Drive Mode Port 0
Open drain low Drive Mode Port 0
Strong drive Drive Mode Port 0
Slow strong drive Drive Mode Port 0
High impedance Drive Mode Port 0
Drive Modes Port 1
Note Registers are not restored in parallel. Do not assume any
particular order to the restoration process.
29h
2Ah
2Bh
Table 14. Available Commands
2Ch
Command
Description
2Dh
01h
Store device configuration to EEPROM POR
defaults
2Eh
2Fh–35h
36h–3Ch
3Dh–43h
44h–4Ah
4Bh–51h
52h–58h
59h–5Fh
60h
02h
03h
04h
05h
06h
07h
Restore Factory Defaults
Drive Modes Port 2
Write EEPROM POR defaults
Read EEPROM POR defaults
Write device configuration
Drive Modes Port 3
Drive Modes Port 4
Drive Modes Port 5
Read device configuration
Drive Modes Port 6
Reconfigure device with stored POR defaults
Drive Modes Port 7
Commands Description
Store Config to E2 POR Defaults Cmd (01h)
Config setting PWM0
Period setting PWM0
Pulse Width setting PWM0
PWM1 settings
61h
62h
The current ports settings (drive modes and output data) and
other configuration registers are saved in the EEPROM by using
the store configuration command (Cmd). These settings are
automatically loaded after the next device power up or if the 07h
command is issued.
63h–65h
…
…
8Dh–8Fh
90h
PWM15 settings
Divider
Restore Factory Defaults Cmd (02h)
91h
Enable
This command replaces the saved user configuration with the
factory default configuration. Current settings are unaffected by
this command. New settings are loaded after the next device
power up or if the 07h command is issued.
92h
CRC
Document Number: 38-12036 Rev. *I
Page 14 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Read E2 POR Defaults Cmd (04h)
Read Device Config Cmd (06h)
This command reads the POR settings stored in the EEPROM.
To read POR defaults the user must:
This command reads the current device configuration. It gives
the user ‘flat-address-space’ access to all device settings.
To read device configuration the user must:
■ Write command 06h
■ Write command 04h
■ Read 146 data bytes (see Table 15 on page 14)
■ Read 1 CRC byte.
■ Read 146 data bytes (see Table 15 on page 14).
■ Read 1 CRC byte.
Write Device Config Cmd (05h)
Reconfigure Device Cmd (07h)
This command sends a new device configuration to the
CY8C95xx. It is followed by 146 data bytes according to
Table 15. The CRC is calculated as the XOR of the 146 data
bytes (00h-91h). If the CRC check fails or an incomplete block is
sent, then the slave responds with a NAK and the device does
not use the data. This gives the user ‘flat-address-space’ access
to all device settings.
This command immediately reconfigures the device with actual
POR defaults from EEPROM. It has the same effect on the
registers as a POR.
To set the current device configuration the user must:
■ Write command 05h
■ Write 146 data bytes with new values of registers
■ Write 1 CRC byte calculated as XOR of previous 146 data
bytes.
If the CRC check passes, then the device uses the new settings
immediately.
Content of the data block is described in Table 15 on page 14.
Document Number: 38-12036 Rev. *I
Page 15 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Electrical Specifications
This section lists the DC and AC electrical specifications of the CY8C95xxA device. For the most up to date electrical specifications,
confirm that you have the most recent data sheet by going to the web at http://www.cypress.com.
Specifications are valid for –40 C T 85 C and T 100 C, except where noted.
A
J
Absolute Maximum Ratings
Table 16. Absolute Maximum Ratings
Symbol Description
TSTG Storage temperature
Min
Typ
Max
Units
Notes
–55
25
+100
C
Higher storage temperatures
reduces data retention time.
Recommended storage temper-
ature is +25 C ± 25 C. Extended
duration storage temperatures
above 65C degrades reliability.
TBAKETEMP Bake Temperature
TBAKETIME Bake Time
–
125
–
See
package
label
C
See
package
label
72
Hours
TA
Ambient temperature with power applied
–40
–0.5
–
–
–
+85
C
V
Vdd
VIO
Supply voltage on Vdd relative to Vss
DC input voltage
+6.0
Vss - 0.5
Vdd +
0.5
V
VIOZ
DC voltage applied to tri-state
Vss - 0.5
–
Vdd +
0.5
V
IMIO
ESD
LU
Maximum current into any port pin
Electro Static Discharge Voltage
Latch up current
–25
2000
–
–
–
–
+50
–
mA
V
Human Body Model ESD.
200
mA
Operating Temperature
Table 17. Operating Temperature
Symbol
TA
TJ
Description
Min
–40
–40
Typ
–
Max
+85
Units
C
C
Notes
Ambient temperature
Junction temperature
–
+100
The temperature rise from
ambient to junction is package
specific. See “Thermal Imped-
ances per Package” on page 23.
The user must limit the power
consumption to comply with this
requirement.
Document Number: 38-12036 Rev. *I
Page 16 of 32
CY8C9520A
CY8C9540A
CY8C9560A
DC Electrical Characteristics
DC Chip-Level Specifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 18. CY8C9520A DC Chip-Level Specifications
Symbol
Vdd
Description
Supply voltage
Min
3.00
–
Typ
–
Max
5.25
5
Units
Notes
V
IDD
Supply current Vdd 5 V
Supply current Vdd 3.3 V
3.8
2.3
mA Conditions are 5.0 V, TA = 25 C, IOH = 0.
mA Conditions are 3.3 V, TA = 25 C, IOH = 0.
IDD3
–
3
Table 19. CY8C9540A DC Chip-Level Specifications
Symbol
Vdd
Description
Supply voltage
Min
3.00
–
Typ
–
Max
5.25
9
Units
Notes
V
IDD
Supply current Vdd 5 V
Supply current Vdd 3.3 V
6
mA Conditions are 5.0 V, TA = 25 C, IOH = 0.
mA Conditions are 3.3 V, TA = 25 C, IOH = 0.
IDD3
–
3.3
6
Table 20. CY8C9560A DC Chip-Level Specifications
Symbol
Vdd
Description
Supply voltage
Min
3.00
–
Typ
–
Max
5.25
25
Units
V
Notes
IDD
Supply current Vdd 5 V
Supply current Vdd 3.3 V
15
5
mA
mA
Conditions are 5.0 V, TA = 25 C, IOH = 0.
Conditions are 3.3 V, TA = 25 C, IOH = 0.
IDD3
–
9
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 21. DC Programming Specifications
Symbol
FlashENPB
FlashENT
FlashDR
Description
Flash (EEPROM) endurance (by block)
Flash endurance (total)[3]
Flash data retention
Min
10,000
1,800,000
10
Typ
–
Max
Units
–
Notes
–
–
–
Erase/write cycles by block.
Erase/write cycles.
–
–
–
Years
DC I2C Specifications
Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 22. DC I2C Specifications[4]
Symbol
Description
Min
Typ
–
Max
Units
Notes
V
V
Input low level
Input high level
–
–
0.3 × V
V
V
V
3.0 V V 3.6 V
ILI2C
DD
DD
–
0.25 × V
–
4.75 V V 5.25 V
DD
DD
0.7 × V
–
3.0 V V 5.25 V
IHI2C
DD
DD
Note
3. A maximum of 180 x 10,000 block endurance cycles is allowed. This may be balanced between operations on 180x1 blocks of 10,000 maximum cycles each, 180x2
blocks of 5,000 maximum cycles each, or 180x4 blocks of 2,500 maximum cycles each (to limit the total number of cycles to 180x10,000 and that no single block
ever sees more than 10,000 cycles).
4. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 38-12036 Rev. *I
Page 17 of 32
CY8C9520A
CY8C9540A
CY8C9560A
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 23. DC GPIO Specifications
Symbol
VOH
Description
High output level
Min
Typ
Max
Units
Notes
Vdd - 1.0
–
–
V
IOH = 10 mA for any one pin,
Vdd = 4.75 to 5.25 V.
40 mA maximum combined IOH for
GPort0; GPort2_Bit3; GPort3;
GPort5_Bit2, 3, 6, 7; GPort6.
40 mA maximum combined IOH for
GPort1; GPort2_Bit0, 1, 2; GPort4;
GPort5_Bit0, 1, 4, 5; GPort7.
80 mA maximum combined IOH.
VOL
Low output level
–
–
0.75
V
IOL = 25 mA for any one pin,
Vdd = 4.75 to 5.25 V.
100 mA maximum combined IOL for
GPort0; GPort2_Bit3; GPort3;
GPort5_Bit2, 3, 6, 7; GPort6.
100 mA maximum combined IOL for
GPort1; GPort2_Bit0, 1, 2; GPort4;
GPort5_Bit0, 1, 4, 5; GPort7.
200 mA maximum combined IOL
.
IOH
IOL
High Level Source Current
Low Level Sink Current
10
25
–
–
–
–
mA VOH = Vdd–1.0 V, see the limitations of
the total current in the note for VOH
mA VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VIL
VIH
IIL
Input low level
–
2.1
–
–
–
0.8
–
V
V
Vdd = 3.0 to 5.5.
Vdd = 3.0 to 5.5.
Input high level
Input leakage (absolute value)
Capacitive load on pins as input
1
–
nA Gross tested to 1 A.
CIN
–
3.5
10
pF Package and pin dependent.
Temp = 25 C.
COUT
Capacitive load on pins as output
–
3.5
10
pF Package and pin dependent.
Temp = 25 C.
RPU
RPD
Pull-up resistor
4
4
5.6
5.6
8
8
k None
k None
Pull-down resistor
Document Number: 38-12036 Rev. *I
Page 18 of 32
CY8C9520A
CY8C9540A
CY8C9560A
AC Electrical Characteristics
AC GPIO Specifications
Table 24 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only or unless otherwise specified.
Table 24. AC GPIO Specifications
Symbol
FGPIO
Description
Min
0
Typ
–
Max
12
Units
Notes
GPIO Operating Frequency
MHz Normal Strong Mode
TRiseF
TFallF
TRiseS
TFallS
Rise time, normal strong mode,
Cload = 50 pF
3
–
18
ns Vdd = 4.75 to 5.25 V,
10%–90%
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
IO access time
2
–
18
–
ns Vdd = 4.75 to 5.25 V,
10%–90%
10
10
27
22
ns Vdd = 3 to 5.25 V,
10%–90%
–
ns Vdd = 3 to 5.25 V,
10%–90%
TIOAccess
–
–
–
2.485
–
ms None
TPulsewidth
Minimum pulse width on I/Os to assert INT
line.
5.03
ms No I2C activity or
EEPROM operation
happens during input
pulse duration.
Figure 8. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC PWM Specifications
Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only or unless otherwise specified.
Table 25. AC PWM Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Jitter24MHzPWM 24 MHz based PWM peak-to-peak period
jitter
–
0.1
1.5
%
24 MHz, 1.5 MHz,
93.75 kHz and 367.6 Hz
(programmable)
sources.
Jitter32kHzPWM 32 kHz-based PWM peak-to-peak period
jitter
–
2.5
5.0
%
32 kHz clock source.
F24MHzPWM
F32kHzPWM
F1.5MHzPWM
Input Frequency of 24 MHz based PWM
Input Frequency of 32 kHz based PWM
Input frequency of 1.5 MHz based PWM
23.4
15
24
32
24.6
64
MHz
kHz
1.46
1.5
1.53
MHz
Document Number: 38-12036 Rev. *I
Page 19 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Table 25. AC PWM Specifications
F93.75kHzPWM Input Frequency of 93.75 kHz based PWM
91.40
93.75
96.09
kHz
AC I2C Specifications
Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only or unless otherwise specified.
Table 26. AC Characteristics of the I2C SDA and SCL Pins
Standard Mode
Symbol
Description
Units
Notes
Min
0
Max
100
–
FSCLI2C
SCL clock frequency
kHz
THDSTAI2C
Hold time (repeated) START condition. After this period,
the first clock pulse is generated.
4.0
s
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
LOW period of the SCL clock
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
s
s
s
s
ns
s
s
ns
HIGH period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
250
4.0
4.7
–
Setup time for STOP condition
Bus free time between a STOP and START Condition
Pulse width of spikes are suppressed by the input filter.
TSPI2C
Note: Fast mode I2C is not supported.
Figure 9. Definition for Timing for Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
TSPI2C
TSUSTAI2C
TBUFI2C
THDDATI2C
THDSTAI2C
I2C_SCL
THIGHI2C TLOWI2C
TSUSTOI2C
P
S
S
Sr
Repeated START Condition
STOP Condition
START Condition
AC EEPROM Write Specifications
Table 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only or unless otherwise specified.
Table 27. AC EEPROM Write Specifications
Symbol
TEEPROMWrite_Hot
TEEPROMWrite_Cold
Description
Min
–
Typ
–
Max
100
200
Units
ms
Notes
0 °C Tj 100 °C
–40 °C Tj 0 °C
EEPROM Erase + Write time
EEPROM Erase + Write time
–
–
ms
Document Number: 38-12036 Rev. *I
Page 20 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Packaging Dimensions
This section illustrates the packaging specifications for the CY8C95xxA device, along with the thermal impedances for each package
and the solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Figure 10. 28-pin SSOP (210 Mils) Package Outline
51-85079 *F
Document Number: 38-12036 Rev. *I
Page 21 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Figure 11. 48-pin SSOP (300 Mils) Package Outline
51-85061 *F
Figure 12. 100-pin TQFP (14 × 14 × 1.0 mm) Package Outline
51-85048 *I
Document Number: 38-12036 Rev. *I
Page 22 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Thermal Impedances
Table 28. Thermal Impedances per Package
[5]
Package
Typical JA
101 C/W
69 C/W
28-pin SSOP
48-pin SSOP
100-pin TQFP
48 C/W
Solder Reflow Specifications
Table 29 shows the solder reflow temperature limits that must not be exceeded.
Table 29. Solder Reflow Specifications
Package
Maximum Peak Temperature (TC) Maximum Time above TC – 5 C
28-pin SSOP
48-pin SSOP
100-pin TQFP
260 °C
260 °C
260 °C
30 seconds
30 seconds
30 seconds
Notes
5. TJ = TA + POWER x
JA.
Document Number: 38-12036 Rev. *I
Page 23 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Features and Ordering Information
Table 30 lists the CY8C95xxA device’s key package features and ordering codes. A definition of the ordering number code follows.
Table 30. CY8C95xxA Device Key Features and Ordering Information
EEPROM
(Bytes)
Temperature
Range
PWM
Sources
Configurable
I/O Pins
Package
Ordering Code [6]
28 Pin (210 Mil) SSOP
CY8C9520A-24PVXI
3K
–40 C to +85C
–40 C to +85C
–40 C to +85C
–40 C to +85C
–40 C to +85C
–40 C to +85C
4
4
8
8
20
20
40
40
60
60
28 Pin (210 Mil) SSOP (Tape and Reel) CY8C9520A-24PVXIT
48 Pin (300 Mil) SSOP CY8C9540A-24PVXI
48 Pin (300 Mil) SSOP (Tape and Reel) CY8C9540A-24PVXIT
3K
11K
11K
27K
27K
100 Pin TQFP
CY8C9560A-24AXI
CY8C9560A-24AXIT
16
16
100 Pin TQFP (Tape and Reel)
Ordering Code Definitions
CY 8 C 9 xxx-SPxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
C = Commercial
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX/LTX/LQX/LCX = QFN Pb-Free
AX = TQFP Pb-Free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Note
6. The A after the existing port expander part number indicates new device firmware.
Document Number: 38-12036 Rev. *I
Page 24 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Acronyms
Table 31 lists the acronyms that are used in this document.
Table 31. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
Description
alternating current
application programming interface
POR
power on reset
API
PSoC® Programmable System-on-Chip
CMOS complementary metal oxide semiconductor
PWM
SSOP
TQFP
UART
pulse width modulator
shrink small-outline package
thin quad flat pack
CRC
DC
cyclic redundancy check
direct current
EEPROM electrically erasable programmable read-only
memory
universal asynchronous reciever / transmitter
GPIO
I/O
general purpose I/O
input/output
USB
WDT
XRES
universal serial bus
watchdog timer
external reset
MSB
PCB
most-significant bit
printed circuit board
Document Conventions
Units of Measure
Table 32 lists the units of measures.
Table 32. Units of Measure
Symbol
°C
Unit of Measure
Symbol
mm
ms
nA
ns
Unit of Measure
degree Celsius
hertz
millimeter
millisecond
nanoampere
nanosecond
ohm
Hz
kHz
k
kilohertz
kilohm
MHz
µA
megahertz
microampere
microsecond
microvolt
%
percent
µs
pF
picofarad
volt
V
V
Vrms
mA
microvolts root-mean-square
milliampere
W
watt
Numeric Conventions
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Document Number: 38-12036 Rev. *I
Page 25 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
(ADC)
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that
create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
buffer
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclicredundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
Document Number: 38-12036 Rev. *I
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CY8C9520A
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CY8C9560A
Glossary (continued)
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
(DAC)
converter performs the reverse operation.
duty cycle
emulator
The relationship of a clock period high time to its low time, expressed as a percent.
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency
gain
The number of cycles or events per unit of time, for a periodic function.
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high
with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
routine (ISR)
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage
detect (LVD)
A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Document Number: 38-12036 Rev. *I
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CY8C9520A
CY8C9540A
CY8C9560A
Glossary (continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
modulator
noise
The reference to a circuit containing both analog and digital techniques and components.
A device that imposes a signal on a carrier.
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
parity
A circuit that may be crystal controlled and is used to generate a clock frequency.
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
Power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoCDesigner™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
reset
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
shift register
slave device
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
SROM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
Document Number: 38-12036 Rev. *I
Page 28 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Glossary (continued)
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V.
A name for a power net meaning “voltage source.” The most negative power supply signal.
VSS
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 38-12036 Rev. *I
Page 29 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Errata
This section describes the errata for CY8C9560A device. Details include the trigger condition, scope of impact, available workaround,
and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
CY8C9560A
Qualification Status
CY8C9560A Rev. A – In Production
Errata Summary
The following table defines the errata applicability to available devices.
Items
Part Number
CY8C9560A
Silicon Revision
Fix Status
1. The command 01h cannot store more
than128 bytes of configuration data from
SRAM to EEPROM.
A
No silicon fix planned.
Workaround is required.
1. The command 01h cannot store more than128 bytes of configuration data from SRAM to EEPROM.
❐ Problem Definition
The Store Config to E2 POR Defaults Cmd (01h) can write only up to 128 bytes of configuration data from SRAM to the EEPROM.
Configuration data exceeding 128 bytes are ignored.
❐ Parameters Affected
NA
❐ Trigger Condition
NA
❐ Scope of Impact
Configuration data from SRAM to EEPROM exceeding 128 bytes are ignored.
❐ Workaround
As a workaround, use the Write E2 POR Defaults Cmd (03h) command to explicitly write all configuration data to EEPROM
using I2C.
❐ Fix Status
No fixes are planned. You must use the recommended workaround.
Document Number: 38-12036 Rev. *I
Page 30 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Document History Page
Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM
Document Number: 38-12036
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
346754
392484
HMT
HMT
See ECN New silicon, document.
*A
See ECN Correct pin 79 on the TQFP. Add AC PWM Output Jitter spec. table. Upgrade
to CY Perform logo and update zip code and trademarks.
*B
*C
1336984
HMT /
AESA
See ECN Update typical and recommended Storage Temperature per industrial specs.
Update copyright and trademarks. Add Watchdog timer details. Add “A” to
existing part numbers to indicate new firmware. Fix errors. Implement CY
template.
2843174
YARA
01/08/2010 Added Contents. Updated Overview. Updated Pin 11 description in Figure 2
on page 5. Modified Note 3. Added IOH and IOL specifications in DC GPIO
Specifications. Removed “Output Jitter” from AC PWM Specifications section
on page 18. Added F24MHzPWM, F32kHzPWM, and F93.5kHzPWM specifi-
cations in Table 25. Added Table 27.
*D
*E
2903402
3110285
NJF
NJF
04/01/2010 Updated Cypress website links
Added TBAKETEMP and TBAKETIME parameters
Updated package diagrams
12/14/10
Added text “When the part is held in reset all In and Out pins are held at their
default High-Z State” to section “External Reset Pin (XRES)” on page 9.
Added DC I2C Specifications table.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes made to I2C Timing Diagram. It has been updated for
clearer understanding.
*F
3381717
4512488
NPD
09/23/11
Updated solder reflow specifications to improve clarity.
Updated package diagrams.
*G
DIMA
09/24/2014 Updated Pin Descriptions:
Updated Extendable Soft Addressing:
Updated description.
Updated Interrupt Pin (INT):
Updated description.
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated DC GPIO Specifications:
Updated Table 23:
Added RPU, RPD parameters and their details.
Updated AC Electrical Characteristics:
Updated AC GPIO Specifications:
Updated Table 24:
Added TIOAccess parameter and its details.
Updated AC I2C Specifications:
Updated Table 26 (Removed the column “Fast Mode”).
Updated Figure 9 (No change in figure, removed “Fast” in caption only).
Updated Packaging Dimensions:
spec 51-85061 – Changed revision from *E to *F.
spec 51-85048 – Changed revision from *E to *I.
Updated to new template.
Completing Sunset Review.
*H
*I
4569861
4708108
ASRI
DIMA
11/22/2014 Added Errata.
04/01/2015 Added minimum input pulse width in Table 24.
Removed reference to obsolete application note, AN2304.
Document Number: 38-12036 Rev. *I
Page 31 of 32
CY8C9520A
CY8C9540A
CY8C9560A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
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psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
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cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12036 Rev. *I
Revised April 1, 2015
Page 32 of 32
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
2
2
2
Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided
2
that the system conforms to the I C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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