CY9BF466RPMC-G-MNK1E2

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CY9B460R Series

32-bit Arm^®Cortex^®-M4F

FM4 Microcontroller

The CY9B460R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and

competitive cost.

These series are based on the Arm^®Cortex^®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions

such as Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I²C, LIN).

Features

32-bit Arm^®Cortex^®-M4F Core

◼Processor version: r0p1

◼Up to 160 MHz Frequency Operation

◼FPU built-in

[SRAM]

This is composed of three independent SRAMs (SRAM0,

SRAM1 and SRAM2). SRAM0 is connected to I-code bus or

D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are

connected to System bus of Cortex-M4F core.

◼SRAM0: Up to 64 Kbytes

◼SRAM1: Up to 32 Kbytes

◼SRAM2: Up to 32 Kbytes

◼Support DSP instruction

◼Memory Protection Unit (MPU): improves the reliability of an

embedded system

External Bus Interface

◼Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 128 peripheral interrupts

and 16 priority levels

◼Supports SRAM, NOR, NAND Flash and SDRAM device

◼Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)

◼8-/16-bit Data width

◼24-bit System timer (Sys Tick): System timer for OS task

management

◼Up to 25-bit Address bit

On-chip Memories

◼Maximum Access size: 256 Mbyte

◼Supports Address/Data multiplex

◼Supports external RDY function

◼Supports scramble function

[Flash memory]

These series are based on two independent on-chip Flash

memories.

◼MainFlash memory

Up to 1024 Kbytes

Built-in Flash Accelerator System with 16 Kbytes trace

◼Possible to set the validity/invalidity of the scramble function

for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4

Mbytes units.

buffer memory

The read access to Flash memory can be achieved

without wait-cycle up to operation frequency of 72 MHz.

Even at the operation frequency more than 72 MHz, an

equivalent access to Flash memory can be obtained by

Flash Accelerator System.

◼Possible to set two kinds of the scramble key

◼Note: It is necessary to prepare the dedicated software

library to use the scramble function.

Security function for code protection

◼WorkFlash memory

32 Kbytes

Read cycle:

CAN Interface (Max 2 channels)

◼Compatible with CAN Specification 2.0A/B

◼Maximum transfer rate: 1 Mbps

◼Built-in 32 message buffer

• 6wait-cycle: the operation frequency more than 120

MHz, and up to 160 MHz

• 4wait-cycle: the operation frequency more than 72 MHz,

and up to 120 MHz

• 2wait-cycle: the operation frequency more than 40 MHz,

and up to 72 MHz

• 0wait-cycle: the operation frequency up to 40MHz

Multi-function Serial Interface (Max 8 channels)

◼64 bytes with FIFO (the FIFO step numbers are variable

depending on the settings of the communication mode or bit

length.)

Security function is shared with code protection

◼Operation mode is selectable from the followings for each

channel.

UART

CSIO

LIN

I²C

Cypress Semiconductor Corporation

Document Number: 002-04868 Rev. *F

• 198 Champion Court

•

San Jose, CA 95134-1709

408-943-2600

Revised November 30, 2020

CY9B460R Series

[UART]

DSTC (Descriptor System data Transfer Controller)

(128 channels)

◼Full-duplex double buffer

The DSTC can transfer data at high-speed without going via

the CPU. The DSTC adopts the Descriptor system and,

following the specified contents of the Descriptor which has

already been constructed on the memory, can access directly

the memory /peripheral device and performs the data transfer

operation.

◼Selection with or without parity supported

◼Built-in dedicated baud rate generator

◼External clock available as a serial clock

◼Hardware Flow control : Automatically control the

transmission by CTS/RTS (only ch.4)

It supports the software activation, the hardware activation and

the chain activation functions.

◼Various error detect functions available (parity errors,

framing errors, and overrun errors)

A/D Converter (Max 24 channels)

[CSIO]

[12-bit A/D Converter]

◼Full-duplex double buffer

◼Successive Approximation type

◼Built-in 3 units

◼Built-in dedicated baud rate generator

◼Overrun error detect function available

◼Serial chip select function (ch.6 and ch.7 only)

◼Supports high-speed SPI (ch.4 and ch.6 only)

◼Data length 5 to 16-bit

◼Conversion time: 0.5 μs @ 5 V

◼Priority conversion available (priority at 2 levels)

◼Scanning conversion mode

◼Built-in FIFO for conversion data storage (for SCAN

conversion: 16 steps, for Priority conversion: 4 steps)

[LIN]

◼LIN protocol Rev.2.1 supported

◼Full-duplex double buffer

◼Master/Slave mode supported

DA converter (Max 2 channels)

◼R-2R type

◼12-bit resolution

◼LIN break field generation (can change to 13 to 16-bit

Base Timer (Max 8 channels)

Operation mode is selectable from the followings for each

channel.

length)

◼LIN break delimiter generation (can change to 1 to 4-bit

length)

◼16-bit PWM timer

◼16-bit PPG timer

◼Various error detect functions available (parity errors,

framing errors, and overrun errors)

◼16-/32-bit reload timer

◼16-/32-bit PWC timer

[I²C]

◼Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)

supported

General Purpose I/O Port

This series can use its pins as general purpose I/O ports when

they are not used for external bus or peripherals. Moreover,

the port relocate function is built in. It can set which I/O port

the peripheral function can be allocated.

◼Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A

and ch.7=ch.B) supported

DMA Controller (8 channels)

DMA Controller has an independent bus for CPU, so CPU and

DMA Controller can process simultaneously.

◼Capable of pull-up control per pin

◼Capable of reading pin level directly

◼Built-in the port relocate function

◼8 independently configured and operated channels

◼Transfer can be started by software or request from the built-

in peripherals

◼Up to 100 high-speed general-purpose I/O ports @ 120 pin

Package

◼Transfer address area: 32-bit (4 Gbytes)

◼Some pin is 5V tolerant I/O.

◼Transfer mode: Block transfer/Burst transfer/Demand

transfer

◼See "Pin Description" and "I/O Circuit Type" for the

corresponding pins.

◼Transfer data type: bytes/half-word/word

◼Transfer block count: 1 to 16

◼Number of transfers: 1 to 65536

Document Number: 002-04868 Rev. *F

Page 2 of 167

CY9B460R Series

Multi-function Timer (Max 2 units)

Watch Counter

The Multi-function timer is composed of the following blocks.

The Watch counter is used for wake up from the low-power

consumption mode. It is possible to select the main clock, sub

clock, built-in high-speed CR clock or built-in low-speed CR

clock as the clock source.

Minimum resolution: 6.25 ns

◼16-bit free-run timer × 3 ch./unit

◼Input capture × 4 ch./unit

Interval timer: up to 64s (Max) @ Sub Clock: 32.768 kHz

◼Output compare × 6 ch./unit

◼A/D activation compare × 6 ch./unit

◼Waveform generator × 3 ch./unit

External Interrupt Controller Unit

◼External interrupt input pin: Max 16 pins

◼Include one non-maskable interrupt (NMI)

◼16-bit PPG timer × 3 ch./unit

The following function can be used to achieve the motor

control.

Watchdog Timer (2 channels)

A watchdog timer can generate interrupts or a reset when a

time-out value is reached.

◼PWM signal output function

This series consists of two different watchdogs, a "Hardware"

watchdog and a "Software" watchdog.

◼DC chopper waveform output function

◼Dead time function

"Hardware" watchdog timer is clocked by low-speed internal

CR oscillator. Therefore, "Hardware" watchdog is active in any

power saving mode except STOP.

◼Input capture function

◼A/D convertor activate function

◼DTIF (Motor emergency stop) interrupt function

CRC (Cyclic Redundancy Check) Accelerator

The CRC accelerator helps a verify data transmission or

storage integrity.

Real-time clock (RTC)

The Real-time clock can count Year/Month/Day/Hour/Minute/

Second/A day of the week from 00 to 99.

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

◼CCITT CRC16 Generator Polynomial: 0x1021

◼Interrupt function with specifying date and time

(Year/Month/Day/Hour/Minute) is available. This function is

also available by specifying only Year, Month, Day, Hour or

Minute.

◼IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

SD Card Interface

It is possible to use the SD card that conforms to the following

standards.

◼Timer interrupt function after set time or each set time.

◼Capable of rewriting the time with continuing the time count.

◼Leap year automatic count is available.

◼Part 1 Physical Layer Specification version 3.01

◼Part E1 SDIO Specification version 3.00

◼Part A2 SD Host Controller Standard Specification version

3.00

Quadrature Position/Revolution Counter (QPRC)

(Max 2 channels)

The Quadrature Position/Revolution Counter (QPRC) is used

to measure the position of the position encoder. Moreover, it is

possible to use up/down counter.

◼1-bit or 4-bit data bus

Clock and Reset

◼The detection edge of the three external event input pins

AIN, BIN and ZIN is configurable.

[Clocks]

Five clock sources (2 external oscillators, 2 internal CR

oscillator, and Main PLL) that are dynamically selectable.

◼16-bit position counter

◼16-bit revolution counter

◼Two 16-bit compare registers

◼Main clock:

◼Sub Clock:

4 MHz to 48 MHz

32.768 kHz

◼High-speed internal CR Clock: 4 MHz

◼Low-speed internal CR Clock: 100 kHz

◼Main PLL Clock

Dual Timer (32-/16-bit Down Counter)

The Dual Timer consists of two programmable 32-/16-bit down

counters.

Operation mode is selectable from the followings for each

channel.

◼Free-running

◼Periodic (=Reload)

◼One-shot

Document Number: 002-04868 Rev. *F

Page 3 of 167

CY9B460R Series

[Resets]

VBAT

The consumption power during the RTC operation can be

reduced by supplying the power supply independent from the

RTC (calendar circuit)/32 kHz oscillation circuit. The following

circuits can also be used.

◼Reset requests from INITX pin

◼Power on reset

◼Software reset

◼RTC

◼Watchdog timers reset

◼Low voltage detector reset

◼Clock supervisor reset

◼32 kHz oscillation circuit

◼Power-on circuit

◼Back up register: 32 bytes

◼Port circuit

Clock Super Visor (CSV)

Clocks generated by internal CR oscillators are used to

supervise abnormality of the external clocks.

Debug

◼External OSC clock failure (clock stop) is detected, reset is

asserted.

◼Serial Wire JTAG Debug Port (SWJ-DP)

◼Embedded Trace Macrocells (ETM) provide comprehensive

debug and trace facilities.

◼External OSC frequency anomaly is detected, interrupt or

reset is asserted.

Unique ID

Unique value of the device (41-bit) is set.

Low-Voltage Detector (LVD)

This Series include 2-stage monitoring of voltage on the VCC

pins. When the voltage falls below the voltage has been set,

Low-Voltage Detector generates an interrupt or reset.

Power Supply

◼Two Power Supplies

◼LVD1: error reporting via interrupt

◼LVD2: auto-reset operation

◼Wide range voltage:

VCC

= 2.7 V to 5.5 V

◼Power supply for VBAT:

VBAT

Low-power Consumption Mode

Six low-power consumption modes are supported.

◼SLEEP

◼TIMER

◼RTC

◼STOP

◼Deep standby RTC (selectable from with/without RAM

retention)

◼Deep standby stop (selectable from with/without RAM

retention)

Document Number: 002-04868 Rev. *F

Page 4 of 167

CY9B460R Series

Contents

1. Product Lineup.................................................................................................................................................................. 7

2. Packages ........................................................................................................................................................................... 9

3. Pin Assignment............................................................................................................................................................... 10

4. Pin Description................................................................................................................................................................ 16

5. I/O Circuit Type................................................................................................................................................................ 45

6. Handling Precautions ..................................................................................................................................................... 53

6.1

6.2

6.3

Precautions for Product Design................................................................................................................................... 53

Precautions for Package Mounting.............................................................................................................................. 54

Precautions for Use Environment................................................................................................................................ 55

7. Handling Devices ............................................................................................................................................................ 56

8. Block Diagram................................................................................................................................................................. 59

9. Memory Size .................................................................................................................................................................... 60

10. Memory Map .................................................................................................................................................................... 60

11. Pin Status in Each CPU State ........................................................................................................................................ 63

12. Electrical Characteristics ............................................................................................................................................... 71

12.1 Absolute Maximum Ratings......................................................................................................................................... 71

12.2 Recommended Operating Conditions.......................................................................................................................... 72

12.3 DC Characteristics....................................................................................................................................................... 75

12.3.1 Current Rating.............................................................................................................................................................. 75

12.3.2 Pin Characteristics ....................................................................................................................................................... 83

12.4 AC Characteristics....................................................................................................................................................... 85

12.4.1 Main Clock Input Characteristics.................................................................................................................................. 85

12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 86

12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 86

12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)......................................... 87

12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) .... 87

12.4.6 Reset Input Characteristics.......................................................................................................................................... 87

12.4.7 Power-on Reset Timing................................................................................................................................................ 88

12.4.8 GPIO Output Characteristics........................................................................................................................................ 88

12.4.9 External Bus Timing..................................................................................................................................................... 89

12.4.10 Base Timer Input Timing......................................................................................................................................... 102

12.4.11 CSIO/UART Timing ................................................................................................................................................ 103

12.4.12 External Input Timing.............................................................................................................................................. 136

12.4.13 Quadrature Position/Revolution Counter Timing .................................................................................................... 137

12.4.14 I²C Timing............................................................................................................................................................... 139

12.4.15 SD Card Interface Timing ....................................................................................................................................... 142

12.4.16 ETM Timing ............................................................................................................................................................ 144

12.4.17 JTAG Timing........................................................................................................................................................... 145

12.5 12-bit A/D Converter.................................................................................................................................................. 146

12.6 12-bit D/A Converter.................................................................................................................................................. 149

12.7 Low-Voltage Detection Characteristics...................................................................................................................... 150

12.7.1 Low-Voltage Detection Reset..................................................................................................................................... 150

12.7.2 Interrupt of Low-Voltage Detection............................................................................................................................. 150

12.8 MainFlash Memory Write/Erase Characteristics........................................................................................................ 151

12.9 WorkFlash Memory Write/Erase Characteristics....................................................................................................... 151

12.10 Standby Recovery Time ............................................................................................................................................ 152

12.10.1 Recovery cause: Interrupt/WKUP........................................................................................................................... 152

12.10.2 Recovery cause: Reset........................................................................................................................................... 154

Document Number: 002-04868 Rev. *F

Page 5 of 167

CY9B460R Series

13. Ordering Information .................................................................................................................................................... 156

14. Package Dimensions .................................................................................................................................................... 157

15. Major Changes .............................................................................................................................................................. 164

Document History............................................................................................................................................................... 165

Sales, Solutions, and Legal Information........................................................................................................................... 167

Document Number: 002-04868 Rev. *F

Page 6 of 167

CY9B460R Series

1. Product Lineup

Memory Size

Product name

CY9BF466M/N/R

512 Kbytes

CY9BF467M/N/R

768 Kbytes

CY9BF468M/N/R

1024 Kbytes

MainFlash memory

WorkFlash memory

On-chip SRAM

SRAM0

32 Kbytes

64 Kbytes

32 Kbytes

16 Kbytes

32 Kbytes

96 Kbytes

48 Kbytes

24 Kbytes

32 Kbytes

128 Kbytes

64 Kbytes

32 Kbytes

SRAM1

Document Number: 002-04868 Rev. *F

Page 7 of 167

CY9B460R Series

Function

CY9BF466M

CY9BF467M

CY9BF468M

CY9BF466N

CY9BF467N

CY9BF468N

CY9BF466R

CY9BF467R

CY9BF468R

Product name

Pin count

CPU

80

100/112

120/144

Cortex-M4F, MPU, NVIC 128ch.

Freq.

160 MHz

2.7 V to 5.5 V

2 ch. (Max)

8 ch.

Power supply voltage range

CAN

DMAC

DSTC

128 ch.

Addr:25-bit (Max),

R/W data: 8/16-bit

(Max),

Addr:25-bit (Max),

R/W data: 8/16-bit

(Max),

Addr:19-bit (Max),

R/W data: 8-bit

(Max),

CS:5 (Max),

SRAM,

External Bus Interface

CS:9 (Max),

SRAM,

NOR Flash,

SDRAM

CS:9 (Max),

SRAM,

NOR Flash,

NAND Flash, SDRAM

NOR Flash

Multi-function Serial Interface

8 ch. (Max)

(UART/CSIO/LIN/I²C)

Base Timer

(PWC/Reload timer/PWM/PPG)

A/D activation compare

Input capture

6 ch.

4 ch.

3 ch.

6 ch.

3 ch.

Free-run timer

Output compare

Waveform generator

PPG

2 units (Max)

SD Card Interface

QPRC

1 unit

2 ch. (Max)

1 unit

Dual Timer

Real-Time Clock

Watch Counter

CRC Accelerator

Watchdog Timer

External Interrupts

I/O Ports

1 unit

Yes

1 ch. (SW) + 1 ch. (HW)

16 pins (Max) + NMI × 1

63 pins (Max)

16 ch. (3 units)

80 pins (Max)

24 ch. (3 units)

100 pins (Max)

12-bit A/D Converter

12-bit D/A Converter

2 units (Max)

CSV (Clock Super Visor)

Yes

LVD (Low-Voltage Detector)

2 ch.

High-speed

Built-in CR

4 MHz

100 kHz

SWJ-DP/ETM

Yes

Low-speed

Debug Function

Unique ID

Notes:

−

All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.

It is necessary to use the port relocate function of the I/O port according to your function use.

−

See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics” for accuracy of

built-in CR.

Document Number: 002-04868 Rev. *F

Page 8 of 167

CY9B460R Series

2. Packages

CY9BF466M

CY9BF467M

CY9BF468M

CY9BF466N

CY9BF467N

CY9BF468N

CY9BF466R

CY9BF467R

CY9BF468R

Product name

Package

LQFP: LQH080 (0.5 mm pitch)

LQFP: LQJ080 (0.65 mm pitch)

QFP: PQH100 (0.65 mm pitch)

LQFP: LQI100 (0.5 mm pitch)

LQFP: LQM120 (0.5 mm pitch)

BGA: LDC112 (0.5 mm pitch)

BGA: LDC144 (0.5 mm pitch)



-



-



-



-



: Supported

Note:

−

See "Package Dimensions" for detailed information on each package.

Document Number: 002-04868 Rev. *F

Page 9 of 167

CY9B460R Series

3. Pin Assignment

LQH080/LQJ080

(TOP VIEW)

VCC

1

2

3

4

5

6

7

8

9

60 VSS

P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0

P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0

P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0

59 P21/AN17/SIN0_0/INT06_1

58 P22/CROUT_0/AN16/TIOB7_1/SOT0_0

57 P23/AN15/TIOA7_1/SCK0_0/RTO00_1

56 P1B/AN11/SCK4_1/IC02_1/MAD18_0

55 P1A/AN10/SOT4_1/IC01_1/MAD17_0

54 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0

53 P18/AN08/SCK2_2/MAD15_0

P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0

P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0

P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0

P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0

P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0

52 AVRH

P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10

P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11

P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12

P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 13

P3A/TIOA0_1/AIN0_0/RTO00_0 14

51 AVRL

50 AVSS

LQFP - 80

49 AVCC

48 P17/AN07/SOT2_2/WKUP3/MAD14_0

47 P16/AN06/SIN2_2/INT14_1/MAD13_0

46 P15/AN05/SCK0_1/MAD12_0

P3B/TIOA1_1/BIN0_0/RTO01_0 15

P3C/TIOA2_1/ZIN0_0/RTO02_0 16

45 P14/AN04/SOT0_1/IC03_2/MAD11_0

44 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0

43 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0

42 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0

41 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0

P3D/TIOA3_1/RTO03_0/MAD00_0 17

P3E/TIOA4_1/RTO04_0/MAD01_0 18

P3F/TIOA5_1/RTO05_0/MAD02_0 19

VSS 20

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-04868 Rev. *F

Page 10 of 167

CY9B460R Series

LQI100

(TOP VIEW)

VCC

P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0

P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0

P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0

1

2

3

4

5

6

7

8

9

75 VSS

74 P20/AN18/AIN1_1/INT05_0/MAD24_0

73 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0

72 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1

71 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0

70 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0

69 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0

68 P1C/AN12/CTS4_1/IC03_1/MAD19_0

67 P1B/AN11/SCK4_1/IC02_1/MAD18_0

66 P1A/AN10/SOT4_1/IC01_1/MAD17_0

65 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0

64 P18/AN08/SCK2_2/MAD15_0

P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0

P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0

P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0

P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0

P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0

P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 10

P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 11

P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 12

P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0 13

P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0 14

P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 15

P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 16

P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 17

P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 18

P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 19

P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 20

P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 21

P3D/TIOA3_1/RTO03_0/MAD00_0 22

LQFP - 100

63 AVRH

62 AVRL

61 AVSS

60 AVCC

59 P17/AN07/SOT2_2/WKUP3/MAD14_0

58 P16/AN06/SIN2_2/INT14_1/MAD13_0

57 P15/AN05/SCK0_1/MAD12_0

56 P14/AN04/SOT0_1/IC03_2/MAD11_0

55 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0

54 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0

53 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0

52 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0

51 VCC

P3E/TIOA4_1/RTO04_0/MAD01_0 23

P3F/TIOA5_1/RTO05_0/MAD02_0 24

VSS 25

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-04868 Rev. *F

Page 11 of 167

CY9B460R Series

LQM120

(TOP VIEW)

VCC

P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0

P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0

P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0

P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0

P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0

P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0

P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0

P57/SCK6_0/MADATA07_0

1

2

3

4

5

6

7

8

9

90 VSS

89 P20/AN18/AIN1_1/INT05_0/MAD24_0

88 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0

87 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1

86 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0

85 P24/RX1_0/SIN2_1/RTO01_1/INT01_2

84 P25/TX1_0/TIOA5_0/SOT2_1/RTO02_1

83 P26/TIOB5_0/SCK2_1/RTO03_1

82 P27/TIOA6_2/RTO04_1/INT02_2

81 P1F/ADTG_4/TIOB6_2/RTO05_1

80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0

79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0

78 P1C/AN12/CTS4_1/IC03_1/MAD19_0

77 P1B/AN11/SCK4_1/IC02_1/MAD18_0

76 P1A/AN10/SOT4_1/IC01_1/MAD17_0

75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0

74 P18/AN08/SCK2_2/MAD15_0

P58/SIN4_2/AIN1_0/INT04_2/MADATA08_0 10

P59/RX1_1/SOT4_2/BIN1_0/INT07_1/MADATA09_0 11

P5A/TX1_1/SCK4_2/ZIN1_0/MADATA10_0 12

P5B/CTS4_2/MADATA11_0 13

LQFP - 120

P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_0 14

P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_0 15

P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_0 16

P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_0 17

P34/TX0_1/TIOB4_1/FRCK0_0/MNALE_0 18

P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MNCLE_0 19

P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 20

P37/SOT5_2/IC01_0/INT05_2/MNREX_0 21

P38/SCK5_2/IC00_0/INT06_2 22

73 AVRH

72 AVRL

71 AVSS

70 AVCC

69 P17/AN07/SOT2_2/WKUP3/MAD14_0

68 P16/AN06/SIN2_2/INT14_1/MAD13_0

67 P15/AN05/SCK0_1/MAD12_0

P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 23

P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 24

P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 25

P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 26

P3D/TIOA3_1/RTO03_0/MAD00_0 27

66 P14/AN04/SOT0_1/IC03_2/MAD11_0

65 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0

64 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0

63 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0

62 P10/AN00/RX1_2/SIN1_1/FRCK0_2/INT02_1/MAD07_0

61 VCC

P3E/TIOA4_1/RTO04_0/MAD01_0 28

P3F/TIOA5_1/RTO05_0/MAD02_0 29

VSS 30

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-04868 Rev. *F

Page 12 of 167

CY9B460R Series

PQH100

(TOP VIEW)

P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_0 81

P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_0 82

P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_0 83

P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_0 84

P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 85

P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 86

P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_0 87

P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_0 88

P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_0 89

P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_0 90

P34/TX0_1/TIOB4_1/FRCK0_0/MADATA11_0 91

P35/RX0_1/TIOB5_1/IC03_0/INT08_1/MADATA12_0 92

P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 93

50 P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1

49 P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0

48 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0

47 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0

46 P1C/AN12/CTS4_1/IC03_1/MAD19_0

45 P1B/AN11/SCK4_1/IC02_1/MAD18_0

44 P1A/AN10/SOT4_1/IC01_1/MAD17_0

43 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0

42 P18/AN08/SCK2_2/MAD15_0

QFP - 100

41 AVRH

40 AVRL

39 AVSS

38 AVCC

P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 94

P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 95

P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_0 96

P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_0 97

P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_0 98

37 P17/AN07/SOT2_2/WKUP3/MAD14_0

36 P16/AN06/SIN2_2/INT14_1/MAD13_0

35 P15/AN05/SCK0_1/MAD12_0

34 P14/AN04/SOT0_1/IC03_2/MAD11_0

33 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0

32 P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0

31 P11/AN01/TX1_2/SOT1_1/IC00_2/MAD08_0

P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_0 99

P3D/TIOA3_1/RTO03_0/MAD00_0 100

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-04868 Rev. *F

Page 13 of 167

CY9B460R Series

LDC112

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

TCK/

SWCLK

A

B

C

D

E

F

VSS

VCC

P50

P53

P55

P31

P34

VSS

P39

P3C

P3E

VCC

VSS

P81

VSS

P51

P54

P56

P32

P35

P37

P3A

P3D

P3F

VSS

P40

P80

P60

P52

VCC

P61

VSS

AN21

AN22

AN23

P0A

AN19

AN20

P0B

P0C

VSS

P0D

VSS

P0E

VSS

VCC

AN17

AN15

TMS/

SWDIO

P62 TRSTX

TDO/

SWO

P63

TDI

AN18

AN16

index

P30

P33

P36

P38

P3B

AN14

AN12

AN10

AN08

AN06

AN13 AVRH

AN11 AVRL

AN09 AVSS

AN07 AVCC

G

H

J

AN05

AN03

AN01

VSS

X1

AN04

AN02

AN00

VCC

VSS

K

L

P43

P42

P41

P45

VSS

X0A

P48

INITX

X1A

P4B

P49

VSS

P4C

VCC

VBAT

P4E

P4D

C

VSS

MD0

X0

M

N

P44

MD1

VSS

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-04868 Rev. *F

Page 14 of 167

CY9B460R Series

LDC144

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

A

B

C

D

E

F

VSS

VCC

P50

P52

P55

P59

P31

P35

P39

VSS

P3F

VCC

VSS

P81

VSS

P51

P53

P56

P5A

P32

P36

P3A

P3D

P41

VSS

P40

P80

P60

VSS

P54

P57

P5B

P33

P37

P3B

P3E

VSS

P43

P42

VCC

P61

P62

VSS

P58

P30

P34

P38

P3C

VSS

P44

VSS

INITX

VSS

P63

P64

P66

P67

P68

VSS

TCK/

VSS

TDO/

AN21

AN20

AN19

P0A

VSS

P0B

P0D

VSS

P24

P0C

VSS

AN17

P25

VCC

VSS

P0E

SWCLK SWO

TDI

AN23

AN22

AN18

AN16

P26

VSS

AN15

P27

TMS/

SWDIO

P65 TRSTX

index

P1F

AN14

AN10

AN07

AN04

AN02

VSS

MD0

X0

AN13

AN12

G

H

J

AN11

AN08

AN05

VSS

P74

AN09 AVRH

AN06 AVRL

AN03 AVSS

AN01 AVCC

K

L

P45

VSS

X1A

X0A

P49

P48

VSS

P4C

P4B

P70

P4E

P4D

C

P72

P71

VCC

VSS

AN00

VSS

X1

VSS

VCC

VSS

M

N

VSS

VBAT

P73

MD1

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-04868 Rev. *F

Page 15 of 167

CY9B460R Series

4. Pin Description

List of pin numbers

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these

pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)

to select the pin

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

LQFP120

LQFP100

QFP100

79

BGA112

B1

BGA144

B1

1

VCC

-

P50

CTS4_0

AIN0_2

2

3

4

5

6

7

2

3

4

5

6

7

2

3

4

5

6

7

80

81

82

83

84

85

C1

C2

C3

D1

D2

E1

C1

C2

D1

D2

D3

E1

E

K

I

RTO10_0

(PPG10_0)

INT00_0

MADATA00_0

P51

RTS4_0

BIN0_2

RTO11_0

(PPG10_0)

INT01_0

MADATA01_0

P52

SCK4_0

(SCL4_0)

ZIN0_2

RTO12_0

(PPG12_0)

MADATA02_0

P53

TIOA1_2

SOT4_0

(SDA4_0)

I

RTO13_0

(PPG12_0)

MADATA03_0

P54

TIOB1_2

SIN4_0

K

RTO14_0

(PPG14_0)

INT02_0

MADATA04_0

P55

ADTG_1

SIN6_0

K

RTO15_0

(PPG14_0)

INT07_2

MADATA05_0

Document Number: 002-04868 Rev. *F

Page 16 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

P56

LQFP120

LQFP100

QFP100

BGA112

BGA144

SOT6_0

(SDA6_0)

8

86

E2

E

K

DTTI1X_0

INT08_2

MADATA06_0

P57

SCK6_0

9

-

E3

E4

E

I

(SCL6_0)

MADATA07_0

P58

SIN4_2

10

AIN1_0

K

INT04_2

MADATA08_0

P59

RX1_1

SOT4_2

(SDA4_2)

11

-

F1

E

K

BIN1_0

INT07_1

MADATA09_0

P5A

TX1_1

SCK4_2

12

-

F2

E

I

(SCL4_2)

ZIN1_0

MADATA10_0

P5B

13

14

-

F3

F4

CTS4_2

MADATA11_0

P30

TIOB0_1

RTS4_2

9

87

E3

E

Q

INT15_2

WKUP1

-

MADATA07_0

MADATA12_0

P31

14

-

F4

TIOB1_1

SIN3_1

15

G1

10

-

10

-

88

-

F1

-

I

K

INT09_2

-

MADATA08_0

MADATA13_0

15

G1

Document Number: 002-04868 Rev. *F

Page 17 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

P32

LQFP120

LQFP100

QFP100

BGA112

BGA144

TIOB2_1

16

G2

SOT3_1

11

-

89

F2

-

(SDA3_1)

N

K

INT10_1

-

MADATA09_0

MADATA14_0

P33

16

-

G2

ADTG_6

TIOB3_1

17

G3

12

90

F3

SCK3_1

N

K

(SCL3_1)

INT04_0

MADATA10_0

MADATA15_0

P34

-

17

-

G3

TX0_1

18

G4

13

-

91

-

G1

-

TIOB4_1

FRCK0_0

MADATA11_0

MNALE_0

P35

E

I

-

18

G4

RX0_1

19

H1

TIOB5_1

IC03_0

14

-

92

-

G2

-

E

K

INT08_1

MADATA12_0

MNCLE_0

-

19

H1

Document Number: 002-04868 Rev. *F

Page 18 of 167

CY9B460R Series

Pin No

I/O circuit

type

Pin state

type

Pin Name

P36

LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144

SIN5_2

20

H2

15

-

93

-

G3

-

IC02_0

E

K

INT09_1

MADATA13_0

MNWEX_0

P37

-

20

H2

SOT5_2

(SDA5_2)

21

H3

16

-

94

-

H2

-

E

K

IC01_0

INT05_2

MADATA14_0

MNREX_0

P38

-

21

H3

SCK5_2

(SCL5_2)

22

-

H4

-

17

95

H3

E

K

IC00_0

INT06_2

MADATA15_0

P39

ADTG_2

DTTI0X_0

RTCCO_2

SUBOUT_2

MSDCLK_0

P3A

13

-

23

24

25

18

19

20

96

97

98

J1

J2

J3

J1

J2

J3

L

I

TIOA0_1

AIN0_0

14

-

G

I

RTO00_0

(PPG00_0)

MSDCKE_0

P3B

TIOA1_1

BIN0_0

15

-

I

RTO01_0

(PPG00_0)

MRASX_0

Document Number: 002-04868 Rev. *F

Page 19 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

P3C

LQFP120

LQFP100

QFP100

BGA112

BGA144

TIOA2_1

ZIN0_0

16

-

26

21

99

K1

J4

G

I

RTO02_0

(PPG02_0)

MCASX_0

P3D

TIOA3_1

27

28

29

22

23

24

17

100

K2

L1

L2

K2

K3

L1

G

I

RTO03_0

(PPG02_0)

MAD00_0

P3E

TIOA4_1

18

19

1

RTO04_0

(PPG04_0)

MAD01_0

P3F

TIOA5_1

2

RTO05_0

(PPG04_0)

MAD02_0

VSS

30

31

25

26

20

-

3

4

N1

M1

N1

M1

-

VCC

P40

TIOA0_0

32

33

34

27

28

29

-

5

6

7

N2

N3

M3

N2

L2

N3

G

K

I

RTO10_1

(PPG10_1)

INT12_1

P41

TIOA1_0

RTO11_1

(PPG10_1)

INT13_1

P42

TIOA2_0

RTO12_1

(PPG12_1)

MSDWEX_0

P43

ADTG_7

TIOA3_0

35

30

-

8

L3

M3

G

I

RTO13_1

(PPG12_1)

MCSX8_0

Document Number: 002-04868 Rev. *F

Page 20 of 167

CY9B460R Series

Pin No

LQFP80 QFP100

I/O circuit

type

Pin state

type

Pin Name

P44

LQFP120

LQFP100

BGA112

BGA144

TIOA4_0

36

31

21

22

9

M4

L4

R

J

RTO14_1

(PPG14_1)

DA0

P45

TIOB0_0

37

32

10

L5

K5

J

RTO15_1

(PPG14_1)

DA1

38

39

33

34

23

24

11

12

M6

N5

N4

N5

INITX

P46

B

P

C

S

X0A

P47

40

41

42

35

36

37

25

26

27

13

14

15

N6

L6

M5

L6

Q

O

T

X1A

P48

U

VREGCTL

P49

M7

K6

VWAKEUP

VBAT

C

43

44

45

46

38

39

40

41

28

29

30

31

16

17

18

19

N8

N7

N8

N9

M9

-

N9

N10

M8

VSS

VCC

P4B

TIOB1_0

SCS7_1

MAD03_0

P4C

47

42

32

20

L7

L8

L7

E

I

TIOB2_0

SCK7_1

48

43

33

21

K7

N

I

(SCL7_1)

AIN1_2

MAD04_0

P4D

TIOB3_0

SOT7_1

(SDA7_1)

49

44

34

22

M9

M8

N

K

BIN1_2

INT13_2

MAD05_0

P4E

TIOB4_0

SIN7_1

ZIN1_2

50

45

35

23

L9

L8

I

Q

FRCK1_1

INT11_1

WKUP2

MAD06_0

Document Number: 002-04868 Rev. *F

Page 21 of 167

CY9B460R Series

Pin No

LQFP80 QFP100

I/O circuit

type

Pin state

type

Pin Name

P70

LQFP120

LQFP100

BGA112

BGA144

TX0_0

51

-

K8

TIOA4_2

AIN0_1

IC13_1

P71

E

I

RX0_0

TIOB4_2

BIN0_1

IC12_1

INT15_1

P72

52

53

-

L9

K

TIOA6_0

SIN2_0

ZIN0_1

IC11_1

INT14_2

P73

-

K9

E

TIOB6_0

SOT2_0

54

55

-

M10

L10

E

K

(SDA2_0)

IC10_1

INT03_2

P74

SCK2_0

I

(SCL2_0)

DTTI1X_1

PE0

56

57

58

46

47

48

36

37

38

24

25

26

M10

M11

N11

N10

M11

N11

C

J

E

D

A

MD1

MD0

PE2

A

X0

PE3

59

49

39

27

N12

A

B

X1

60

61

50

51

40

-

28

29

N13

M13

N13

M13

VSS

-

VCC

P10

AN00

RX1_2

SIN1_1

FRCK0_2

INT02_1

MAD07_0

62

52

41

30

L13

L12

F

M

Document Number: 002-04868 Rev. *F

Page 22 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

P11

LQFP120

LQFP100

QFP100

BGA112

BGA144

AN01

TX1_2

63

53

42

31

L12

K12

F

L

SOT1_1

(SDA1_1)

IC00_2

MAD08_0

P12

AN02

SCK1_1

(SCL1_1)

64

54

43

32

K13

K11

F

L

IC01_2

RTCCO_1

SUBOUT_1

MAD09_0

P13

AN03

SIN0_1

IC02_2

INT03_1

MAD10_0

P14

65

66

55

56

44

45

33

34

K12

J13

J12

J11

F

M

AN04

SOT0_1

L

(SDA0_1)

IC03_2

MAD11_0

P15

AN05

67

68

57

58

46

47

35

36

J12

J11

J10

F

L

SCK0_1

(SCL0_1)

MAD12_0

P16

AN06

H12

SIN2_2

INT14_1

MAD13_0

P17

M

AN07

SOT2_2

69

59

48

37

H12

H11

F

P

(SDA2_2)

WKUP3

MAD14_0

AVCC

70

71

72

73

60

61

62

63

49

50

51

52

38

39

40

41

H13

G13

F13

E13

K13

J13

H13

G13

-

AVSS

AVRL

AVRH

Document Number: 002-04868 Rev. *F

Page 23 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

P18

LQFP120

LQFP100

QFP100

BGA112

BGA144

AN08

74

64

53

42

H11

H10

F

L

SCK2_2

(SCL2_2)

MAD15_0

P19

AN09

SIN4_1

IC00_1

INT05_1

MAD16_0

P1A

75

76

77

65

66

67

54

43

44

45

G12

G11

F12

G12

G11

G10

M

AN10

SOT4_1

55

56

M

L

(SDA4_1)

IC01_1

MAD17_0

P1B

AN11

SCK4_1

L

(SCL4_1)

IC02_1

MAD18_0

P1C

AN12

78

79

80

81

82

68

69

70

-

46

47

48

-

F11

E12

E11

-

F13

F12

F11

F10

E13

CTS4_1

IC03_1

MAD19_0

P1D

F

E

L

I

AN13

RTS4_1

DTTI0X_1

MAD20_0

P1E

AN14

ADTG_5

FRCK0_1

MAD21_0

P1F

ADTG_4

TIOB6_2

RTO05_1

(PPG04_1)

P27

TIOA6_2

-

K

RTO04_1

(PPG04_1)

INT02_2

Document Number: 002-04868 Rev. *F

Page 24 of 167

CY9B460R Series

Pin No

LQFP80 QFP100

I/O circuit

type

Pin state

type

Pin Name

P26

LQFP120

LQFP100

BGA112

BGA144

TIOB5_0

SCK2_1

83

-

E12

E

I

(SCL2_1)

RTO03_1

(PPG02_1)

P25

TX1_0

TIOA5_0

84

-

E11

I

SOT2_1

(SDA2_1)

RTO02_1

(PPG02_1)

P24

RX1_0

SIN2_1

85

-

E10

K

RTO01_1

(PPG00_1)

INT01_2

P23

AN15

TIOA7_1

57

SCK0_0

86

71

49

D13

F

L

(SCL0_0)

RTO00_1

(PPG00_1)

-

MAD22_0

P22

CROUT_0

AN16

58

87

72

50

D12

TIOB7_1

F

L

SOT0_0

(SDA0_0)

-

ZIN1_1

P21

59

AN17

SIN0_0

BIN1_1

INT06_1

MAD23_0

P20

88

89

73

74

51

52

C13

C12

D11

C12

F

M

-

59

-

AN18

-

AIN1_1

INT05_0

MAD24_0

VSS

90

91

75

76

60

61

53

54

A13

B13

A13

A12

-

VCC

Document Number: 002-04868 Rev. *F

Page 25 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

P0E

LQFP120

LQFP100

QFP100

BGA112

BGA144

TIOB5_2

SCS6_1

IC13_0

92

77

62

55

A12

B13

L

I

S_CLK_0

MDQM1_0

P0D

TIOA5_2

SCK6_1

(SCL6_1)

93

78

63

56

B11

C10

L

I

IC12_0

S_CMD_0

MDQM0_0

P0C

TIOA6_1

SOT6_1

(SDA6_1)

94

79

64

57

B10

A11

L

I

IC11_0

S_DATA1_0

MALE_0

P0B

TIOB6_1

SIN6_1

95

80

65

58

A10

B10

IC10_0

L

K

INT00_1

S_DATA0_0

MCSX0_0

P0A

SIN1_0

FRCK1_0

INT12_2

S_DATA3_0

MCSX1_0

P09

96

81

66

59

A9

D9

L

K

67

-

AN19

TRACED0

TIOA3_2

97

82

60

B9

C9

M

N

SOT1_0

(SDA1_0)

67

S_DATA2_0

MCSX5_0

P08

AN20

TRACED1

TIOB3_2

98

83

-

61

C9

B9

F

N

SCK1_0

(SCL1_0)

MCSX4_0

Document Number: 002-04868 Rev. *F

Page 26 of 167

CY9B460R Series

Pin No

LQFP80 QFP100

I/O circuit

type

Pin state

type

Pin Name

P07

LQFP120

LQFP100

BGA112

BGA144

AN21

TRACED2

TIOA0_2

99

84

-

62

63

64

A8

A9

F

N

SCK7_0

(SCL7_0)

MCLKOUT_0

P06

AN22

TRACED3

TIOB0_2

100

85

-

B8

D8

N

SOT7_0

(SDA7_0)

MCSX3_0

P05

AN23

ADTG_0

TRACECLK

SIN7_0

INT01_1

MCSX2_0

P04

101

86

-

C8

O

102

103

104

105

87

88

89

90

68

69

70

71

65

66

67

68

C7

B7

C6

A6

B8

D7

C7

B7

TDO

E

G

H

G

SWO

P03

TMS

SWDIO

P02

TDI

MCSX6_0

P01

TCK

SWCLK

P00

106

107

91

92

72

-

69

70

B6

A5

D6

A7

TRSTX

MCSX7_0

VSS

E

-

H

-

P68

TIOB7_2

108

109

-

C6

B6

E

K

SCK3_0

(SCL3_0)

INT00_2

P67

TIOA7_2

I

SOT3_0

(SDA3_0)

Document Number: 002-04868 Rev. *F

Page 27 of 167

CY9B460R Series

Pin No

LQFP80 QFP100

I/O circuit

type

Pin state

type

Pin Name

P66

LQFP120

LQFP100

BGA112

BGA144

ADTG_8

SIN3_0

INT11_2

P65

110

-

A6

E

K

TIOB7_0

111

112

-

D5

C5

I

SCK5_1

(SCL5_1)

P64

TIOA7_0

-

E

K

SOT5_1

(SDA5_1)

INT10_2

P63

93

-

73

-

71

-

C5

-

CROUT_1

RX0_2

113

B5

SIN5_1

INT03_0

S_CD_0

MWEX_0

P62

K

93

73

71

C5

ADTG_3

TX0_2

114

115

116

94

95

96

74

75

76

72

73

74

B5

B4

B3

C4

B4

B3

SIN5_0

INT04_1

S_WP_0

MOEX_0

P61

I

K

TIOB2_2

SOT5_0

E

I

(SDA5_0)

RTCCO_0

SUBOUT_0

P60

TIOA2_2

SCK5_0

(SCL5_0)

I

F

NMIX

WKUP0

MRDY_0

VCC

117

118

119

97

98

99

77

78

79

75

76

77

A4

A3

A2

A4

A3

A2

-

P80

H

R

P81

Document Number: 002-04868 Rev. *F

Page 28 of 167

CY9B460R Series

Pin No

LQFP80

I/O circuit

type

Pin state

type

Pin Name

LQFP120

LQFP100

QFP100

BGA112

BGA144

A1

120

100

80

-

78

-

A1

A7

B2

B12

C11

H1

N4

M5

N7

L11

A11

M12

M2

-

A5

A8

A10

B2

B11

B12

C3

VSS

C11

C13

D4

D10

K1

K4

-

K10

L3

-

L5

-

L11

L13

M2

-

VSS

-

M4

-

M6

-

M7

-

M12

N6

-

Document Number: 002-04868 Rev. *F

Page 29 of 167

CY9B460R Series

List of pin functions

The number after the underscore (“_”) in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these

pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)

to select the pin.

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

BGA

112

BGA

144

120

100

80

100

ADTG_0

101

7

86

-

64

C8

ADTG_1

ADTG_2

ADTG_3

ADTG_4

ADTG_5

ADTG_6

ADTG_7

ADTG_8

AN00

7

85

96

72

-

E1

23

114

81

80

17

35

110

62

63

64

65

66

67

68

69

74

75

76

77

78

79

80

86

87

88

89

97

98

99

100

101

32

24

99

37

14

100

33

25

5

18

94

-

13

74

-

J1

B5

C4

A/D converter external trigger input pin

-

F10

F11

G3

70

12

30

-

48

90

8

E11

F3

12

-

L3

M3

A6

-

52

53

54

55

56

57

58

59

64

65

66

67

68

69

70

71

72

73

74

82

83

84

85

86

27

19

84

32

9

41

42

43

44

45

46

47

48

53

54

55

56

-

30

31

32

33

34

35

36

37

42

43

44

45

46

47

48

49

50

51

52

60

61

62

63

64

5

L13

L12

K13

K12

J13

J12

J11

H12

H11

G12

G11

F12

F11

E12

E11

D13

D12

C13

C12

B9

L12

K12

K11

J12

J11

J10

H12

H11

H10

G12

G11

G10

F13

F12

F11

D13

D12

D11

C12

C9

AN01

AN02

AN03

AN04

AN05

AN06

ADC

AN07

AN08

AN09

AN10

AN11

A/D converter analog input pin.

ANxx describes ADC ch.xx.

AN12

AN13

-

AN14

-

AN15

57

58

59

-

AN16

AN17

AN18

AN19

67

-

AN20

C9

B9

AN21

-

A8

A9

AN22

-

B8

D8

AN23

-

C8

TIOA0_0

TIOA0_1

TIOA0_2

TIOB0_0

TIOB0_1

TIOB0_2

TIOA1_0

TIOA1_1

TIOA1_2

TIOB1_0

TIOB1_1

TIOB1_2

-

N2

Base timer ch.0 TIOA pin

Base timer ch.0 TIOB pin

Base timer ch.1 TIOA pin

Base timer ch.1 TIOB pin

14

-

97

62

10

87

63

6

J2

A8

A9

Base

Timer 0

22

9

L5

K5

E3

F4

85

28

20

5

-

B8

D8

-

N3

L2

15

5

98

83

20

88

84

J3

D1

D2

Base

Timer 1

47

15

6

42

10

6

32

10

6

L7

F1

G1

D2

D3

Document Number: 002-04868 Rev. *F

Page 30 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

TIOA2_0

34 29

-

7

M3

K1

B3

L8

F2

B4

L3

K2

B9

M9

F3

C9

M4

L1

-

N3

TIOA2_1

TIOA2_2

TIOB2_0

TIOB2_1

TIOB2_2

TIOA3_0

TIOA3_1

TIOA3_2

TIOB3_0

TIOB3_1

TIOB3_2

TIOA4_0

TIOA4_1

TIOA4_2

TIOB4_0

TIOB4_1

TIOB4_2

TIOA5_0

TIOA5_1

TIOA5_2

TIOB5_0

TIOB5_1

TIOB5_2

TIOA6_0

TIOA6_1

TIOA6_2

TIOB6_0

TIOB6_1

TIOB6_2

TIOA7_0

TIOA7_1

TIOA7_2

TIOB7_0

TIOB7_1

TIOB7_2

TX0_0

Base timer ch.2 TIOA pin

26

116

48

16

115

35

27

97

49

17

98

36

28

51

50

18

52

84

29

93

83

19

92

53

94

82

54

95

81

112

86

109

111

87

108

51

18

114

52

19

113

84

12

63

85

11

62

21

96

43

11

95

30

22

82

44

12

83

31

23

-

16

76

33

11

75

-

99

74

21

89

73

8

J4

B3

Base

Timer 2

K7

Base timer ch.2 TIOB pin

Base timer ch.3 TIOA pin

Base timer ch.3 TIOB pin

Base timer ch.4 TIOA pin

Base timer ch.4 TIOB pin

Base timer ch.5 TIOA pin

Base timer ch.5 TIOB pin

Base timer ch.6 TIOA pin

Base timer ch.6 TIOB pin

Base timer ch.7 TIOA pin

Base timer ch.7 TIOB pin

CAN interface ch.0 TX output pin

CAN interface ch.0 RX output pin

CAN interface ch.1 TX output pin

CAN interface ch.1 RX output pin

G2

B4

M3

K2

17

67

34

12

-

100

60

22

90

61

9

C9

Base

Timer 3

M8

G3

B9

21

18

-

L4

1

K3

-

K8

Base

Timer 4

45

13

-

35

-

23

91

-

L9

G1

-

L8

G4

L9

-

E11

L1

24

78

-

19

63

-

2

L2

B11

-

56

-

C10

E12

H1

Base

Timer 5

14

77

-

92

55

-

G2

A12

-

62

-

B13

K9

79

-

64

-

57

-

B10

-

A11

E13

M10

B10

F10

C5

Base

Timer 6

-

80

-

65

-

58

-

A10

-

71

-

57

-

49

-

D13

-

D13

B6

Base

Timer 7

-

D5

72

-

58

-

50

-

D12

-

D12

C6

-

K8

TX0_1

13

94

-

91

72

-

G1

B5

-

G4

C4

TX0_2

74

-

CAN 0

RX0_0

L9

RX0_1

14

93

-

92

71

-

G2

C5

-

H1

RX0_2

73

-

B5

TX1_0

E11

F2

TX1_1

-

TX1_2

53

-

42

-

31

-

L12

-

K12

E10

F1

CAN 1

RX1_0

RX1_1

-

RX1_2

52

41

30

L13

L12

Document Number: 002-04868 Rev. *F

Page 31 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

BGA

112

BGA

144

120

100

80

100

SWCLK

Serial wire debug interface clock input pin

105

90

71

68

A6

B7

D7

Serial wire debug interface data input /

output pin

SWDIO

103

88

69

66

SWO

Serial wire viewer output pin

JTAG test clock input pin

102

105

104

102

103

101

97

87

90

89

87

88

86

82

83

84

85

91

22

23

24

42

43

44

45

52

53

54

55

56

57

58

59

64

65

66

67

68

69

70

71

73

74

68

71

70

68

69

-

65

68

67

65

66

64

60

61

62

63

69

100

1

C7

B8

TCK

A6

B7

TDI

JTAG test data input pin

C6

C7

TDO

JTAG debug data output pin

JTAG test mode state input/output pin

Trace CLK output pin of ETM

C7

B8

Debugger

TMS

B7

D7

TRACECLK

TRACED0

TRACED1

TRACED2

TRACED3

TRSTX

C8

-

B9

C9

98

-

C9

B9

Trace data output pin of ETM

JTAG test reset Input pin

99

-

A8

A9

100

106

27

-

B8

D8

72

17

18

19

32

33

34

35

41

42

43

44

45

46

47

48

53

54

55

56

-

B6

D6

MAD00_0

MAD01_0

MAD02_0

MAD03_0

MAD04_0

MAD05_0

MAD06_0

MAD07_0

MAD08_0

MAD09_0

MAD10_0

MAD11_0

MAD12_0

MAD13_0

MAD14_0

MAD15_0

MAD16_0

MAD17_0

MAD18_0

MAD19_0

MAD20_0

MAD21_0

MAD22_0

MAD23_0

MAD24_0

K2

28

L1

K3

29

2

L2

L1

47

20

21

22

23

30

31

32

33

34

35

36

37

42

43

44

45

46

47

48

49

51

52

L7

48

L8

K7

49

M9

L9

M8

L8

50

62

L13

L12

K13

K12

J13

J12

J11

H12

H11

G12

G11

F12

F11

E12

E11

D13

C13

C12

L12

K12

K11

J12

J11

J10

H12

H11

H10

G12

G11

G10

F13

F12

F11

D13

D11

C12

63

64

65

66

External

Bus

External bus interface address bus

67

68

69

74

75

76

77

78

79

-

80

-

86

-

88

-

89

-

Document Number: 002-04868 Rev. *F

Page 32 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

MCSX0_0

95 80 65 58

A10

A9

C8

B8

C9

B9

C6

B6

L3

B10

D9

C8

D8

B9

C9

C7

D6

M3

C1

C2

D1

D2

D3

E1

E2

E3

E4

F1

MCSX1_0

96

101

100

98

97

104

106

35

2

81

86

85

83

82

89

91

30

2

66

-

59

64

63

61

60

67

69

8

MCSX2_0

MCSX3_0

-

MCSX4_0

External bus interface chip select output pin

-

MCSX5_0

67

70

72

-

MCSX6_0

MCSX7_0

MCSX8_0

MADATA00_0

MADATA01_0

MADATA02_0

MADATA03_0

MADATA04_0

MADATA05_0

MADATA06_0

MADATA07_0

MADATA08_0

MADATA09_0

MADATA10_0

MADATA11_0

MADATA12_0

MADATA13_0

MADATA14_0

MADATA15_0

MDQM0_0

2

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

56

55

C1

C2

C3

D1

D2

E1

E2

E3

F1

3

4

5

6

7

8

9

External bus interface data bus

(Address / data multiplex bus)

10

11

12

13

14

15

16

17

93

92

10

11

12

13

14

15

16

17

78

77

10

11

12

-

F2

F3

F2

G1

G2

G3

H2

H3

B11

A12

F3

External

Bus

-

F4

-

G1

G2

G3

C10

B13

-

63

62

External bus interface byte mask signal

output pin

MDQM1_0

External bus interface Address Latch enable

output signal for multiplex

MALE_0

94

79

96

84

-

64

76

-

57

74

62

-

B10

B3

A8

-

A11

B3

A9

G4

H1

H3

H2

C4

B5

External bus interface external RDY input

signal

MRDY_0

116

99

External bus interface external clock output

MCLKOUT_0

MNALE_0

MNCLE_0

MNREX_0

MNWEX_0

MOEX_0

External bus interface ALE signal to control

NAND Flash output pin

18

-

External bus interface CLE signal to control

NAND Flash output pin

19

-

External bus interface read enable signal to

control NAND Flash

21

-

External bus interface write enable signal to

control NAND Flash

20

-

External bus interface read enable signal for

SRAM

114

113

94

93

74

73

72

71

B5

C5

External bus interface write enable signal for

SRAM

MWEX_0

Document Number: 002-04868 Rev. *F

Page 33 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

SDRAM interface

MSDCLK_0

23

18

-

96

J1

SDRAM clock output pin

SDRAM interface

SDRAM clock enable pin

MSDCKE_0

MRASX_0

MCASX_0

MSDWEX_0

24

25

26

34

19

20

21

29

97

98

99

7

J2

J3

J4

N3

External

Bus

SDRAM interface

SDRAM row address strobe pin

J3

SDRAM interface

SDRAM column address strobe pin

K1

M3

SDRAM interface

SDRAM write enable pin

-

INT00_0

INT00_1

INT00_2

INT01_0

INT01_1

INT01_2

INT02_0

INT02_1

INT02_2

INT03_0

INT03_1

INT03_2

INT04_0

INT04_1

INT04_2

INT05_0

INT05_1

INT05_2

INT06_1

INT06_2

INT07_1

INT07_2

INT08_1

INT08_2

INT09_1

INT09_2

INT10_1

INT10_2

INT11_1

INT11_2

INT12_1

INT12_2

INT13_1

INT13_2

INT14_1

INT14_2

INT15_1

INT15_2

NMIX

2

80

58

-

C1

A10

-

C1

B10

C6

C2

C8

E10

D3

L12

E13

B5

External interrupt request 00 input pin

External interrupt request 01 input pin

External interrupt request 02 input pin

External interrupt request 03 input pin

External interrupt request 04 input pin

External interrupt request 05 input pin

95

108

3

80

-

65

-

3

81

64

-

C2

C8

-

101

85

6

86

-

6

84

30

-

D2

L13

-

62

82

113

65

54

17

114

10

89

75

21

88

22

11

7

52

-

41

-

93

55

-

73

44

-

71

33

-

C5

K12

-

J12

M10

G3

C4

E4

12

94

-

12

74

-

90

72

-

F3

B5

-

74

65

16

73

17

-

52

43

94

51

95

-

C12

G12

H2

C13

H3

-

C12

G12

H3

D11

H4

F1

54

-

59

-

External interrupt request 06 input pin

External interrupt request 07 input pin

External interrupt request 08 input pin

External interrupt request 09 input pin

External interrupt request 10 input pin

External interrupt request 11 input pin

External interrupt request 12 input pin

External interrupt request 13 input pin

External interrupt request 14 input pin

External

Interrupt

-

7

85

92

86

93

88

89

-

E1

G2

E2

G3

F1

F2

-

E1

19

8

14

8

-

H1

E2

8

20

15

16

112

50

110

32

96

33

49

68

53

52

14

116

15

10

11

-

H2

G1

G2

C5

L8

10

11

-

45

-

35

-

23

-

L9

-

A6

27

81

28

44

58

-

5

N2

A9

N3

M9

J11

-

N2

D9

L2

66

-

59

6

34

47

-

22

36

-

M8

H12

K9

-

L9

External interrupt request 15 input pin

Non-Maskable Interrupt input pin

9

87

74

E3

B3

F4

96

76

B3

Document Number: 002-04868 Rev. *F

Page 34 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

BGA

112

BGA

144

120

100

80

100

P00

P01

P02

P03

P04

P05

P06

P07

P08

P09

P0A

P0B

P0C

P0D

P0E

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P1A

P1B

P1C

P1D

P1E

P1F

P20

P21

P22

P23

P24

P25

P26

P27

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

62

63

64

65

66

67

68

69

74

75

76

77

78

79

80

81

89

88

87

86

85

84

83

82

91

72

69

B6

D6

90

89

88

87

86

85

84

83

82

81

80

79

78

77

52

53

54

55

56

57

58

59

64

65

66

67

68

69

70

-

71

70

69

68

-

68

67

66

65

64

63

62

61

60

59

58

57

56

55

30

31

32

33

34

35

36

37

42

43

44

45

46

47

48

-

A6

B7

C6

C7

B7

D7

C7

B8

C8

-

B8

D8

General-purpose I/O port 0

-

A8

A9

-

C9

B9

67

66

65

64

63

62

41

42

43

44

45

46

47

48

53

54

55

56

-

B9

C9

A9

D9

A10

B10

B11

A12

L13

L12

K13

K12

J13

J12

J11

H12

H11

G12

G11

F12

F11

E12

E11

-

B10

A11

C10

B13

L12

K12

K11

J12

J11

J10

H12

H11

H10

G12

G11

G10

F13

F12

F11

F10

C12

D11

D12

D13

E10

E11

E12

E13

GPIO

General-purpose I/O port 1

-

74

73

72

71

-

52

51

50

49

-

C12

C13

D12

D13

-

59

58

57

-

General-purpose I/O port 2

-

Document Number: 002-04868 Rev. *F

Page 35 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

P30

P31

P32

P33

P34

P35

P36

P37

P38

P39

P3A

P3B

P3C

P3D

P3E

P3F

P40

P41

P42

P43

P44

P45

P46

P47

P48

P49

P4B

P4C

P4D

P4E

P50

P51

P52

P53

P54

P55

P56

P57

P58

P59

P5A

P5B

14 87

9

E3

F1

F2

F3

G1

G2

G3

H2

H3

J1

J2

J3

K1

K2

L1

L2

N2

N3

M3

L3

M4

L5

N5

N6

L6

M7

L7

L8

M9

L9

C1

C2

C3

D1

D2

E1

E2

-

F4

G1

G2

G3

G4

H1

H2

H3

H4

J1

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

32

33

34

35

36

37

39

40

41

42

47

48

49

50

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

27

28

29

30

31

32

34

35

36

37

42

43

44

45

2

10

11

12

-

88

89

90

91

92

93

94

95

96

97

98

99

100

1

-

General-purpose I/O port 3

-

13

14

15

16

17

18

19

-

J2

J3

J4

K2

K3

L1

2

5

N2

L2

-

6

-

7

N3

M3

L4

-

8

21

22

24

25

26

27

32

33

34

35

2

9

GPIO

10

12

13

14

15

20

21

22

23

80

81

82

83

84

85

86

-

K5

N5

M5

L6

General-purpose I/O port 4

K6

L7

K7

M8

L8

C1

C2

D1

D2

D3

E1

E2

E3

E4

F1

F2

F3

3

4

5

6

7

General-purpose I/O port 5

8

9

-

10

11

12

13

-

Document Number: 002-04868 Rev. *F

Page 36 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

BGA

112

BGA

144

120

100

80

100

P60

P61

P62

P63

P64

P65

P66

P67

P68

P70

P71

P72

P73

P74

P80

P81

PE0

PE2

PE3

116

115

114

113

112

111

110

109

108

51

96

76

74

B3

95

94

93

-

75

74

73

-

73

72

71

-

B4

B5

C4

C5

B5

General-purpose I/O port 6

-

C5

-

D5

-

A6

-

B6

-

C6

GPIO

-

K8

52

-

L9

General-purpose I/O port 7

53

-

K9

54

-

M10

L10

A3

55

-

118

119

56

98

99

46

48

49

73

55

78

79

36

38

39

59

44

76

77

24

26

27

51

33

A3

A2

M10

N11

N12

C13

K12

General-purpose I/O port 8

A2

N10

N11

N12

D11

J12

General-purpose I/O port E

58

59

SIN0_0

SIN0_1

88

Multi-function serial interface ch.0 input pin

65

Multi-function serial interface ch.0 output

pin.

This pin operates as SOT0 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA0 when it is used in an I²C

(operation mode 4).

SOT0_0

(SDA0_0)

87

66

86

67

72

56

71

57

58

45

57

46

50

34

49

35

D12

J13

D13

J12

D12

J11

D13

J10

Multi-

function

Serial

0

SOT0_1

(SDA0_1)

Multi-function serial interface ch.0 clock I/O

pin.

This pin operates as SCK0 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SCL0 when it is used in an I²C

(operation mode 4).

SCK0_0

(SCL0_0)

SCK0_1

(SCL0_1)

SIN1_0

SIN1_1

96

62

81

52

66

41

59

30

A9

D9

Multi-function serial interface ch.1 input pin

L13

L12

Multi-function serial interface ch.1 output

pin.

This pin operates as SOT1 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA1 when it is used in an I²C

(operation mode 4).

SOT1_0

(SDA1_0)

97

63

98

64

82

53

83

54

67

42

-

60

31

61

32

B9

C9

Multi-

function

Serial

1

SOT1_1

(SDA1_1)

L12

C9

K12

B9

SCK1_0

(SCL1_0)

Multi-function serial interface ch.1 clock I/O

pin.

This pin operates as SCK1 when it is used

in a CSIO (operation modes 4) and as SCL1

when it is used in an I²C (operation mode 4).

SCK1_1

(SCL1_1)

43

K13

K11

Document Number: 002-04868 Rev. *F

Page 37 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

SIN2_0

53

-

K9

SIN2_1

SIN2_2

Multi-function serial interface ch.2 input pin

85

68

-

E10

H12

58

47

36

J11

SOT2_0

(SDA2_0)

Multi-function serial interface ch.2 output

pin.

This pin operates as SOT2 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA2 when it is used in an I²C

(operation mode 4).

54

84

69

55

83

74

-

M10

E11

H11

L10

E12

H10

SOT2_1

(SDA2_1)

Multi-

-

function

Serial

2

SOT2_2

(SDA2_2)

59

-

48

-

37

-

H12

SCK2_0

(SCL2_0)

-

Multi-function serial interface ch.2 clock I/O

pin.

This pin operates as SCK2 when it is used

in a CSIO (operation modes 2) and as SCL2

when it is used in an I²C (operation mode 4).

SCK2_1

(SCL2_1)

-

SCK2_2

(SCL2_2)

64

53

42

H11

SIN3_0

SIN3_1

110

15

-

A6

G1

Multi-function serial interface ch.3 input pin

10

88

F1

Multi-function serial interface ch.3 output

pin.

This pin operates as SOT3 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA3 when it is used in an I²C

(operation mode 4).

SOT3_0

(SDA3_0)

109

16

-

B6

G2

C6

G3

Multi-

function

Serial

3

SOT3_1

(SDA3_1)

11

-

11

-

89

-

F2

-

SCK3_0

(SCL3_0)

Multi-function serial interface ch.3 clock I/O

pin.

This pin operates as SCK3 when it is used

in a CSIO (operation modes 2) and as SCL3

when it is used in an I²C (operation mode 4).

108

17

SCK3_1

(SCL3_1)

12

90

F3

SIN4_0

SIN4_1

SIN4_2

6

84

43

-

D2

G12

-

D3

Multi-function serial interface ch.4 input pin

75

10

65

-

54

-

G12

E4

SOT4_0

(SDA4_0)

Multi-function serial interface ch.4 output

pin.

This pin operates as SOT4 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA4 when it is used in an I²C

(operation mode 4).

5

83

44

-

D1

G11

-

D2

SOT4_1

(SDA4_1)

76

11

4

66

-

55

-

G11

F1

SOT4_2

(SDA4_2)

Multi-

function

Serial

4

SCK4_0

(SCL4_0)

4

82

45

-

C3

F12

-

D1

Multi-function serial interface ch.4 clock I/O

pin.

This pin operates as SCK4 when it is used

in a CSIO (operation modes 2) and as SCL4

when it is used in an I²C (operation mode 4).

SCK4_1

(SCL4_1)

77

12

67

-

56

-

G10

F2

SCK4_2

(SCL4_2)

CTS4_0

CTS4_1

CTS4_2

RTS4_0

RTS4_1

RTS4_2

2

-

80

46

-

C1

F11

-

C1

F13

F3

Multi-function serial interface ch.4 CTS input

78

13

3

68

-

3

-

81

47

87

C2

E12

E3

C2

F12

F4

Multi-function serial interface ch.4 RTS

output pin

79

14

69

9

Document Number: 002-04868 Rev. *F

Page 38 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

BGA

112

BGA

144

120

100

80

100

SIN5_0

114

113

20

94

74

72

B5

-

C4

B5

H2

SIN5_1

SIN5_2

Multi-function serial interface ch.5 input pin

-

15

93

G3

SOT5_0

(SDA5_0)

Multi-function serial interface ch.5 output

pin.

This pin operates as SOT5 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA5 when it is used in an I²C

(operation mode 4).

115

112

21

95

-

75

-

73

-

B4

-

B4

C5

H3

B3

D5

H4

SOT5_1

(SDA5_1)

Multi-

function

Serial

5

SOT5_2

(SDA5_2)

16

96

-

94

74

-

H2

B3

-

SCK5_0

(SCL5_0)

116

111

22

76

-

Multi-function serial interface ch.5 clock I/O

pin.

This pin operates as SCK5 when it is used

in a CSIO (operation modes 2) and as SCL5

when it is used in an I²C (operation mode 4).

SCK5_1

(SCL5_1)

SCK5_2

(SCL5_2)

17

-

95

H3

SIN6_0

SIN6_1

7

85

58

E1

Multi-function serial interface ch.6 input pin

95

80

65

A10

B10

Multi-function serial interface ch.6 output

pin.

This pin operates as SOT6 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA6 when it is used in an I²C

(operation mode 4).

SOT6_0

(SDA6_0)

8

86

57

-

E2

B10

-

E2

SOT6_1

(SDA6_1)

94

9

79

-

64

-

A11

E3

Multi-

function

Serial

6

SCK6_0

(SCL6_0)

Multi-function serial interface ch.6 clock I/O

pin.

This pin operates as SCK6 when it is used

in a CSIO (operation modes 2) and as SCL6

when it is used in an I²C (operation mode 4).

SCK6_1

(SCL6_1)

93

92

78

77

63

62

56

55

B11

A12

C10

B13

Multi-function serial interface ch.6 serial chip

select pin

SCS6_1

SIN7_0

SIN7_1

101

50

86

45

-

64

23

C8

L9

C8

L8

Multi-function serial interface ch.7 input pin

35

Multi-function serial interface ch.7 output

pin.

This pin operates as SOT7 when it is used

in a UART/CSIO/LIN (operation modes 0 to

3) and as SDA7 when it is used in an I²C

(operation mode 4).

SOT7_0

(SDA7_0)

100

49

85

44

84

-

63

22

62

B8

M9

A8

D8

M8

A9

SOT7_1

(SDA7_1)

34

-

Multi-

function

Serial

7

SCK7_0

(SCL7_0)

Multi-function serial interface ch.7 clock I/O

pin.

99

This pin operates as SCK7 when it is used

in a CSIO (operation modes 2) and as SCL7

when it is used in an I²C (operation mode 4).

SCK7_1

(SCL7_1)

48

47

43

42

33

32

21

20

L8

L7

K7

L7

Multi-function serial interface ch.7 serial chip

select pin

SCS7_1

Document Number: 002-04868 Rev. *F

Page 39 of 167

CY9B460R Series

Pin No

function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

DTTI0X_0

Input signal controlling wave form generator

outputs RTO00 to RTO05 of Multi-function

timer 0.

23

18

13

96

J1

DTTI0X_1

79

69

-

47

E12

F12

FRCK0_0

FRCK0_1

FRCK0_2

IC00_0

IC00_1

IC00_2

IC01_0

IC01_1

IC01_2

IC02_0

IC02_1

IC02_2

IC03_0

IC03_1

IC03_2

18

80

62

22

75

63

21

76

64

20

77

65

19

78

66

13

70

52

17

65

53

16

66

54

15

67

55

14

68

56

-

91

48

30

95

43

31

94

44

32

93

45

33

92

46

34

G1

G4

16-bit free-run timer ch.0 external clock

input pin

-

E11

L13

H3

F11

L12

H4

41

-

54

42

-

G12

L12

H2

G12

K12

H3

55

43

-

G11

K13

G3

G11

K11

H2

16-bit input capture ch.0 input pin of Multi-

function timer 0.

ICxx describes channel number.

56

44

-

F12

K12

G2

G10

J12

H1

-

F11

J13

F13

J11

45

Multi-

function

Timer

0

RTO00_0

(PPG00_0)

Wave form generator output pin of Multi-

function timer 0.

This pin operates as PPG00 when it is used

in PPG0 output modes.

24

86

25

85

26

84

27

83

28

82

29

81

19

71

20

-

14

57

15

-

97

49

98

-

J2

D13

J3

-

J2

RTO00_1

(PPG00_1)

D13

J3

RTO01_0

(PPG00_0)

Wave form generator output pin of Multi-

function timer 0.

This pin operates as PPG00 when it is used

in PPG0 output modes.

RTO01_1

(PPG00_1)

E10

J4

RTO02_0

(PPG02_0)

Wave form generator output pin of Multi-

function timer 0.

This pin operates as PPG02 when it is used

in PPG0 output modes.

21

-

16

-

99

-

K1

-

RTO02_1

(PPG02_1)

E11

K2

RTO03_0

(PPG02_0)

Wave form generator output pin of Multi-

function timer 0.

This pin operates as PPG02 when it is used

in PPG0 output modes.

22

-

17

-

100

-

K2

-

RTO03_1

(PPG02_1)

E12

K3

RTO04_0

(PPG04_0)

Wave form generator output pin of Multi-

function timer 0.

This pin operates as PPG04 when it is used

in PPG0 output modes.

23

-

18

-

1

L1

-

RTO04_1

(PPG04_1)

-

E13

L1

RTO05_0

(PPG04_0)

Wave form generator output pin of Multi-

function timer 0.

This pin operates as PPG04 when it is used

in PPG0 output modes.

24

-

19

-

2

L2

-

RTO05_1

(PPG04_1)

-

F10

Document Number: 002-04868 Rev. *F

Page 40 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

DTTI1X_0

Input signal controlling wave form generator

outputs RTO10 to RTO15 of Multi-function

timer 1.

8

-

86

E2

-

E2

DTTI1X_1

55

-

L10

FRCK1_0

FRCK1_1

IC10_0

IC10_1

IC11_0

IC11_1

IC12_0

IC12_1

IC13_0

IC13_1

96

50

95

54

94

53

93

52

92

51

81

45

80

-

66

35

65

-

59

23

58

-

A9

L9

A10

-

D9

16-bit free-run timer ch.1 external clock

input pin

L8

B10

M10

A11

K9

79

-

64

-

57

-

B10

-

16-bit input capture ch.1 input pin of Multi-

function timer 1.

ICxx describes channel number.

78

-

63

-

56

-

B11

-

C10

L9

77

-

62

-

55

-

A12

-

B13

K8

RTO10_0

(PPG10_0)

Wave form generator output pin of Multi-

function timer 1.

This pin operates as PPG10 when it is used

in PPG1 output modes.

2

-

80

5

C1

N2

C2

N3

C3

M3

D1

L3

C1

N2

C2

L2

RTO10_1

(PPG10_1)

32

3

27

3

Multi-

function

Timer

1

RTO11_0

(PPG10_0)

Wave form generator output pin of Multi-

function timer 1.

This pin operates as PPG10 when it is used

in PPG1 output modes.

3

-

81

6

RTO11_1

(PPG10_1)

33

4

28

4

RTO12_0

(PPG12_0)

Wave form generator output pin of Multi-

function timer 1.

This pin operates as PPG12 when it is used

in PPG1 output modes.

4

-

82

7

D1

N3

D2

M3

D3

L4

RTO12_1

(PPG12_1)

34

5

29

5

RTO13_0

(PPG12_0)

Wave form generator output pin of Multi-

function timer 1.

This pin operates as PPG12 when it is used

in PPG1 output modes.

5

-

83

8

RTO13_1

(PPG12_1)

35

6

30

6

RTO14_0

(PPG14_0)

Wave form generator output pin of Multi-

function timer 1.

This pin operates as PPG14 when it is used

in PPG1 output modes.

6

21

7

22

84

9

D2

M4

E1

L5

RTO14_1

(PPG14_1)

36

7

31

7

RTO15_0

(PPG14_0)

Wave form generator output pin of Multi-

function timer 1.

This pin operates as PPG14 when it is used

in PPG1 output modes.

85

10

E1

K5

RTO15_1

(PPG14_1)

37

32

AIN0_0

AIN0_1

AIN0_2

BIN0_0

BIN0_1

BIN0_2

ZIN0_0

ZIN0_1

ZIN0_2

24

51

2

19

-

14

-

97

-

J2

-

J2

QPRC ch.0 AIN input pin

QPRC ch.0 BIN input pin

QPRC ch.0 ZIN input pin

K8

C1

J3

2

80

98

-

C1

J3

-

Quadrature

Position/

Revolution

Counter

0

25

52

3

20

-

15

-

L9

C2

J4

3

81

99

-

C2

K1

-

26

53

4

21

-

16

-

K9

D1

4

82

C3

Document Number: 002-04868 Rev. *F

Page 41 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

AIN1_0

10

-

E4

C12

K7

F1

AIN1_1

QPRC ch.1 AIN input pin

89

48

11

88

49

12

87

50

115

64

23

115

64

23

74

43

-

52

21

-

C12

L8

AIN1_2

33

-

Quadrature

Position/

Revolution

Counter

1

BIN1_0

-

BIN1_1

QPRC ch.1 BIN input pin

QPRC ch.1 ZIN input pin

73

44

-

51

22

-

C13

M9

-

D11

M8

F2

BIN1_2

34

-

ZIN1_0

ZIN1_1

72

45

95

54

18

95

54

18

96

9

-

50

23

73

32

96

73

32

96

74

87

23

37

9

D12

L9

D12

L8

ZIN1_2

35

75

43

13

75

43

13

76

9

RTCCO_0

RTCCO_1

RTCCO_2

SUBOUT_0

SUBOUT_1

SUBOUT_2

WKUP0

WKUP1

WKUP2

WKUP3

DA0

B4

K13

J1

B4

K11

J1

0.5 seconds pulse output pin of Real-time

clock

Real-time clock

B4

K13

J1

B4

K11

J1

Sub clock output pin

Deep standby mode return signal input pin 0 116

Deep standby mode return signal input pin 1 14

Deep standby mode return signal input pin 2 50

Deep standby mode return signal input pin 3 69

B3

E3

L9

B3

F4

Low-Power

Consumption

Mode

45

59

31

32

36

35

48

21

22

26

L8

H12

M4

L5

H11

L4

D/A converter ch.0 analog output pin

D/A converter ch.1 analog output pin

On-board regulator control pin

36

37

41

DAC

DA1

10

14

K5

L6

VREGCTL

L6

VBAT

The return signal input pin from a

hibernation state

VWAKEUP

S_CLK_0

S_CMD_0

42

92

93

37

77

78

27

62

63

15

55

56

M7

K6

SD memory card interface

SD memory card clock output pin

A12

B11

B13

C10

SD memory card interface

SD memory card command output

S_DATA1_0

S_DATA0_0

S_DATA3_0

S_DATA2_0

94

95

96

97

79

80

81

82

64

65

66

67

57

58

59

60

B10

A10

A9

A11

B10

D9

SD memory card interface

SD memory card data bus

SD I/F

B9

C9

SD memory card interface

SD memory card detection pin

S_CD_0

S_WP_0

INITX

113

114

38

93

94

33

73

74

23

71

72

11

C5

B5

M6

B5

C4

N4

SD memory card interface

SD memory card write protection

External Reset Input pin.

A reset is valid when INITX="L".

Reset

Mode

Mode 1 pin.

During serial programming to Flash

memory, MD1="L" must be input.

MD1

MD0

56

57

46

47

36

37

24

25

M10

M11

N10

M11

Mode 0 pin.

During normal operation, MD0="L" must be

input. During serial programming to Flash

memory, MD0="H" must be input.

Document Number: 002-04868 Rev. *F

Page 42 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

1

-

79

B1

M1

M8

M13

B13

A4

A5

N1

N10

N13

A13

A1

A7

B2

B12

C11

H1

N4

M5

N7

L11

A11

M12

M2

-

B1

31

26

41

51

76

97

92

25

40

50

75

100

-

4

M1

M9

M13

A12

A4

46

31

-

19

29

54

75

70

3

Power

VCC

Power supply Pin

61

91

61

77

-

117

107

A7

30

20

30

40

60

80

-

N1

45

18

28

53

78

-

N9

60

N13

A13

A1

90

120

-

A5

-

A8

-

A10

B2

-

B11

B12

C3

-

GND

VSS

GND Pin

-

C11

C13

D4

-

D10

K1

-

K4

-

K10

L3

-

L5

-

L11

L13

M2

M4

M6

M7

M12

N6

-

GND

VSS

GND Pin

-

X0

Main clock (oscillation) input pin

Main clock (oscillation) I/O pin

Sub clock (oscillation) input pin

Sub clock (oscillation) I/O pin

58

59

39

40

87

113

48

49

34

35

72

93

38

39

24

25

58

73

26

27

12

13

50

71

N11

N12

N5

N6

D12

C5

N11

N12

N5

X1

X0A

X1A

Clock

M5

D12

B5

CROUT_0

CROUT_1

Built-in high-speed CR-osc clock output port

A/D converter and D/A converter

analog power supply pin

AVCC

AVRL

AVRH

70

72

73

60

62

63

49

51

52

38

40

41

H13

F13

E13

K13

H13

G13

ADC

Power

A/D converter analog reference voltage

input pin

A/D converter analog reference voltage

input pin

Document Number: 002-04868 Rev. *F

Page 43 of 167

CY9B460R Series

Pin No

Function

Pin name

Function description

LQFP LQFP LQFP QFP

120 100 80 100

BGA

112

BGA

144

VBAT power supply pin.

Backup power supply (battery etc.) and

system power supply.

VBAT

Power

VBAT

43

38

28

16

N8

N7

ADC

GND

A/D converter and D/A converter

GND pin

AVSS

C

71

44

61

39

50

29

39

17

G13

N9

J13

N8

C pin

Power supply stabilization capacity pin

Note:

−

While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant

to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in

other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP

controller.

Document Number: 002-04868 Rev. *F

Page 44 of 167

CY9B460R Series

5. I/O Circuit Type

Type

Circuit

Remarks

A

It is possible to select the

main oscillation / GPIO

function

Pull-up

resistor

When the main oscillation is

selected.

P-ch

Digital output

X1

• Oscillation feedback resistor

: Approximately 1 MΩ

• With Standby mode control

N-ch

When the GPIO is selected.

R

• CMOS level output.

• CMOS level hysteresis input

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

Pull-up resistor control

Digital input

• I_OH= -4 mA, I_OL= 4 mA

Standby mode control

Clock input

Feedback

resistor

Standby mode control

Digital input

Standby mode control

Pull-up

resistor

R

P-ch

N-ch

P-ch

Digital output

X0

Digital output

Pull-up resistor control

B

• CMOS level hysteresis input

• Pull-up resistor

: Approximately 50 kΩ

Pull-up resistor

Digital input

Document Number: 002-04868 Rev. *F

Page 45 of 167

CY9B460R Series

Type

Circuit

Remarks

C

• Open drain output

• CMOS level hysteresis input

Digital input

N-ch

Digital output

E

• CMOS level output

• CMOS level hysteresis input

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

P-ch

Digital output

• I_OH= -4 mA, I_OL= 4 mA

N-ch

Digital output

R

Pull-up resistor control

Digital input

Standby mode control

Document Number: 002-04868 Rev. *F

Page 46 of 167

CY9B460R Series

Type

Circuit

Remarks

F

• CMOS level output

• CMOS level hysteresis input

• With input control

• Analog input

• With pull-up resistor control

• With standby mode control

P-ch

Digital output

• Pull-up resistor

: Approximately 50 kΩ

• I_OH= -4 mA, I_OL= 4 mA

N-ch

Digital output

Pull-up resistor control

R

Digital input

Standby mode control

Analog input

Input control

G

• CMOS level output

• CMOS level hysteresis input

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

• I_OH= -12 mA, I_OL= 12 mA

P-ch

Digital output

N-ch

R

Pull-up resistor

control

Digital input

Standby mode

control

Document Number: 002-04868 Rev. *F

Page 47 of 167

CY9B460R Series

Type

Circuit

Remarks

H

• CMOS level output

• CMOS level hysteresis input

• With standby mode control

• I_OH=-20.5 mA, I_OL= 18.5 mA

Digital output

P-ch

N-ch

R

Digital input

Standby mode

Control

I

• CMOS level output

• CMOS level hysteresis input

• 5 V tolerant

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

• I_OH= -4 mA, I_OL= 4 mA

• Available to control of PZR

registers.

P-ch

Digital output

N-ch

R

Pull-up resistor

control

Digital input

Standby mode control

J

CMOS level hysteresis input

Mode input

Document Number: 002-04868 Rev. *F

Page 48 of 167

CY9B460R Series

Type

Circuit

Remarks

L

• CMOS level output

• CMOS level hysteresis input

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

• I_OH= -8 mA, I_OL= 8 mA

P-ch

Digital output

N-ch

Pull-up resistor

control

R

Digital input

Standby mode

control

M

• CMOS level output

• CMOS level hysteresis input

• With input control

• Analog input

• With pull-up resistor control

• With standby mode control

P-ch

• Pull-up resistor

: Approximately 50 kΩ

• I_OH= -8 mA, I_OL= 8 mA

Digital output

N-ch

Pull-up resistor

control

R

Digital input

Standby mode

control

Analog input

Input control

Document Number: 002-04868 Rev. *F

Page 49 of 167

CY9B460R Series

Type

Circuit

Remarks

N

・ CMOS level output

・ CMOS level hysteresis input

・ 5 V tolerant

・ Pull-up resistor control

・ Standby mode control

・ Pull-up resistor:

Pull-up resistor

control

P-ch

N-ch

approximately 50 kΩ

Digital output

・ I_OH= -4 mA, I_OL= 4 mA (GPIO)

・ I_OL= 20 mA (Fast mode Plus)

・ Available to control of PZR

register (pseudo-open drain

control)

N-ch

Digital output

・ For PZR registers, refer to GPIO

in the FM4 Family Peripheral

Manual Main Part (002-04856).

・ When this pin is used as an I²C

pin, the digital output P-ch

transistor is always off.

Fast mode

control

R

Digital input

Standby mode

control

O

・ CMOS level output

・ CMOS level hysteresis input

・ 5 V tolerant

・ Pull-up resistor control

・ Pull-up resistor:

Pull-up resistor

control

approximately 50 kΩ

P-ch

・ I_OH= -4 mA, I_OL= 4 mA

・ Available to control of PZR

register (pseudo-open drain

control)

P-ch

N-ch

Digital output

・ For PZR registers, refer to GPIO

in the “FM4 Family Peripheral

Manual Main Part (002-04856)”.

・ For I/O setting, refer to VBAT

Domain in the FM4 Family

Peripheral Manual Main Part

(002-04856).

Digital output

R

Digital input

Document Number: 002-04868 Rev. *F

Page 50 of 167

CY9B460R Series

Type

Circuit

Remarks

P

• CMOS level output

• CMOS level hysteresis input

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

• I_OH= -4 mA, I_OL= 4 mA

P-ch

Pull-up resistor

control

Digital output

P-ch

X0A

• For I/O setting, refer to VBAT

Domain in the Peripheral

Manual

N-ch

Digital output

R

Digital input

Standby mode

control

OSC

Q

It is possible to select the sub

oscillation / GPIO function

When the sub oscillation is

selected.

Pull-up resistor

control

Digital output

P-ch

• Oscillation feedback resistor

: Approximately 10 MΩ

P-ch

X1A

• With Standby mode control

• When the GPIO is selected.

• CMOS level output.

N-ch

Digital output

• CMOS level hysteresis input

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

: Approximately 50 kΩ

R

• I_OH= -4 mA, I_OL= 4 mA

Digital input

• For I/O setting, refer to VBAT

Domain in the Peripheral

Manual

Standby mode

control

OSC

RX

Standby mode

control

Clock input

Document Number: 002-04868 Rev. *F

Page 51 of 167

CY9B460R Series

Type

Circuit

Remarks

R

• CMOS level output

• CMOS level hysteresis input

• Analog output

• With pull-up resistor control

• With standby mode control

• Pull-up resistor

Pull-up resistor

control

Digital output

P-ch

: Approximately 50 kΩ

• I_OH= -12 mA, I_OL= 12 mA

(4.5 V to 5.5 V)

• I_OH= -8 mA, I_OL= 8 mA

(2.7 V to 4.5 V)

N-ch

Digital output

R

Digital input

Standby mode

control

Analog output

Document Number: 002-04868 Rev. *F

Page 52 of 167

CY9B460R Series

6. Handling Precautions

Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in

which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to

minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

Absolute Maximum Ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of

certain established limits, called absolute maximum ratings. Do not exceed these ratings.

Recommended Operating Conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical

characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely

affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users

considering application outside the listed conditions are advised to contact their sales representative beforehand.

Processing and Protection of Pins

These precautions must be followed when handling the pins which connect semiconductor devices to power supply and

input/output functions.

1. Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,

and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the

design stage.

2. Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such

conditions if present for extended periods of time can damage the device.

Therefore, avoid this type of connection.

3. Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected

through an appropriate resistance to a power supply pin or ground pin.

Latch-up

Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally

high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess

of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or

damage from high heat, smoke or flame. To prevent this from happening, do the following:

1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal

noise, surge levels, etc.

2. Be sure that abnormal current flows do not occur during the power-on sequence.

Observance of Safety Regulations and Standards

Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic

interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.

Fail-Safe Design

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-04868 Rev. *F

Page 53 of 167

CY9B460R Series

Precautions Related to Usage of Devices

Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office

equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)

are requested to consult with sales representatives before such use. The company will not be responsible for damages arising

from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you

should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales

representative.

Lead Insertion Type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,

or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow

soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be

subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to

Cypress recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact

deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be

verified before mounting.

Surface Mount Type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily

deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open

connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of

mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended

conditions.

Lead-Free Packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction

strength may be reduced under some conditions of use.

Storage of Semiconductor Devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption

of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,

reducing moisture resistance and causing packages to crack. To prevent, do the following:

1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in

locations where temperature changes are slight.

2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C

and 30°C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica

gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.

4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended

conditions for baking.

Condition: 125°C/24 h

Document Number: 002-04868 Rev. *F

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CY9B460R Series

Static Electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following

precautions:

1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be

needed to remove electricity.

2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1

MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is

recommended.

4. Ground all fixtures and instruments, or protect with anti-static measures.

5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.

For reliable performance, do the following:

1. Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are

anticipated, consider anti-humidity processing.

2. Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,

use anti-static measures or processing to prevent discharges.

3. Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If

you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.

4. Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide

shielding as appropriate.

5. Smoke, Flame

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices

begin to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of Cypress products in other special environmental conditions should consult with sales

representatives.

Document Number: 002-04868 Rev. *F

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CY9B460R Series

7. Handling Devices

Power supply pins

In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to

prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground

lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the

ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also

advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this

device.

Power supply pins

A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed

operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the

fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard

VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power

supply.

Crystal oscillator circuit

Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,

X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as

possible.

It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by

ground plane as this is expected to produce stable operation.

Evaluate oscillation of your using crystal oscillator by your mount board.

Sub crystal oscillator

This series sub oscillator circuit is low gain to keep the low current consumption.

The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.

• Surface mount type

Size:

Load capacitance: Approximately 6 pF to 7 pF

• Lead type

Load capacitance: Approximately 6 pF to 7 pF

More than 3.2 mm × 1.5 mm

Using an external clock

When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0.

X1(PE3) can be used as a general-purpose I/O port.

Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to

X0A. X1A (P47) can be used as a general-purpose I/O port.

• Example of Using an External Clock

Device

X0(X0A)

Set as External

clock input

Can be used as

general-purpose

I/O ports.

X1(PE3), X1A (P47)

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CY9B460R Series

Handling when using Multi-function serial pin as I²C pin

If it is using the multi-function serial pin as I²C pins, P-ch transistor of digital output is always disabled.

However, I²C pins need to keep the electrical characteristic like other pins and not to connect to the external I²C bus system with

power OFF.

C Pin

This series contains the regulator. Be sure to connect a smoothing capacitor (C_S) for the regulator between the C pin and the GND

pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.

However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F

characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use

by evaluating the temperature characteristics of a capacitor.

A smoothing capacitor of about 4.7 μF would be recommended for this series.

C

Device

C_S

VSS

GND

Mode pins (MD0)

Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance

stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection

impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is

because of preventing the device erroneously switching to test mode due to noise.

Notes on power-on

Turn power on/off in the following order or at the same time. The device operates normally after all power on.

VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns

Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part (002-04856).

If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.

Turning on : VBAT → VCC

VCC → AVCC → AVRH

Turning off : AVRH → AVCC → VCC

VCC → VBAT

Serial Communication

There is a possibility to receive wrong data due to the noise or other causes on the serial communication.

Therefore, design a printed circuit board so as to avoid noise.

Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the

end. If an error is detected, retransmit the data.

Differences in features among the products with different memory sizes and between Flash products and

MASK products

The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics

among the products with different memory sizes and between Flash products and MASK products are different because chip

layout and memory structures are different.

If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.

Document Number: 002-04868 Rev. *F

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CY9B460R Series

Pull-Up function of 5V tolerant I/O

Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O.

Adjoining wiring on circuit board

If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility

that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as

possible between both wirings and insert the ground pattern between them in order to avoid this possibility.

Device

P46/

X0A

P47/

X1A

P48/

P49/

VREGCTL VWAKEUP

Not allowed to run

both wirings in parallel

Ground

Insert the ground pattern

Handling when using debug pins

When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set

them as output, do not set them as input.

Document Number: 002-04868 Rev. *F

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CY9B460R Series

8. Block Diagram

MB9BF466M/N/R, F467M/N/R, F468M/N/R

TRSTX,TCK,

TDI,TMS

TDO

SRAM0

32/48/64 Kbytes

SWJ-DP

TPIU*

ETM*

ROM

Table

TRACEDx,

TRACECLK

SRAM1

16/24/32 Kbytes

I

Cortex-M4ꢀCore

@160 MHz(Max)

D

SRAM2

16/24/32 Kbytes

FPU MPU NVIC

Sys

MainFlash I/F

MainFlash

1 Mbytes/

768 Kbytes/

512 Kbytes

Trace Buffer

(16 Kbytes)

Dual-Timer

Security

Watchdog Timer

(Software)

WorkFlash

32 Kbytes

WorkFlash I/F

Clock Reset

Generator

INITX

DMAC

8ch.

Watchdog Timer

(Hardware)

CSV

DSTC

CLK

S_CLK,S_CMD

S_DATAx

S_CD,S_WP

SD-CARD I/F

TX0,

RX0

CAN

TX1,

RX1

CAN

Source Clock

Main

Osc

GPIO

X0

X1

CR

P0x,

P1x,

PLL

100 kHz

CR

4 MHz

.

PIN-Function-Ctrl

.

VBAT Domain

PEx

X0A

X1A

Sub

Osc

MADx

CROUT

MADATAx

External Bus I/F

AVCC,

AVSS,

AVRH

MCSXx,MDQMx,

MOEX,MWEX,

MALE,MRDY,

MNALE,MNCLE,

MNWEX,MNREX,

MCLKOUT,MSDWEX,

MSDCLK,MSDCKE,

MRASX,MCASX

12-bit A/D Converter

Unit 0

ANxx

CAN Prescaler

LVD Ctrl

Power-On

Reset

Unit 1

Unit 2

ADTGx

LVD

Regulator

C

IRQ-Monitor

CRC Accelerator

Watch Counter

TIOAx

TIOBx

Base Timer

16-bit 16ch./

32-bit 8ch.

AINx

BINx

ZINx

QPRC

2ch.

WKUPx

Deep Standby Ctrl

Peripheral Clock Gating

Low-speed CR Prescaler

A/D Activation Compare

6ch.

VWAKEUP

VBAT Domain

Real-Time Clock

Port Ctrl.

VREGCTL

RTCCO,

SUBOUT

16-bit Input Capture

4ch.

IC0x

External Interrupt

Controller

16pin + NMI

INTx

NMIX

16-bit Free-run Timer

3ch.

FRCK0

16-bit Output Compare

6ch.

MD0,

MD1

MODE-Ctrl

DTTI0X

RTO0x

SCKx

SINx

Waveform Generator

3ch.

Multi-function Serial I/F

8ch.

HW flow control(ch.4)

SOTx

CTS4

RTS4

16-bit PPG

3ch.

12-bit D/A Converter

2units

DAx

Multi-function Timer × 2

*: For the CY9BF466M, CY9BF467M and CY9BF468M, ETM is not available.

Document Number: 002-04868 Rev. *F

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CY9B460R Series

9. Memory Size

See "Memory size" in "Product Lineup" to confirm the memory size.

10.Memory Map

Memory Map (1)

Peripherals Area

Reserved

0x41FF_FFFF

0x4007_0000

0x4006_F000

0x4006_E000

GPIO

SD-Card I/F

Reserved

0x4006_4000

0x4006_3000

0x4006_2000

0x4006_1000

0x4006_0000

0xFFFF_FFFF

Reserved

0xE010_0000

Cortex-M4 Private

CAN ch.1

CAN ch.0

DSTC

DMAC

Peripherals

0xE000_0000

Reserved

0x4004_0000

0x4003_F000

EXT-bus I/F

Reserved

External Device

Area

0x4003_C800

0x4003_C100

0x4003_C000

0x4003_B000

0x4003_A000

0x4003_9000

0x4003_8000

0x4003_7000

0x4003_6000

0x4003_5000

0x4003_4000

0x4003_3000

0x4003_2000

0x4003_1000

0x4003_0000

0x4002_F000

0x4002_E000

Peripheral Clock Gating

Low Speed CR Prescaler

RTC/Port Ctrl

Watch Counter

CRC

0x6000_0000

Reserved

0x4400_0000

0x4200_0000

MFS

CAN prescaler

Reserved

32 Mbytes

Bit band alias

LVD/DS mode

Reserved

Peripherals

Reserved

0x4000_0000

D/AC

Reserved

Int-Req.Read

EXTI

Reserved

0x2400_0000

0x2200_0000

32 Mbytes

Bit band alias

CR Trim

Reserved

0x4002_8000

0x4002_7000

0x4002_6000

0x4002_5000

0x4002_4000

0x2010_0000

0x200E_0000

0x200C_0000

A/DC

QPRC

Base Timer

PPG

WorkFlash I/F

WorkFlash

Reserved

0x2004_8000

0x2004_0000

0x2003_8000

0x2000_0000

0x1FFF_0000

0x0050_0000

0x0040_0000

Reserved

SRAM2

SRAM1

Reserved

SRAM0

Reserved

0x4002_2000

0x4002_1000

0x4002_0000

MFT Unit1

MFT Unit0

See "lMemory Map (2)"

for the memory size

details.

Reserved

0x4001_6000

0x4001_5000

Security/CR Trim

Dual Timer

Reserved

0x4001_3000

MainFlash

0x4001_2000

0x4001_1000

SW WDT

HW WDT

0x0000_0000

0x4001_0000

Clock/Reset

Reserved

0x4000_1000

0x4000_0000

MainFlash I/F

Document Number: 002-04868 Rev. *F

Page 60 of 167

CY9B460R Series

Memory Map (2)

MB9BF468M/N/R

MB9BF467M/N/R

MB9BF466M/N/R

0x2008_0000

0x200C_8000

0x200C_0000

0x2008_0000

0x200C_8000

0x200C_0000

0x2008_0000

Reserved

0x200C_8000

0x200C_0000

WorkFlash

32 Kbytes

WorkFlash

32 Kbytes

WorkFlash

32 Kbytes

Reserved

0x2004_8000

0x2004_0000

Reserved

0x2004_6000

0x2004_0000

0x2003_A000

SRAM2

32 Kbytes

0x2004_4000

0x2004_0000

0x2003_C000

SRAM2

24 Kbytes

SRAM2

16 Kbytes

SRAM1

24 Kbytes

SRAM1

32 Kbytes

16 Kbytes

0x2003_8000

0x2000_0000

Reserved

0x2000_0000

0x1FFF_4000

0x2000_0000

0x1FFF_8000

SRAM0

32 Kbytes

SRAM0

48 Kbytes

SRAM0

64 Kbytes

0x1FFF_0000

Reserved

0x0050_0000

0x0040_2000

0x0040_0000

0x0050_0000

0x0040_2000

0x0040_0000

0x0050_0000

0x0040_2000

0x0040_0000

CR trimming

Security

CR trimming

Security

CR trimming

Security

Reserved

0x0010_0000

Reserved

0x000C_0000

MainFlash

1 Mbytes

0x0008_0000

0x0000_0000

MainFlash

768 Kbytes

MainFlash

512 Kbytes

0x0000_0000

Document Number: 002-04868 Rev. *F

Page 61 of 167

CY9B460R Series

Peripheral Address Map

Start address

End address

Bus

AHB

Peripherals

0x4000_0000

0x4000_1000

0x4001_0000

0x4001_1000

0x4001_2000

0x4001_3000

0x4001_5000

0x4001_6000

0x4002_0000

0x4002_1000

0x4002_2000

0x4002_4000

0x4002_5000

0x4002_6000

0x4002_7000

0x4002_8000

0x4002_E000

0x4002_F000

0x4003_0000

0x4003_1000

0x4003_2000

0x4003_3000

0x4003_4000

0x4003_5000

0x4003_5800

0x4003_6000

0x4003_7000

0x4003_8000

0x4003_9000

0x4003_A000

0x4003_B000

0x4003_C000

0x4003_C100

0x4003_C800

0x4003_F000

0x4004_0000

0x4006_0000

0x4006_1000

0x4006_2000

0x4006_3000

0x4006_4000

0x4006_E000

0x4006_F000

0x4006_7000

0x200E_0000

0x4000_0FFF

0x4000_FFFF

0x4001_0FFF

0x4001_1FFF

0x4001_2FFF

0x4001_4FFF

0x4001_5FFF

0x4001_FFFF

0x4002_0FFF

0x4002_1FFF

0x4003_FFFF

0x4002_4FFF

0x4002_5FFF

0x4002_6FFF

0x4002_7FFF

0x4002_DFFF

0x4002_EFFF

0x4002_FFFF

0x4003_0FFF

0x4003_1FFF

0x4003_4FFF

0x4003_3FFF

0x4003_4FFF

0x4003_57FF

0x4003_5FFF

0x4003_6FFF

0x4003_7FFF

0x4003_8FFF

0x4003_9FFF

0x4003_AFFF

0x4003_BFFF

0x4003_C0FF

0x4003_C7FF

0x4003_EFFF

0x4003_FFFF

0x4005_FFFF

0x4006_0FFF

0x4006_1FFF

0x4006_2FFF

0x4006_3FFF

0x4006_DFFF

0x4006_EFFF

0x4006_FFFF

0x41FF_FFFF

0x200E_FFFF

MainFlash I/F register

Reserved

Clock/Reset Control

Hardware Watchdog timer

Software Watchdog timer

Reserved

APB0

Dual-Timer

Reserved

Multi-function timer unit0

Multi-function timer unit1

Reserved

PPG

Base Timer

APB1

Quadrature Position/Revolution Counter

A/D Converter

Reserved

Internal CR trimming

Reserved

External Interrupt Controller

Interrupt Request Batch-Read Function

Reserved

D/A Converter

Reserved

Low Voltage Detector

Deep standby mode Controller

Reserved

APB2

CAN prescaler

Multi-function serial Interface

CRC

Watch Counter

RTC/Port Ctrl

Low-speed CR Prescaler

Peripheral Clock Gating

Reserved

External Memory interface

Reserved

DMAC register

DSTC register

CAN ch.0

CAN ch.1

AHB

Reserved

SD-Card I/F

GPIO

Reserved

WorkFlash I/F register

Document Number: 002-04868 Rev. *F

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CY9B460R Series

11.Pin Status in Each CPU State

The terms used for pin status have the following meanings.

◼INITX=0

This is the period when the INITX pin is the "L" level.

◼INITX=1

This is the period when the INITX pin is the "H" level.

◼SPL=0

This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".

◼SPL=1

This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".

◼Input enabled

Indicates that the input function can be used.

◼Internal input fixed at "0"

This is the status that the input function cannot be used. Internal input is fixed at "L".

◼Hi-Z

Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.

◼Setting disabled

Indicates that the setting is disabled.

◼Maintain previous state

Maintains the state that was immediately prior to entering the current mode.

If a built-in peripheral function is operating, the output follows the peripheral function.

If the pin is being used as a port, that output is maintained.

◼Analog input is enabled

Indicates that the analog input is enabled.

◼Trace output

Indicates that the trace function can be used.

◼GPIO selected

In Deep standby mode, pins switch to the general-purpose I/O port.

◼Setting prohibition

Prohibition of a setting by specification limitation.

Document Number: 002-04868 Rev. *F

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CY9B460R Series

List of Pin Status

Power-on

reset or

low-voltage input

detection

state

Device

internal

reset

Return from

Deep

standby

INITX

Run mode

or SLEEP

mode state

TIMER mode,

RTC mode, or

STOP mode state

Deep standby RTC

mode or Deep standby

STOP mode state

state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

INITX=1

‐

Power

supply

stable

INITX=1

-

Power supply

stable

Power supply

stable

Power supply

stable

‐

INITX=0 INITX=1

INITX=1

‐

SPL=0

SPL=1

SPL=0

SPL=1

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Setting

Internal

input fixed

at "0"

Internal

input fixed

at "0"

GPIO

selected

Setting

disabled disabled

Setting

GPIO

selected

disabled

A

Main crystal

oscillator

Input

input pin/

enabled

enabled enabled enabled

enabled

External main

clock input

selected

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Setting

Internal

input fixed

at "0"

Internal

input fixed

at "0"

GPIO

selected

Setting

disabled

GPIO

selected

disabled

Hi-Z /

Maintain

External main

clock input

selected

Setting

Internal

input fixed

at "0"

Internal

input fixed

at "0"

Setting

disabled disabled

Setting

disabled

B

Maintain

Hi-Z /

Internal Internal

input

fixed

at "0"

Hi-Z /

state/When state/When state/When state/When state/When state/When

Internal

input fixed

at "0"/

oscillation

stops*¹,

Hi-Z /

Internal

input fixed

at "0"

oscillation

stops*¹,

Hi-Z /

Internal

input fixed

at "0"

oscillation

stops*¹,

Hi-Z /

Internal

input fixed

at "0"

oscillation

stops*¹,

Hi-Z /

Internal

input fixed

at "0"

oscillation

stops*¹,

Hi-Z /

Internal

input fixed

at "0"

oscillation

stops*¹,

Hi-Z /

Internal

input fixed

at "0"

Main crystal

oscillator

output pin

input

fixed

at "0"

or Input

enable

Pull-up /

Input

Pull-up /

Input

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up / Pull-up /

Input Input

enabled enabled

INITX

input pin

C

D

enabled

Input

Mode

input pin

Input

enabled enabled

enabled

Input

Mode

Input

input pin

enabled enabled

enabled

E

Maintain

Hi-Z /

Input

Hi-Z /

Input

Setting

GPIO

selected

Setting

disabled disabled

Setting

GPIO

selected

GPIO

selected

disabled

enabled

Document Number: 002-04868 Rev. *F

Page 64 of 167

CY9B460R Series

Power-on

reset or

low-voltage input

detection

state

Device

internal

reset

Return from

Deep

standby

INITX

Run mode

or SLEEP

mode state

TIMER mode,

RTC mode, or

STOP mode state

Deep standby RTC

mode or Deep standby

STOP mode state

state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

INITX=1

‐

Power

supply

stable

INITX=1

-

Power supply

stable

Power supply

stable

Power supply

stable

‐

INITX=0 INITX=1

INITX=1

‐

SPL=0

SPL=1

SPL=0

SPL=1

Maintain

Setting

NMIX

selected

Setting

disabled disabled

Setting

disabled

GPIO

selected

Hi-Z /

WKUP

input

Resource

other than

above

Maintain

WKUP

input

enabled

F

Hi-Z /

Input

enabled enabled

Hi-Z /

Input

Internal

input fixed

at "0"

selected

enabled

Hi-Z

Maintain

GPIO

selected

Maintain

Pull-up / Pull-up /

Input

enabled enabled

JTAG

selected

Input

Maintain

GPIO

G

Hi-Z /

selected

Internal

input fixed

at "0"

Setting

Internal

input fixed

at "0"

Internal

input fixed

at "0"

GPIO

selected

Setting

disabled disabled

Setting

GPIO

selected

disabled

Maintain

Pull-up / Pull-up /

JTAG

selected

Hi-Z

Input

enabled enabled

Maintain

Resource

other than

above

GPIO

H

Hi-Z /

selected

Internal

input fixed

at "0"

Setting

Internal

input fixed

at "0"

Internal

input fixed

at "0"

Setting

disabled disabled

Setting

GPIO

selected

disabled

GPIO

selected

GPIO

Resource

selected

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Hi-Z /

Input

enabled enabled

Hi-Z /

Input

Internal

input fixed

at "0"

Internal

input fixed

at "0"

GPIO

selected

I

Hi-Z

GPIO

selected

Analog output Setting

Setting

disabled disabled

Setting

*2

*3

selected

disabled

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Resource

other than

above

Internal

input fixed

at "0"

GPIO

selected

J

Hi-Z /

Maintain

Hi-Z /

Input

enabled enabled

Hi-Z /

Input

Internal

input fixed

at "0"

Hi-Z

selected

GPIO

selected

Document Number: 002-04868 Rev. *F

Page 65 of 167

CY9B460R Series

Power-on

reset or

low-voltage input

detection

state

Device

internal

reset

Return from

Deep

standby

INITX

Run mode

or SLEEP

mode state

TIMER mode,

RTC mode, or

STOP mode state

Deep standby RTC

mode or Deep standby

STOP mode state

state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

INITX=1

‐

Power

supply

stable

INITX=1

-

Power supply

stable

Power supply

stable

Power supply

stable

‐

INITX=0 INITX=1

INITX=1

‐

SPL=0

SPL=1

SPL=0

SPL=1

External

Maintain

Setting

interrupt

enabled

selected

Setting

disabled disabled

Setting

disabled

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Internal

input fixed

at "0"

Resource

other than

above

GPIO

selected

K

Hi-Z /

Input

enabled enabled

Hi-Z /

Input

Internal

input fixed

at "0"

Hi-Z

selected

GPIO

selected

Hi-Z /

Internal Internal

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

fixedat

"0" /

Analog

input

fixedat

"0" /

Analog

input

Analog input

selected

enabled

L

enabled enabled

Resource

other than

above

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Setting

Internal

input fixed

at "0"

Internal

input fixed

at "0"

Setting

disabled disabled

Setting

GPIO

selected

disabled

GPIO

selected

Document Number: 002-04868 Rev. *F

Page 66 of 167

CY9B460R Series

Power-on

reset or

low-voltage input

detection

state

Device

internal

reset

Return from

Deep

standby

INITX

Run mode

or SLEEP

mode state

TIMER mode,

RTC mode, or

STOP mode state

Deep standby RTC

mode or Deep standby

STOP mode state

state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

INITX=1

‐

Power

supply

stable

INITX=1

-

Power supply

stable

Power supply

stable

Power supply

stable

‐

INITX=0 INITX=1

INITX=1

‐

SPL=0

SPL=1

SPL=0

SPL=1

Hi-Z /

Internal Internal

input

fixed

at "0" /

Analog

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

fixed

at "0" /

Analog

input

Analog input

selected

Hi-Z

enabled

enabled enabled

External

interrupt

enabled

selected

M

Maintain

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Setting

Internal

input fixed

at "0"

Resource

other than

above

Setting

disabled disabled

Setting

GPIO

selected

disabled

Hi-Z /

Internal

input fixed

at "0"

selected

GPIO

selected

Hi-Z /

Internal Internal

input

fixed

at"0" /

Analog

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

fixed

at "0" /

Analog

input

Analog input

selected

Hi-Z

enabled

enabled enabled

N

Trace

selected

Trace

output

GPIO

Hi-Z /

Resource

other than

above

selected

Internal

input fixed

at "0"

Maintain

Setting

Internal

input fixed

at "0"

Setting

disabled disabled

Setting

GPIO

selected

Hi-Z /

disabled

Internal

input fixed

at "0"

selected

GPIO

selected

Document Number: 002-04868 Rev. *F

Page 67 of 167

CY9B460R Series

Power-on

reset or

low-voltage input

detection

state

Device

internal

reset

Return from

Deep

standby

INITX

Run mode

or SLEEP

mode state

TIMER mode,

RTC mode, or

STOP mode state

Deep standby RTC

mode or Deep standby

STOP mode state

state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

INITX=1

‐

Power

supply

stable

INITX=1

-

Power supply

stable

Power supply

stable

Power supply

stable

‐

INITX=0 INITX=1

INITX=1

‐

SPL=0

SPL=1

SPL=0

SPL=1

Hi-Z /

Internal Internal

input

fixed

at "0" /

Analog

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

fixed

at "0" /

Analog

input

Analog input

selected

Hi-Z

enabled

enabled enabled

Trace

selected

Trace

output

O

External

interrupt

enabled

selected

Maintain

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Setting

Internal

input fixed

at "0"

Setting

disabled disabled

Setting

GPIO

selected

disabled

Resource

other than

above

Hi-Z /

Internal

input fixed

at "0"

selected

GPIO

selected

Hi-Z /

Internal Internal

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

fixedat

"0" /

Analog

input

fixedat

"0" /

Analog

input

Analog input

selected

Hi-Z

enabled

enabled enabled

Hi-Z /

WKUP

input

WKUP

input

enabled

Maintain

P

WKUP

enabled

Maintain

Resource

other than

above

Setting

disabled disabled

Setting

GPIO

selected

GPIO

disabled

Hi-Z /

selected

Internal

input fixed

at "0"

Internal

input fixed

at "0"

Internal

input fixed

at "0"

selected

GPIO

selected

Document Number: 002-04868 Rev. *F

Page 68 of 167

CY9B460R Series

Power-on

reset or

low-voltage input

detection

state

Device

internal

reset

Return from

Deep

standby

INITX

Run mode

or SLEEP

mode state

TIMER mode,

RTC mode, or

STOP mode state

Deep standby RTC

mode or Deep standby

STOP mode state

state

mode state

Function

group

Power

supply

unstable

Power

supply

stable

INITX=1

‐

Power

supply

stable

INITX=1

-

Power supply

stable

Power supply

stable

Power supply

stable

‐

INITX=0 INITX=1

INITX=1

‐

SPL=0

SPL=1

SPL=0

SPL=1

Hi-Z /

WKUP

input

WKUP

input

enabled

WKUP

enabled

Maintain

enabled

Setting

disabled

Setting

disabled disabled

Setting

External

interrupt

enabled

selected

Maintain

GPIO

selected

Q

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Internal

input fixed

at "0"

Resource

other than

above

Hi-Z /

Input

enabled enabled

Hi-Z /

Input

Internal

input fixed

at "0"

Hi-Z

selected

GPIO

selected

GPIO

Hi-Z /

selected

Internal

input fixed

at "0"

Maintain

Hi-Z /

Input

Hi-Z /

Input

Maintain

input fixed

at "0"

Internal

input fixed

at "0"

GPIO

selected

GPIO

selected

R

enabled enabled state

*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep

standby STOP mode.

*2: Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode.

*3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.

Document Number: 002-04868 Rev. *F

Page 69 of 167

CY9B460R Series

List of VBAT Domain Pin Status

Return

from

Deep

Return

from

VBAT

RTC

mode

state

Run

mode or

SLEEP

mode

Device

internal

reset

Deep standby

RTC mode or Deep

VBAT

RTC

mode

state

INITX

Power-on

input

TIMER mode,

RTC mode, or

STOP mode state

reset*1

standby STOP mode standby

state

mode

state

Function

group

Power

supply

unstable

Power

supply supply

stable

Power

Power supply

stable

supply Power supply stable Power supply stable supply

stable

INITX=1

-

stable

‐

INITX=0 INITX=1 INITX=1

INITX=1

-

‐

SPL=0

SPL=1

SPL=0

SPL=1

Maintain Maintain Maintain Maintain

Previous Previous previous previous

Maintain

GPIO

selected

Setting

disabled

Setting

prohibition

Previous Previous Previous Previous

state

-

state

Sub crystal

oscillator

input pin /

External

sub clock

input

S

Maintain

Input

enabled enabled enabled enabled enabled

enabled

selected

Maintain Maintain

previous previous

Maintain Maintain

Previous Previous

Maintain

GPIO

selected

Setting

disabled

Setting

prohibition

Previous Previous Previous Previous

state

-

state

External

sub clock Setting

input

selected

Maintain Maintain

previous previous

Maintain

Maintain Maintain

Previous Previous

Maintain

disabled

state

T

Hi-Z /

Maintain

Sub crystal input

oscillator fixed at

output pin "0"/

or Input

Maintain Maintain

Previous Previous

Maintain Maintain

Previous previous

state/When state/When state/When state/When

oscillation oscillation oscillation oscillation

stops,

Hi-Z*2

state

stops,

Hi-Z*2

stops,

Hi-Z*2

stops,

Hi-Z*2

enable

Resource

selected

Maintain Maintain Maintain Maintain

previous previous previous previous

Maintain

Maintain Maintain Maintain

previous previous previous

U

Hi-Z

state

GPIO

selected

*1: When VBAT and VCC power on.

*2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the previous state.

When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop.

Document Number: 002-04868 Rev. *F

Page 70 of 167

CY9B460R Series

12.Electrical Characteristics

12.1 Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

Power supply voltage *^1,*²

Power supply voltage (VBAT) *¹*³

Analog power supply voltage *¹*⁴

Analog reference voltage *¹*⁴

V_CC

V_SS- 0.5

V_SS+ 6.5

V

,

V_BAT

V

,

AV_CC

AVRH

,

V_CC+ 0.5

(≤ 6.5V)

V_SS- 0.5

V

Input voltage *¹

V_I

V_SS+ 6.5

5V tolerant

AV_CC+ 0.5

(≤ 6.5V)

Analog pin input voltage *¹

Output voltage *¹

V_IA

V_O

V_CC+ 0.5

(≤ 6.5V)

V_SS- 0.5

V

10

20

22.4

4

mA

4mA type

8mA type

12mA type

I²C Fm+

4mA type

8mA type

12mA type

I²C Fm+

"L" level maximum output current *⁵

"L" level average output current *⁶

I_OL

-

8

I_OLAV

-

12

20

100

50

- 10

"L" level total maximum output current

"L" level total maximum output current *⁷

∑I_OL

-

∑I_OLAV

4mA type

"H" level maximum output current *⁵

"H" level average output current *⁶

I_OH

-

20

mA

°C

8mA type

12mA type

4mA type

8mA type

12mA type

- 20

- 4

I_OHAV

8

- 12

- 100

- 50

+ 150

"H" level total maximum output current

"H" level total average output current *⁷

Storage temperature

∑I_OH

-

∑I_OHAV

T_STG

-

- 55

*1: These parameters are based on the condition that V_SS= AV_SS= 0.0V.

*2: V_CCmust not drop below V_SS- 0.5V.

*3: V_BATmust not drop below V_SS- 0.5V.

*4: Ensure that the voltage does not exceed V_CC+ 0.5V, for example, when the power is turned on.

*5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.

*6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a

100ms period.

*7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms.

WARNING:

−

Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current

or temperature) in excess of absolute maximum ratings.

Do not exceed any of these ratings.

Document Number: 002-04868 Rev. *F

Page 71 of 167

CY9B460R Series

12.2 Recommended Operating Conditions

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

2.7*³

Max

Power supply voltage

V_CC

-

5.5

V

Power supply voltage (VBAT)

Analog power supply voltage

Analog reference voltage

V_BAT

AV_CC

AVRH

Tj

2.7

*2

5.5

V

5.5

V

AV_CC=V_CC

AV_CC

+ 125

*1

V

Junction temperature

Ambient temperature

- 40

°C

Operating

temperature

T_A

*1: The maximum temperature of the ambient temperature (T_A) can guarantee a range that does not exceed the

junction temperature (Tj).

The calculation formula of the ambient temperature (T_A) is shown below.

T_A(Max) = Tj(Max) - Pd(Max) × θja

Pd:

θja:

Power dissipation (W)

Package thermal resistance (°C/W)

Pd (Max) = V_CC× I_CC(Max) + Σ (I_OL×V_OL) + Σ ((V_CC-V_OH) × (- I_OH))

I_OL

I_OH

V_OL

V_OH

:

"L" level output current

"H" level output current

"L" level output voltage

"H" level output voltage

:

*2: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See “5. 12-bit A/D

Converter” for the details.

*3: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction

execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is

possible to operate only.

Package thermal resistance and maximum permissible power for each package are shown below.

The operation is guaranteed maximum permissible power or less for semiconductor devices.

Table for package thermal resistance and maximum permissible power

Maximum permissible power (mW)

Thermal resistance

Package

Printed circuit board

θja (°C/W)

T_A=+85°C

T_A=+105°C

333

Single-layered both sides

4 layers

60

39

58

38

57

38

48

34

62

43

60

40

55

40

667

LQH080

(0.5mm pitch)

1026

690

513

335

526

351

526

417

588

323

465

333

500

364

500

Single-layered both sides

4 layers

LQJ080

(0.65mm pitch)

1053

702

Single-layered both sides

4 layers

LQI100

(0.5mm pitch)

1053

833

Single-layered both sides

4 layers

PQH100

(0.65mm pitch)

1177

645

Single-layered both sides

4 layers

LQM120

(0.5mm pitch)

930

Single-layered both sides

4 layers

667

LDC112

(0.5mm pitch)

1000

727

Single-layered both sides

4 layers

LDC144

(0.5mm pitch)

1000

Document Number: 002-04868 Rev. *F

Page 72 of 167

CY9B460R Series

WARNING:

−

The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All

of the device's electrical characteristics are warranted when the device is operated under these conditions.

Any use of semiconductor devices will be under their recommended operating condition.

Operation under any conditions other than these conditions may adversely affect reliability of device and could result in

device failure.

No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you

are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Calculation method of power dissipation (Pd)

The power dissipation is shown in the following formula.

Pd = V_CC× I_CC+ Σ (I_OL× V_OL) + Σ ((V_CC-V_OH) × (-I_OH))

I_OL

I_OH

V_OL

V_OH

:

"L" level output current

"H" level output current

"L" level output voltage

"H" level output voltage

:

I_CCis a current consumed in device.

It can be analyzed as follows.

I_CC= I_CC(INT) + ΣI_CC(IO)

I_CC(INT): Current consumed in internal logic and memory, etc. through regulator

ΣI_CC(IO): Sum of current (I/O switching current) consumed in output pin

For I_CC(INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include I_CC(IO) for

a value at pin fixed).

For Icc (IO), it depends on system used by customers.

The calculation formula is shown below.

I_CC(IO) = (C_INT+ C_EXT) × V_CC× fsw

C_INT

C_EXT

f_SW

:

Pin internal load capacitance

External load capacitance of output pin

Pin switching frequency

Parameter

Symbol

Conditions

Capacitance value

4mA type

8mA type

12mA type

1.93pF

3.45pF

3.42pF

Pin internal load

capacitance

C_INT

Calculate I_CC(Max) as follows when the power dissipation can be evaluated by yourself.

1. Measure current value I_CC(Typ) at normal temperature (+25°C).

2. Add maximum leak current value I_CC(leak_max) at operating on a value in (1).

I_CC(Max) = I_CC(Typ) + I_CC(leak_max)

Parameter

Symbol

Conditions

Tj = +125°C

Current value

45.5mA

26.8mA

16.2mA

Maximum leak current at

operating

I_CC(leak_max)

Tj = +105°C

Tj = +85°C

Document Number: 002-04868 Rev. *F

Page 73 of 167

CY9B460R Series

Current explanation diagram

Pd = V_CC×I_CC+ Σ(I_OL×V_OL)＋Σ((V_CC-V_OH)×(－I_OH))

I_CC= I_CC(INT)＋ΣI_CC(IO)

V_CC

A

I_CC

Chip

ΣI_CC(IO)

I_CC(INT)

A

I_OL

Regulator

V_OL

V

Flash

V_OH

A

I_OH

V

Logic

RAM

C_EXT

I_CC(IO)

Document Number: 002-04868 Rev. *F

Page 74 of 167

CY9B460R Series

12.3 DC Characteristics

12.3.1 Current Rating

Table 12-1. Typical and maximum current consumption in Normal operation(PLL), code running from Flash memory

(Flash accelerator mode and trace buffer function enabled)

Value

name

Parameter

Symbol

Conditions

Frequency*⁴

Unit

Remarks

Typ*¹

Max*²

103

98

160MHz

144MHz

120MHz

100MHz

80MHz

60MHz

40MHz

20MHz

8MHz

54

49

41

35

28

22

16

8.9

5.1

3.8

34

31

26

22

18

14

10

6.2

3.8

3.1

90

3

84

*

77

When all

peripheral clocks

are ON

mA

71

64

58

54

Normal

Power

supply

current

4MHz

53

I_CC

VCC

operation*^5,*⁶

(PLL)

160MHz

144MHz

120MHz

100MHz

80MHz

60MHz

40MHz

20MHz

8MHz

83

80

75

71

3

*

67

When all

peripheral clocks

are OFF

mA

63

59

55

53

4MHz

52

Table 12-2. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from

Flash memory (Flash accelerator mode and trace buffer function disabled)

Value

Typ*¹

name

Parameter

Symbol

Conditions

Frequency*⁷

Unit

Remarks

Max*²

126

120

112

104

97

160MHz

144MHz

120MHz

100MHz

80MHz

60MHz

40MHz

20MHz

8MHz

74

68

59

52

44

36

27

17

8.3

5.4

51

47

42

37

33

28

21

13

6.9

4.6

3

*

When all

peripheral clocks

are ON

mA

89

79

67

58

Normal

Power

supply

current

4MHz

55

I_CC

VCC

operation*⁸

(PLL)

160MHz

144MHz

120MHz

100MHz

80MHz

60MHz

40MHz

20MHz

8MHz

103

100

94

90

3

*

85

When all

peripheral clocks

are OFF

mA

80

73

64

56

4MHz

54

Document Number: 002-04868 Rev. *F

Page 75 of 167

CY9B460R Series

*1: T_A=+25°C, V_CC=3.3V

*2: Tj=+125°C, V_CC=5.5V

*3: When all ports are fixed.

*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2

*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)

*6: Data access is nothing to MainFlash memory

*7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK

*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)

Table 12-3. Typical and maximum current consumption in Normal operation(PLL), code with data accessing running from

Flash memory (flash 0 wait-cycle mode and read access 0 wait)

Value

name

Frequency*⁴

(MHz)

Parameter

Symbol

Conditions

Unit

Remarks

Typ*¹

46

Max*²

98

72MHz

60MHz

48MHz

40

92

33

85

3

*

36MHz

27

78

When all

peripheral clocks

are ON

mA

24MHz

12MHz

8MHz

19

70

61

58

55

85

81

76

71

65

59

56

54

11

8.5

5.5

33

Normal

Power

supply

current

4MHz

I_CC

VCC

operation*⁵

(PLL)

72MHz

60MHz

48MHz

36MHz

24MHz

12MHz

8MHz

29

25

3

*

20

When all

peripheral clocks

are OFF

mA

15

9.2

6.9

4.6

4MHz

*1: T_A=+25°C, V_CC=3.3V

*2: Tj=+125°C, V_CC=5.5V

*3: When all ports are fixed.

*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK

*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)

Document Number: 002-04868 Rev. *F

Page 76 of 167

CY9B460R Series

Table 12-4. Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing

running from Flash memory (flash 0 wait-cycle mode and read access 0 wait

Value

name

Parameter

Symbol

Conditions

Frequency*⁴

Unit

Remarks

Typ*¹

Max*²

3

*

When all

peripheral clocks

are ON

3.3

51

mA

Normal

operation*⁵

(built-in high-

speed CR)

4MHz

3

*

When all

peripheral clocks

are OFF

2.8

51

48

mA

3

*

When all

peripheral clocks

are ON

0.64

0.56

0.64

0.58

Normal

Power

supply

current

operation*⁵

(sub oscillation)

I_CC

VCC

32kHz

3

*

When all

peripheral clocks

are OFF

3

*

When all

peripheral clocks

are ON

Normal

operation*⁵

(built-in

100kHz

3

*

low-speed CR)

When all

peripheral clocks

are OFF

*1: T_A=+25°C, V_CC=3.3V

*2: Tj=+125°C, V_CC=5.5V

*3: When all ports are fixed.

*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2

*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)

Document Number: 002-04868 Rev. *F

Page 77 of 167

CY9B460R Series

Table 12-5. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2

Value

Typ*¹

35

name

Parameter

Symbol

Conditions

Frequency*⁴

Unit

Remarks

Max*²

84

81

76

72

68

64

60

55

53

52

65

63

61

60

58

56

54

53

52

51

160MHz

144MHz

120MHz

100MHz

80MHz

60MHz

40MHz

20MHz

8MHz

32

27

3

23

*

19

When all

peripheral clocks

are ON

mA

15

11

6.5

4.1

3.3

16

Power

supply

current

Sleep

operation

(PLL)

4MHz

I_CCS

VCC

160MHz

144MHz

120MHz

100MHz

80MHz

60MHz

40MHz

20MHz

8MHz

14

12

11

3

*

9.0

7.4

5.6

3.9

2.9

2.6

When all

peripheral clocks

are OFF

mA

4MHz

Table 12-6. Typical and maximum current consumption in Sleep operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK

Value

name

Parameter

Symbol

Conditions

Frequency*⁵

Unit

Remarks

Typ*¹

22

19

16

Max*²

71

72MHz

60MHz

48MHz

68

64

61

3

*

36MHz

12

When all

peripheral clocks

are ON

mA

24MHz

12MHz

8MHz

9.0

5.8

4.6

3.6

9.5

8.3

7.1

5.8

4.6

3.5

3.0

2.7

58

55

54

52

58

57

56

55

53

52

51

Sleep

operation

(PLL)

Power

supply

current

4MHz

I_CCS

VCC

72MHz

60MHz

48MHz

36MHz

24MHz

12MHz

8MHz

3

*

When all

peripheral clocks

are OFF

mA

4MHz

*1: T_A=+25°C, V_CC=3.3V

*2: Tj=+125°C, V_CC=5.5V

*3: When all ports are fixed.

*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2

*5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK

Document Number: 002-04868 Rev. *F

Page 78 of 167

CY9B460R Series

Table 12-7. Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 =

PCLK2 = HCLK/2

Value

name

Parameter

Symbol

Conditions

Frequency*⁴

Unit

Remarks

Typ*¹

Max*²

3

*

When all

peripheral clocks

are ON

1.5

49

mA

Sleep

operation

(built-in high-

speed CR)

4MHz

3

*

When all

peripheral clocks

are OFF

1.0

49

48

mA

3

*

When all

peripheral clocks

are ON

0.59

0.51

Sleep

operation

(sub oscillation)

Power

supply

current

32kHz

I_CCS

VCC

3

*

When all

peripheral clocks

are OFF

3

*

When all

peripheral clocks

are ON

0.61

0.53

48

mA

Sleep

operation

(built-in low-

speed CR)

100kHz

3

*

When all

peripheral clocks

are OFF

*1: T_A=+25°C, V_CC=3.3V

*2: Tj=+125°C, V_CC=5.5V

*3: When all ports are fixed.

*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2

Document Number: 002-04868 Rev. *F

Page 79 of 167

CY9B460R Series

Table 12-8. Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode

Value

name

Parameter

Symbol

Conditions

Frequency

Unit

mA

Remarks

*³, *⁴

Typ*¹

Max*²

0.33

1.8

T_A=+25°C

*³, *⁴

I_CCH

STOP mode

-

15

22

2.2

16

22

1.8

15

22

1.8

15

22

1.8

15

22

mA

T_A=+85°C

*³, *⁴

-

T_A=+105°C

*³, *⁴

0.70

T_A=+25°C

*³, *⁴

TIMER mode

(built-in high-speed 4MHz

CR)

-

T_A=+85°C

*³, *⁴

-

T_A=+105°C

*³, *⁴

0.33

T_A=+25°C

*³, *⁴

Power supply

current

TIMER mode

32kHz

I_CCT

VCC

-

(sub oscillation)

T_A=+85°C

*³, *⁴

-

T_A=+105°C

*³, *⁴

0.34

T_A=+25°C

*³, *⁴

TIMER mode

(built-in

low-speed CR)

100kHz

32kHz

-

T_A=+85°C

*³, *⁴

-

T_A=+105°C

*³, *⁴

0.33

T_A=+25°C

*³, *⁴

RTC mode

I_CCR

-

(sub oscillation)

T_A=+85°C

*³, *⁴

T_A=+105°C

*1: V_CC=3.3V

*2: V_CC=5.5V

*3: When all ports are fixed.

*4: When LVD is off

Document Number: 002-04868 Rev. *F

Page 80 of 167

CY9B460R Series

Table 12-9. Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT

Value

Parameter

Symbol

Pin name

Conditions

Frequency

Unit

Remarks

Typ*¹

Max*²

*³, *⁴

29

140

μA

T_A=+25°C

*³, *⁴

Deep standby

STOP mode

(When RAM is

off)

-

644

μA

T_A=+85°C

*³, *⁴

-

1011

273

T_A=+105°C

*³, *⁴

I_CCHD

-

48

T_A=+25°C

*³, *⁴

Deep standby

STOP mode

(When RAM is

on)

-

2676

4162

140

T_A=+85°C

*³, *⁴

-

T_A=+105°C

*³, *⁴

VCC

29

T_A=+25°C

*³, *⁴

Deep standby

RTC mode

(When RAM is

off)

-

644

T_A=+85°C

*³, *⁴

-

1011

273

Power

supply

current

T_A=+105°C

*³, *⁴

I_CCRD

32kHz

48

T_A=+25°C

*³, *⁴

Deep standby

RTC mode

(When RAM is

on)

-

2676

4162

0.29

5.77

10.6

22.6

35.2

41.8

T_A=+85°C

*³, *⁴

-

T_A=+105°C

*³, *⁴, *⁵

0.015

T_A=+25°C

*³, *⁴, *⁵

RTC stop*6

-

T_A=+85°C

*³, *⁴, *⁵

-

T_A=+105°C

*³, *⁴

I_CCVBAT

VBAT

-

1.53

T_A=+25°C

*³, *⁴

RTC

operation*6

-

T_A=+85°C

*³, *⁴

T_A=+105°C

*1: V_CC=3.3V

*2: V_CC=5.5V

*3: When all ports are fixed.

*4: When LVD is off

*5: When sub oscillation is OFF

*6: In the case of setting RTC after VCC power on

Document Number: 002-04868 Rev. *F

Page 81 of 167

CY9B460R Series

Table 12-10. Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

Low-voltage

detection circuit

(LVD) power

supply current

For occurrence of

interrupt

I_CCLVD

At operation

-

4

7

μA

Main flash

memory

write/erase

current

VCC

I_CCFLASH

At Write/Erase

-

13.4

11.5

15.9

13.6

mA

Work flash

memory

write/erase

current

I_CCWFLASH

◼Peripheral current dissipation

Frequency (MHz)

80

Clock system

Peripheral

Unit

mA

Remarks

40

160

HCLK

GPIO

All ports

0.22

0.74

0.32

0.14

0.93

0.02

0.16

0.43

1.48

0.61

0.27

1.81

0.06

0.34

0.85

2.88

DMAC

-

DSTC

-

1.17

0.55

3.63

0.11

0.66

External bus I/F

SD card I/F

CAN

-

1ch.

4ch.

Base timer

Multi-functional

timer/PPG

1unit/4ch.

1unit

0.55

0.04

1.09

0.09

2.17

0.17

PCLK1

PCLK2

mA

Quadrature

position/Revolution

counter

A/DC

1unit

1ch.

0.20

0.31

0.39

0.62

0.78

-

Muli-function serial

Document Number: 002-04868 Rev. *F

Page 82 of 167

CY9B460R Series

12.3.2 Pin Characteristics

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= 0V)

Value

Typ

Parameter

Symbol

Pin name

CMOS

Conditions

Unit

Remarks

Min

Max

hysteresis

input pin,

MD0, MD1

-

V_CC×0.8

-

V_CC+ 0.3

V

"H" level input

voltage

(hysteresis

input)

5V tolerant

input pin

V_IHS

-

V_CC×0.8

V_CC×0.7

-

V_SS+ 5.5

V

Input pin

doubled as

I²C Fm+

CMOS

hysteresis

input pin,

MD0, MD1

-

V_SS- 0.3

-

V_CC×0.2

V

"L" level input

voltage

(hysteresis

input)

5V tolerant

input pin

V_ILS

-

V_SS- 0.3

V_SS

-

V_CC×0.2

V_CC×0.3

V

Input pin

doubled as

I²C Fm+

V_CC≥ 4.5 V,

I_OH= - 4mA

4mA type

8mA type

V_CC- 0.5

-

V_CC

V

V_CC< 4.5 V,

I_OH= - 2mA

V_CC≥ 4.5 V,

I_OH= - 8mA

V_CC

V_OH

V_CC< 4.5 V,

I_OH= - 4mA

"H" level output

voltage

V_CC≥ 4.5 V,

I_OH= - 12mA

12mA type

V_CC- 0.5

-

V_CC

V

V_CC< 4.5 V,

I_OH= - 8mA

V_CC≥ 4.5 V,

I_OH= - 4mA

The pin

doubled as

I²C Fm+

V_CC

At GPIO

V_CC< 4.5 V,

I_OH= - 3mA

Document Number: 002-04868 Rev. *F

Page 83 of 167

CY9B460R Series

Value

Typ

Parameter

Symbol

Pin name

Conditions

V_CC≥ 4.5 V,

Unit

Remarks

Min

Max

I_OL= 4mA

4mA type

V_SS

-

0.4

V

V_CC< 4.5 V,

I_OL= 2mA

V_CC≥ 4.5 V,

I_OH= 8mA

8mA type

V_SS

-

0.4

V

V_CC< 4.5 V,

I_OH= 4mA

V_CC≥ 4.5 V,

I_OL= 12mA

"L" level output

voltage

V_OL

12mA type

V_SS

V_CC< 4.5 V,

I_OL= 8mA

V_CC≥ 4.5 V,

I_OH= 4mA

At GPIO

The pin

V_CC< 4.5 V,

I_OH= 3mA

doubled as

V_SS

-

0.4

+ 5

V

I²C Fm+

At I²C

Fm+

V_CC≤ 5.5 V,

I_OH= 20mA

Input leak

current

I_IL

-

- 5

μA

kΩ

V_CC≥ 4.5 V

25

30

50

80

100

200

Pull-up resistor

value

R_PU

Pull-up pin

V_CC< 4.5 V

Other than

VCC,

VBAT,

VSS,

AVCC,

AVSS,

AVRH

Input

capacitance

C_IN

-

5

15

pF

Document Number: 002-04868 Rev. *F

Page 84 of 167

CY9B460R Series

12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Max

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

V

_CC≥ 4.5V

4

48

When crystal oscillator is

connected

MHz

V_CC< 4.5V

20

Input frequency

Input clock cycle

F_CH

V

_CC≥ 4.5V

V_CC< 4.5V

_CC≥ 4.5V

V_CC< 4.5V

48

MHz

When using external clock

20

X0,

X1

V

20.83

50

250

t_CYLH

-

ns

%

When using external clock

P_WH/t_CYLH

P_WL/t_CYLH

,

Input clock pulse

width

45

-

55

5

t_CF,

t_CR

Input clock rising time

and falling time

-

ns

F_CC

-

160

80

MHz

Base clock (HCLK/FCLK)

APB0 bus clock*²

APB1 bus clock*²

APB2 bus clock*²

F_CP0

F_CP1

F_CP2

Internal operating

clock*¹frequency

160

80

-

6.25

12.5

6.25

12.5

-

ns

Base clock (HCLK/FCLK)

APB0 bus clock*²

APB1 bus clock*²

APB2 bus clock*²

t_CYCC

t_CYCP0

t_CYCP1

t_CYCP2

Internal operating

clock*¹cycle time

*1: For more information about each internal operating clock, see "Chapter: Clock" in "FM4 Family Peripheral Manual".

*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.

X0

Document Number: 002-04868 Rev. *F

Page 85 of 167

CY9B460R Series

12.4.2 Sub Clock Input Characteristics

(V_BAT= 2.7V to 5.5V, V_SS= 0V)

Value

Typ

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

When crystal

oscillator is

connected

-

32.768

-

kHz

Input frequency

1/ t_CYLL

When using

external clock

-

32

10

45

-

100

31.25

55

kHz

μs

X0A,

X1A

When using

external clock

Input clock cycle

t_CYLL

-

PWH/t_CYLL

,

When using

external clock

Input clock pulse width

%

PWL/t_CYLL

0.8 × V_BAT

X0A

AT

V_BAT

V_BATV_B

12.4.3 Built-in CR Oscillation Characteristics

◼Built-in High-speed CR

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Typ

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Tj = -20°C to + 105°C

Tj = - 40°C to + 125°C

3.92

3.88

3

4

4.08

4.12

5

Clock frequency

F_CRH

When trimming*1

MHz

F_CRH

When not trimming

*2

Frequency

stabilization time

t_CRWT

-

30

μs

*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.

*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-

speed CR clock as source clock.

◼Built-in Low-speed CR

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Typ

Max

Clock frequency

F_CRL

-

50

100

150

kHz

Document Number: 002-04868 Rev. *F

Page 86 of 167

CY9B460R Series

12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Typ

Unit

Remarks

Parameter

Symbol

Min

Max

PLL oscillation stabilization wait time*¹

(LOCK UP time)

t_LOCK

200

-

μs

PLL input clock frequency

F_PLLI

-

4

-

16

MHz

PLL multiplication rate

13

200

-

80

multiplier

MHz

F_PLLO

F_CLKPLL

320

160

PLL macro oscillation clock frequency

Main PLL clock frequency*²

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM4 Family Peripheral Manual".

12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Typ

Unit

Remarks

Parameter

Symbol

Min

Max

PLL oscillation stabilization wait time*¹

(LOCK UP time)

t_LOCK

200

-

μs

F_PLLI

-

3.8

50

190

-

4

-

4.2

75

MHz

PLL input clock frequency

PLL multiplication rate

multiplier

MHz

PLL macro oscillation clock frequency

Main PLL clock frequency*²

F_PLLO

F_CLKPLL

-

320

160

-

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM4 Family Peripheral Manual ".

Note:

−

Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has

been trimmed.

12.4.6 Reset Input Characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

t_INITX

Pin name

Condition

Unit

ns

Remarks

Min

Max

Reset input time

INITX

-

500

-

Document Number: 002-04868 Rev. *F

Page 87 of 167

CY9B460R Series

12.4.7 Power-on Reset Timing

(V_SS= 0V, T_A= - 40°C to + 85°C)

Value

Typ

Name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

1

t_OFF

dV/dt

t_PRT

-

50

-

ms

*

Power supply shut down time

Power ramp rate

VCC

V_CC: 0.2V to 2.70V

-

1.3

1000 mV/µs *²

0.60 ms

Time until releasing Power-on reset

0.33

*1: V_CCmust be held below 0.2V for a minimum period of t_OFF. Improper initialization may occur if this condition is not met.

*2: This dV/dt characteristic is applied at the power-on of cold start (t_OFF>50ms).

Note:

− If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.

2.7V

V_CC

V_DH

0.2V

dV/dt

tPRT

tOFF

Internal RST

release

start

RST Active

CPU Operation

Glossary:

V_DH: detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics”.

12.4.8 GPIO Output Characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Unit

Value

Parameter

Symbol

Pin name

Conditions

Min

Max

50

32

V

_CC≥ 4.5 V

-

MHz

Output frequency

t_PCYCLE

Pxx*

V_CC< 4.5 V

*: GPIO is a target.

Pxx

t_PCYCLE

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Page 88 of 167

CY9B460R Series

12.4.9 External Bus Timing

External bus clock output characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Max

Min

V

_CC≥ 4.5 V

-

50*²

32*³

MHz

Output frequency

t_CYCLE

MCLKOUT*¹

V_CC< 4.5 V

*1: The external bus clock (MCLKOUT) is a divided clock of HCLK.

For more information about setting of clock divider, see "Chapter: External Bus Interface" in “FM4 Family Peripheral Manual”.

*2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100MHz.

*3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64MHz.

0.8 × Vcc

MCLK

t_CYCLE

External bus signal input/output characteristics

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Parameter

Symbol

V_IH

Conditions

Value

Unit

Remarks

0.8 × V_CC

0.2 × V_CC

0.8 × V_CC

0.2 × V_CC

V

Signal input characteristics

V_IL

-

V_OH

V_OL

Signal output characteristics

V_IH

V_IL

V_IH

V_IL

Signal input

V_OH

V_OL

V_OH

V_OL

Signal output

Document Number: 002-04868 Rev. *F

Page 89 of 167

CY9B460R Series

Separate Bus Access Asynchronous SRAM Mode

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

t_OEW

Pin name

MOEX

Conditions

Unit

Max

Min

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

MOEX

MCLK×n-3

-

ns

Minimum pulse width

-9

+9

MCSX[7:0],

MAD[24:0]

MCSX↓→Address output

delay time

t_{CSL – AV}

t_{OEH - AX}

t_{CSL - OEL}

t_{OEH - CSH}

t_{CSL - RDQML}

t_{DS - OE}

-12

+12

MCLK×m+9

MCLK×m+12

MCLK×m+9

MCLK×m+12

MCLK×m+9

MCLK×m+12

MCLK×m+9

MCLK×m+12

-

MOEX,

MOEX↑→Address hold

time

0

ns

MAD[24:0]

MCLK×m-9

MCSX↓→

MOEX↓ delay time

MCLK×m-12

MOEX,

MCSX[7:0]

MOEX↑→

0

MCSX↑ time

MCLK×m-9

MCSX↓→MDQM↓

delay time

MCSX,

MDQM[1:0]

MCLK×m-12

20

38

MOEX,

Data set up→MOEX↑

time

MADATA[15:0]

-

MOEX↑→

MOEX,

t_{DH - OE}

0

-

Data hold time

MADATA[15:0]

MWEX

t_WEW

MWEX

MCLK×n-3

0

Minimum pulse width

MCLK×m+9

MCLK×m+12

MCLK×n+9

MCLK×n+12

MCLK×m+9

MCLK×m+12

MCLK×n+9

MCLK×n+12

MCLK+9

MWEX,

MWEX↑→Address output

delay time

t_{WEH - AX}

t_{CSL - WEL}

t_{WEH - CSH}

t_CSL-WDQML

t_CSL-DX

MAD[24:0]

MCLK×n-9

MCSX↓→MWEX↓ delay

time

MCLK×n-12

MWEX,

MCSX[7:0]

MWEX↑→MCSX↑ delay

time

0

MCLK×n-9

MCLK×n-12

MCLK-9

MCSX,

MCSX↓→MDQM↓ delay

time

MDQM[1:0]

MCSX↓→

MCSX,

Data output time

MADATA[15:0]

MCLK-12

MCLK+12

MCLK×m+9

MCLK×m+12

MWEX↑→

MWEX,

t_{WEH - DX}

0

Data hold time

MADATA[15:0]

Note:

When the external load capacitance C_L= 30pF (m=0 to 15, n=1 to 16)

−

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CY9B460R Series

t_CYCLE

MCLK

t_OEH-CSH

t_WEH-CSH

t_WEH-AX

MCSX[7:0]

MAD[24:0]

MOEX

t_CSL-AV

t_OEH-AX

t_CSL-AV

Address

t_CSL-OEL

t_OEW

t_CSL-WDQML

t_CSL-RDQML

MDQM[1:0]

t_CSL-WEL

t_WEW

MWEX

t_DS-OE

t_DH-OE

t_WEH-DX

MADATA[15:0]

Invalid

RD

WD

t_CSL-DX

Document Number: 002-04868 Rev. *F

Page 91 of 167

CY9B460R Series

Separate Bus Access Synchronous SRAM Mode

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

t_AV

Pin name

MCLK,

Conditions

Unit

Max

Min

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

9

Address delay time

1

ns

MAD[24:0]

12

9

t_CSL

t_CSH

t_REL

t_REH

t_DS

12

9

MCLK,

MCSX delay time

MOEX delay time

MCSX[7:0]

12

9

12

9

MCLK,

MOEX

12

19

37

Data set up

MCLK,

-

→MCLK↑ time

MADATA[15:0]

MCLK↑→

MCLK,

t_DH

0

1

Data hold time

MADATA[15:0]

9

t_WEL

t_WEH

t_DQML

t_DQMH

t_ODS

t_OD

12

9

MCLK,

MWEX

MWEX delay time

12

9

12

9

MCLK,

MDQM[1:0]

delay time

MDQM[1:0]

12

MCLK+18

MCLK+24

MCLK↑→

MCLK,

MCLK+1

1

ns

Data output time

MADATA[15:0]

18

24

MCLK↑→

MCLK,

Data hold time

MADATA[15:0]

Note:

When the external load capacitance C_L= 30pF

−

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Page 92 of 167

CY9B460R Series

t_CYCLE

MCLK

t_CSL

t_CSH

MCSX[7:0]

MAD[24:0]

MOEX

t_AV

Address

t_REL

t_REH

t_DQML

t_DQMH

t_DQML

t_DQMH

t_WEH

t_OD

MDQM[1:0]

t_WEL

MWEX

t_DS

t_DH

MADATA[15:0]

RD

Invalid

WD

t_ODS

Document Number: 002-04868 Rev. *F

Page 93 of 167

CY9B460R Series

Multiplexed Bus Access Asynchronous SRAM Mode

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Max

Min

V_CC≥ 4.5V

V_CC< 4.5V

10

20

Multiplexed address

delay time

t_ALE-CHMADV

0

ns

MALE,

MADATA[15:0]

V_CC≥ 4.5V

V_CC< 4.5V

MCLK×n+0

MCLK×n+10

MCLK×n+20

Multiplexed address

hold time

t_CHMADH

ns

Note:

−

When the external load capacitance C_L= 30pF (m=0 to 15, n=1 to 16)

MCLK

MCSX[7:0]

MALE

MAD [24:0]

MOEX

MDQM [1:0]

MWEX

MADATA[15:0]

Document Number: 002-04868 Rev. *F

Page 94 of 167

CY9B460R Series

Multiplexed Bus Access Synchronous SRAM Mode

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

ns

Remarks

Min

Max

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

9

t_CHAL

1

12

9

ns

MCLK,

MALE delay time

ALE

t_CHAH

12

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

MCLK↑→

Multiplexed address

delay time

t_CHMADV

1

t_OD

ns

MCLK,

MADATA[15:0]

MCLK↑→

Multiplexed data output

time

t_CHMADX

t_OD

Note:

−

When the external load capacitance C_L= 30pF

MCLK

MCSX[7:0]

MALE

MAD [24:0]

MOEX

MDQM [1:0]

MWEX

MADATA[15:0]

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Page 95 of 167

CY9B460R Series

NAND Flash Mode

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Max

Min

V_CC≥ 4.5V

V_CC< 4.5V

MNREX

t_NREW

MNREX

MCLK×n-3

-

ns

Min pulse width

V_CC≥ 4.5V 20

V_CC< 4.5V 38

-

Data set up

MNREX,

t_{DS – NRE}

→MNREX↑ time

MADATA[15:0]

V_CC≥ 4.5V

0

MNREX↑→

MNREX,

t_{DH – NRE}

-

Data hold time

MADATA[15:0]

V_CC< 4.5V

V_CC≥ 4.5V MCLK×m-9

V_CC< 4.5V MCLK×m-12

V_CC≥ 4.5V MCLK×m-9

V_CC< 4.5V MCLK×m-12

V_CC≥ 4.5V MCLK×m-9

V_CC< 4.5V MCLK×m-12

MCLK×m+9

MCLK×m+12

MNALE↑→

MNALE,

MNWEX

t_{ALEH - NWEL}

t_{ALEL - NWEL}

t_{CLEH - NWEL}

t_{NWEH - CLEL}

t_NWEW

ns

MNWEX delay time

MCLK×m+9

MCLK×m+12

MCLK×m+9

MCLK×m+12

MCLK×m+9

MCLK×m+12

MNALE↓→

MNALE,

MNWEX

MNWEX delay time

MNCLE↑→

MNCLE,

MNWEX

MNWEX delay time

V_CC≥ 4.5V

0

MNWEX↑→

MNCLE,

MNWEX

MNCLE delay time

V_CC< 4.5V

V_CC≥ 4.5V

MCLK×n-3

V_CC< 4.5V

MNWEX

-

Min pulse width

V_CC≥ 4.5V - 9

V_CC< 4.5V -12

+ 9

MNWEX↓→

MNWEX,

t_{NWEL – DV}

t_{NWEH – DX}

Data output time

MADATA[15:0]

+12

V_CC≥ 4.5V

0

MCLK×m+9

MCLK×m+12

MNWEX↑→

MNWEX,

Data hold time

MADATA[15:0]

V_CC< 4.5V

Note:

−

When the external load capacitance C_L= 30pF (m=0 to 15, n=1 to 16)

Document Number: 002-04868 Rev. *F

Page 96 of 167

CY9B460R Series

NAND Flash Read

MCLK

MNREX

MADATA[15:0]

Read

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Page 97 of 167

CY9B460R Series

NAND Flash Address Write

MCLK

MNALE

MNCLE

MNWEX

MADATA[15:0]

Write

NAND Flash Command Write

MCLK

MNALE

MNCLE

MNWEX

MADATA[15:0]

Write

Document Number: 002-04868 Rev. *F

Page 98 of 167

CY9B460R Series

External Ready Input Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

MCLK↑

Symbol

Pin name

Conditions

V_CC≥ 4.5V

V_CC< 4.5V

Unit

Remarks

Min

Max

19

37

MCLK,

MRDY

MRDY input

setup time

t_RDYI

-

ns

When RDY is input

···

MCLK

Over 2cycle

Original

MOEX

MWEX

t_RDYI

MRDY

When RDY is released

··· ···

MCLK

2 cycle

Extended

MOEX

MWEX

tRDYI

0.5×VCC

MRDY

Document Number: 002-04868 Rev. *F

Page 99 of 167

CY9B460R Series

SDRAM Mode

(V_CC= 2.7V to 3.6V, V_SS= 0V)

Value

Parameter

Symbol

t_CYCSD

t_AOSD

Pin name

MSDCLK

Unit

Min

Max

Output frequency

-

32

MHz

ns

MSDCLK,

MAD[15:0]

Address delay time

2

12

20

12

-

MSDCLK,

MADATA[31:0]

MSDCLK↑→Data output delay time t_DOSD

2

1

2

23

0

ns

MSDCLK↑→Data output

t_DOZSD

MSDCLK,

MADATA[31:0]

Hi-Z time

MSDCLK,

MDQM[1:0]

MDQM[1:0] delay time

MCSX delay time

MRASX delay time

MCASX delay time

MSDWEX delay time

MSDCKE delay time

Data set up time

t_WROSD

t_MCSSD

t_RASSD

t_CASSD

t_MWESD

t_CKESD

t_DSSD

MSDCLK,

MCSX8

MSDCLK,

MRASX

MSDCLK,

MCASX

MSDCLK,

MSDWEX

MSDCLK,

MSDCKE

MSDCLK,

MADATA[31:0]

MSDCLK,

MADATA[31:0]

Data hold time

t_DHSD

-

Note:

When the external load capacitance C_L= 30pF

−

Document Number: 002-04868 Rev. *F

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CY9B460R Series

SDRAM Access

t_CYCSD

MSDCLK

MAD[24:0]

MDQM[1:0]

MCSX

t_AOSD

Address

t_WROSD

t_MCSSD

t_RASSD

MRASX

t_CASSD

t_MWESD

t_CKESD

MCASX

MSDWEX

MSDCKE

t_DSSD

t_DHSD

MADATA[15:0]

RD

t_DOSD

t_DOZSD

WD

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CY9B460R Series

12.4.10 Base Timer Input Timing

Timer input timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Max

TIOAn/TIOBn

(when using as

ECK, TIN)

t_TIWH

,

Input pulse width

-

2t_CYCP

-

ns

t_TIWL

t_TIWH

t_TIWL

ECK

TIN

V_IHS

V_ILS

Trigger input timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Max

TIOAn/TIOBn

(when using as

TGIN)

t_TRGH

,

Input pulse width

-

2t_CYCP

-

ns

t_TRGL

t_TRGH

t_TRGL

V_IHS

TGIN

V_ILS

Note:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data sheet.

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CY9B460R Series

12.4.11 CSIO/UART Timing

Synchronous serial (SPI = 0, SCINV = 0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min

V_CC≥ 4.5V

Unit

name

Parameter

Symbol

Conditions

Max

Min

Max

Baud rate

-

8

-

8

Mbps

ns

Serial clock cycle time

t_SCYC

SCKx

4t_CYCP

- 30

-

4t_CYCP

-

SCKx,

SOTx

SCK↓→SOT delay time

t_SLOVI

t_IVSHI

t_SHIXI

+ 30

- 20

30

0

+ 20

ns

Internal shift

clock operation

SCKx,

SINx

SIN→SCK↑

setup time

50

0

-

SCKx,

SINx

SCK↑→SIN hold time

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

SCKx

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCKx,

SOTx

SCK↓→SOT delay time

t_SLOVE

t_IVSHE

t_SHIXE

-

50

-

30

-

ns

External shift

clock

SCKx,

SINx

SIN→SCK↑

setup time

10

20

10

20

operation

SCKx,

SINx

SCK↑→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance CL = 30pF.

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CY9B460R Series

t_SCYC

V_OH

SCK

V_OL

t_SLOVI

V_OH

V_OL

SOT

SIN

t_IVSHI

V_IH

V_IL

t_SHIXI

V_IH

V_IL

MS bit = 0

t_SLSH

t_SHSL

V_IH

tR

V_IH

SCK

V_IL

F

t

t_SLOVE

V_OH

V_OL

SOT

SIN

t_IVSHE

V_IH

V_IL

t_SHIXE

V_IH

V_IL

MS bit = 1

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CY9B460R Series

Synchronous serial (SPI = 0, SCINV = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min

-

V_CC≥ 4.5V

Unit

name

-

Parameter

Symbol

Conditions

Max

8

Min

Max

Baud rate

-

8

Mbps

ns

Serial clock cycle time

t_SCYC

SCKx

4t_CYCP

- 30

-

4t_CYCP

-

SCKx,

SOTx

SCK↑→SOT delay time

t_SHOVI

t_IVSLI

t_SLIXI

+ 30

- 20

30

0

+ 20

ns

Internal shift

clock operation

SCKx,

SINx

SIN→SCK↓

setup time

50

0

-

SCKx,

SINx

SCK↓→SIN hold time

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

SCKx

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCKx,

SOTx

SCK↑→SOT delay time

t_SHOVE

t_IVSLE

t_SLIXE

-

50

-

30

-

ns

SCKx,

SINx

External shift

clock operation

SIN→SCK↓

setup time

10

20

10

20

SCKx,

SINx

SCK↓→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 105 of 167

CY9B460R Series

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

V_OH

V_OL

SOT

SIN

t_IVSLI

V_IH

V_IL

t_SLIXI

V_IH

V_IL

MS bit = 0

t_SHSL

t_SLSH

V_IH

tF

SCK

SOT

V_IL

tR

V_IL

t_SHOVE

V_OH

V_OL

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

SIN

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 106 of 167

CY9B460R Series

Synchronous serial (SPI = 1, SCINV = 0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min

V_CC≥ 4.5V

Unit

name

Parameter

Symbol

Conditions

Max

Min

Max

Baud rate

-

8

-

8

Mbps

ns

Serial clock cycle time

t_SCYC

SCKx

4t_CYCP

- 30

-

4t_CYCP

-

SCKx,

SOTx

SCK↑→SOT delay time

t_SHOVI

t_IVSLI

t_SLIXI

+ 30

- 20

+ 20

ns

SCKx,

SINx

SIN→SCK↓

setup time

Internal shift

clock operation

50

0

-

30

-

SCKx,

SINx

SCK↓→SIN hold time

SOT→SCK↓ delay time

0

SCKx,

SOTx

t_SOVLI

2t_CYCP- 30

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

SCKx

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCKx,

SOTx

SCK↑→SOT delay time

t_SHOVE

t_IVSLE

t_SLIXE

-

50

-

30

-

ns

SCKx,

SINx

External shift

clock operation

SIN→SCK↓

setup time

10

20

10

20

SCKx,

SINx

SCK↓→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 107 of 167

CY9B460R Series

t_SCYC

V_OH

V_OL

SCK

SOT

t_SHOVI

t_SOVLI

V_OH

V_OL

V_OH

V_OL

t_IVSLI

t_SLIXI

V_IH

V_IL

V_IH

V_IL

SIN

MS bit = 0

t_SLSH

t_SHSL

SCK

V_IH

tF

V_IH

V_IL

V_IH

V_IL

t_SHOVE

tR

*

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

MS bit = 1

*: Changes when writing to TDR register

Document Number: 002-04868 Rev. *F

Page 108 of 167

CY9B460R Series

Synchronous serial (SPI = 1, SCINV = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min

V_CC≥ 4.5V

Unit

name

Parameter

Symbol

Conditions

Max

Min

Max

Baud rate

-

8

-

8

Mbps

ns

Serial clock cycle time

t_SCYC

SCKx

4t_CYCP

- 30

-

4t_CYCP

-

SCKx,

SOTx

SCK↓→SOT delay time

t_SLOVI

t_IVSHI

t_SHIXI

t_SOVHI

+ 30

- 20

+ 20

ns

SCKx,

SINx

SIN→SCK↑

setup time

50

0

-

30

-

Internal shift

clock operation

SCKx,

SINx

SCK↑→SIN hold time

SOT→SCK↑ delay time

0

SCKx,

SOTx

2t_CYCP- 30

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

SCKx

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCKx,

SOTx

SCK↓→SOT delay time

t_SLOVE

t_IVSHE

t_SHIXE

-

50

-

30

-

ns

SCKx,

SINx

External shift

clock operation

SIN→SCK↑

setup time

10

20

10

20

SCKx,

SINx

SCK↑→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 109 of 167

CY9B460R Series

t_SCYC

V_OL

V_OH

SCK

t_SOVHI

t_SLOVI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_SHIXI

t_IVSHI

V_IH

V_IL

V_IH

V_IL

MS bit = 0

t_SHSL

t_SLSH

tR

tF

SCK

V_IH

V_IL

t_SLOVE

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 110 of 167

CY9B460R Series

When using synchronous serial chip select (SCINV = 0, CSLVL=1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-50

Max

(*¹)+0

Min

Max

(*¹)+0

SCS↓→SCK↓setup time

SCK↑→SCS↑ hold time

t_CSSI

t_CSHI

(*¹)-50

(*²)+0

(*³)-50

ns

Internal shift

clock

operation

(*²)+0

(*³)-50

(*²)+50

(*³)+50

+5t_CYCP

(*²)+50

(*³)+50

+5t_CYCP

SCS deselect time

t_CSDI

ns

+5t_CYCP

SCS↓→SCK↓setup time

SCK↑→SCS↑ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+30

-

3t_CYCP+30

-

ns

0

-

0

-

External shift

clock

operation

3t_CYCP+30

-

3t_CYCP+30

-

SCS↓→SUT delay time

SCS↑→SUT delay time

-

40

-

40

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 111 of 167

CY9B460R Series

SCS

output

tCSDI

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

SCS input

SCK input

tCSDE

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 112 of 167

CY9B460R Series

When using synchronous serial chip select (SCINV = 1, CSLVL=1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-50

Max

(*¹)+0

Min

Max

(*¹)+0

SCS↓→SCK↑setup time

SCK↓→SCS↑ hold time

t_CSSI

t_CSHI

(*¹)-50

(*²)+0

(*³)-50

ns

Internal shift

clock

operation

(*²)+0

(*³)-50

(*²)+50

(*³)+50

+5t_CYCP

(*²)+50

(*³)+50

+5t_CYCP

SCS deselect time

t_CSDI

ns

+5t_CYCP

SCS↓→SCK↑setup time

SCK↓→SCS↑ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+30

-

3t_CYCP+30

-

ns

0

-

0

-

External shift

clock

operation

3t_CYCP+30

-

3t_CYCP+30

-

SCS↓→SOT delay time

SCS↑→SOT delay time

-

40

-

40

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 113 of 167

CY9B460R Series

SCS

output

t^CSDI

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

SCS input

SCK input

tCSDE

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 114 of 167

CY9B460R Series

When using synchronous serial chip select (SCINV = 0, CSLVL=0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-50

Max

(*¹)+0

Min

Max

(*¹)+0

SCS↑→SCK↓setup time

SCK↑→SCS↓ hold time

t_CSSI

t_CSHI

(*¹)-50

(*²)+0

(*³)-50

ns

Internal shift

clock

operation

(*²)+0

(*³)-50

(*²)+50

(*³)+50

+5t_CYCP

(*²)+50

(*³)+50

+5t_CYCP

SCS deselect time

t_CSDI

ns

+5t_CYCP

SCS↑→SCK↓setup time

SCK↑→SCS↓ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+30

-

3t_CYCP+30

-

ns

0

-

0

-

External shift

clock

operation

3t_CYCP+30

-

3t_CYCP+30

-

SCS↑→SOT delay time

SCS↓→SOT delay time

-

40

-

40

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 115 of 167

CY9B460R Series

tCSDI

SCS

output

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

tCSDE

SCS input

SCK input

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 116 of 167

CY9B460R Series

When using synchronous serial chip select (SCINV = 1, CSLVL=0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-50

Max

(*¹)+0

Min

Max

(*¹)+0

SCS↑→SCK↑setup time

SCK↓→SCS↓ hold time

t_CSSI

t_CSHI

(*¹)-50

(*²)+0

(*³)-50

ns

Internal shift

clock

operation

(*²)+0

(*³)-50

(*²)+50

(*³)+50

+5t_CYCP

(*²)+50

(*³)+50

+5t_CYCP

SCS deselect time

t_CSDI

ns

+5t_CYCP

SCS↑→SCK↑setup time

SCK↓→SCS↓ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+30

-

3t_CYCP+30

-

ns

0

-

0

-

External shift

clock

operation

3t_CYCP+30

-

3t_CYCP+30

-

SCS↑→SOT delay time

SCS↓→SOT delay time

-

40

-

40

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 117 of 167

CY9B460R Series

tCSDI

SCS

output

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

tCSDE

SCS input

SCK input

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 118 of 167

CY9B460R Series

High-speed synchronous serial (SPI = 0, SCINV = 0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min Max

V_CC≥ 4.5V

name

Parameter

Serial clock cycle time

SCK↓→SOT delay time

Symbol

t_SCYC

Conditions

Unit

Min

4t_CYCP

Max

SCKx

4t_CYCP

-10

-

ns

SCKx,

SOTx

t_SLOVI

+10

-10

+10

-

Internal shift

clock operation

14

SIN→SCK↑

SCKx,

SINx

t_IVSHI

-

12.5

ns

setup time

12.5*

SCKx,

SINx

SCK↑→SIN hold time

t_SHIXI

t_SLSH

t_SHSL

5

-

5

-

ns

Serial clock "L" pulse width

Serial clock "H" pulse width

SCKx

2t_CYCP– 5

t_CYCP+ 10

2t_CYCP– 5

t_CYCP+ 10

SCKx,

SOTx

SCK↓→SOT delay time

t_SLOVE

t_IVSHE

t_SHIXE

-

15

-

15

-

ns

External shift

clock operation

SIN→SCK↑

SCKx,

SINx

5

setup time

SCKx,

SINx

SCK↑→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

These characteristics only guarantee the following pins.

−

No chip select:

Chip select:

SIN4_1, SOT4_1, SCK4_1

SIN6_1, SOT6_1, SCK6_1, SCS6_1

When the external load capacitance CL = 30pF. (For *, when CL = 10pF)

Document Number: 002-04868 Rev. *F

Page 119 of 167

CY9B460R Series

t_SCYC

V_OH

SCK

V_OL

t_SLOVI

V_OH

V_OL

SOT

SIN

t_IVSHI

V_IH

V_IL

t_SHIXI

V_IH

V_IL

MS bit = 0

t_SLSH

t_SHSL

V_IH

tR

V_IH

SCK

V_IL

F

t

t_SLOVE

V_OH

V_OL

SOT

SIN

t_IVSHE

V_IH

V_IL

t_SHIXE

V_IH

V_IL

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 120 of 167

CY9B460R Series

High-speed synchronous serial (SPI = 0, SCINV = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min Max

V_CC≥ 4.5V

name

Parameter

Symbol

Conditions

Unit

Min

Max

Serial clock cycle time

t_SCYC

t_SHOVI

t_IVSLI

SCKx

4t_CYCP

-10

-

4t_CYCP

-

ns

SCKx,

SOTx

SCK↑→SOT delay time

+10

-10

+10

Internal shift

clock operation

14

SIN→SCK↓

SCKx,

SINx

-

12.5

-

setup time

12.5*

SCKx,

SINx

SCK↓→SIN hold time

t_SLIXI

5

-

5

-

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK↑→SOT delay time

t_SLSH

t_SHSL

t_SHOVE

t_IVSLE

t_SLIXE

SCKx

2t_CYCP– 5

-

2t_CYCP– 5

-

t_CYCP+ 10

-

t_CYCP+ 10

-

SCKx,

SOTx

-

15

-

15

-

External shift

clock operation

SIN→SCK↓

SCKx,

SINx

5

setup time

SCKx,

SINx

SCK↓→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

These characteristics only guarantee the following pins.

−

No chip select:

Chip select:

SIN4_1, SOT4_1, SCK4_1

SIN6_1, SOT6_1, SCK6_1, SCS6_1

When the external load capacitance CL = 30pF. (For *, when CL = 10pF)

Document Number: 002-04868 Rev. *F

Page 121 of 167

CY9B460R Series

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

V_OH

V_OL

SOT

SIN

t_IVSLI

V_IH

V_IL

t_SLIXI

V_IH

V_IL

MS bit = 0

t_SHSL

t_SLSH

V_IH

tF

SCK

V_IL

tR

V_IL

t_SHOVE

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 122 of 167

CY9B460R Series

High-speed synchronous serial (SPI = 1, SCINV = 0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min Max

V_CC≥ 4.5V

name

Parameter

Symbol

Conditions

Unit

Min

Max

Serial clock cycle time

t_SCYC

t_SHOVI

t_IVSLI

SCKx

4t_CYCP

-10

-

4t_CYCP

-

ns

SCKx,

SOTx

SCK↑→SOT delay time

+10

-10

+10

14

SIN→SCK↓

SCKx,

SINx

Internal shift

clock operation

-

12.5

-

setup time

12.5*

SCKx,

SINx

SCK↓→SIN hold time

t_SLIXI

5

-

5

-

SCKx,

SOTx

SOT→SCK↓ delay time

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK↑→SOT delay time

t_SOVLI

t_SLSH

t_SHSL

t_SHOVE

t_IVSLE

t_SLIXE

2t_CYCP– 10

-

2t_CYCP– 10

-

SCKx

2t_CYCP– 5

-

2t_CYCP– 5

-

t_CYCP+ 10

-

t_CYCP+ 10

-

SCKx,

SOTx

-

15

-

15

-

External shift

clock operation

SIN→SCK↓

SCKx,

SINx

5

setup time

SCKx,

SINx

SCK↓→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

tCYCP indicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

These characteristics only guarantee the following pins.

−

No chip select:

Chip select:

SIN4_1, SOT4_1, SCK4_1

SIN6_1, SOT6_1, SCK6_1, SCS6_1

When the external load capacitance CL = 30pF. (For *, when CL = 10pF)

Document Number: 002-04868 Rev. *F

Page 123 of 167

CY9B460R Series

t_SCYC

V_OH

V_OL

SCK

SOT

SIN

t_SHOVI

t_SOVLI

V_OH

V_OL

V_OH

V_OL

t_IVSLI

t_SLIXI

V_IH

V_IL

V_IH

V_IL

MS bit = 0

t_SLSH

t_SHSL

SCK

V_IH

tF

V_IH

V_IL

V_IH

V_IL

t_SHOVE

tR

*

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

MS bit = 1

*: Changes when writing to TDR register

Document Number: 002-04868 Rev. *F

Page 124 of 167

CY9B460R Series

High-speed synchronous serial (SPI = 1, SCINV = 1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

Min Max

V_CC≥ 4.5V

name

Parameter

Symbol

Conditions

Unit

Min

Max

Internal shift clock operation

t_SCYC

t_SLOVI

t_IVSHI

t_SHIXI

t_SOVHI

t_SLSH

t_SHSL

t_SLOVE

t_IVSHE

t_SHIXE

SCKx

4t_CYCP

-10

-

4t_CYCP

-

ns

SCKx,

SOTx

SCK↓→SOT delay time

+10

-10

+10

14

SIN→SCK↑

SCKx,

SINx

Internal shift

clock operation

-

12.5

-

setup time

12.5*

SCKx,

SINx

SCK↑→SIN hold time

5

-

5

-

SCKx,

SOTx

SOT→SCK↑ delay time

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK↓→SOT delay time

2t_CYCP– 10

-

2t_CYCP– 10

-

SCKx

2t_CYCP– 5

-

2t_CYCP– 5

-

t_CYCP+ 10

-

t_CYCP+ 10

-

SCKx,

SOTx

-

15

-

15

-

External shift

clock operation

SIN→SCK↑

SCKx,

SINx

5

setup time

SCKx,

SINx

SCK↑→SIN hold time

-

SCK falling time

SCK rising time

tF

SCKx

-

5

-

5

ns

tR

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

These characteristics only guarantee the following pins.

−

No chip select:

Chip select:

SIN4_1, SOT4_1, SCK4_1

SIN6_1, SOT6_1, SCK6_1, SCS6_1

When the external load capacitance CL = 30pF. (For *, when CL = 10pF)

Document Number: 002-04868 Rev. *F

Page 125 of 167

CY9B460R Series

t_SCYC

V_OL

V_OH

SCK

t_SOVHI

t_SLOVI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_SHIXI

t_IVSHI

V_IH

V_IL

V_IH

V_IL

MS bit = 0

t_SHSL

t_SLSH

tR

tF

SCK

V_IH

V_IL

t_SLOVE

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 126 of 167

CY9B460R Series

When using high-speed synchronous serial chip select (SCINV = 0, CSLVL=1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-20

Max

(*¹)+0

Min

Max

(*¹)+0

SCS↓→SCK↓setup time

SCK↑→SCS↑ hold time

t_CSSI

t_CSHI

(*¹)-20

(*²)+0

ns

(*²)+0

(*²)+20

Internal shift

clock operation

(*³)-20

+5t_CYCP

(*³)+20

+5t_CYCP

(*³)-20

+5t_CYCP

(*³)+20

+5t_CYCP

SCS deselect time

t_CSDI

ns

SCS↓→SCK↓setup time

SCK↑→SCS↑ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+15

-

3t_CYCP+15

-

ns

0

-

0

-

External shift

clock operation

3t_CYCP+15

-

3t_CYCP+15

-

SCS↓→SOT delay time

SCS↑→SOT delay time

-

25

-

25

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 127 of 167

CY9B460R Series

SCS

output

tCSDI

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

SCS input

SCK input

tCSDE

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 128 of 167

CY9B460R Series

When using high-speed synchronous serial chip select (SCINV = 1, CSLVL=1)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-20

Max

(*¹)+0

Min

(*¹)-20

Max

(*¹)+0

SCS↓→SCK↑setup time

SCK↓→SCS↑ hold time

t_CSSI

t_CSHI

ns

Internal shift

clock

operation

(*²)+0

(*³)-20

(*²)+20

(*³)+20

+5t_CYCP

(*²)+0

(*³)-20

(*²)+20

(*³)+20

+5t_CYCP

SCS deselect time

t_CSDI

ns

+5t_CYCP

SCS↓→SCK↑setup time

SCK↓→SCS↑ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+15

-

3t_CYCP+15

-

ns

0

-

0

-

External shift

clock

operation

3t_CYCP+15

-

3t_CYCP+15

-

SCS↓→SOT delay time

SCS↑→SOT delay time

-

25

-

25

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 129 of 167

CY9B460R Series

SCS

output

t^CSDI

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

SCS input

SCK input

tCSDE

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 130 of 167

CY9B460R Series

When using high-speed synchronous serial chip select (SCINV = 0, CSLVL=0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-20

Max

(*¹)+0

Min

Max

(*¹⁾+0

SCS↑→SCK↓setup time

SCK↑→SCS↓ hold time

t_CSSI

t_CSHI

(*¹)-20

(*²)+0

ns

(*²)+0

(*²)+20

Internal shift

clock operation

(*³)-20

+5t_CYCP

(*³)+20

+5t_CYCP

(*³)-20

+5t_CYCP

(*³)+20

+5t_CYCP

SCS deselect time

t_CSDI

ns

SCS↑→SCK↓setup time

SCK↑→SCS↓ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+15

-

3t_CYCP+15

-

ns

0

-

0

-

External shift

clock operation

3t_CYCP+15

-

3t_CYCP+15

-

SCS↑→SOT delay time

SCS↓→SOT delay time

-

25

-

25

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this datasheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 131 of 167

CY9B460R Series

tCSDI

SCS

output

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

tCSDE

SCS input

SCK input

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 132 of 167

CY9B460R Series

When using high-speed synchronous serial chip select (SCINV = 1, CSLVL=0)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

V_CC< 4.5V

V_CC≥ 4.5V

Parameter

Symbol

Conditions

Unit

Min

(*¹)-20

Max

(*¹)+0

Min

Max

(*¹)+0

SCS↑→SCK↑setup time

SCK↓→SCS↓ hold time

t_CSSI

t_CSHI

(*¹)-20

(*²)+0

(*³)-20

ns

Internal shift

clock

operation

(*²)+0

(*³)-20

(*²)+20

(*³)+20

+5t_CYCP

(*²)+20

(*³)+20

+5t_CYCP

SCS deselect time

t_CSDI

ns

+5t_CYCP

SCS↑→SCK↑setup time

SCK↓→SCS↓ hold time

SCS deselect time

t_CSSE

t_CSHE

t_CSDE

t_DSE

3t_CYCP+15

-

3t_CYCP+15

-

ns

0

-

0

-

External shift

clock

operation

3t_CYCP+15

-

3t_CYCP+15

-

SCS↑→SOT delay time

SCS↓→SOT delay time

-

25

-

25

-

t_DEE

0

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see "Block Diagram" in this data sheet.

−

About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM4 Family Peripheral Manual".

When the external load capacitance CL = 30pF.

Document Number: 002-04868 Rev. *F

Page 133 of 167

CY9B460R Series

tCSDI

SCS

output

tCSHI

tCSSI

SCK

output

SOT

(SPI=0)

SOT

(SPI=1)

MS bit = 0

tCSDE

SCS input

SCK input

tCSHE

tCSSE

tDEE

SOT

(SPI=0)

tDSE

SOT

(SPI=1)

MS bit = 1

Document Number: 002-04868 Rev. *F

Page 134 of 167

CY9B460R Series

External clock (EXT = 1): when in asynchronous mode only

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK falling time

t_SLSH

t_SHSL

tF

t_CYCP+ 10

-

ns

t_CYCP+ 10

-

C_L= 30pF

-

5

SCK rising time

tR

tF

t_SHSL

t_SLSH

SCK

V_IH

V_IL

Document Number: 002-04868 Rev. *F

Page 135 of 167

CY9B460R Series

12.4.12 External Input Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Min

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Max

ADTG

A/D converter trigger input

1

-

2t_CYCP

*

-

ns

FRCKx

ICxx

Free-run timer input clock

Input capture

t_INH

,

Input pulse

width

1

t_INL

DTTIxX

-

2t_CYCP

-

ns

Waveform generator

2t_CYCP+ 100*¹

500*²

INT00 to INT31,

NMIX

External interrupt,

NMI

WKUPx

500*³

Deep standby wake up

*1: t_CYCPindicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.

About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "Block

Diagram" in this data sheet.

*2: When in STOP mode, in timer mode.

*3: When in deep standby RTC mode, in deep standby STOP mode.

Document Number: 002-04868 Rev. *F

Page 136 of 167

CY9B460R Series

12.4.13 Quadrature Position/Revolution Counter Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

AIN pin "H" width

Symbol

t_AHL

Conditions

Unit

Max

Min

-

AIN pin "L" width

BIN pin "H" width

BIN pin "L" width

t_ALL

t_BHL

t_BLL

BIN rising time from

AIN pin "H" level

t_AUBU

t_BUAD

t_ADBD

t_BDAU

t_BUAU

t_AUBD

t_BDAD

t_ADBU

PC_Mode2 or PC_Mode3

AIN falling time from

BIN pin "H" level

BIN falling time from

AIN pin "L" level

AIN rising time from

BIN pin "L" level

AIN rising time from

BIN pin "H" level

2t_CYCP

*

-

ns

BIN falling time from

AIN pin "H" level

AIN falling time from

BIN pin "L" level

BIN rising time from

AIN pin "L" level

ZIN pin "H" width

ZIN pin "L" width

t_ZHL

t_ZLL

QCR:CGSC="0"

AIN/BIN rising and falling time

from determined ZIN level

t_ZABE

t_ABEZ

QCR:CGSC="1"

Determined ZIN level from

AIN/BIN rising and falling time

*: t_CYCPindicates the APB bus clock cycle time except stop when in STOP mode, in timer mode.

About the APB bus number which Quadrature Position/Revolution Counter is connected to, see “Block Diagram” in this

data sheet.

tALL

tAHL

AIN

BIN

tADBD

tAUBU

tBUAD

tBDAU

tBHL

tBLL

Document Number: 002-04868 Rev. *F

Page 137 of 167

CY9B460R Series

tBLL

tBHL

BIN

AIN

tBDAD

tBUAU

tAUBD

tADBU

tAHL

tALL

ZIN

AIN/BIN

Document Number: 002-04868 Rev. *F

Page 138 of 167

CY9B460R Series

12.4.14 I²C Timing

Standard-mode, Fast-mode

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Standard-mode

Min Max

100

Fast-mode

Min Max

Parameter

Symbol

Conditions

Unit

kHz

Remarks

SCL clock frequency

F_SCL

0

400

(Repeated) START

condition hold time

SDA ↓ → SCL ↓

t_HDSTA

4.0

-

0.6

-

μs

SCL clock "L" width

SCL clock "H" width

t_LOW

t_HIGH

4.7

4.0

-

1.3

0.6

-

μs

(Repeated) START

condition setup time

SCL ↑ → SDA ↓

t_SUSTA

4.7

-

0.6

-

μs

C_L= 30pF,

R = (Vp/I_OL)*¹

Data hold time

t_HDDAT

t_SUDAT

0

3.45*²

-

0

0.9*³

-

μs

ns

SCL ↓ → SDA ↓ ↑

Data setup time

250

100

SDA ↓ ↑ → SCL ↑

STOP condition setup

time

SCL ↑ → SDA ↑

t_SUSTO

4.0

4.7

-

0.6

1.3

-

μs

Bus free time between

"STOP condition" and

"START condition"

t_BUF

2MHz ≤

4

2t_CYCP

4t_CYCP

6t_CYCP

8t_CYCP

*

-

2t_CYCP

4t_CYCP

6t_CYCP

8t_CYCP

*

-

ns

t_CYCP<40MHz

40MHz ≤

t_CYCP<60MHz

60MHz ≤

t_CYCP<80MHz

80MHz ≤

t_CYCP<100MHz

5

Noise filter

t_SP

*

100MHz ≤

10t_CYCP

*

10t_CYCP

*

4

t_CYCP<120MHz

120MHz ≤

12t_CYCP

4

t_CYCP<140MHz

140MHz ≤

14t_CYCP

4

t_CYCP<160MHz

160MHz ≤

16t_CYCP

4

t_CYCP<180MHz

*1: R and C_Lrepresent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power

supply voltage of the pull-up resistance and I_OLindicates V_OLguaranteed current.

*2: The maximum t_HDDATmust satisfy that it does not extend at least "L" period (t_LOW) of device's SCL signal.

*3: A Fast-mode I²C bus device can be used on a Standard-mode I²C bus system as long as the device satisfies the

requirement of "t_SUDAT≥ 250 ns".

*4: t_CYCPis the APB bus clock cycle time.

About the APB bus number that I²C is connected to, see "Block Diagram" in this data sheet.

*5: The noise filter time can be changed by register settings.

Change the number of the noise filter steps according to APB bus clock frequency.

Document Number: 002-04868 Rev. *F

Page 139 of 167

CY9B460R Series

Fast-mode Plus (Fm+)

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Fast-mode Plus (Fm+)*⁶

Min Max

1000

Parameter

Symbol

Conditions

Unit

Remarks

SCL clock frequency

F_SCL

0

kHz

(Repeated) START condition

hold time

t_HDSTA

0.26

-

μs

SDA ↓ → SCL ↓

SCL clock "L" width

SCL clock "H" width

SCL clock frequency

t_LOW

0.5

-

μs

t_HIGH

t_SUSTA

0.26

(Repeated) START condition

hold time

SDA ↓ → SCL ↓

C_L= 30pF,

R = (Vp/I_OL)*¹

t_HDDAT

0

0.45*^2,*³

μs

Data setup time

t_SUDAT

t_SUSTO

50

-

ns

μs

SDA ↓ ↑ → SCL ↑

STOP condition setup time

SCL ↑ → SDA ↑

0.26

Bus free time between

"STOP condition" and

"START condition"

t_BUF

0.5

-

μs

60MHz ≤

4

6 t_CYCP

*

-

ns

t_CYCP<80MHz

80MHz ≤

8 t_CYCP

*

t_CYCP<100MHz

100MHz ≤

4

10 t_CYCP

12 t_CYCP

14 t_CYCP

16 t_CYCP

*

t_CYCP<120MHz

5

Noise filter

t_SP

*

120MHz ≤

t_CYCP<140MHz

140MHz ≤

t_CYCP<160MHz

160MHz ≤

t_CYCP<180MHz

*1: R and C_Lrepresent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power

supply voltage of the pull-up resistance and I_OLindicates V_OLguaranteed current.

*2: The maximum t_HDDATmust satisfy that it does not extend at least "L" period (t_LOW) of device's SCL signal.

*3: A Fast-mode I²C bus device can be used on a Standard-mode I²C bus system as long as the device satisfies the requirement of

"t_SUDAT≥ 250 ns".

*4: t_CYCPis the APB bus clock cycle time.

About the APB bus number that I²C is connected to, see "Block Diagram" in this data sheet.

To use Fast-mode Plus (Fm+), set the peripheral bus clock at 64 MHz or more.

*5: The noise filter time can be changed by register settings.

Change the number of the noise filter steps according to APB bus clock frequency.

*6: When using Fast-mode Plus (Fm+), set the I/O pin to the mode corresponding to I²C Fm+ in the EPFR register.

See "Chapter: I/O Port" in "FM4 Family Peripheral Manual" for the details.

Document Number: 002-04868 Rev. *F

Page 140 of 167

CY9B460R Series

SDA

SCL

Document Number: 002-04868 Rev. *F

Page 141 of 167

CY9B460R Series

12.4.15 SD Card Interface Timing

Default-Speed Mode

◼Clock CLK (All values are referred to V_IHand V_IL)

(V_CC= 2.7V to 3.6V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

S_CLK

Conditions

Remarks

Min

Max

Clock frequency Data Transfer

Mode

f_PP

0

16

MHz

kHz

Clock frequency Identification

Mode

f_OD

S_CLK

0*/100

400

C_CARD

10pF

≤

Clock low time

Clock high time

Clock rising time

Clock falling time

t_WL

S_CLK

10

-

ns

(1card)

t_WH

t_TLH

t_THL

-

10

-

*: 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required.

◼Card Inputs CMD, DAT (referenced to Clock CLK)

Value

Parameter

Input set-up time

Input hold time

Symbol

Pin name

Conditions

Remarks

ns

Min

Max

S_CMD,

t_ISU

5

-

C_CARD

10pF

≤

S_DATA3:0

S_CMD,

(1card)

t_IH

S_DATA3:0

◼Card Outputs CMD, DAT (referenced to Clock CLK)

Value

Parameter

Symbol

Pin name

Conditions

Remarks

Min

Max

S_CMD,

Output Delay time during Data

Transfer Mode

t_ODLY

0

22

50

ns

C_CARD

40pF

(1card)

≤

S_DATA3:0

S_CMD,

Output Delay time during

Identification Mode

t_ODLY

S_DATA3:0

t_WH

t_WL

V_IH

t_THL

S_CLK

V_IH

V_IL

(SD Clock)

t_TLH

t_IH

t_ISU

S_CMD,

V_IH

V_IL

V_IH

V_IL

S_DATA3:0

(Card Input)

t_ODLY(Min)

t_ODLY(Max)

S_CMD,

V_OH

V_OL

V_OH

V_OL

S_DATA3:0

(Card Output)

Default-Speed Mode

Note:

−

The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the

Host.

Document Number: 002-04868 Rev. *F

Page 142 of 167

CY9B460R Series

High-Speed Mode

◼Clock CLK (All values are referred to V_IHand V_IL)

(V_CC= 2.7V to 3.6V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

S_CLK

Conditions

Remarks

Min

Max

Clock frequency Data Transfer

Mode

f_PP

0

32

MHz

C_CARD

10pF

(1card)

≤

Clock low time

Clock high time

Clock rising time

Clock falling time

t_WL

S_CLK

7

-

ns

t_WH

t_TLH

t_THL

-

3

-

◼Card Inputs CMD, DAT (referenced to Clock CLK)

Value

Parameter

Input set-up time

Input hold time

Symbol

Pin name

Conditions

Remarks

Min

Max

S_CMD,

t_ISU

8

2

-

ns

C_CARD

10pF

≤

S_DATA3:0

S_CMD,

(1card)

t_IH

ns

S_DATA3:0

◼Card Outputs CMD, DAT (referenced to Clock CLK)

Value

Parameter

Symbol

Pin name

Conditions

Remarks

Min

Max

S_CMD,

C_L≤ 40pF

(1card)

Output Delay time during Data

Transfer Mode

t_ODLY

-

22

ns

S_DATA3:0

S_CMD,

C_L≥ 15pF

(1card)

Output Hold time

t_OH

C_L

2.5

-

ns

S_DATA3:0

Total System capacitance for

each line*

-

1card

40

pF

*: In order to satisfy severe timing, host shall drive only one card.

t_WH

t_WL

V_IH

S_CLK

V_IH

50%V_CC

t_IH

V_IL

(SD Clock)

t_TLH

t_THL

t_ISU

S_CMD,

V_IH

V_IL

V_IH

V_IL

S_DATA3:0

(Card Input)

t_OH(Min)

t_ODLY(Max)

S_CMD,

V_OH

V_OL

V_OH

V_OL

S_DATA3:0

(Card Output)

High-Speed Mode

Notes:

−

The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the

Host.

−

In high-speed mode, set the Clock frequency (fPP) and the AHB Bus Clock frequency to the same values.

Document Number: 002-04868 Rev. *F

Page 143 of 167

CY9B460R Series

12.4.16 ETM Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Max

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

2

-

9

TRACECLK,

TRACED[3:0]

Data hold

t_ETMH

ns

15

50

32

-

MHz

ns

TRACECLK

frequency

1/ t_TRACE

-

TRACECLK

20

TRACECLK

clock cycle

t_TRACE

31.25

-

ns

Note:

−

When the external load capacitance C_L= 30pF.

HCLK

TRACECLK

TRACED[3:0]

Document Number: 002-04868 Rev. *F

Page 144 of 167

CY9B460R Series

12.4.17 JTAG Timing

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

t_JTAGS

t_JTAGH

t_JTAGD

Pin name

TCK,

Conditions

Unit

Remarks

Min

Max

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

V_CC≥ 4.5V

V_CC< 4.5V

TMS, TDI setup time

15

-

ns

TMS, TDI

TCK,

TMS, TDI hold time

TDO delay time

Note:

TMS, TDI

-

25

45

TCK,

TDO

−

When the external load capacitance C_L= 30pF.

TCK

TMS/TDI

TDO

Document Number: 002-04868 Rev. *F

Page 145 of 167

CY9B460R Series

12.5 12-bit A/D Converter

Electrical Characteristics for the A/D Converter

(V_CC= AV_CC= 2.7V to 5.5V, V_SS= AV_SS= AVRL = 0V)

Value

Typ

name

Parameter

Resolution

Symbol

Unit

bit

Remarks

Min

Max

-

12

Integral Nonlinearity

- 4.5

+ 4.5

LSB

mV

Differential

Nonlinearity

-

-2.5

- 15

-

+ 2.5

AVRH = 2.7V to

5.5V

Zero transition voltage V_ZT

ANxx

+ 15

Full-scale transition

V_FST

AVRH - 15

AVRH + 15

mV

voltage

Conversion time

Sampling time*²

-

0.5*¹

0.15

0.3

-

μs

AV_CC≥ 4.5V

AV_CC< 4.5V

AV_CC≥ 4.5V

AV_CC< 4.5V

Ts

10

25

1000

Compare clock

cycle*³

Tcck

Tstt

-

ns

μs

50

State transition time to

operation permission

-

1.0

A/D 1unit

operation

-

0.69

1.0

0.92

18

mA

μA

Power supply current

(analog + digital)

-

AVCC

AVRH

When A/D stop

A/D 1unit

operation

AVRH=5.5V

Reference power

supply current

(AVRH)

1.1

1.97

mA

-

0.3

-

6.3

μA

pF

When A/D stop

Analog input capacity

C_AIN

R_AIN

-

12.05

1.2

1.8

4

AV_CC≥ 4.5V

AV_CC< 4.5V

Analog input

resistance

-

kΩ

Interchannel disparity

-

LSB

μA

V

Analog port input leak

current

ANxx

5

Analog input voltage

-

AV_SS

4.5

-

AVRH

AV_CC

Tcck < 50ns

Tcck ≥ 50ns

Reference voltage

AVRH

V

2.7

*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).

The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns

(AV_CC≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*⁴of sampling

time and compare clock cycle, see "Chapter: A/D Converter" in "FM4 Family Peripheral Manual Analog Macro Part". The

register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at

Base clock (HCLK).

*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1).

*3: The compare time (Tc) is the value of (Equation 2).

*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock

are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in

this data sheet.

Document Number: 002-04868 Rev. *F

Page 146 of 167

CY9B460R Series

Comparator

ANxx

Analog input pin

Rext

R_AIN

Analog signal

source

C_AIN

(Equation 1) Ts ≥ (R_AIN+ Rext ) × C_AIN× 9

Ts:

Sampling time

R_AIN

:

Input resistance of A/D = 1.2kΩ at 4.5V < AV_CC< 5.5V

Input resistance of A/D = 1.8kΩ at 2.7V < AV_CC< 4.5V

Input capacity of A/D = 12.05pF at 2.7V < AV_CC< 5.5V

Output impedance of external circuit

C_AIN

:

Rext:

(Equation 2) Tc = Tcck × 14

Tc:

Compare time

Compare clock cycle

Tcck:

Document Number: 002-04868 Rev. *F

Page 147 of 167

CY9B460R Series

Definition of 12-bit A/D Converter Terms

• Resolution:

• Integral Nonlinearity:

Analog variation that is recognized by an A/D converter.

Deviation of the line between the zero-transition point (0b000000000000 ←→

0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from

the actual conversion characteristics.

• Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code

by 1 LSB.

Integral Nonlinearity

Differential Nonlinearity

0xFFF

Actual conversion

characteristics

0xFFE

0xFFD

0x(N+1)

0xN

characteristics

{1 LSB(N-1) + V_ZT}

V_FST

Ideal characteristics

(Actually-

measured

value)

V_NT

0x004

(Actually-measured

value)

V_(N+1)T

(Actually-measured

value)

0x(N-1)

0x(N-2)

0x003

0x002

Actual conversion

characteristics

V_NT

(Actually-measured

value)

Ideal characteristics

0x001

(Actually-measured value)

Analog input

V_ZT

Actual conversion characteristics

AVss

AVRH

AVss

AVRH

Analog input

V_NT- {1LSB × (N - 1) + V_ZT

1LSB

}

Integral Nonlinearity of digital output N =

Differential Nonlinearity of digital output N =

[LSB]

V_{(N + 1) T}- V_NT

1LSB

- 1 [LSB]

V_FST- V_ZT

1LSB =

4094

N:

V_ZT:

A/D converter digital output value.

Voltage at which the digital output changes from 0x000 to 0x001.

Voltage at which the digital output changes from 0xFFE to 0xFFF.

Voltage at which the digital output changes from 0x(N − 1) to 0xN.

V_FST

:

V_NT

:

Document Number: 002-04868 Rev. *F

Page 148 of 167

CY9B460R Series

12.6 12-bit D/A Converter

Electrical Characteristics for the D/A Converter

(V_CC= AV_CC= 2.7Vto5.5V, V_SS= AV_SS= 0V)

Value

Typ

name

Parameter

Resolution

Symbol

Unit

Remarks

Min

Max

12

-

bit

tc20

tc100

INL

0.56

2.79

- 16

- 0.98

-

0.69

0.81

4.06

+ 16

+ 1.5

10.0

+ 1.4

4.50

-

μs

Load 20pF

Conversion time

3.42

μs

Load 100pF

Integral Nonlinearity*

-

LSB

mV

kΩ

Differential Nonlinearity*

DNL

DAx

-

When setting 0x000

When setting 0xFFF

D/A operation

Output voltage offset

V_OFF

R_O

- 20.0

3.10

2.0

-

3.80

-

Analog output impedance

MΩ

When D/A stop

D/A 1unit operation

AV_CC=3.3V

260

330

410

μA

IDDA

IDSA

D/A 1unit operation

AV_CC=5.0V

Power supply current*

*: During no load

AVCC

400

-

510

-

620

14

μA

When D/A stop

Document Number: 002-04868 Rev. *F

Page 149 of 167

CY9B460R Series

12.7 Low-Voltage Detection Characteristics

12.7.1 Low-Voltage Detection Reset

Value

Typ

Parameter

Symbol

Conditions

Unit

Remarks

Min

2.25

2.30

Max

2.65

Detected voltage

Released voltage

VDL

VDH

-

2.45

2.50

V

When voltage drops

When voltage rises

2.70

V

12.7.2 Interrupt of Low-Voltage Detection

Value

Typ

2.8

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

2.58

2.67

2.76

2.85

2.94

3.04

3.31

3.40

3.50

3.68

3.77

3.86

3.96

3.02

3.13

3.24

3.34

3.45

3.56

3.88

3.99

4.10

4.32

4.42

4.53

4.64

V

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

SVHI = 00111

2.9

3.0

3.1

3.2

3.3

3.6

3.7

3.8

4.0

4.1

4.2

4.3

V

SVHI = 00100

SVHI = 01100

SVHI = 01111

SVHI = 01110

SVHI = 01001

SVHI = 01000

SVHI = 11000

LVD stabilization wait

time

T_LVDW

-

4480×t_CYCP

*

μs

*: t_CYCPindicates the APB2 bus clock cycle time.

Document Number: 002-04868 Rev. *F

Page 150 of 167

CY9B460R Series

12.8 MainFlash Memory Write/Erase Characteristics

(V_CC= 2.7V to 5.5V)

Value

Typ

Parameter

Unit

Remarks

Min

Max

3.7

Large Sector

Small Sector

0.7

Includes write time prior to

internal erase

Sector erase time

-

s

0.3

12

1.1

Write cycles

100

< 100 times

Half word (16-bit)

write time

Not including system-level

overhead time

-

μs

s

Write cycles

> 100 times

200

68

Includes write time prior to

internal erase

Chip erase time

13.6

Write cycles and data hold time

Erase/Write cycles (cycle)

Data hold time (year)

1,000

20 *

10 *

10,000

100,000

5 *

*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test

result into average temperature value at + 85°C) .

12.9 WorkFlash Memory Write/Erase Characteristics

(V_CC= 2.7V to 5.5V)

Value

Typ

Parameter

Sector erase time

Unit

Remarks

Min

Max

1.5

-

0.3

s

Includes write time prior to internal erase

Half word (16-bit)

write time

20

200

6

μs

s

Not including system-level overhead time

Includes write time prior to internal erase

Chip erase time

-

1.2

Write cycles and data hold time

Erase/Write cycles (cycle)

Data hold time (year)

1,000

20 *

10,000

100,000

10 *

5 *

*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test

result into average temperature value at + 85°C).

Document Number: 002-04868 Rev. *F

Page 151 of 167

CY9B460R Series

12.10Standby Recovery Time

12.10.1 Recovery cause: Interrupt/WKUP

The time from recovery cause reception of the internal circuit to the program operation start is shown.

Recovery count time

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Unit

μs

Remarks

Typ

HLK×1

Max*

Sleep mode

High-speed CR Timer mode

Main Timer mode

40

80

μs

PLL Timer mode

Low-speed CR timer mode

Sub timer mode

450

896

900

μs

1136

RTC mode

stop mode

316

270

581

540

μs

Ticnt

(High-speed CR /Main/PLL run mode return)

RTC mode

stop mode

(Low-speed CR/sub run mode return)

without

RAM

retention

365

667

μs

Deep standby RTC mode with RAM retention

Deep standby stop mode with RAM retention

with RAM

retention

*: The maximum value depends on the built-in CR accuracy.

Example of standby recovery operation (when in external interrupt recovery*)

Ext.INT

Interrupt factor

Active

accept

Ticnt

Interrupt factor

clear by CPU

CPU

Operation

Start

*: External interrupt is set to detecting fall edge.

Document Number: 002-04868 Rev. *F

Page 152 of 167

CY9B460R Series

Example of standby recovery operation (when in internal resource interrupt recovery*)

Internal

Resource INT

Interrupt factor

accept

Active

Ticnt

Interrupt factor

clear by CPU

CPU

Operation

Start

*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.

Notes:

−

The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and

"Operations of Standby Modes" in FM4 Family Peripheral Manual.

−

When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption

mode transition. See "Chapter: Low Power Consumption Mode" in "FM4 Family Peripheral Manual".

Document Number: 002-04868 Rev. *F

Page 153 of 167

CY9B460R Series

12.10.2 Recovery cause: Reset

The time from reset release to the program operation start is shown.

Recovery count time

(V_CC= 2.7V to 5.5V, V_SS= 0V)

Value

Parameter

Symbol

Unit

Remarks

Typ

Max*

266

Sleep mode

155

μs

High-speed CR Timer mode

Main Timer mode

266

PLL Timer mode

Low-speed CR timer mode

Sub timer mode

315

567

μs

Trcnt

RTC mode

stop mode

315

567

μs

without

RAM

retention

Deep standby RTC mode with RAM retention

Deep standby stop mode with RAM retention

336

667

with RAM

retention

*^:The maximum value depends on the built-in CR accuracy.

Example of standby recovery operation (when in INITX recovery)

INITX

Internal RST

RST Active

Release

Trcnt

CPU

Operation

Start

Document Number: 002-04868 Rev. *F

Page 154 of 167

CY9B460R Series

Example of standby recovery operation (when in internal resource reset recovery*)

Internal

Resource RST

Internal RST

RST Active

Release

Trcnt

CPU

Operation

Start

*: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause.

Notes:

−

The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and

"Operations of Standby Modes" in FM4 Family Peripheral Manual.

−

The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See "11.4.6 Power-on

Reset Timing" in "11.4. AC Characteristics" in "Electrical Characteristics" for the detail on the time during the power-on

reset/low-voltage detection reset.

−

When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is

necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.

The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-04868 Rev. *F

Page 155 of 167

CY9B460R Series

13.Ordering Information

Part Number

Flash

RAM

128 KB

Package

CY9BF468MPMC-G-MNE2

CY9BF467MPMC-G-MNE2

CY9BF466MPMC-G-MNE2

CY9BF468NPMC-G-MNE2

CY9BF467NPMC-G-MNE2

CY9BF466NPMC-G-MNE2

CY9BF468RPMC-G-MNE2

CY9BF467RPMC-G-MNE2

CY9BF466RPMC-G-MNE2

1 MB

768 KB

Plastic・LQFP (0.5 mm pitch), 80 pin

96 KB

64 KB

128 KB

96 KB

64 KB

128 KB

96 KB

64 KB

(LQH080)

512 KB

1 MB

Plastic・LQFP (0.5 mm pitch), 100 pin

768 KB

512 KB

1 MB

(LQI100)

Plastic・LQFP (0.5 mm pitch), 120 pin

768 KB

512 KB

(LQM120)

Document Number: 002-04868 Rev. *F

Page 156 of 167

CY9B460R Series

14.Package Dimensions

Package Type

Package Code

LQFP-120

LQM120

4

D

5

7

D1

90

61

90

91

60

E1

E

4

5

7

3

6

31

120

1

30

1

2

A-B

5

D

7

e

0.10

C

3

BOTTOM VIEW

0.20

C A-B D

0.08

C

A-B

D

b

8

TOP VIEW

2

A

c

9

θ

A

SEATING

PLANE

A1

10

b

0.25

A'

SECTION A-A'

0.08

C

L

SIDE VIEW

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

1.70

A

A1

b

0.05

0.17 0.22 0.27

0.115 0.195

18.00 BSC

0.15

c

D

D1

e

16.00 BSC

0.50 BSC

E

18.00 BSC

16.00 BSC

E1

L

0.45 0.60 0.75

0° 8°

θ

002-16172 **

PACKAGE OUTLINE, 120 LEAD LQFP

18.0X18.0X1.7 MM LQM120 REV**

Document Number: 002-04868 Rev. *F

Page 157 of 167

CY9B460R Series

Package Type

Package Code

LQFP-100

LQI100

4

D

5

7

5

7

D1

75

51

75

76

50

76

E1

E

5

4

7

3

6

100

26

100

1

25

2

5

7

e

0.10

C

A-B D

3

BOTTOM VIEW

0.20

C A-B D

b

8

0.08

C

A-B

D

TOPVIEW

2

A

9

A

SEATING

PLANE

c

A1

A'

0.25

b

L1

0.08

C

10

SECTION A-A'

L

SIDE VIEW

DETAIL A

NOTES:

1. ALL DIMENSIONSAREIN MILLIMETERS.

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

1.70

2. DATUM PLANEH ISLOCATED ATTHEBOTTOM OF THE MOLD PARTING

LINECOINCIDENTWITH WHERETHELEAD EXITSTHEBODY.

3. DATUMSA-BAND D TO BEDETERMINED ATDATUM PLANEH.

A

A1

b

0.05

0.15

0.09

0.15

0.27

0.20

4. TO BEDETERMINED ATSEATING PLANEC.

5. DIMENSIONSD1 AND E1 DO NOTINCLUDEMOLD PROTRUSION.

ALLOW ABLEPROTRUSION IS0.25mm PRESIDE.

c

D

16.00 BSC

14.00 BSC

0.50 BSC

DIMENSIONSD1 AND E1 INCLUDEMOLD MISMATCH AND AREDETERMINED

ATDATUM PLANE H.

D1

e

6. DETAILSOF PIN 1 IDENTIFIERAREOPTIONALBUTMUSTBE LOCATED

WITHIN THEZONEINDICATED.

E

16.00 BSC

14.00 BSC

7. REGARDLESSOFTHERELATIVESIZEOF THEUPPERAND LOWERBODY

SECTIONS. DIMENSIONSD1 AND E1 AREDETERMINED ATTHELARGEST

FEATUREOF THEBODY EXCLUSIVEOF MOLD FLASH AND GATE BURRS.

BUTINCLUDING ANY MISMATCH BETWEEN THEUPPERAND LOWER

SECTIONSOF THEMOLDERBODY.

E1

L

0.45

0.60 0.75

L1

0.30 0.50 0.70

8. DIMENSION b DOESNOTINCLUDE DAMBARPROTRUSION. THEDAMBAR

PROTRUSION (S) SHALL NOTCAUSETHELEAD WIDTH TO EXCEED b

MAXIMUM BY MORETHAN 0.08mm. DAMBARCANNOTBELOCATED ON

THELOWERRADIUSORTHELEAD FOOT.

9. THESEDIMENSIONSAPPLY TO THEFLATSECTION OF THE LEAD

BETWEEN 0.10mm AND 0.25mm FROM THELEAD TIP.

10. A1 ISDEFINED ASTHEDISTANCEFROM THESEATING PLANE TO

THELOWESTPOINTOF THEPACKAGEBODY.

PACKAGE OUTLINE, 100 LEAD LQFP

14.0X14.0X1.7 MM LQI100 REV*A

002-11500 *A

Document Number: 002-04868 Rev. *F

Page 158 of 167

CY9B460R Series

Package Type

Package Code

QFP-100

PQH100

D

4

D1

5

7

80

51

80

81

50

81

E1

E

4

5

7

6

3

100

31

100

1

30

1

2

5

7

e

0.20

C

A-B

D

3

BOTTOM VIEW

b

0.40

C A-B D

0.13

C A-B

D

8

TOP VIEW

2

θ

9

c

A

SEATING

PLANE

L2

A'

10

0.10

C

b

SECTION A-A'

DETAIL A

SIDE VIEW

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

3.35

A

A1

b

0.05

0.27

0.11

0.45

0.37

0.23

0.32

c

D

23.90 BSC

20.00 BSC

0.65 BSC

D1

e

E

17.90 BSC

14.00 BSC

E1

0°

8°

0.88 1.03

1.95 REF

0.25 BSC

θ

L

0.73

L1

L2

PACKAGE OUTLINE, 100 LEAD QFP

20.00X14.00X3.35 MM PQH100 REV**

002-15156 **

Document Number: 002-04868 Rev. *F

Page 159 of 167

CY9B460R Series

Package Type

Package Code

LQFP-80

LQH080

4

5

D

7

D1

60

41

60

61

40

61

5

7

E1

E

4

3

6

80

21

80

1

20

1

2

5

8

7

D

0.10

C

A-B D

BOTTOM VIEW

3

e

0.08

A-B

D

b

0.20

C A-B D

TOP VIEW

2

A

SEATING

PLANE

9

c

A'

L1

0.25

0.08

C

A1

b

L

10

SIDE VIEW

SECTION A-A'

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

1.70

A

A1

b

0.05

0.15

0.09

0.15

0.27

0.20

c

D

14.00 BSC.

D1

e

12.00 BSC.

0.50 BSC

E

14.00 BSC.

12.00 BSC.

E1

L

0.45 0.60 0.75

0.30 0.50 0.70

L1

PACKAGE OUTLINE, 80 LEAD LQFP

12.0X12.0X1.7 MM LQH080 Rev **

002-11501 **

Document Number: 002-04868 Rev. *F

Page 160 of 167

CY9B460R Series

Package Type

Package Code

LQFP-80

LQJ080

4

5

D

7

D1

60

41

60

61

40

61

E1

E

5

7

4

3

6

80

21

80

1

20

b

20

1

2

5

7

0.10

C

A-B

D

e

3

0.20

C A-B D

ddd

A-B

D

8

2

A

9

A

θ

SEATING

PLANE

c

A'

A1

b

0.10

C

0.25

L

L1

10

SECTION A-A'

DIMENSIONS

SYMBOL

MIN. NOM. MAX.

1.70

A

A1

b

0.00

0.16 0.32 0.38

0.09 0.20

0.20

c

D

16.00 BSC

14.00 BSC

0.65 BSC

D1

e

E

16.00 BSC

14.00 BSC

E1

L

0.45 0.60 0.75

0.30 0.50 0.70

L1

θ

0°

8°

PACKAGE OUTLINE, 80 LEAD LQFP

14.0X14.0X1.7 MM LQJ080 REV**

002-14043 **

Document Number: 002-04868 Rev. *F

Page 161 of 167

CY9B460R Series

Package Type

Package Code

BGA-112

LDC112

A

0.20

C A

13

12

11

10

9

7

8

7

6

5

B

4

3

2

1

N

M

L

K

J

H

G

F

E

D

C

B

A

INDEX MARK

8

PIN A1

CORNER

7

112xφb

0.05

C

A

B

0.20

C B

6

TOPVIEW

BOTTOM VIEW

DETAILA

0.20

C

0.10

C

SIDEVIEW

DETAIL A

NOTES

1. ALLDIMENSIONSARE IN MILLIMETERS.

DIMENSIONS

SYMBOL

A

MIN. NOM. MAX.

1.35

2. DIMENSIONSAND TOLERANCES METHODSPERASMEY14.5-2009.

THISOUTLINE CONFORMSTO JEP95, SECTION 4.5.

3. BALL POSITION DESIGNATION PERJEP95, SECTION 3, SPP-010.

4. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.

A

D

E

0.15

0.25

7.00 BSC

6.00 BSC

13

0.35

1

5. SYMBOL "MD"ISTHE BALLMATRIX SIZE IN THE "D"DIRECTION.

SYMBOL "ME"ISTHE BALLMATRIX SIZE IN THE "E"DIRECTION.

n ISTHE NUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX

SIZE MD X ME.

D

E

1

6. DIMENSION "b"ISMEASURED ATTHE MAXIMUM BALL DIAMETER

IN A PLANE PARALLEL TO DATUM C.

1

7. "SD" AND "SE" ARE MEASURED WITH RESPECTTO DATUMSA AND BAND

DEFINE THE POSITION OF THE CENTERSOLDERBALL IN THE OUTERROW.

WHEN THERE ISAN ODD NUMBEROF SOLDERBALLSIN THE OUTERROW,

"SD"OR"SE"=0.

WHEN THERE ISAN EVEN NUMBEROF SOLDERBALLSIN THE OUTERROW,

"SD"= eD/2 AND "SE" = eE/2.

MD

ME

n

13

112

8. A1 CORNERTO BE IDENTIFIED BY CHAMFER, LASERORINK MARK.

METALLIZED MARK INDENTATION OROTHERMEANS.

Φb

eD

0.20

0.30

0.40

0.50 BSC

0.00

9. "+"INDICATESTHE THEORETICAL CENTEROF DEPOPULATED BALLS.

eE

SD /SE

PACKAGE OUTLINE, 112 BALLFBGA

7.0X7.0X1.35 MM LDC112 REV**

002-16663 **

Document Number: 002-04868 Rev. *F

Page 162 of 167

CY9B460R Series

Package Type

Package Code

BGA-144

LDC144

A

0.20

2X

C A

13

12

11

10

9

7

8

7

6

5

B

4

3

2

1

N

M

L

K

J

H

G

F

E

D

C

B

A

INDEX MARK

8

PIN A1

CORNER

7

144xφb

0.05

C A B

0.20

2X

C B

6

TOPVIEW

BOTTOM VIEW

DETAILA

0.20

C

0.08

C

SIDEVIEW

DETAIL A

NOTES

1. ALLDIMENSIONSARE IN MILLIMETERS.

DIMENSIONS

SYMBOL

A

MIN. NOM. MAX.

1.30

2. DIMENSIONSAND TOLERANCES METHODSPERASMEY14.5-2009.

THISOUTLINE CONFORMSTO JEP95, SECTION 4.5.

3. BALL POSITION DESIGNATION PERJEP95, SECTION 3, SPP-010.

4. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.

A

D

E

0.15

0.25

7.00 BSC

6.00 BSC

13

0.35

1

5. SYMBOL "MD"ISTHE BALLMATRIX SIZE IN THE "D"DIRECTION.

SYMBOL "ME"ISTHE BALLMATRIX SIZE IN THE "E"DIRECTION.

n ISTHE NUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX

SIZE MD X ME.

D

E

1

6. DIMENSION "b"ISMEASURED ATTHE MAXIMUM BALL DIAMETER

IN A PLANE PARALLEL TO DATUM C.

1

7. "SD" AND "SE" ARE MEASURED WITH RESPECTTO DATUMSA AND BAND

DEFINE THE POSITION OF THE CENTERSOLDERBALL IN THE OUTERROW.

WHEN THERE ISAN ODD NUMBEROF SOLDERBALLSIN THE OUTERROW,

"SD"OR"SE"=0.

WHEN THERE ISAN EVEN NUMBEROF SOLDERBALLSIN THE OUTERROW,

"SD"= eD/2 AND "SE" = eE/2.

MD

ME

n

13

144

8. A1 CORNERTO BE IDENTIFIED BY CHAMFER, LASERORINK MARK.

METALLIZED MARK INDENTATION OROTHERMEANS.

Φb

eD

0.20

0.30

0.40

0.50 BSC

0.00

9. "+"INDICATESTHE THEORETICAL CENTEROF DEPOPULATED BALLS.

eE

SD /SE

PACKAGE OUTLINE, 144 BALLFBGA

7.0X7.0X1.3 MM LDC144 REV**

002-16662 **

Document Number: 002-04868 Rev. *F

Page 163 of 167

CY9B460R Series

15.Major Changes

Spansion Publication Number: DS709-00002

Page

Section

Change Results

Preliminary → Data Sheet

Deleted the following description :

-

Description

The products which are described in this data sheet are

placed into TYPE4 product categories in "FM4

Family Peripheral Manual".

1

Features

Revised the following description :

Multi-Function Serial Interface

[I²c]

Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3 and

ch.7) supported

3

→Fast mode Plus (Fm+) (Max 1000 kbps, only for

ch.3=ch.A and ch.7=ch.B) supported

Features

Unique Id

Added new section

7

9

Product Lineup

Function

Added “Unique ID”

51, 52

59

I/O Circuit Type

Revised the remarks of “Type O, P, Q”

Added new section

Handling Devices

Handling When Using Debug Pins

60

Block Diagram

Revised the block diagram

Electrical Characteristics

2. Recommended Operating Conditions

Revised “Table for package thermal resistance and

maximum permissible power”

73

Electrical Characteristics

3. Dc Characteristics

(1) Current Rating

• Revised the value of TBD

• Revised the unit of “ICCHD”, “ICCRD”, “ICCVBAT”

mA → µA

76 to 81

• Added the note to “ICCVBAT”

Electrical Characteristics

4. Ac Characteristics

(2) Sub Clock Input Characteristics

Revised the waveform chart

86

Electrical Characteristics

4. Ac Characteristics

(3) Built-In Cr Oscillationcharacteristics

• Revised the value of TBD

• Revised the table and the note of “Built-in High-speed

CR”

Electrical Characteristics

5. 12-Bit A/D Converter

・Electrical Characteristics For The A/D

Converter

• Revised the value of TBD

• Revised the condition of the electrical characteristics

table

145

148

Electrical Characteristics

6. 12-Bit D/A Converter

・Electrical Characteristics For The D/A

Converter

• Revised the value of TBD

• Revised the condition and Remarks of the electrical

characteristics table

Electrical Characteristics

• Revised the value of TBD

151

153

10. Standby Recovery Time

(1) Recovery Cause: Interrupt/Wkup

• Revised the table of Recovery count time

Electrical Characteristics

10. Standby Recovery Time

(2) Recovery Cause:Reset

• Revised the value of TBD

• Revised the table of Recovery count time

NOTE: Please see “Document History” about later revised information.

Document Number: 002-04868 Rev. *F

Page 164 of 167

CY9B460R Series

Document History

Document Title: CY9B460R Series, 32-bit Arm® Cortex®-M4F FM4 Microcontroller

Document Number: 002-04868

Submission

Revision

ECN

Description of Change

Date

Migrated to Cypress and assigned document number 002-04868.

No change to document contents or format.

**

-

06/27/2013

Updated to Cypress template.

*A

*B

5157624

5516291

03/03/2016

02/01/2017

Updated “12.4.7 Power-On Reset Timing”. Changed parameter from

“Power Supply rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and add some

comments (Page 88)

Modified the Chapter name “12.4.11 UART Timing” to “12.4.11 CSIO/UART Timing”.

(Page 103)

Modified “12.4.11 CSIO/UART Timing”. Deleted “SPI=1, MS=0” in the titles and added

MS=0,1 in the schematic (Page 111-118, 127-134)

Added the Baud rate spec in “12.4.11 CSIO/UART Timing”. (Page 104, 106, 108, 110)

“Modified RTC description in “Features, Real-Time Clock(RTC)”

Changed starting count value from 01 to 00. Deleted “second, or day of the week” in

the Interrupt function (Page 3)

Added Maximum Access size in “Features” (Page 1)

Modifications related to the VBAT in the following chapter.

“7. Handling Devices” Notes on Power-on (Page 57)

“11. Pin Status in Each CPU State” List of VBAT Domain Pin Status (Page 70)

“12.3.1 Current Rating” Table12-9. Typical and Maximum Current Consumption in Deep

Standby STOP Mode, Deep Standby RTC Mode and VBAT (Page 81)

Added Notes for JTAG (Page 44), Changed “J-TAG” to” JTAG” in “4 List of Pin

Functions” (Page 32)

Modify typo in number of power supply (Three -> Two) (Page 4)

Updated Package code and dimensions as follows (Page 9-15, 72, 156-163)

FPT-120P-M37 -> LQM120, FPT-100P-M23 -> LQI100,

FPT-100P-M36 -> PQH100, FPT-80P-M37 -> LQH080,

FPT-80P-M40 -> LQJ080, BGA-112P-M05 -> LDC112,

BGA-144P-M09 -> LDC144

Changed the mode name of I2C as follows (Page 2, 139-140)

Typical mode -> Standard-mode, High-speed mode -> Fast-mode

Modified from “Analog port input current” to “Analog port input leak current” in “12.5 12-

bit A/D Converter” (Page 146)

Document Number: 002-04868 Rev. *F

Page 165 of 167

CY9B460R Series

Submission

Date

Revision

ECN

Description of Change

Modified according to the Datasheet Errata as below (No.1-9)

1. Modified Reference voltage value in “Electrical Characteristics for the A/D Converter”

in “12.5 12-bit A/D Converter” (Page 146)

*B (cont.) 5516291

02/01/2017

2. Modified typo in “Features, Processor version” (Page 1)

3. Updated Remarks of Type H, I in “5. I/O Circuit Type” (Page 48)

4. Updated “List of VBAT Domain Pin Status” (Page 70)

5. Modified “12.2 Recommended Operating Conditions” (Page 72)

6. Added “Frequency stabilization time” spec in “12.4.3 Built-in CR Oscillation

Characteristics” (Page 86)

7. Added “Conversion time” spec in “12.6 12-bit D/A Converter”

(Page 149)

8. Modified some spec values in “12.10.1 Recovery cause: Interrupt/WKUP” (Page

152) and “12.10.2 Recovery cause: Reset” (Page 154)

9. Modified the “sampling time” and “State transition time to operation permission” spec

values in ”12.5 12-bit A/D Converter” (Page 146)

Deleted MPNs below from “13. Ordering Information” (Page 156)

MB9BF466RBGL-GE1, MB9BF467RBGL-GE1, MB9BF468RBGL-GE1

Added MPNs below to “13. Ordering Information” (Page 156)

MB9BF466RBGL-GK7E1, MB9BF467RBGL-GK7E1, MB9BF468RBGL-GK7E1

Updated IO circuit (type A) (Page 46)

Modified the expression of the “Reference power supply current” “12.5 12-bit A/D

Converter” (Page 147)

Modified the expression of the “Built-in CR” and add Note in the “1. Product Lineup”

(Page 8)

Modified typo(SCLKx_0 -> SCKx_0) (Page 104, 106, 108, 110)

Updated Cypress Logo and Copyright.

*C

*D

5738077

5873294

05/16/2017

09/25/2017

Fix minor issue on new note

1. New note format had been updated from *x to *^x

2. Changed “FM4 Family Peripheral Manual Main Part (002-04857)” to “FM4 Family

Peripheral Manual Main Part (002-04856)”.

3. Changed “(MN709-00001)” to “(002-04856)”.

Updated Ordering Information:

Updated part numbers.

*E

*F

6604923

7034068

06/26/2019

11/30/2020

Updated to new template.

Updated Document Title to read as “CY9B460R Series, 32-bit Arm^®Cortex^®-M4F FM4

Microcontroller”.

Replaced MB with CY in all MPNs across the document.

Fixed typos across the document.

Updated Ordering Information:

Updated part numbers.

Completing Sunset Review.

Document Number: 002-04868 Rev. *F

Page 166 of 167

CY9B460R Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the

office closest to you, visit us at Cypress Locations.

Products

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cypress.com/arm

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Training | Components

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firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress

reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property

rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants

you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and

reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either

directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or

compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING

CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,

“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security

Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the

extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of

any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.

It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk

Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants,

and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the

High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from

any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns

harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use

of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited

extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written

authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-04868 Rev. *F

November 30, 2020

Page 167 of 167


型号：	CY9BF466RPMC-G-MNK1E2
厂家：	Infineon
描述：	FM4 CY9BFx6xM/N/R-Series Motor Control Arm® Cortex®-M4 Microcontroller (MCU) Family 微控制器
文件：	总168页 (文件大小：3424K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY9BF466RPMC-G-MNK1E2 [INFINEON]

相关型号：

CY9BF466RPMC-GNE2

CY9BF466RPMC-GNK1E2

CY9BF467MPMC1-G-JNE2

CY9BF467MPMC1-G-JNE2

CY9BF467NPQC-G-JNE2

CY9BF467RBGL-GE1

CY9BF467RBGL-GK7E1

CY9BF468MPMC1-G-JNE2

CY9BF468MPMC1-G-JNE2

CY9BF468NPMC-G-MNE2

CY9BF468NPMC-GNE2

CY9BF468NPQC-G-JNE2