CYB06445LQI-S3D42_技术文档

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

PSoC 64 "Secure Boot" MCU

General Description

PSoC^®6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The PSoC 64

product line, based on the PSoC 6 MCU platform, features out-of-box security functionality, providing an isolated root-of-trust with true

attestation and provisioning services. In addition, it delivers a pre-configured secured execution environment which supports system

software for various IoT platforms; and enables TLS authentication, secured storage, and secured firmware management. PSoC 64

also includes a rich execution environment for application development, with RTOS support that communicates with the secured

execution environment.

Features

32-bit Dual CPU Subsystem

Cypress Bootloader

■ Open source MCUBoot^[1]based bootloader optimized for

PSoC 64

Note: In PSoC 64 the Cortex M0+ is reserved for system

functions, and is not available for applications.

■ 150-MHz Arm^®Cortex^®-M4F (CM4) CPU with single-cycle

multiply, floating point, and memory protection unit (MPU)

■ Pre-built bootloader binary capable of validating, launching and

updating signed user application images

■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply

and MPU

■ Tightly integrated with provisioned debug and boot policies to

inherit and implement security policies

■ User-selectable core logic operation at either 1.1 V or 0.9 V

Low-Power 1.7-V to 3.6-V Operation

■ Active CPU current slope with 1.1-V core operation

❐ Cortex-M4: 40 µA/MHz

❐ Cortex-M0+: 20 µA/MHz

■ Six power modes for fine-grained power management

■ On-chip DC-DC buck converter, <1 µA quiescent current

■ Backup domain with 64 bytes of memory and real-time clock

Flexible Clocking Options

■ Active CPU current slope with 0.9-V core operation

❐ Cortex-M4: 22 µA/MHz

❐ Cortex-M0+: 15 µA/MHz

■ 8-MHz internal main oscillator (IMO) with ±2% accuracy

■ Ultra-low-power 32-kHz internal low-speed oscillator (ILO)

■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)

■ Phase-locked loop (PLL) for multiplying clock frequencies

■ Frequency-locked loop (FLL) for multiplying IMO frequency

■ Integer and fractional peripheral clock dividers

■ Three DMA controllers

Memory Subsystem

■ 384-KB application flash, 32-KB auxiliary flash (AUXflash), and

32-KB supervisory flash (SFlash); read-while-write (RWW)

support. Two 8-KB flash caches, one for each CPU.

■ 176-KB SRAM with programmable power control and retention

granularity

Quad-SPI (QSPI)/Serial Memory Interface (SMIF)

■ Execute-In-Place (XIP) from external quad SPI flash

■ On-the-fly encryption and decryption

■ One-time-programmable (OTP) 1-Kb eFuse array

Hardware-Based Root-of-Trust (RoT)

■ RoTbased on immutable boot-up code, flash content hash, and

Cypress public key that ensures firmware integrity prior to

provisioning

■ 4-KB cache for greater XIP performance with lower power

■ Supports single, dual, and quad interfaces with throughput up

to 320 Mbps

■ Supports trusted RoT handover to maintain chain of trust and

establish OEM trust anchor for secured boot

Segment LCD Drive

■ Device generates a unique device ID and a device secret key

during the provisioning process, which can be used for

attestation and signing

■ Supports up to 52 segments and up to 8 commons.

■ Operates in system Deep Sleep mode

Serial Communication

Immutable “Secure Boot” Support

■ Seven run-time configurable serial communication blocks

(SCBs)

■ Flexible chain of trust can use different signatures for different

images

❐ Six SCBs: configurable as SPI, I²C, or UART

❐ One Deep Sleep SCB: configurable as SPI or I²C

■ ECC-based image signature validation

■ USB Full-Speed device interface

■ One SD Host Controller/eMMC/SD controller

■ One CAN FD block

Note

1. For details, refer to https://mcuboot.com/.

Cypress Semiconductor Corporation

Document Number: 002-28785 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

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408-943-2600

Revised October 26, 2022

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Timing and Pulse-Width Modulation

Device Identification and Revisions

■ Product line ID (12-bit): 0x105

■ Twelve timer/counter/pulse-width modulators (TCPWMs)

■ Center-aligned, edge, and pseudo-random modes

■ Comparator-based triggering of kill signals

■ Major/Minor die revision ID: 1/2

■ Firmware revisions: ROM Boot: 7.1, Flash Boot: 4.0.2.1842

(see Boot Code section)

Programmable Analog

■ 12-bit 2-Msps SAR ADC with differential and single-ended

modes and 16-channel sequencer with result averaging

This product line has a JTAG ID which is available through the

SWJ interface. It is a 32-bit ID, where:

■ Two low-power comparators available in system Deep Sleep

and Hibernate modes

■ The most significant digit is the device revision, based on the

Major Die Revision

■ Built-in temperature sensor connected to ADC

■ The next four digits correspond to the part number, for example

"E4B0" as a hexadecimal number

Up to 53 Programmable GPIOs

■ Two Smart I/O™ ports (8 I/Os) enable Boolean operations on

GPIO pins; available during system Deep Sleep

■ The three least significant digits are the manufacturer ID, in this

case "069" as a hexadecimal number

■ Programmable drive modes, strengths, and slew rates

■ Two overvoltage-tolerant (OVT) pins

The Silicon ID system call can be used by firmware to get Silicon

ID and ROM Boot data. For more information, see the technical

reference manual (TRM).

Capacitive Sensing

The Flash Boot version can be read directly from designated

addresses 0x1600 2004 and 0x1600 2018. For more

information, see the technical reference manual (TRM).

■ CypressCapSense^®sigma-delta(CSD)providesbest-in-class

signal-to-noise ratio (SNR), liquid tolerance, and proximity

sensing

■ Enables dynamic usage of both self and mutual sensing

■ Automatic hardware tuning (SmartSense™)

Cryptography Accelerator

■ Hardware acceleration for symmetric and asymmetric

cryptographic methods and hash functions

■ True random number generation (TRNG) function

Packages

■ 68 QFN

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PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Contents

Development Ecosystem................................................. 4

PSoC 6 MCU Resources .............................................4

Blocks and Functionality................................................. 6

Functional Description..................................................... 8

CPU and Memory Subsystem .....................................8

System Resources ....................................................12

Programmable Analog Subsystems ..........................14

Programmable Digital ................................................15

Fixed-Function Digital ................................................16

GPIO .........................................................................17

Special-Function Peripherals ....................................18

PSoC 64 Security ......................................................21

Pinouts ............................................................................ 24

Power Supply Considerations....................................... 31

Electrical Specifications ................................................ 34

Absolute Maximum Ratings .......................................34

Device-Level Specifications ......................................34

Analog Peripherals ....................................................43

Digital Peripherals .....................................................49

Memory .....................................................................52

System Resources ....................................................53

Ordering Information...................................................... 62

PSoC 6 MPN Decoder ..............................................63

Packaging........................................................................ 64

Acronyms........................................................................ 66

Document Conventions ................................................. 68

Units of Measure .......................................................68

Errata ............................................................................... 69

Revision History ............................................................. 70

Sales, Solutions, and Legal Information ...................... 72

Worldwide Sales and Design Support .......................72

Products ....................................................................72

PSoC® Solutions ......................................................72

Cypress Developer Community .................................72

Technical Support .....................................................72

Document Number: 002-28785 Rev. *I

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PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Development Ecosystem

PSoC 6 MCU Resources

Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate

it into your design. The following is an abbreviated list of resources for PSoC 6 MCU:

■ Overview: PSoC Portfolio, PSoC Roadmap

■ Product Selectors: PSoC 6 MCU

■ Development Tools

❐ ModusToolbox^®software enables cross platform code de-

velopment with a robust suite of tools and software libraries

■ Application Notes cover a broad range of topics, from basic

to advanced level, and include the following:

❐ AN221774: Getting Started with PSoC 6 MCU

❐ AN218241: PSoC 6 MCU Hardware Design Guide

❐ AN213924: PSoC 6 MCU Device Firmware Update Guide

❐ AN215656: PSoC 6 MCU Dual-CPU System Design

❐ AN219528: PSoC 6 MCU Power Reduction Techniques

❐ AN85951: PSoC 4, PSoC 6 MCU CapSense Design Guide

❐ “Secure Boot” SDK includes all required libraries, tools, and

sample code to provision and develop applications for

PSoC 64 MCUs.

❐ CY8CPROTO-064B0S3PSoC64“SecureBoot”Prototyping

Kit: a low-cost hardware platform that enables design and

debug of the PSoC 64 CYB06445LQI-S3D42 product line.

❐ PSoC 6 CAD libraries provide footprint and schematic sup-

port for common tools. BSDL files and IBIS models are also

available.

■ Training Videos are available on a wide range of topics

including the PSoC 6 MCU 101 series

■ CodeExamplesdemonstrateproductfeaturesandusage,and

are also available on Cypress GitHub repositories.

■ Cypress Developer Community enables connection with

fellow PSoC developers around the world, 24 hours a day, 7

days a week, and hosts a dedicated PSoC 6 MCU Community

■ Technical Reference Manuals (TRMs) provide detailed

descriptions of PSoC 6 MCU architecture and registers.

■ PSoC 6 MCU Programming Specification provides the infor-

mation necessary to program PSoC 6 MCU nonvolatile

memory

ModusToolbox™ IDE and the PSoC 6 SDK

ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive

development experience for creating converged MCU and wireless systems. It is:

■ Comprehensive - it has the resources you need

■ Flexible - you can use the resources in your own workflow

■ Atomic - you can get just the resources you want

Cypress provides a large collection of code repositories on GitHub. This includes:

■ Board Support Packages (BSPs) aligned with Cypress kits

■ Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL)

■ Middleware enabling industry-leading features such as CapSense, Bluetooth Low Energy, and mesh networks

■ An extensive set of thoroughly tested code example applications

Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Cypress MCUs. It is a generic

interface that can be used across multiple product families. For example, it wraps the PSoC 6 PDL with a simplified API, but the PDL

exposes all low-level peripheral functionality. You can leverage the HAL's simpler and more generic interface for most of an application,

even if one portion requires finer-grained control.

ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a

project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox. For

information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and AN228571: Getting Started

with PSoC 6 MCU on ModusToolbox.

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PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 1. ModusToolbox Software Tools

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Datasheet

Blocks and Functionality

Figure 2 shows the major subsystems and a simplified view of their interconnections. The color coding shows the lowest power mode

where the particular block is still functional (for example, the SRAM is functional down to system Deep Sleep mode).

Figure 2. Block Diagram

Color Key:

Power Modes and

PSoC 64 “Secure Boot” MCU

CYB06445LQI-S3D42

Domains

Programmable Analog

SAR ADC 12 bit

System Resources

System LP/ULP Mode

CPUs Active/Sleep

Power

Clocks

Temperature

Sensor

OVP

POR

LVD

BOD

IMO

FLL

ECO

2x PLL

System

DeepSleep Mode

Buck Regulator

XRES Reset

Backup Regs

2x MCWDT

ILO

WDT

WCO

RTC

System

PMIC Control

Hibernate Mode

Backup

Domain

CPU Subsystem

SCB

Cortex M4F CPU

150/50 MHz, 1.1/0.9 V

SWJ, ETM, ITM, CTI

Cortex M0+ CPU

100/25 MHz, 1.1/0.9 V

SWJ, MTB, CTI

3x DMA

Controller

Crypto

DES/TDES, AES, SHA,

CRC, TRNG, RSA/ECC

Accelerator

USB

PHY

Flash

512 KB + 32 KB + 32 KB

8 KB cache for each CPU

SRAM

256 KB

ROM

64 KB

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PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

This product line has up to 512 KB of flash; however 128 KB is reserved for system usage, leaving 384 KB for applications. The 32-KB

auxiliary flash (AUXflash) is also reserved, and is not available for applications. It also has up to 256 KB of SRAM; however 80 KB is

reserved for system usage, leaving 176 KB for applications.

The PSoC 64 devices offer an immutable, RoT-based boot-up process, which allows only signed applications to be booted up. In

addition, user assets such as keys and debug policies can be provisioned on the device in an HSM environment and made immutable.

PSoC 64 also allows for root-of-trust based cryptography services which can be accessed using system calls.

There are three debug access ports, one each for CM4 and CM0+, and a system port. All debug and test interfaces can be permanently

disabled during final production provisioning to avoid any malicious reprogramming or reading of flash and register contents.

PSoC 6 MCU devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All

device interfaces can be permanently disabled for applications concerned about a reprogrammed device or starting and interrupting

flash programming sequences. All programming, debug, and test interfaces can be disabled.

Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does

not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required

to fully support debug.

The Eclipse IDE for ModusToolbox provides fully integrated programming and debug support for these devices. The SWJ (SWD and

JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust

flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, PSoC 6

provides multiple levels of device security.

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PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Functional Description

The following sections provide an overview of the features,

capabilities and operation of each functional block identified in

the block diagram in Figure 2. For more detailed information,

refer to the following documentation:

CPU and Memory Subsystem

PSoC 6 has multiple bus masters, as Figure 2 shows. They are:

CPUs, DMA controllers, QSPI, USB, SD Host controller, and a

Crypto block. Generally, all memory and peripherals can be

accessed and shared by all bus masters through multi-layer Arm

AMBA high-performance bus (AHB) arbitration. Accesses

between CPUs can be synchronized using an inter-processor

communication (IPC) block.

■ Board Support Package (BSP) Documentation

BSPs are available on GitHub. They are aligned with Cypress

kits and provide files for basic device functionality such as

hardware configuration files, startup code, and linker files.

The BSP also includes other libraries that are required to sup-

port a kit. Each BSP has its own documentation, but typically

includes an API reference such as the example here. This

search link finds all currently available BSPs on the Cypress

GitHub site.

CPUs

There are two Arm Cortex CPUs:

The Cortex-M4 (CM4) has single-cycle multiply, a floating-point

unit (FPU), and a memory protection unit (MPU). It can run at up

to 150 MHz. This is the main CPU, designed for a short interrupt

response time, high code density, and high throughput.

■ Hardware Abstraction Layer API Reference Manual

The Cypress Hardware Abstraction Layer (HAL) provides a

high-level interface to configure and use hardware blocks on

Cypress MCUs. It is a generic interface that can be used

across multiple product families. You can leverage the HAL's

simpler and more generic interface for most of an application,

even if one portion requires finer-grained control. The HAL

API Reference provides complete details. Example applica-

tions that use the HAL download it automatically from the

GitHub repository.

CM4 implements a version of the Thumb instruction set based

on Thumb-2 technology (defined in the Armv7-M Architecture

Reference Manual).

The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU.

It can run at up to 100 MHz; however, for CM4 speeds above 100

MHz, CM0+ and bus peripherals are limited to half the speed of

CM4. Thus, for CM4 running at 150 MHz, CM0+ and peripherals

are limited to 75 MHz.

In PSoC 64, the initial CM0+ frequency is set according to a

provisioned security policy (see PSoC 64 Security). The

frequency ranges from 8 MHz to 50 MHz. For more information,

see the Register TRM and Architecture TRM.

■ Peripheral Driver Library (PDL) Application Programming

Interface (API) Reference Manual

The Peripheral Driver Library (PDL) integrates device header

files and peripheral drivers into a single package and supports

all PSoC 6 MCU product lines. The drivers abstract the hard-

ware functions into a set of easy-to-use APIs. These are fully

documented in the PDLAPI Reference. Example applications

that use the PSoC 6 PDL download it automatically from the

GitHub repository.

CM0+ is the secondary CPU; it is used to implement system calls

and device-level security, safety, and protection features. CM0+

provides a secured, uninterruptible boot function. This helps

ensure that post boot, system integrity is checked and memory

and peripheral access privileges are enforced.

CM0+ implements the Armv6-M Thumb instruction set (defined

in the Armv6-M Architecture Reference Manual).

■ Architecture Technical Reference Manual (TRM)

The architecture TRM provides a detailed description of each

resource in the device. This is the next reference to use if it is

necessary to understand the operation of the hardware below

the software provided by PDL. It describes the architecture

and functionality of each resource and explains the operation

of each resource in all modes. It provides specific guidance

regarding the use of associated registers.

The CPUs have the following power draw, at V_DDD= 3.3 V and

using the internal buck regulator:

Table 1. Active Current Slope at V_DDD= 3.3 V Using the

Internal Buck Regulator

System Power Mode

ULP

LP

■ Register Technical Reference Manual

Cortex-M0+

Cortex-M4

15 A/MHz

22 A/MHz

20 A/MHz

40 A/MHz

The register TRM provides a complete list of all registers in

the device. It includes the breakdown of all register fields,

their possible settings, read/write accessibility, and default

states. All registers that have a reasonable use in typical ap-

plications have functions to access them from within PDL.

Note that ModusToolbox and PDL may provide software de-

fault conditions for some registers that are different from and

override the hardware defaults.

CPU

The CPUs can be selectively placed in their Sleep and Deep

Sleep power modes as defined by Arm.

Both CPUs have nested vectored interrupt controllers (NVIC) for

rapid and deterministic interrupt response, and wakeup interrupt

controllers (WIC) for CPU wakeup from Deep Sleep power

mode.

The CPUs have extensive debug support. PSoC 6 has a debug

access port (DAP) that acts as the interface for device

programming and debug. An external programmer or debugger

(the “host”) communicates with the DAP through the device

serial wire debug (SWD) or Joint Test Action Group (JTAG)

interface pins. Through the DAP (and subject to device security

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PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

restrictions), the host can access the device memory and

peripherals as well as the registers in both CPUs.

Direct Memory Access (DMA) Controllers

This product line has three DMA controllers, with 32, 29, and 2

channels, which support CPU-independent accesses to memory

and peripherals. The descriptors for DMA channels can be in

SRAM or flash. Therefore, the number of descriptors is limited

only by the size of the memory. Each descriptor can transfer data

in two nested loops with configurable address increments to the

source and destination. The size of data transfer per descriptor

varies based on the type of DMA channel. Refer to the technical

reference manual (TRM) for detail.

Each CPU offers debug and trace features as follows:

■ CM4 supports six hardware breakpoints and four watchpoints,

4-bit embedded trace macrocell (ETM), serial wire viewer

(SWV), and printf()-style debugging through the single wire

output (SWO) pin.

■ CM0+ supports four hardware breakpoints and two watch-

points, and a micro trace buffer (MTB) with 4-KB dedicated

RAM.

Cryptography Accelerator (Crypto)

PSoC 6 also has an Embedded Cross Trigger for synchronized

debugging and tracing of both CPUs.

This subsystem consists of hardware implementation and

acceleration of cryptographic functions and random number

generators.

Interrupts

This product line has 174 system and peripheral interrupt

sources, and supports interrupts and system exceptions on both

CPUs. CM4 has 174 interrupt request lines (IRQ), with the

interrupt source ‘n’ directly connected to IRQn. CM0+ has eight

interrupts IRQ[7:0] with configurable mapping of one or more

interrupt sources to any of the IRQ[7:0]. CM0+ also supports

eight internal (software only) interrupts.

The Crypto subsystem supports the following:

■ Encryption/Decryption Functions

❐ Data Encryption Standard (DES)

❐ Triple DES (3DES)

❐ Advanced Encryption Standard (AES) (128-, 192-, 256-bit)

❐ Elliptic Curve Cryptography (ECC)

❐ RSA cryptography functions

Each interrupt supports configurable priority levels (eight levels

for CM4 and four levels for CM0+). Up to four system interrupts

can be mapped to each of the CPUs' non-maskable interrupts

(NMI). Up to 39 interrupt sources are capable of waking the

device from Deep Sleep power mode using the WIC. Refer to the

technical reference manual (TRM).

■ Hashing functions

❐ Secure Hash Algorithm (SHA)

❐ SHA-1

❐ SHA-224/-256/-384/-512

■ Message authentication functions (MAC)

❐ Hashed message authentication code (HMAC)

❐ Cipher-based message authentication code (CMAC)

InterProcessor Communication (IPC)

In addition to the Arm SEV and WFE instructions, a hardware

InterProcessor Communication (IPC) block is included. It

includes 16 IPC channels and 16 IPC interrupt structures. The

IPC channels can be used to implement data communication

between the processors. Each IPC channel also implements a

locking scheme which can be used to manage shared resources.

The IPC interrupts let one processor interrupt the other, signaling

an event. This is used to trigger events such as notify and release

of the corresponding IPC channels. Some IPC channels and

other resources are reserved, as Table 2 shows:

■ 32-bit cyclic redundancy code (CRC) generator

■ Random number generators

❐ Pseudo random number generator (PRNG)

❐ True random number generator (TRNG)

Protection Units

This product line has multiple types of protection units to control

erroneous or unauthorized access to memory and peripheral

registers. CM4 and CM0+ have Arm MPUs for protection at the

bus master level. Other bus masters use additional MPUs.

Shared memory protection units (SMPUs) help implement

protection for memory resources that are shared among multiple

bus masters. Peripheral protection units (PPU) are similar to

SMPUs but are designed for protecting the peripheral register

space.

Table 2. Distribution of IPC Channels and Other Resources

Resources Available

Resources Consumed

IPC channels,

16 available

13 reserved

IPC interrupts,

16 available

13 reserved

Protection units support memory and peripheral access

attributes including address range, read/write, code/data,

privilege level, secured/non-secured, and protection context.

Some protection unit resources are reserved for system usage;

see the technical reference manual for details. Up to eight

protection contexts (boot is in protection context 0) allow access

privileges for memory and system resources to be set by the boot

process per protection context by bus master and code privilege

level.

Other interrupts

CM0+ NMI

1 reserved

Reserved

Other resources:

clock dividers, DMA channels, etc.

4 CM0+ interrupt mux

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In PSoC 64, multiple protection contexts are used to isolate the

different security levels within the device. The CM0+ makes use

of several of them during the boot sequence, bootloading,

system calls, etc. Protection context 6 is used for the user

application code that runs on the CM4 CPU. The SMPUs are set

up by default and cannot be modified by the user. See section 8

in the Architecture TRM for the protection context assignment.

See section 8 in the Architecture TRM for the protection context

assignment.

■ eFuse

A one-time-programmable (OTP) eFuse array consists of

1024 bits, all of which are reserved for system use. The bits

are used for storing hash values, unique IDs, or other similar

PSoC 64 parameters.

Each fuse is individually programmed; once programmed (or

“blown”), its state cannot be changed. Blowing a fuse transi-

tions it from the default state of 0 to 1. To program an eFuse,

V_DDIO0must be at 2.5 V ±5%, at 14 mA.

Memory

Because blowing an eFuse is an irreversible process, pro-

gramming is recommended only in mass production under

controlled factory conditions. For more information, see

PSoC 6 MCU Programming Specifications.

PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks.

■ Flash

There is up to 512 KB of flash; however 128 KB is reserved

for system usage, leaving 384 KB for applications. The 32-KB

auxiliary flash (AUXflash) is also reserved, and is not avail-

able for applications.

Boot Code

Two blocks of code, ROM Boot and Flash Boot, are

pre-programmed into the device and work together to provide

device startup and configuration, basic security features,

life-cycle stage management and other system functions.

There are also two 32-KB flash sectors:

❐ AUXflash

❐ Supervisory flash (SFlash). Data stored in Sflash includes

device trim values, Flash Boot code, and encryption keys.

After the device transitions into the “Secure” lifecycle stage,

SFlash can no longer be changed.

■ ROM Boot

On a device reset, the boot code in ROM is the first code to

execute. This code performs the following:

❐ Integrity checks of flash boot code

❐ Device trim setting (calibration)

❐ Setting the device protection units

The flash uses 128-bit-wide accesses to reduce power. Write

operations can be performed at the row level. A row is

512 bytes. Read operations are supported in both Low Power

and Ultra-Low Power modes, however write operations may

not be performed in Ultra-Low Power mode.

❐ Settingdeviceaccessrestrictionsfor“Secure”lifecyclestates

ROM cannot be changed and acts as the root of trust in a

secured system.

The flash controller has two caches, one for each CPU. Each

cache is 8 KB, with 4-way set associativity.

■ Flash Boot

■ SRAM

Flash boot is firmware stored in SFlash that ensures that only

a validated application may run on the device. It also ensures

that the firmware image has not been modified, such as by a

malicious third party.

Up to 256 KB of SRAM is provided, however, 80 KB is re-

served for system usage, leaving 176 KB for applications..

Power control and retention granularity is implemented in

32-KB blocks allowing the user to control the amount of mem-

ory retained in Deep Sleep. Memory is not retained in Hiber-

nate mode.

Flash boot:

❐ Is validated by ROM Boot

❐ Runs after ROM Boot and before the user application

❐ Enables system calls

■ ROM

The 64-KB ROM, also referred to as the supervisory ROM

(SROM), provides code (ROM Boot) for several system func-

tions. The ROM contains device initialization, flash write, se-

curity, eFuse programming, and other system-level routines.

ROM code is executed only by the CM0+ CPU, in protection

context 0. A system function can be initiated by either CPU,

or through the DAP. This causes an NMI in CM0+, which

causes CM0+ to execute the system function.

❐ Enables provisioning and device policy features

❐ Implements RoT-based services for cryptography

❐ Provides secured storage for keys and certificates

❐ Validates and launches first image based on policies

provisioned in the device

❐ Uses mbed TLS v2.24

If the user application cannot be validated, then flash boot

ensures that the device is transitioned into a safe state. Refer

to the PSoC 64 Security section for more details.

Document Number: 002-28785 Rev. *I

Page 10 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Memory Map

Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided

into the Arm-defined regions shown in Table 8. Note that code can be executed from the Code and External RAM regions.

Table 3. Address Map for CM4 and CM0+

Address Range

Name

Code

Use

Program code region. Data can also be placed here. It includes the exception

vector table, which starts at address 0.

0x0000 0000 – 0x1FFF FFFF

0x2000 0000 – 0x3FFF FFFF

0x4000 0000 – 0x5FFF FFFF

SRAM

Data region. This region is not supported in PSoC 6.

All peripheral registers. Code cannot be executed from this region. CM4 bit-band

in this region is not supported in PSoC 6.

Peripheral

External

RAM

SMIF or Quad SPI, (see the Quad-SPI (QSPI)/Serial Memory Interface (SMIF)

section). Code can be executed from this region.

0x6000 0000 – 0x9FFF FFFF

0xA000 0000 – 0xDFFF FFFF

External

Device

Not used.

Private

Peripheral

Bus

0xE000 0000 – 0xE00F FFFF

0xE010 0A000 – 0xFFFF FFFF

Provides access to peripheral registers within the CPU core.

Device-specific system registers.

Device

The device memory map shown in Table 4 applies to both CPUs. That is, the CPUs share access to all PSoC 6 MCU memory and

peripheral registers.

Table 4. Internal Memory Address Map for CM4 and CM0+

Address Range

Memory Type

Size

0x0000 0000 – 0x0000 FFFF

ROM

64 KB

0x0800 0000 – 0x0802 BFFF

0x0802 C000 - 0x0803 FFFF

Application SRAM

System SRAM

Up to 176 KB

80 KB

0x1000 0000 – 0x1005 FFFF

0x1006 0000 - 0x1007 FFFF

Application flash

Secured code flash

Used for secured boot, secured bootloader,

and system calls

Up to 384 KB

128 KB

0x1400 0000 – 0x1400 7FFF

0x1600 0000 – 0x1600 7FFF

Auxiliary flash, reserved for system use

Supervisory flash, for secured access

32 KB

Note that PSoC 6 SRAM is located in the Arm Code region for both CPUs (see Table 8). There is no physical memory located in the

CPUs’ Arm SRAM regions.

Document Number: 002-28785 Rev. *I

Page 11 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

■ CPU Sleep – CPU code execution is halted in system LP or

ULP mode

System Resources

Power System

■ CPU Deep Sleep – CPU code execution is halted and system

Deep Sleep is requested in system LP or ULP mode

The power system provides assurance that voltage levels are as

required for each respective mode and will either delay mode

entry (on power-on reset (POR), for example) until voltage levels

are as required for proper function or generate resets (brown-out

detect (BOD)) when the power supply drops below specified

levels. The design guarantees safe chip operation between

power supply voltage dropping below specified levels (for

example, below 1.7 V) and the reset occurring. There are no

voltage sequencing requirements.

■ System Deep Sleep – Only low-frequency peripherals are

available after both CPUs enter CPU Deep Sleep mode

■ System Hibernate – Device and I/O states are frozen and the

device resets on wakeup

CPU Active, Sleep, and Deep Sleep are standard Arm-defined

power modes supported by the Arm CPU instruction set

architecture (ISA). System LP, ULP, Deep Sleep and Hibernate

modes are additional low-power modes supported by PSoC 6

MCU.

The V_DDDsupply (1.7 to 3.6 V) powers an on-chip buck regulator

or a low-dropout regulator (LDO), selectable by the user. In

addition, both the buck and the LDO offer a selectable (0.9 or

1.1 V) core operating voltage (V_CCD). The selection lets users

choose between two system power modes:

Clock System

Figure 15 shows that the clock system of this product line

consists of the following:

■ System Low Power (LP) operates V_CCDat 1.1 V and offers high

performance, with no restrictions on device configuration.

■ Internal main oscillator (IMO)

■ Internal low-speed oscillator (ILO)

■ Watch crystal oscillator (WCO)

■ External MHz crystal oscillator (ECO)

■ External clock input

■ System Ultra Low Power (ULP) operates V_CCDat 0.9 V for

exceptional low power, but imposes limitations on clock

speeds.

In addition, a backup domain adds an “always on” functionality

using a separate power domain supplied by a backup supply

(V_BACKUP) such as a battery or supercapacitor.

It includes a real-time clock (RTC) with alarm feature, supported

■ One phase locked-loop (PLL)

■ One frequency-locked loop (FLL)

by

a 32.768-kHz watch crystal oscillator (WCO), and

power-management IC (PMIC) control. Refer to Power Supply

Considerations for more details.

Clocks may be buffered and brought out to a pin on a Smart I/O

port.

Power Modes

The default clocking when the application starts is CLK_HF[0]

being driven by the IMO and the FLL. CLK_HF[0], clk_fast,

clk_peri, and clk_slow are all either 50 MHz (LP mode) or 25 MHz

(ULP mode). All other clocks, including all peripheral clocks, are

off.

PSoC 6 MCU can operate in four system and three CPU power

modes. These modes are intended to minimize the average

power consumption in an application. For more details on power

modes and other power-saving configuration options, see the

application note, AN219528: PSoC 6 MCU Low-Power Modes

and Power Reduction Techniques and the Architecture TRM,

Power Modes chapter (contact your local Cypress sales

representative for the latest TRM).

Internal Main Oscillator (IMO)

The IMO is the primary source of internal clocking. It is trimmed

at the factory to achieve the specified accuracy. The IMO

frequency is 8 MHz and tolerance is ± 2%.

Power modes supported by PSoC 6 MCUs, in order of

decreasing power consumption, are:

The IMO can operate in system Deep Sleep mode to drive the

LCD block for better contrast (and higher power) than is possible

with the 32-kHz mode.

■ System Low Power (LP) – All peripherals and CPU power

modes are available at maximum speed

■ System Ultra Low Power (ULP) – All peripherals and CPU

power modes are available, but with limited speed

Internal Low-Speed Oscillator (ILO)

The ILO is a very low power oscillator, nominally 32 kHz, which

operates in all power modes. The ILO can be calibrated against

a higher accuracy clock for better accuracy.

■ CPUActive – CPU is executing code in system LPor ULPmode

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Page 12 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 3. Clocking Diagram

Yellow multiplexers

are glitch safe

Path Mux

Root mux

(FLL/PLL)

FLL

clk_fast

Divider

CM4

CLK_HF[0]

CLK_HF[1]

Predivider

(1/2/4/8)

Peripheral

clocks

IMO

clk_peri

Peripheral

Clock Dividers

TCPWM

SCB

EXTCLK

clk_slow

Predivider

(1/2/4/8)

PLL

clk_ext

CM0+

AHB

Divider

ECO

CapSense

CLK_PATH2

CLK_HF[2]

CLK_HF[3]

CLK_HF[4]

Analog

Subsystem

Predivider

(1/2/4/8)

ALTHF

QSPI/SMIF

DMA

CLK_PATH3

CLK_PATH4

Smart I/O

eFuse

MMIO

PPU

Predivider

(1/2/4/8)

USB

Predivider

(1/2/4/8)

SD Host

System LP/ULP Domain

System Deep Sleep /

Hibernate Domain

Crypto

ILO

clk_peri

CLK_LF

clk_mf

LCD

Predivider

(1/2/3...256)

WCO

IMO/4

External Crystal Oscillators

Table 5. ECO Usage Guidelines

Figure 4 shows all of the external crystal oscillator circuits for this

product line. The component values shown are typical; check the

ECO Specifications for the crystal values, and the crystal

datasheet for the load capacitor values. The ECO and WCO

require balanced external load capacitors. For more information,

see the TRM and AN218241, PSoC 6 MCU Hardware Design

Considerations.

Max

Drive Strength Drive Strength

Ports

Frequency for V_DDD≤ 2.7 V for V_DDD≤ 2.7 V

Port 11

60 MHz for

SMIF (QSPI)

DRIVE_SEL 2 DRIVE_SEL 3

Ports 12 Slow slew rate No restrictions No restrictions

and 13 setting

Figure 4. Oscillator Circuits

PSoC 6

Watchdog Timers (WDT, MCWDT)

PSoC 6 MCU has one WDT and two multi-counter WDTs

(MCWDT). The WDT has a 16-bit free-running counter. Each

MCWDT has two 16-bit counters and one 32-bit counter, with

multiple operating modes. All of the 16-bit counters can generate

a watchdog device reset. All of the counters can generate an

interrupt on a match event.

The WDT is clocked by the ILO. It can generate interrupt/wakeup

in system LP/ULP, Deep Sleep, and Hibernate power modes.

The MCWDTs are clocked by LFCLK (ILO or WCO). It can

generate periodic interrupt/wakeup in system LP/ULP and Deep

Sleep power modes.

MHz XTAL

32.768 kHz XTAL

Clock Dividers

C_L/ 2

Integer and fractional clock dividers are provided for peripheral

use and timing purposes. There are:

If the ECO is used, note that its performance is affected by GPIO

switching noise. GPIO ports should be used as Table 5 shows.

See also Table 6 for additional restrictions for general analog

subsystem use.

■ Four 8-bit clock dividers

■ Eight 16-bit integer clock dividers

■ Two 16.5-bit fractional clock dividers

■ One 24.5-bit fractional clock divider

Document Number: 002-28785 Rev. *I

Page 13 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Trigger Routing

Programmable Analog Subsystems

PSoC 6 MCU contains a trigger multiplexer block. This is a

collection of digital multiplexers and switches that are used for

routing trigger signals between peripheral blocks and between

GPIOs and peripheral blocks.

12-bit SAR ADC

The 12-bit, 2-Msps SAR ADC can operate at a maximum clock

rate of 36 MHz and requires a minimum of 18 clocks at that

frequency to do a 12-bit conversion. One of three internal

reference voltages may be used for the ADC reference voltage.

The references are, V_DD, V_DD/2, and V_REF(nominally 1.2 V and

trimmed to ±1%). An external reference may also be used, by

either driving the VREF pin or routing an external reference to

GPIO pin P9.3. These reference options allow ratio-metric

readings or absolute readings at the accuracy of the reference

used. The input range of the ADC is the full supply voltage

between V_SSand V_DDA/V_DDIOA. The SAR ADC may be

configured with a mix of single-ended and differential signals in

the same configuration.

There are two types of trigger routing. Trigger multiplexers have

reconfigurability in the source and destination. There are also

hardwired switches called “one-to-one triggers”, which connect

a specific source to a destination. The user can enable or disable

the route.

Reset

PSoC 6 MCU can be reset from a variety of sources:

■ Power-on reset (POR) to hold the device in reset while the

power supply ramps up to the level required for the device to

function properly. POR activates automatically at power-up.

The SAR ADC’s sample-and-hold (S/H) aperture is

programmable to allow sufficient time for signals with a high

impedance to settle sufficiently, if required. System performance

is 65 dB for true 12-bit precision provided appropriate references

are used and system noise levels permit it. To improve

performance in noisy conditions, an external bypass capacitor

for the internal reference amplifier (through the fixed “VREF”

pin), may be added.

■ Brown-out detect (BOD) reset to monitor the digital voltage

supply V_DDDand generate a reset if V_DDDfalls below the

minimum required logic operating voltage.

■ External reset dedicated pin (XRES) to reset the device using

an external source. The XRES pin is active low. It can be

connected either to a pull-up resistor to V_DDD, or to an active

drive circuit, as Figure 5 shows. If a pull-up resistor is used,

select its value to minimize current draw when the pin is pulled

low; 4.7 kΩ is typical.

The SAR is connected to a fixed set of pins through an input

multiplexer. The multiplexer cycles through the selected

channels autonomously (sequencer scan) and does so with zero

switching overhead (that is, the aggregate sampling bandwidth

is equal to 2 Msps whether it is for a single channel or distributed

over several channels). The result of each channel is buffered,

so that an interrupt may be triggered only when a full scan of all

channels is complete. Also, a pair of range registers can be set

to detect and cause an interrupt if an input exceeds a minimum

and/or maximum value. This allows fast detection of out-of-range

values without having to wait for a sequencer scan to be

completed and the CPU to read the values and check for

out-of-range values in software. The SAR can also be

connected, under firmware control, to most other GPIO pins via

the Analog Multiplexer Bus (AMUXBUS). The SAR is not

available in system Deep Sleep and Hibernate modes as it

requires a high-speed clock (up to 36 MHz). The SAR operating

range is 1.71 to 3.6 V.

Figure 5. XRES Connection Diagram

1.7 to 3.6 V

PSoC 6

V_DDD

4.7 kΩ typ.

XRES

drive

■ Watchdog timer (WDT or MCWDT) to reset the device if

firmware fails to service it within a specified timeout period.

■ Software-initiated reset to reset the device on demand using

firmware.

Temperature Sensor

■ Logic-protectionfaultcantrigger aninterruptorresetthedevice

if unauthorized operating conditions occur; for example,

reaching a debug breakpoint while executing privileged code.

An on-chip temperature sensor is part of the SAR and may be

scanned by the SAR ADC. It consists of a diode, which is biased

by a current source that can be disabled to save power. The

temperature sensor may be connected directly to the SAR ADC

as one of the measurement channels. The ADC digitizes the

temperature sensor’s output and a Cypress-supplied software

function may be used to convert the reading to temperature

which includes calibration and linearization.

■ Hibernate wakeup reset to bring the device out of the system

Hibernate power mode.

Reset events are asynchronous and guarantee reversion to a

known state. Some of the reset sources are recorded in a

register, which is retained through reset and allows software to

determine the cause of the reset.

Low-Power Comparators

Two low-power comparators are provided, which can operate in

all power modes. This allows other analog system resources to

be disabled while retaining the ability to monitor external voltage

levels during system Deep Sleep and Hibernate modes. The

comparator outputs are normally synchronized to avoid

metastability unless operating in an asynchronous power mode

(Hibernate) where the system wake-up circuit is activated by a

comparator-switch event.

Document Number: 002-28785 Rev. *I

Page 14 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 6 shows an overview of the analog subsystem. This diagram is a high-level abstraction. See the TRM for detailed connectivity

information.

Figure 6. Analog Subsystem

Red dots indicate

AMUXBUS splitter

switches

AMUXBUSA

AMUXBUSB

CSD

shield_pad

vref_ext

csh

cmod

amuxbusa

amuxbusb

P6.0

LPCOMP0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

inp

inn

LPCOMP1

inp

inn

P5.0

P5.1

P5.6

P5.7

P9.3

P9.2

P9.1

P9.0

AREF, 1.2 V

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P10.6

P10.7

SAR ADC

vplus

vminus

vref

SARREF

V_DDA

V_DDA/ 2

TEMP

temp

V_SS

To V_REFpin, for bypass capacitor

Each Smart I/O block contains a data unit (DU) and eight lookup

tables (LUTs).

Programmable Digital

Smart I/O

The DU:

Smart I/O is a programmable logic fabric that enables Boolean

operations on signals traveling from device internal resources to

the GPIO pins or on signals traveling into the device from

external sources. A Smart I/O block sits between the GPIO pins

and the high-speed I/O matrix (HSIOM) and is dedicated to a

single port.

■ Performs unique functions based on a selectable opcode.

■ Can source input signals from internal resources, the GPIO

port, or a value in the DU register.

Each LUT:

■ Has three selectable input sources. The input signals may be

sourced from another LUT, an internal resource, an external

signal from a GPIO pin, or from the DU.

There are two Smart I/O blocks: one on Port 8 and one on Port 9.

When Smart I/O is not enabled, all signals on Port 8 and Port 9

bypass the Smart I/O hardware.

■ Acts as a programmable Boolean logic table.

■ Can be synchronous or asynchronous.

Smart I/O supports:

■ System Deep Sleep operation

■ Boolean operations without CPU intervention

■ Asynchronous or synchronous (clocked) operation

Document Number: 002-28785 Rev. *I

Page 15 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

SPI Mode: The SPI mode supports full Motorola SPI, TI Secure

Simple Pairing (SSP) (essentially adds a start pulse that is used

to synchronize SPI Codecs), and National Microwire (half-duplex

form of SPI). The SPI block supports an EZSPI mode in which

the data interchange is reduced to reading and writing an array

in memory. The SPI interface operates with a 25-MHz clock.

Fixed-Function Digital

Timer/Counter/Pulse-width Modulator (TCPWM)

■ The TCPWM supports the following operational modes:

❐ Timer-counter with compare

❐ Timer-counter with capture

USB Full-Speed Device Interface

❐ Quadrature decoding

❐ Pulse width modulation (PWM)

❐ Pseudo-random PWM

❐ PWM with dead time

This product line incorporates a full-speed USB device interface.

The device can have up to eight endpoints. A 512-byte SRAM

buffer is provided and DMA is supported.

■ Up, down, and up/down counting modes.

Note: If the USB pins are not used, connect V_DDUSBto ground

and leave the P14.0/USBDP and P14.1/USBDM pins

unconnected.

■ Clock prescaling (division by 1, 2, 4, ... 64, 128)

■ Double buffering of compare/capture and period values

■ Underflow, overflow, and capture/compare output signals

■ Supports interrupt on:

❐ Terminal count – Depends on the mode; typically occurs on

overflow or underflow

❐ Capture/compare – The count is captured to the capture reg-

ister or the counter value equals the value in the compare

register

Quad-SPI/Serial Memory Interface (SMIF)

A serial memory interface is provided, running at up to 80 MHz.

It supports single, dual, and quad SPI configurations, and

supports up to four external memory devices. It supports two

modes of operation:

■ Memory-mapped I/O (MMIO), a command mode interface that

provides data access via registers and FIFOs

■ Complementary output for PWMs

■ Execute in Place (XIP), in which AHB reads and writes are

directly translated to SPI read and write transfers.

■ Selectable start, reload, stop, count, and capture event signals

for each TCPWM; with rising edge, falling edge, both edges,

and level trigger options. The TCPWM has a Kill input to force

outputs to a predetermined state.

In XIP mode, the external memory is mapped into the PSoC 6

MCU internal address space, enabling code execution directly

from the external memory. To improve performance, a 4-KB

cache is included. XIP mode also supports AES-128 on-the-fly

encryption and decryption, enabling secured storage and access

of code and data in the external memory.

In this device there are:

■ Four 32-bit TCPWMs

■ Eight 16-bit TCPWMs

Serial Communication Blocks (SCB)

This product line has seven SCBs:

LCD

This block drives LCD commons and segments; routing is

available to most of the GPIOs. One to eight of the GPIOs must

be used for commons, the rest can be used for segments.

■ Six can implement either I²C, UART, or SPI.

■ One SCB (SCB #6) can operate in system Deep Sleep mode

with an external clock; this SCB can be either SPI slave or I²C

slave.

I²C Mode: The SCB can implement a full multi-master and slave

interface (it is capable of multimaster arbitration). This block can

operate at speeds of up to 1 Mbps (Fast Mode Plus). It also

supports EZI2C, which creates a mailbox address range and

effectively reduces I²C communication to reading from and

writing to an array in memory. The SCB supports a 256-byte

FIFO for receive and transmit.

The LCD block has two modes of operation: high speed (8 MHz)

and low speed (32 kHz). Both modes operate in system LP, ULP,

and Deep Sleep modes, however the low-speed mode operates

with reduced contrast in system Deep Sleep mode. The 8-MHz

IMO is available in system Deep Sleep mode, and can be used

to generate a clock for the LCD block. Review the number of

common and segment lines, viewing angle requirements, and

prototype performance, and then select the appropriate LCD

clock frequency before using system Deep Sleep mode.

SD Host Controller

The I²C peripheral is compatible with I²C standard-mode, Fast

Mode, and Fast Mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/O is implemented with GPIO in open-drain modes.

This product line contains one Secure Digital (SD) host

controller. It provides communication with IoT connectivity

devices such as Bluetooth, Bluetooth Low-Energy and WiFi

radios, as well as combination devices. The controller also

supports embedded MultiMediaCards (eMMC) and Secure

Digital (SD) cards.

UART Mode: This is a full-feature UART operating at up to

8 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows the

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. A 256-byte FIFO allows

much greater CPU service latencies to be tolerated.

Several bus speed modes under the SD specification are

supported:

■ DS (default speed)

■ HS (high speed)

■ SDR12 (single data rate)

■ SDR25

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Page 16 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

■ SDR50

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ DDR50 (double data rate)

For eMMC, the supported modes are:

■ BWC (backward compatibility)

■ SDR

■ Input threshold select (CMOS or LVTTL)

■ Hold mode for latching previous state (used for retaining the

I/O state in system Hibernate mode)

Maximum clock restrictions and capacitive loads apply to some

modes, and are also dependent on system power mode

(LP/ULP). Refer to the SD Host Controller and eMMC

Specifications for details.

■ Selectable slew rates for dV/dt-related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

up to 8 pins in width. Data output and pin state registers store,

respectively, the values to be driven on the pins and the input

states of the pins.

The SD Host Controller complies with the following standards.

Refer to the specifications documents for more information on

the protocol and operations.

■ SD Specifications Part 1 Physical Layer Specification Version

6.00, supporting card capacities for SDSC (up to 2 GB), SDHC

(up to 32 GB) and SDXC (up to 2 TB).

Every pin can generate an interrupt if enabled; each port has an

interrupt request (IRQ) associated with it.

The port 3 pins are capable of overvoltage-tolerant (OVT)

■ SD Specifications Part A2 SD Host Controller Standard Speci-

fication Version 4.20

operation, where the input voltage may be higher than V_DDD

.

OVT pins are commonly used with I²C, to allow powering the

chip OFF while maintaining a physical connection to an

operating I²C bus without affecting its functionality.

■ SD Specifications Part E1 SDIO Specifications Version 4.10

■ Embedded Multi-Media Card (eMMC) Electrical Standard 5.1

GPIO pins can be ganged to source or sink higher values of

current. GPIO pins, including OVT pins, may not be pulled up

higher than the absolute maximum; see Electrical Specifications.

The SD host controller is configured as a master. To be fully

compatible with features provided in the driver software for

speed and efficiency, it supports advanced DMA version 3

(ADMA3), defined by the SDIO standard, and has a 1 KB RX/TX

FIFO allowing double buffering of 512-byte blocks.

During power-on and reset, the pins are forced to the analog

input drive mode, with input and output buffers disabled, so as

not to crowbar any inputs and/or cause excess turn-on current.

CAN FD Block

A multiplexing network known as the high-speed I/O matrix

(HSIOM) is used to multiplex between various peripheral and

analog signals that may connect to an I/O pin.

This product line has one CAN FD block for industrial and

automotive applications. The block includes Time-Stamp support

and has a 4-KB message RAM. FD Data rates of up to 5 Mbps

are supported. DMA transfers are supported.

Analog performance is affected by GPIO switching noise. In

order to get the best analog performance, the following

frequency and drive mode constraints must be applied. The

DRIVE_SEL values (see Table 6) represent drive strengths

(please see the Architecture and Register TRMs for further

detail).

GPIO

This product line has up to 53 GPIOs, which implement the

following:

See also Table 5 for additional restrictions for ECO use.

■ Eight drive strength modes:

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

Table 6. DRIVE_SEL Values

Ports

Ports 0, 1

Max Frequency

8 MHz

Drive Strength for V_DDD≤ 2.7 V Drive Strength for V_DDD> 2.7 V

DRIVE_SEL 2

DRIVE_SEL 1

DRIVE_SEL 2

DRIVE_SEL 1

No restrictions

DRIVE_SEL 3

DRIVE_SEL 2

DRIVE_SEL 3

DRIVE_SEL 2

No restrictions

Port 2

50 MHz

Ports 3 to 10

Ports 11 to 12

Ports 9 and 10

16 MHz; 25 MHz for SPI

80 MHz for SMIF (QSPI).

Slow slew rate setting for TQFP

Packages for ADC performance

Document Number: 002-28785 Rev. *I

Page 17 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

IDAC

Special-Function Peripherals

The CSD block has two programmable current sources, which

offer the following features:

CapSense Subsystem

CapSense is supported in PSoC 6 MCU through a CapSense

sigma-delta (CSD) hardware block. It is designed for

high-sensitivity self-capacitance and mutual-capacitance

measurements, and is specifically built for user interface

solutions.

■ 7-bit resolution

■ Sink and source current modes

■ A current source programmable from 37.5 nA to 609 A

In addition to CapSense, the CSD hardware block supports three

general-purpose functions. These are available when CapSense

is not being used. Alternatively, two or more functions can be

time-multiplexed in an application under firmware control. The

four functions supported by the CSD hardware block are:

■ Two IDACs that can be used in parallel to form one 8-bit IDAC

Comparator

The CapSense subsystem comparator operates in the system

Low Power and Ultra-Low Power modes. The inverting input is

connected to an internal programmable reference voltage and

the non-inverting input can be connected to any GPIO via the

AMUXBUS.

■ CapSense

■ 10-bit ADC

■ Programmable current sources (IDAC)

■ Comparator

CapSense Hardware Subsystem

Figure 7 shows the high-level hardware overview of the

CapSense subsystem, which includes a delta sigma converter,

internal clock dividers, a shield driver, and two programmable

current sources.

CapSense

Capacitive touch sensors are designed for user interfaces that

rely on human body capacitance to detect the presence of a

finger on or near a sensor. Cypress CapSense solutions bring

elegant, reliable, and simple capacitive touch sensing functions

to applications including IoT, industrial, automotive, and home

appliances.

The inputs are managed through analog multiplexed buses

(AMUXBUS A/B). The input and output of all functions offered by

the CSD block can be provided on any GPIO or on a group of

GPIOs under software control, with the exception of the

comparator output and external capacitors that use dedicated

GPIOs.

The Cypress-proprietary CapSense technology offers the

following features:

Self-capacitance is supported by the CSD block using

AMUXBUS A, an external modulator capacitor, and a GPIO for

each sensor. There is a shield electrode (optional) for

self-capacitance sensing. This is supported using AMUXBUS B

and an optional external shield tank capacitor (to increase the

drive capability of the shield driver) should this be required.

Mutual-capacitance is supported by the CSD block using

AMUXBUS A, two external integrated capacitors, and a GPIO for

transmit and receive electrodes.

■ Best-in-class signal-to-noise ratio (SNR) and robust sensing

under harsh and noisy conditions

■ Self-capacitance (CSD) and mutual-capacitance (CSX)

sensing methods

■ Support for various widgets, including buttons, matrix buttons,

sliders, touchpads, and proximity sensors

■ High-performance sensing across a variety of materials

■ Best-in-class liquid tolerance

The ADC does not require an external component. Any GPIO

that can be connected to AMUXBUS A can be an input to the

ADC under software control. The ADC can accept V_DDAas an

input without needing GPIOs (for applications such as battery

voltage measurement).

■ SmartSense™ auto-tuning technology that helps avoid

complex manual tuning processes

■ Superior immunity against external noise

■ Spread-spectrum clocks for low radiated emissions

■ Gesture and built-in self-test libraries

■ Ultra-low power consumption

The two programmable current sources (IDACs) in

general-purpose mode can be connected to AMUXBUS A or B.

They can therefore connect to any GPIO pin. The comparator

resides in the delta-sigma converter. The comparator inverting

input can be connected to the reference. Both comparator inputs

can be connected to any GPIO using AMUXBUS B; see

Figure 6. The reference has a direct connection to a dedicated

GPIO; see Table 9.

■ An integrated graphical CapSense tuner for real-time tuning,

testing, and debugging

ADC

The CSD block can operate in active and sleep CPU power

modes, and seamlessly transition between system LP and ULP

modes. It can be powered down in system Deep Sleep and

Hibernate modes. Upon wakeup from Hibernate mode, the CSD

block requires re-initialization. However, operation can be

resumed without re-initialization upon exit from Deep Sleep

mode, under firmware control.

The CapSense subsystem slope ADC offers the following

features:

■ Selectable 8- or 10-bit resolution

■ Selectable input range: GND to V_REFand GND to V_DDAon any

GPIO input

■ MeasurementofV_DDAagainst aninternal referencewithoutthe

use of GPIO or external components

Document Number: 002-28785 Rev. *I

Page 18 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 7. CapSense Hardware Subsystem

AMUXBUS

A

B

GPIO Pin

GPIO

Cell

CSD Sensor 1

C_S1

Clock Input

GPIO Pin

C_MODPin

GPIO

Cell

CSD Sensor 2

C_S2

CSD Hardware Block

C_MOD

Sense clock

Clock

Generator

C_{SH_TANK}

(optional)

GPIO Pin

Shield Drive

Circuit

Modulator

Clock

GPIO

Cell

Compensation

IDAC

C_SHIELD

Shield Electrode

Modulator

IDAC

GPIO Pin

Tx

IDAC control

GPIO

Cell

CSX Sensor 3

C_S3

Raw

Count

Sigma Delta

Converter

GPIO Pin

C_INTAPin

Rx

GPIO

Cell

V_REF

GPIO

Cell

C_INTA

C_INTB

C_INTBPin

GPIO

Cell

ADC Input

IDAC Outputs

Comp Input

Document Number: 002-28785 Rev. *I

Page 19 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 18 shows the high-level software overview. Cypress

provides middleware libraries for CapSense, ADC, and IDAC on

GitHub to enable quick integration. The Board Support Package

for any kit with CapSense capabilities automatically includes the

CapSense library in any application that uses the BSP.

CapSense and ADC middleware use the CSD interrupt to

implement non-blocking sensing and A-to-D conversion.

Therefore, interrupt service routines are a defined part of the

middleware, which must be initialized by the application.

Middleware and drivers can operate on either CPU. Cypress

recommends using the middleware only in one CPU. If both

CPUs must access the CSD driver, memory access should be

managed in the application.

User applications interact only with middleware to implement

functions of the CSD block. The middleware interacts with

underlying drivers to access hardware as necessary. The CSD

driver facilitates time-multiplexing of the CSD hardware if more

than one piece of CSD-related middleware is present in a project.

It prevents access conflicts in this case.

Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design

Guide for more details on CSX sensing, CSD sensing, shield

electrode usage and its benefits, and capacitive system design

guidelines.

ModusToolbox Software provides a CapSense configurator to

enable fast library configuration. It also provides a tuner for

performance evaluation and real-time tuning of the system. The

tuner requires an EZI2C communication interface in the

application to enable real-time tuning capability. The tuner can

update configuration parameters directly in the device as well as

in the configurator.

Refer to theAPI reference guides for CapSense, ADC, and IDAC

available on GitHub.

Figure 8. CapSense Software/Firmware Subsystem

Application Program

Middleware

Software

Configuration

Tuner

SCB Driver

(EZI2C)

GPIO / Clock

CSD Driver

CSD Block

Drivers

SCB

GPIOs / Clock

Hardware and Drivers

Document Number: 002-28785 Rev. *I

Page 20 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

The first step in using a PSoC 64 device is to inject the following

information into the device - a process called provisioning:

PSoC 64 Security

All PSoC 64 “Secure” MCU product lines feature enhanced

security functionality. They provide an isolated root of trust (RoT)

with true attestation and provisioning services. Cypress also

provides a “Secure Boot” SDK which includes all required

libraries, tools, and sample code to provision PSoC 64 devices.

The SDK also provides provisioning scripts with sample keys

and policies, a pre-built bootloader image, and tools for signing

firmware images. For more information, see the “Secure Boot”

SDK User Guide.

■ A set of cryptographic public keys, which are used to:

❐ Transfer the RoT from Cypress to the user/OEM, as Figure 9

shows

❐ Validate applications

■ A set of security policies that define how the device should

behave

■ Certificates (optional) used to bind device identity or provide a

The “Secure Boot” SDK also includes entrance exam scripts. An

entrance exam can optionally be run on PSoC 64 devices before

provisioning to ensure that no device tampering has occurred.

chain of trust to a higher certifying authority

■ The Cypress bootloader

Provisioning is done before an application is programmed into

the device.

Figure 9. PSoC 64 Usage Processes

Program

Manufacture

Take Over Root-of-Trust

Setup chip security

Application

User RoT

OEM RoT

Public Key

Cy RoT

Public Key

Unique Device

Identity

Unique Device

Identity

Unique Device

Identity

PSoC 64

Keys, Security

Policies, Certificates

Keys, Security

Policies, Certificates

PSoC 64

Cypress Bootloader

PSoC 64

User Application

PSoC 64

Provisioning is done using a hardware security module (HSM). An HSM is a physical computing device, placed in a secured facility,

that safeguards and manages digital keys for strong authentication, and provides cryptographic processing.

After the device is provisioned, it can be programmed with signed applications. The signature and authenticity of the application is

verified before control is transferred to it.

Document Number: 002-28785 Rev. *I

Page 21 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 10 shows a simplified flash memory map of PSoC 64 assets and immutable sections. As noted in Memory, a portion of device

SRAM is also reserved for system usage.

Figure 10. PSoC 64 “Secure” MCU Asset Memory Map

0x1000:0000

User Application Space

Typically immutable, can be

0x101D:0000

updated if allowed by security

Cypress Bootloader

policy during provisioning

0x101E:0000

“Secure Flash Boot”

Immutable after Cypress

Manufacturing

OEM Asset storage

0x101F:BF00

0x101F:FFFF

Typically immutable, can be

partially updated if allowed by

security policy during provisioning

User Flash

0x1600:7FFF

“Secure Flash Boot” +

Cypress Public Key

0x1600:0000

0x0001:FFFF

Supervisory Flash

Boot ROM

ROM

Immutable after Cypress

Manufacturing

0x0000:0000

Document Number: 002-28785 Rev. *I

Page 22 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Cypress Bootloader

Cypress Bootloader supports external memory over the

PSoC 64 Serial Memory Interface (SMIF). The bootloader

currently supports only external memory vendors who support

the Serial Flash Discovery Protocol (SFDP).

Cypress Bootloader is a port of the open source MCUBoot

library. For more details about this library, refer to MCUBoot

Bootloader design. The current version of Cypress Bootloader

for this device does not support the swap-based images feature

as documented in the MCUBoot design document.

Cypress Bootloader enforces protection contexts for the

bootloader code, so code running in another protection context

cannot overwrite/tamper with the bootloader code. Figure 11

shows the launch sequence of Cypress Bootloader:

Cypress Bootloader is included in the “Secure Boot” SDK as a

pre-built hex image. This image acts as the first image launched

by the PSoC 64 boot code. It parses the provisioned

Boot&Upgrade policy to launch an application image.

Figure 11. Bootloader Launch Sequence

Reads for setting

access policies

Boot ROM +

“Secure Flash Boot”

Address of Bootloader image

and key for verification

Verifies & Launches

Debug Policy

Cypress Bootloader

Boot Policy

Bootloader Certificate

Address of User image

and key for verification

Provisioned Policies

First User Image

Signed with OEM Pvt key

Figure 12 shows a typical application update scenario using Cypress Bootloader:

Figure 12. Bootloader Application Update Sequence

New image available

Bootloader verifies new image

Bootloader updates current

image

Immutable Boot Code

Cypress Bootloader

Immutable Boot Code

Cypress Bootloader

Keys, Policies

Cypress Bootloader

Keys, Policies

Update image,

launches

New Image

Customer

Verifies new

Application v2

Customer Application v1

Signed with User Privkey

Customer Application v2

Signed with User Privkey

image content

and signature

with provisioned

keys

Customer Application v1

Signed with User Privkey

Signed with User

Privkey

Image

Written

Slot#0

Customer Application v2

Signed with User Privkey

Slot#1, empty

Slot#1

Internal (or) External flash

Document Number: 002-28785 Rev. *I

Page 23 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Pinouts

Note: The CYB06445LQI-S3D42 datasheet web page contains a spreadsheet with a consolidated list of pinouts and pin alternate

functions with HSIOM mapping. GPIO ports are powered by V_DDxpins as follows:

■ P0: V_BACKUP

■ P2, P3: V_DDIO2

■ P5, P6, P7, P8: V_DDIO1

■ P9, P10: V_DDIOA, V_DDA(V_DDIOAand V_DDAmust be connected together on the PCB)

■ P11, P12: V_DDIO0

■ P14: V_DDUSB

Table 7. Packages and Pin Information

Package

68-QFN

30

68-QFN

V_DDD

V_CCD

V_DDA

V_DDIOA

V_DDIO0

V_DDIO1

V_DDIO2

V_BACKUP

V_DDUSB

V_SS

68

P6.3

P6.4

67

31

48

P6.5

32

36

P6.6

33

64

P6.7

34

35

P7.0

37

22

P7.1

38

1

P7.2

39

11

P7.3

40

GND PAD

P7.7

41

V_{DD_NS}

V_IND1

XRES

V_REF

P0.0

9

10

8

P8.0

42

P8.1

43

P9.0

44

49

2

P9.1

45

P9.2

46

P0.1

3

P9.3

47

P0.2

4

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P11.0

P11.1

P11.2

P11.3

P11.4

P11.5

P11.6

P11.7

50

P0.3

5

51

P0.4

6

52

P0.5

7

53

P2.0

14

15

16

17

18

19

20

21

23

24

54

P2.1

55

P2.2

56

P2.3

57

P2.4

58

P2.5

59

P2.6

60

P2.7

61

P3.0

62

P3.1

63

Document Number: 002-28785 Rev. *I

Page 24 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 7. Packages and Pin Information

Package

68-QFN

65

68-QFN

P5.0

P5.1

P5.6

P5.7

P6.2

25

26

27

28

29

P12.6

P12.7

66

P14.0 / USBDP

P14.1 / USBDM

13

12

Note: If the USB pins are not used, connect V_DDUSBto ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.

Figure 13. Device Pinout for 68-QFN Package^[2]

V_BACKUP

P0.0

P10.1

P10.0

V_REF

1

2

3

4

5

6

51

50

P0.1

49

48

47

P0.2

P0.3

P0.4

V_DDA

P9.3

P9.2

46

P0.5

XRES

45

44

43

42

P9.1

P9.0

P8.1

P8.0

7

8

9

QFN

(TOP VIEW)

V_{DD_NS}

10

V_IND1

V_DDUSB

P14.1 / USBDM

P7.7

P7.3

11

12

13

41

40

39

P14.0 / USBDP

P7.2

P7.1

P2.0 14

38

37

36

35

P2.1

P2.2

P2.3

15

16

17

P7.0

V_DDIOA

V_{DDIO 1}

Note

2. The center pad on the QFN package should be connected to PCB ground relative to device VDDx for best mechanical, thermal, and electrical performance. For more

information, see AN72845, Design Guidelines for QFN Devices.

Document Number: 002-28785 Rev. *I

Page 25 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Analog and Smart I/O alternate port pin functionality is provided in Table 9.

Table 9. Port Pin Analog, and Smart I/O Functions

Name

P0.0

P0.1

P0.2

P0.3

P0.4

Analog

wco_in

Digital HV

AMUXA

AMUXB

SMARTIO

wco_out

pmic_wakeup_in

hibernate_wakeup[1]

P0.5

P5.6

P5.7

P6.2

P6.3

P6.6

P6.7

P7.0

P7.1

pmic_wakeup_out

lpcomp.inp_comp0

lpcomp.inn_comp0

lpcomp.inp_comp1

lpcomp.inn_comp1

swd_data

swd_clk

amuxbus_a_csd0

amuxbus_b_csd0

csd.cmodpadd

csd.cmodpads

P7.2

csd.csh_tankpadd

csd.csh_tankpads

amuxbus_a_csd0

amuxbus_b_csd0

P7.3

P7.7

csd.vref_ext

amuxbus_a_csd0

amuxbus_a_sar

amuxbus_b_csd0

amuxbus_b_sar

csd.cshieldpads

P8.0

smartio[8].io[0]

smartio[8].io[1]

smartio[9].io[0]

smartio[9].io[1]

smartio[9].io[2]

smartio[9].io[3]

P8.1

P9.0

P9.1

P9.2

P9.3

aref_ext_vref

sarmux_pads[0]

sarmux_pads[1]

sarmux_pads[2]

sarmux_pads[3]

sarmux_pads[4]

sarmux_pads[5]

eco_in

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P12.6

P12.7

eco_out

Document Number: 002-28785 Rev. *I

Page 30 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Power Supply Considerations

The following power system diagrams show typical connections for power pins, with and without usage of the buck regulator.

In these diagrams, the package pin is shown with the pin name, for example "V_DDA, 36". For V_DDxpins, the I/O port that is powered

by that pin is also shown, for example "V_BACKUP, 1; I/O port P0".

In the QFN package, all internal grounds are routed to the metal pad (epad) in the package. This pad must be grounded on the PCB.

Figure 14. 68-QFN Power Connections Diagram

1.7 to 3.6 V

CYB06445LQI-S3D42, 68-QFN package

1 KΩ at

100 MHz

1 KΩ at

100 MHz

V_DDD, 68

V_{DD_NS}, 9

V_IND1, 10

V_CCD, 67

10 µF

1 µF

10 µF

0.1 µF

10 µF

V_BACKUP, 1; I/O port P0

V_DDIO0, 64; I/O ports P11, P12

V_DDIO1, 35; I/O ports P5, P6, P7, P8

V_DDIO2, 22; I/O ports P2, P3

V_DDUSB, 11; I/O port P14

2.2 µH

4.7 µF

1 KΩ at

100 MHz

V_DDA, 48

V_DDIOA, 36; I/O ports P9, P10

GND PAD

Document Number: 002-28785 Rev. *I

Page 31 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 15. 68-QFN (No Buck) Power Connections Diagram

1.7 to 3.6 V

CYB06445LQI-S3D42, 68-QFN package

1 KΩ at

100 MHz

V_DDD, 68

_BACKUP, 1; I/O port P0

V_DDIO0, 64; I/O ports P11, P12

_DDIO1, 35; I/O ports P5, P6, P7, P8

V_DDIO2, 22; I/O ports P2, P3

_DDUSB, 11; I/O port P14

V_DDA, 48

_DDIOA, 36; I/O ports P9, P10

V_{DD_NS}, 9

10 µF

1 µF

10 µF

0.1 µF

V

V_IND1, 10

V

_CCD, 67

4.7 µF

V

1 KΩ at

100 MHz

V

GND PAD

There are as many as eight V_DDxsupply pins, depending on the

package, and multiple V_SSground pins. The power pins are:

■ V_BACKUP: the supply for the backup domain, which includes the

32-kHz WCO and the RTC. It can be a separate supply as low

as 1.4 V, for battery or supercapacitor backup, as Figure 16

shows, otherwise it is connected to V_DDD. It powers I/O port 0.

■ V_DDD: the main digital supply. It powers the LDO and switching

regulators.

Figure 16. Separate Battery Connection to V_BACKUP

■ V_CCD: the main LDO output. It requires a 4.7-µF capacitor for

regulation. The LDO can be turned off when V_CCDis driven

from the switching regulator (see below). For more information,

see the power system block diagram in the device technical

reference manual (TRM).

1.7 to 3.6 V

V_DDD

10 µF

1 µF

0.1 µF

■ V_DDA: the supply for the analog peripherals. Voltage must be

applied to this pin for correct device initialization and boot up.

V_BACKUP

■ V_DDIOA: the supply for I/O ports 9 and 10. It must be connected

to V_DDA

.

1.4 to 3.6 V

■ V_DDIO0: the supply for I/O ports 11 and 12.

■ V_DDIO1: the supply for I/O ports 5, 6, 7, and 8.

■ V_DDIO2: the supply for I/O ports 2 and 3.

■ V_DDUSB: the supply for the USB peripheral and the USBDPand

USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If

USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can

be used as limited-capability GPIOs on I/O port 14.

Document Number: 002-28785 Rev. *I

Page 32 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 10 shows a summary of the I/O port supplies:

No external load should be placed on V_CCD, or V_IND1, whether

or not these pins are used.

Table 10. I/O Power Supplies

There are no power pin sequencing requirements; power

supplies may be brought up in any order. The power

management system holds the device in reset until all power pins

are at the voltage levels required for proper operation.

Port

0

Supply

V_BACKUP

V_DDIO2

V_DDIO1

V_DDIOA

V_DDIO0

V_DDUSB

Alternate Supply

V_DDD

2, 3

–

Note: If a battery is installed on the PCB first, V_DDDmust be

cycled for at least 50 µs. This prevents premature drain of the

battery during product manufacture and storage.

5, 6, 7, 8

9, 10

11, 12

14

–

V_DDA

–

Bypass capacitors must be connected to a common ground from

the V_DDxand other pins, as indicated in the diagrams. Typical

practice for systems in this frequency range is to use a 10-µF or

1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for

example). Note that these are simply rules of thumb and that, for

critical applications, the PCB layout, lead inductance, and

bypass capacitor parasitic should be simulated for optimal

bypassing.

–

Note: If the USB pins are not used, connect V_DDUSBto ground

and leave the P14.0/USBDP and P14.1/USBDM pins unconnect-

ed.

Voltage must be applied to the V_DDDpin, and the V_DDApin as

noted above, for correct device initialization and operation. If an

I/O port is not being used, applying voltage to the corresponding

All capacitors and inductors should be ±20% or better. The

recommended inductor value is 2.2 µH ±20% (for example, TDK

MLP2012H2R2MT0S1).

V

_DDxpin is optional.

■ V_SS: ground pins for the above supplies.All ground pins should

be connected together to a common ground.

It is good practice to check the datasheets for your bypass

capacitors, specifically the working voltage and the DC bias

specifications. With some capacitors, the actual capacitance can

decrease considerably when the applied voltage is a significant

percentage of the rated working voltage.

In addition to the LDO regulator, a switching regulator is

included. The regulator pins are:

■ V_{DD_NS}: the regulator supply.

For more information on pad layout, refer to PSoC 6 CAD

libraries.

■ V_IND1: the regulator output. It is typically used to drive V_CCD

through an inductor.

The V_DDpower pins are not connected on chip. They can be

connected off chip, in one or more separate nets. If separate

power nets are used, they can be isolated from noise from the

other nets using optional ferrite beads, as indicated in the

diagrams.

Document Number: 002-28785 Rev. *I

Page 33 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Electrical Specifications

All specifications are valid for –40 °C ≤ T_A≤ 85 °C and for 1.71 V to 3.6 V except where noted.

Absolute Maximum Ratings

Table 11. Absolute Maximum Ratings^[3]

Spec ID#

SID1

Parameter

Description

Min

Typ

Max Units

Details / Conditions

Analog or digital supply relative to V

–0.5

–

4

V

SS

V

DD_ABS

(V

= V

)

SSD

SSA

Direct digital core voltage input relative to

–0.5

–

1.2

SID2

SID3

V

CCD_ABS

GPIO_ABS

V

SSD

V_DD

0.5

+

V

I

GPIO voltage; V

or V

DDD DDA

SID4

Current per GPIO

–25

–0.5

2200

500

–

25

0.5

–

mA

V

GPIO_ABS

SID5

I

GPIO injection current per pin

GPIO_injection

SID3A

ESD_HBM

ESD_CDM

LU

Electrostatic discharge Human Body Model

Electrostatic discharge Charged Device

Model

–

V

SID4A

SID5A

Pin current for latchup-free operation

–100

–

100

mA

Device-Level Specifications

Table 14 provides detailed specifications of CPU current. Table 12 summarizes these specifications, for rapid review of CPU currents

under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to

generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz.

Table 12. CPU Current Specifications Summary

Condition

= 3.3 V, V

Range

Typ Range

Max Range

LP Mode, V

= 1.1 V, with buck regulator

CCD

DDD

CM4 active, CM0+ sleep

CM0+ active, CM4 sleep

CM4 sleep, CM0+ sleep

CM0+ sleep, CM4 off

0.9–6.3 mA

0.8–3.8 mA

0.7–1.5 mA

0.7–1.3 mA

0.6–0.7 mA

1.5–7 mA

1.3–4.5 mA

1.3–2.2 mA

1.3–2 mA

Across CPUs clock ranges: 8–150/100 MHz; Dhrystone

with flash cache enabled

Minimum regulator current mode

ULP Mode, V = 3.3 V, V

Across CM4/CM0+ CPU active/sleep modes

1.1–1.1 mA

= 0.9 V, with buck regulator

CCD

DDD

CM4 active, CM0+ sleep

CM0+ active, CM4 sleep

CM4 sleep, CM0+ sleep

CM0+ sleep, CM4 off

0.65–1.6 mA

0.51–0.91 mA

0.42–0.76 mA

0.41–0.62 mA

0.39–0.54 mA

7–9 µA

0.8–2.2mA

0.72–1.25 mA

0.65–1.1 mA

0.6–0.9 mA

0.6–0.76 mA

-

Across CPUs clock ranges: 8 – 50/25 MHz; Dhrystone

with flash cache enabled

Minimum regulator current mode

Deep Sleep

Across CM4/CM0+ CPU active/sleep modes

Across SRAM retention

Hibernate

Across V

300–800 nA

-

DDD

Note

3. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 002-28785 Rev. *I

Page 34 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 17. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode

7

6

5

4

3

2

1

0

CM4 Active, CM0+ Sleep 1/2 CM4

CM4 Active, CM0+ Sleep same as CM4

CM0+ Active, CM4 Sleep

0

25

50

75

100

125

150

CPU Clock, MHz

Power Supplies

Table 13. Power Supply DC Specifications

Spec ID#

SID6

Parameter

Description

Internal regulator

Analog power supply voltage. Shorted to

on PCB.

Min

Typ

Max

Units

Details / Conditions

V

1.7

–

3.6

V

–

DDD

Internally unregulated

supply

SID7

1.7

–

3.6

V

DDA

V

DDIOA

Must be ≥ V_DDAif the

CapSense (CSD) block is

used in the application

SID7A

V

GPIO supply for Ports 5 to 8 when present

1.7

–

3.6

V

DDIO1

SID7B

SID7C

V

GPIO supply for Ports 11 and 12

1.7

–

3.6

V

–

DDIO0

DDIO2

GPIO supply for Ports 2 and 3 when present

GPIO supply for Ports 9 and 10 when present.

SID7D

SID7F

V

1.7

–

3.6

V

–

DDIOA

Must be connected to V

on PCB.

DDA

Supply for Port 14 (USB or GPIO) when

present

Min supply is 2.85 V for USB

DDUSB

Backup power and GPIO Port 0 supply when

present

Min. is 1.4 V when V

removed

is

DDD

SID6B

SID8

V

1.7

–

3.6

–

V

BACKUP

CCD1

Output voltage (for core logic bypass)

1.1

0.9

System LP mode

ULP mode. Valid for –20 to

85 °C.

SID9

Output voltage (for core logic bypass)

–

CCD2

X5Rceramicorbetter. Value

for 0.8 to 1.2 V

SID10

SID11

C

External regulator voltage (V

) bypass

CCD

3.8

–

4.7

10

5.6

–

µF

EFC

EXC

Power supply decoupling capacitor

µF X5R ceramic or better

Document Number: 002-28785 Rev. *I

Page 35 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

CPU Current and Transition Times

Table 14. CPU Current and Transition Times

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

LP Range Power Specifications (for V

Cortex-M4. Active Mode

= 1.1 V with Buck and LDO)

CCD

Execute with Cache Disabled (Flash)

V

= 3.3 V, Buck ON, Max

DDD

–

2.3

3.1

5.7

0.9

1.2

2.8

3.2

3.6

6.5

1.5

1.6

3.5

mA

at 60 °C.

Execute from flash; CM4 Active 50 MHz,

CM0+ Sleep 25 MHz. With IMO and FLL.

While(1).

V

= 1.8 V, Buck ON, Max

DDD

SIDF1

SIDF2

I

DD1

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from flash; CM4 Active 8 MHz,

CM0+ Sleep 8 MHz.With IMO. While(1).

I

DD2

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

Execute with Cache Enabled

V

= 3.3 V, Buck ON, Max

DDD

–

6.3

9.7

14.4

4.8

7.4

11.3

2.4

3.7

6.3

0.90

1.3

3

7

mA

at 60 °C.

Execute from cache;CM4 Active 150 MHz,

CM0+ Sleep 75 MHz. IMO and PLL.

Dhrystone.

V

= 1.8 V, Buck ON, Max

DDD

SIDC1

SIDC2

SIDC3

SIDC4

I

11.2

15.1

5.8

8.4

12

DD3

DD4

DD5

DD6

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

Execute from cache;CM4 Active 100 MHz,

CM0+ Sleep 100MHz. IMO and FLL.

Dhrystone.

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

=3.3 V, Buck ON, Max

DDD

3.4

4.1

7.2

1.5

1.8

3.8

at 60 °C.

Execute from cache;CM4 Active 50 MHz,

CM0+ Sleep 25MHz. IMO and FLL.

Dhrystone.

V

= 1.8V, Buck ON, Max

DDD

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from cache;CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. IMO. Dhrystone.

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

Document Number: 002-28785 Rev. *I

Page 36 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 14. CPU Current and Transition Times (continued)

Spec ID# Parameter Description

Min

Typ

Max

Units

Details / Conditions

Cortex-M0+. Active Mode

Execute with Cache Disabled (Flash)

V

= 3.3 V, Buck ON, Max

DDD

–

2.4

3.2

5.6

0.8

1.1

2.6

3.3

3.7

6.3

1.5

1.6

3.4

mA

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from flash;CM4 OFF, CM0+ Active

50 MHz. With IMO and FLL. While (1).

SIDF3

SIDF4

I

DD7

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from flash;CM4 OFF, CM0+ Active

8 MHz. With IMO. While (1).

I

DD8

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

Execute with Cache Enabled

V

= 3.3V, Buck ON, Max

DDD

–

3.8

5.9

9

4.5

6.5

9.7

1.3

1.7

3.4

mA

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from cache;CM4 OFF, CM0+Active

100 MHz. With IMO and FLL. Dhrystone.

SIDC5

SIDC6

I

DD9

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

0.8

1.2

2.6

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from cache;CM4 OFF, CM0+Active

8 MHz. With IMO. Dhrystone.

I

DD10

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

Cortex-M4. Sleep Mode

V

= 3.3 V, Buck ON, Max

DDD

–

1.5

2.2

4

2.2

2.7

4.6

1.9

2.2

4.3

1.3

1.5

3.3

mA

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

CM4 Sleep 100 MHz, CM0+ Sleep 25 MHz.

With IMO and FLL.

SIDS1

SIDS2

SIDS3

I

DD11

DD12

DD13

V

= 1.8 to 3.3 V, LDO,

DDD

max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

1.2

1.7

3.4

0.7

1

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.

With IMO & FLL.

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With

IMO.

V

= 1.8 to 3.3 V, LDO,

DDD

2.4

Max at 85 °C.

Document Number: 002-28785 Rev. *I

Page 37 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 14. CPU Current and Transition Times (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

= 3.3 V, Buck ON, Max

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

Cortex-M0+. Sleep Mode

V

DDD

–

1.3

1.9

3.8

0.7

1

2

mA

CM4 Off, CM0+ Sleep 50 MHz. With IMO

and FLL.

SIDS4

SIDS5

I

2.4

4.6

1.3

1.5

3.3

DD14

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

= 3.3V, Buck ON, Max

DDD

at 60 °C.

V

= 1.8 V, Buck ON, Max

DDD

CM4 Off, CM0+ Sleep 8 MHz. With IMO.

DD15

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

2.4

Max at 85 °C.

Cortex-M4. Minimum Regular Current Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.9

1.2

2.8

0.9

1.3

2.9

1.5

1.7

3.5

1.5

1.8

3.7

mA

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from flash; CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. With IMO. While (1).

SIDLPA1

SIDLPA2

I

DD16

V

= 1.8 to 3.3 V, LDO,

DDD

max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from cache; CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. With IMO. Dhrystone.

DD17

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

Cortex-M0+. Minimum Regulator Current Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.8

1.1

2.7

0.8

1.2

2.7

1.4

1.6

3.6

1.4

1.7

3.6

mA

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from flash; CM4 OFF, CM0+ Active

8 MHz. With IMO. While (1).

SIDLPA3

SIDLPA4

I

DD18

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

V = 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute from cache; CM4 Off, CM0+ Active

8 MHz. With IMO. Dhrystone

DD19

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

Cortex-M4. Minimum Regulator Current Mode

V

=3.3 V, Buck ON, Max

DDD

–

0.7

1

1.1

1.5

3.3

mA

at 60 °C.

V =1.8 V, Buck ON, Max

DDD

at 60 °C.

CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With

IMO.

SIDLPS1

I

DD20

V

= 1.8 to 3.3 V, LDO,

DDD

2.4

Max at 85 °C.

Document Number: 002-28785 Rev. *I

Page 38 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 14. CPU Current and Transition Times (continued)

Spec ID# Parameter Description

Cortex-M0+. Minimum Regulator Current Mode

Min

Typ

Max

Units

Details / Conditions

= 3.3 V, Buck ON, Max

V

DDD

–

0.6

0.9

2.4

1.1

1.5

3.3

mA

at 60 °C.

V

= 1.8 V, Buck ON, Max

DDD

SIDLPS3

I

CM4 Off, CM0+ Sleep 8 MHz. With IMO.

DD22

at 60 °C.

V

= 1.8 to 3.3 V, LDO,

DDD

Max at 85 °C.

ULP RANGE POWER SPECIFICATIONS (for V

Cortex-M4. Active Mode

= 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C.

CCD

Execute with Cache Disabled (Flash)

V

= 3.3 V, Buck ON, Max

DDD

–

1.7

2.1

2.2

2.4

0.8

1

mA

Execute from flash; CM4 Active 50 MHz,

CM0+ Sleep 25 MHz. With IMO and FLL.

While(1).

at 60 °C.

SIDF5

SIDF6

I

DD3

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

0.56

0.75

at 60 °C.

Execute from flash; CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. With IMO. While (1).

I

DD4

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute with Cache Enabled

V

= 3.3 V, Buck ON, Max

DDD

–

1.6

2.4

2.2

2.7

0.8

1.1

mA

Execute from cache; CM4 Active 50 MHz,

CM0+ Sleep 25 MHz. With IMO and FLL.

Dhrystone.

at 60 °C.

SIDC8

SIDC9

I

DD10

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

0.65

0.8

at 60 °C.

Execute from cache; CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. With IMO. Dhrystone.

I

DD11

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Cortex-M0+. Active Mode

Execute with Cache Disabled (Flash)

V

= 3.3 V, Buck ON, Max

DDD

–

1

1.4

1.6

0.75

1

mA

at 60 °C.

Execute from flash; CM4 OFF, CM0+ Active

25 MHz. With IMO and FLL. Write(1).

SIDF7

SIDF8

I

DD16

V

= 1.8 V, Buck ON, Max

DDD

1.34

0.54

0.73

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

Execute from flash; CM4 OFF, CM0+ Active

8 MHz. With IMO. While(1).

I

DD17

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Execute with Cache Enabled

V

= 3.3 V, Buck ON, Max

DDD

–

0.91

1.34

0.51

0.73

1.25

1.6

mA

at 60 °C.

Executefromcache;CM4OFF, CM0+Active

25 MHz. With IMO and FLL. Dhrystone.

SIDC10

SIDC11

I

DD18

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

0.72

0.95

at 60 °C.

Executefromcache;CM4OFF, CM0+Active

8 MHz. With IMO. Dhrystone.

I

DD19

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Cortex-M4. Sleep Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.76

1.1

1.4

mA

at 60 °C.

CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.

With IMO and FLL.

SIDS7

I

DD21

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Document Number: 002-28785 Rev. *I

Page 39 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 14. CPU Current and Transition Times (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

= 3.3 V, Buck ON, Max

at 60 °C.

V

DDD

–

0.42

0.65

mA

CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With

IMO.

SIDS8

I

DD22

V

= 1.8 V, Buck ON, Max

DDD

–

0.59

0.8

mA

at 60 °C.

Cortex-M0+. Sleep Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.62

0.88

0.41

0.58

0.9

1.1

0.6

0.8

mA

at 60 °C.

CM4 Off, CM0+ Sleep 25 MHz. With IMO

and FLL.

SIDS9

I

DD23

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

at 60 °C.

SIDS10

I

CM4 Off, CM0+ Sleep 8 MHz. With IMO.

DD24

V

= 1.8°V, Buck ON,

DDD

Max at 60 °C.

Cortex-M4. Minimum Regulator Current Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.52

0.76

0.54

0.78

0.75

1

mA

at 60 °C.

Execute from flash. CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. With IMO. While(1).

SIDLPA5

SIDLPA6

I

DD25

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

0.76

1

at 60 °C.

Execute from cache. CM4 Active 8 MHz,

CM0+ Sleep 8 MHz. With IMO. Dhrystone.

DD26

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Cortex-M0+. Minimum Regulator Current Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.51

0.75

0.48

0.7

0.75

1

mA

at 60 °C.

Execute from flash. CM4 OFF, CM0+ Active

8 Hz. With IMO. While (1).

SIDLPA7

SIDLPA8

I

DD27

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

V

= 3.3 V, Buck ON, Max

DDD

0.7

0.95

at 60 °C.

Executefromcache. CM4OFF, CM0+Active

8 MHz. With IMO. Dhrystone.

DD28

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Cortex-M4. Minimum Regulator Current Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.4

0.6

0.8

mA

at 60 °C.

CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz. With

IMO.

SIDLPS5

I

DD29

V

= 1.8 V, Buck ON, Max

DDD

0.57

at 60 °C.

Cortex-M0+. Minimum Regulator Current Mode

V

= 3.3 V, Buck ON, Max

DDD

–

0.39

0.56

0.6

0.8

mA

at 60 °C.

SIDLPS7

I

CM4 Off, CM0+ Sleep 8 MHz. With IMO.

DD31

V

= 1.8 V, Buck ON, Max

DDD

at 60 °C.

Deep Sleep Mode

SIDDS2

With internal Buck enabled and 128-KB

SRAM retention

I

–

8

–

µA

DD33B

Document Number: 002-28785 Rev. *I

Page 40 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 14. CPU Current and Transition Times (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

Hibernate Mode

SIDHIB1

SIDHIB2

I

V

= 1.8 V

= 3.3 V

–

300

800

–

nA No clocks running

DD34

DD34A

DDD

nA No clocks running

Power Mode Transition Times

Minimum regulator current to LP transition

time

SID12

T

–

35

µs Including PLL lock time

LPACT_ACT

SID13

SID14

T

Deep Sleep to LP transition time

Hibernate to LP transition time

–

15

–

µs Guaranteed by design

µs Including PLL lock time

DS_LPACT

HIB_ACT

2000

XRES

Table 15. XRES DC Specifications

Spec ID#

SID17

Parameter

Description

when XRES asserted

Min

Typ

Max

Units

Details / Conditions

T

I

–

300

800

–

nA

V

= 1.8 V

DDD

XRES_IDD

DD

SID17A

SID77

–

V

= 3.3 V

DDD

XRES_IDD_1

V

Input voltage HIGH threshold

Input voltage LOW threshold

Input capacitance

0.7 * V_DD

–

CMOS input

IH

IL

SID78

–

0.3 * V_DD

V

CMOS input

SID80

C

V

3

–

pF

mV

µA

–

IN

SID81

Input voltage hysteresis

100

–

HYSXRES

DIODE

Current through protection diode to

100

SID82

I

–

V

/V

DD SS

Table 16. XRES AC Specifications

Spec ID#

SID15

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

POR or XRES release to Active

transition time

Normal mode, 50-MHz

CM0+

–

2000

–

µs

T

XRES_ACT

XRES_PW

SID16

XRES pulse width

5

–

µs

–

GPIO

Table 17. GPIO DC Specifications

Spec ID# Parameter

SID57

Description

Input voltage HIGH threshold

Input current when Pad > V

Min

Typ

Max

Units Details / Conditions

V

0.7 * V_DD

–

V

CMOS Input

IH

for

–

10

µA

2

DDIO

SID57A

I

Per I C Spec

IHS

OVT inputs

SID58

V

Input voltage LOW threshold

–

0.3 * V_DD

V

CMOS Input

IL

SID241

SID242

SID243

SID244

SID59

LVTTL input, V < 2.7 V

0.7 * V_DD

–

0.3 * V_DD

–

IH

IL

DD

LVTTL input, V < 2.7 V

–

V

DD

LVTTL input, V ≥ 2.7 V

2.0

–

V

IH

IL

DD

LVTTL input, V ≥ 2.7 V

–

V_DD– 0.5

–

0.8

V

DD

Output voltage HIGH level

Output voltage LOW level

Pull-up resistor

–

V

I

= 8 mA

OH

OL

OH

OL

SID62A

SID63

–

0.4

V

R

3.5

5.6

8.5

kΩ

–

PULLUP

SID64

Pull-down resistor

3.5

8.5

PULLDOWN

Document Number: 002-28785 Rev. *I

Page 41 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 17. GPIO DC Specifications (continued)

Spec ID#

SID65

Parameter

Description

Input leakage current (absolute value)

Input capacitance

Min

Typ

–

Max

2

Units Details / Conditions

I

–

nA 25 °C, V = 3.0 V

IL

DD

SID66

SID67

SID68

C

V

–

100

–

5

pF

mV

µA

–

IN

Input hysteresis LVTTL V > 2.7 V

0

–

HYSTTL

DD

V

Input hysteresis CMOS

0.05 * V_DD

–

HYSCMOS

Current through protection diode to

–

100

SID69

I

–

DIODE

V

/V

DD SS

Maximum total source or sink chip

current

–

200

mA

SID69A

I

TOT_GPIO

Table 18. GPIO AC Specifications

Spec ID#

SID70

Parameter

Description

Min

Typ

Max

Units Details / Conditions

Rise time in Fast Strong Mode. 10% to

Cload = 15 pF, 8-mA

drive strength

–

2.5

ns

T

RISEF

90% of V

.

DD

Fall time in Fast Strong Mode. 10% to

90% of V

Cload = 15 pF, 8-mA

drive strength

–

2.5

SID71

SID72

FALLF

.

DD

Cload = 15 pF, 8-mA

52

142

Rise time in Slow Strong Mode. 10% to

90% of V

T

drive strength, V



RISES_1

DD

.

DD

2.7 V

Cload = 15 pF, 8-mA

drive strength, 2.7 V <

48

–

102

ns

Rise time in Slow Strong Mode. 10% to

90% of V

SID72A

SID73

T

RISES_2

FALLS_1

FALLS_2

.

DD

V

 3.6 V

DD

Fall time in Slow Strong Mode. 10% to

90% of V

Cload= 15 pF, 8 mAdrive

44

42

–

211

93

ns

.

strength, V 2.7 V

DD

Cload = 15 pF, 8-mA

drive strength, 2.7 V <

Fall time in Slow Strong Mode. 10% to

90% of V

SID73A

.

DD

V

 3.6 V

DD

Fall time (30% to 70% of V ) in Slow

Strong mode.

Cload = 10 pF to 400 pF,

8-mA drive strength

20 * V_DDIO

5.5

/

–

250

100

1.5

ns

DD

SID73G

SID74

T

F

FALL_I2C

GPIOUT1

GPIOUT2

GPIOUT3

GPIOUT4

GPIOIN

90/10%, 15-pF load,

60/40 duty cycle

–

MHz

GPIO Fout. Fast Strong mode.

90/10%, 15-pF load,

60/40 duty cycle

SID75

GPIO Fout; Slow Strong mode.

GPIO Fout; Fast Strong mode.

90/10%, 25-pF load,

60/40 duty cycle

100

1.3

SID76

90/10%, 25-pF load,

60/40 duty cycle

SID245

SID246

GPIO Fout; Slow Strong mode.

GPIO input operating frequency;

100

90/10% V

IO

1.71 V  V 3.6 V

DD

Document Number: 002-28785 Rev. *I

Page 42 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Analog Peripherals

Low-Power (LP) Comparator

Table 19. LP Comparator DC Specifications

Spec ID#

SID84

Parameter

Description

Min

–10

–25

Typ

–

Max

10

Units Details/Conditions

Input offset voltage. Normal power

mode.

V

mV

–

OFFSET1

OFFSET2

OFFSET3

SID85A

SID85B

Input offset voltage. Low-power mode.

±12

25

Input offset voltage. Ultra low-power

mode.

25

Hysteresis when enabled in Normal

mode

SID86

V

–

60

80

mV

V

–

HYST1

HYST2

ICM1

HysteresiswhenenabledinLow-power

mode

SID86A

SID87

Input common mode voltage in Normal

mode

0

V_DDIO1– 0.1

–

Input common mode voltage in Low

power mode

SID247

SID247A

SID88

0

V

ICM2

Input common mode voltage in Ultra

low power mode

0

V

ICM3

Common mode rejection ratio in

Normal power mode

CMRR

50

dB

SID89

SID248

SID259

SID90

I

Block current, Normal mode

–

150

10

µA

MΩ

–

CMP1

I

Block current, Low-power mode

Block current in Ultra low-power mode

DC input impedance of comparator

CMP2

I

–

0.3

–

0.85

–

CMP3

ZCMP

35

Table 20. LP Comparator AC Specifications

Spec ID# Parameter Description

LP Comparator AC Specifications

Min

Typ

Max

Units Details/Conditions

Response time, Normal mode, 100 mV

overdrive

SID91

SID258

SID92

T

–

100

1000

20

ns

µs

–

RESP1

RESP2

RESP3

Response time, Low power mode, 100

mV overdrive

Response time, Ultra-low power mode,

100 mV overdrive

Normal and low-power

modes

SID92E

SID92F

T_CMP_EN1

T_CMP_EN2

Time from Enabling to operation

–

10

50

µs Ultra-low-power mode

Document Number: 002-28785 Rev. *I

Page 43 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Temperature Sensor

Table 21. Temperature Sensor Specifications

Spec ID

SID93

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

T

Temperature sensor accuracy

–5

±1

5

°C –40 to +85 °C

SENSACC

Internal Reference

Table 22. Internal Reference Specification

Spec ID

SID93R

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

V

–

1.188

1.2

1.212

V

–

REFBG

SAR ADC

Table 23. 12-bit SAR ADC DC Specifications

Spec ID

SID94

Parameter

Description

SAR ADC Resolution

Min

–

Typ

–

Max Units

Details/Conditions

A_RES

12

16

8

bits

SID95

SID96

SID97

SID98

SID99

A_CHNLS_S Number of channels - single-ended

A-CHNKS_D Number of channels - differential

–

8 full speed.

–

Diff inputs use neighboring I/O

Yes.

A-MONO

Monotonicity

–

-

A_GAINERR Gain error

–

±0.2

2

%

With external reference.

A_OFFSET

A_ISAR_1

Input offset voltage

–

mV Measured with 1-V reference

At 1 Msps. External reference

mode

1.05

mA

SID100

Current consumption at 1 Msps

Current consumption at 2 Msps

–

At 1 Msps. Internal reference

mode

1.3

SID100A

SID1002

SID1003

A_ISAR_2

A_ISAR_3

A_ISAR_4

At 2 Msps. External reference

mode

1.65

2.15

At 2 Msps. Internal reference

mode

SID101

SID102

SID103

SID104

A_VINS

Input voltage range - single-ended

Input voltage range - differential

Input resistance

V_SS

–

1

5

V_DDA

–

V

A_VIND

A_INRES

A_INCAP

kΩ

pF

Input capacitance

–

Table 24. 12-bit SAR ADC AC Specifications

Spec ID

SID106

SID107

Parameter

A_PSRR

Description

Min

70

Typ

–

Max Units

Details/Conditions

Power supply rejection ratio

–

dB

dB Measured at 1 V

A_CMRR

Common mode rejection ratio

Sample rate with external reference

With bypass cap

66

–

SID1081 A_SAMP_1

SID1082 A_SAMP_1

SID108A1 A_SAMP_2

SID108A2 A_SAMP_2

SID108B A_SAMP_3

–

2

1

2

1

Msps

V

-

2.7 - 3.6

1.7 - 3.6

2.7 - 3.6

1.7 - 3.6

DDA

Sample rate with external reference

With bypass cap

Sample rate with V reference;

DD

No bypass cap

Sample rate with V reference;

DD

No bypass cap

Sample rate with internal reference;

With bypass cap

Document Number: 002-28785 Rev. *I

Page 44 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 24. 12-bit SAR ADC AC Specifications (continued)

Spec ID

SID108C A_SAMP_4

SID109 A_SINAD

Parameter

Description

Sample rate with Internal Reference.

No bypass cap

Min

Typ

Max Units

Details/Conditions

–

200

–

ksps

-

Signal-to-noise and distortion ratio

(SINAD).

64

–2

–

dB Fin = 10 kHz

Integral non-linearity.

Up to 1 Msps

SID111A A_INL

SID111B A_INL

SID112A A_DNL

SID112B A_DNL

2

LSB All Reference Mode

External Reference or V

DDA

Integral non-linearity.

2 Msps.

–2.5

–1

–

2.5

1.5

LSB Reference Mode, V

≥ 2 V.

REF

V

= 2.7 V to 3.6 V

DDA

Differential non-linearity.

Up to 1Msps

LSB All Reference Modes

External Reference or V

DDA

Differential non-linearity.

2Msps.

–1

–

1.6

LSB Reference Mode, V

≥ 2V.

REF

V

= 2.7 to 3.6 V

DDA

SID113

A_THD

Total harmonic distortion. 1 Msps.

–65

dB Fin = 10 kHz. V

= 2.7 to 3.6 V.

DDA

CSD

Table 25. CapSense Sigma-Delta (CSD) Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

CSD V2 Specifications

V

> 2 V (with ripple),

DDA

Max allowed ripple on power supply,

DC to 10 MHz

25 °C T ,

SYS.PER#3

V

–

±50

mV

A

DD_RIPPLE

Sensitivity = 0.1 pF

V

> 1.75 V (with ripple),

DDA

25 ° C T ,

Max allowed ripple on power supply,

DC to 10 MHz

A

SYS.PER#16

V

I

±25

mV

DD_RIPPLE_1.8

Parasitic Capacitance (C ) <

P

20 pF, Sensitivity ≥ 0.4 pF

SID.CSD.BLK

SID.CSD#15

Maximum block current

–

4500

µA

V

–

CSD

Voltage reference for CSD and

Comparator

V_DDA

0.6

–

V

0.6

1.2

V

– V

≥ 0.6 V

REF

DDA

REF

External Voltage reference for CSD

and Comparator

V_DDA

0.6

–

SID.CSD#15A

V

I

0.6

–

V

REF_EXT

SID.CSD#16

SID.CSD#17

SID308

IDAC1 (7-bits) block current

IDAC2 (7-bits) block current

Voltage range of operation

–

1900

3.6

µA

V

–

DAC1IDD

DAC2IDD

I

V

I

1.7

1.71 to 3.6 V

CSD

V_DDA

0.6

–

SID308A

SID309

SID310

SID311

SID312

Voltage compliance range of IDAC

0.6

–1

–3

–1

–3

–

V

–

– V ≥ 0.6 V

REF

COMPIDAC

DDA

DNL

INL

1

3

1

3

LSB

DAC1DNL

DAC1INL

DAC2DNL

DAC2INL

If V

< 2 V then for LSB of

DDA

I

2.4 µA or less

DNL

INL

–

If V

< 2 V then for LSB of

DDA

2.4 µA or less

SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization.

SRSS reference. IMO + FLL clock

SID313_1A

SNRC_1

5

–

Ratio 9.5-pF max. capacitance

source. 0.1-pF sensitivity.

Document Number: 002-28785 Rev. *I

Page 45 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)

Spec ID#

Parameter

SNRC_2

Description

Min

Typ

Max

Units

Details / Conditions

SRSS reference. IMO + FLL clock

source. 0.3-pF sensitivity.

SID313_1B

5

–

Ratio 31-pF max. capacitance

Ratio 61-pF max. capacitance

Ratio 12-pF max. capacitance

Ratio 47-pF max. capacitance

Ratio 86-pF max. capacitance

Ratio 27-pF max. capacitance

Ratio 86-pF max. capacitance

Ratio 168 pF Max. capacitance

SRSS reference. IMO + FLL clock

source. 0.6-pF sensitivity.

SID313_1C

SID313_2A

SID313_2B

SID313_2C

SID313_3A

SID313_3B

SID313_3C

SID314

SNRC_3

SNRC_4

SNRC_5

SNRC_6

SNRC_7

SNRC_8

SNRC_9

IDAC

5

–

PASS reference. IMO + FLL clock

source. 0.1-pF sensitivity.

PASS reference. IMO + FLL clock

source. 0.3-pF sensitivity.

5

–

PASS reference. IMO + FLL clock

source. 0.6-pF sensitivity.

5

–

PASS reference. IMO + PLL clock

source. 0.1-pF sensitivity.

5

–

PASS reference. IMO + PLL clock

source. 0.3-pF sensitivity.

5

–

PASS reference. IMO + PLL clock

source. 0.6-pf sensitivity.

5

–

Output current of IDAC1 (7 bits) in

low range

4.2

33.7

270

8

5.7

45.6

365

11.4

91

µA

LSB

LSB = 37.5-nA typ.

LSB = 300-nA typ.

LSB = 2.4-µA typ.

1CRT1

Output current of IDAC1 (7 bits) in

medium range

SID314A

SID314B

SID314C

SID314D

SID314E

SID315

IDAC

1CRT2

Output current of IDAC1 (7 bits) in

high range

1CRT3

Output current of IDAC1 (7 bits) in

low range, 2X mode

LSB = 37.5-nAtyp. 2X output

stage

1CRT12

1CRT22

1CRT32

2CRT1

Output current of IDAC1 (7 bits) in

medium range, 2X mode

LSB = 300-nA typ. 2X output

stage

67

540

4.2

33.7

270

8

Output current of IDAC1 (7 bits) in

LSB = 2.4-µA typ. 2X output

stage

730

5.7

45.6

365

11.4

91

high range, 2X mode. V

> 2 V

DDA

Output current of IDAC2 (7 bits) in

low range

LSB = 37.5-nA typ.

LSB = 300-nA typ.

LSB = 2.4-µA typ.

Output current of IDAC2 (7 bits) in

medium range

SID315A

SID315B

SID315C

SID315D

SID315E

SID315F

SID315G

SID315H

SID320

2CRT2

Output current of IDAC2 (7 bits) in

high range

2CRT3

Output current of IDAC2 (7 bits) in

low range, 2X mode

LSB = 37.5-nAtyp. 2X output

stage

2CRT12

2CRT22

2CRT32

3CRT13

3CRT23

3CRT33

OFFSET

Output current of IDAC2 (7 bits) in

medium range, 2X mode

LSB = 300-nA typ. 2X output

stage

67

540

8

Output current of IDAC2 (7 bits) in

LSB = 2.4-µA typ. 2X output

stage

730

11.4

91

high range, 2X mode. V

> 2V

DDA

Output current of IDAC in 8-bit mode

in low range

LSB = 37.5-nA typ.

LSB = 300-nA typ.

LSB = 2.4-µA typ.

Output current of IDAC in 8-bit mode

in medium range

67

540

–

Output current of IDAC in 8-bit mode

730

1

in high range. V

> 2V

DDA

Polarity set by Source or

Sink

All zeroes input

–

Document Number: 002-28785 Rev. *I

Page 46 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)

Spec ID#

SID321

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

IDAC

Full-scale error less offset

–

±15

%

LSB = 2.4-µA typ.

GAIN

Mismatch between IDAC1 and

IDAC2 in Low mode

SID322

IDAC

–

9.2

6

LSB LSB = 37.5-nA typ.

LSB LSB = 300-nA typ.

LSB LSB = 2.4-µA typ.

MISMATCH1

Mismatch between IDAC1 and

IDAC2 in Medium mode

SID322A

SID322B

SID323

MISMATCH2

MISMATCH3

SET8

Mismatch between IDAC1 and

IDAC2 in High mode

5.8

10

Settling time to 0.5 LSB for 8-bit

IDAC

Full-scale transition. No

external load.

µs

Settling time to 0.5 LSB for 7-bit

IDAC

Full-scale transition. No

external load.

SID324

SID325

–

10

–

µs

SET7

CMOD

External modulator capacitor.

2.2

nF

5-V rating, X7R or NP0 cap.

Table 26. CSD ADC Specifications

Spec ID# Parameter

CSDv2 ADC Specifications

Description

Min Typ Max Units

Details / Conditions

Auto-zeroing is required every milli-

second

–

10

bits

SIDA94

A_RES

Resolution

SID95

A_CHNLS_S

A-MONO

Number of channels - single ended

Monotonicity

–

Yes

–

16

–

SIDA97

V

mode

REF

Reference Source: SRSS

0.6

%

(V

= 1.20 V, V

= 1.6 V, 2.2 V < V

< 2.2 V),

DDA

REF

SIDA98

A_GAINERR_VREF Gain error

<

REF

DDA

2.7 V), (V

2.7 V)

= 2.13 V, V

>

REF

DDA

Reference Source: SRSS

–

0.2

0.5

–

%

(V

=1.20 V, V

=1.6 V,

< 2.2V),

DDA

REF

SIDA98A A_GAINERR_VDDA Gain error

REF

2.2 V < V

< 2.7 V),

DDA

(V

= 2.13 V, V

> 2.7 V)

REF

DDA

After ADC calibration, Ref. Src =

LSB

SRSS, (V

2.2 V),

= 1.20 V, V

<

REF

DDA

SIDA99

A_OFFSET_VREF

Input offset voltage

(V

= 1.6 V, 2.2 V < V

<

DDA

REF

2.7 V),

(V = 2.13 V, V

> 2.7 V)

DDA

REF

After ADC calibration, Ref. Src =

SRSS, (V

2.2 V),

–

0.5

–

LSB

= 1.20 V, V

<

REF

DDA

SIDA99A A_OFFSET_VDDA

(V

= 1.6 V, 2.2 V < V

<

DDA

REF

2.7 V),

(V = 2.13 V, V

> 2.7 V)

DDA

REF

SIDA100 A_ISAR_VREF

SIDA100A A_ISAR_VDDA

Current consumption

–

0.3

–

mA CSD ADC Block current

Document Number: 002-28785 Rev. *I

Page 47 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 26. CSD ADC Specifications (continued)

Spec ID#

Parameter

Description

Min Typ Max Units

Details / Conditions

= 1.20 V, V < 2.2 V),

(V

V_SSA

–

V_REF

V

REF

DDA

= 1.6 V, 2.2 V < V

<

REF

DDA

SIDA101 A_VINS_VREF

SIDA101A A_VINS_VDDA

Input voltage range - single ended

2.7 V),

(V

= 2.13 V, V

> 2.7 V)

< 2.2 V),

REF

DDA

(V

= 1.20 V, V

V_SSA

–

V_DDA

V

REF

= 1.6 V, 2.2 V < V

<

DDA

RE F

Input voltage range - single ended

2.7 V),

(V

= 2.13 V, V

> 2.7 V)

DDA

REF

SIDA103 A_INRES

SIDA104 A_INCAP

SIDA106 A_PSRR

Input charging resistance

Input capacitance

–

15

41

60

10

–

kΩ

pF

dB

µs

–

Power supply rejection ratio (DC)

–

Measured with 50-Ω source

impedance. 10 µs is default

software driver acquisition time

setting. Settling to within 0.05%.

SIDA107 A_TACQ

Sample acquisition time

Conversion time for 8-bit resolution at

conversion rate = Fhclk / (2"(N + 2)).

Clock frequency = 50 MHz.

–

25

60

–

µs

SIDA108 A_CONV8

SIDA108A A_CONV10

Does not include acquisition time.

Conversion time for 10-bit resolution at

conversion rate = Fhclk / (2"(N + 2)).

Clock frequency = 50 MHz.

Signal-to-noise and distortion ratio

(SINAD)

Measured with 50-Ω source

impedance

–

57

52

–

2

1

dB

SIDA109 A_SND_VRE

SIDA109A A_SND_VDDA

Signal-to-noise and distortion ratio

(SINAD)

Measured with 50-Ω source

impedance

dB

Measured with 50-Ω source

impedance

LSB

SIDA111

SIDA111A A_INL_VDDA

SIDA112 A_DNL_VREF

SIDA112A A_DNL_VDDA

A_INL_VREF

Integral non-linearity. 11.6 ksps

Differential non-linearity. 11.6 ksps

Measured with 50-Ω source

impedance

–

Measured with 50-Ω source

impedance

–

Measured with 50-Ω source

impedance

–

Document Number: 002-28785 Rev. *I

Page 48 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Digital Peripherals

Timer/Counter/PWM

Table 27. Timer/Counter/PWM (TCPWM) Specifications

Spec ID#

SID.TCPWM.1

SID.TCPWM.2

SID.TCPWM.2A

Parameter

Description

Min Typ Max Units

Details/Conditions

I

Block current consumption at 8 MHz

Block current consumption at 24 MHz

Block current consumption at 50 MHz

–

70

µA All modes (TCPWM)

TCPWM1

TCPWM2

TCPWM3

180

270

SID.TCPWM.2B

SID.TCPWM.3

I

Block current consumption at 100 MHz

Operating frequency

–

540

µA All modes (TCPWM)

TCPWM4

TCPWM

100 MHz Maximum = 100 MHz

FREQ

Trigger events can be Stop,

Start, Reload, Count, Capture,

or Kill depending on which

mode of operation is selected.

Fc is counter operating

frequency.

Input trigger pulse width for all trigger

events

SID.TCPWM.4

SID.TCPWM.5

TPWM

2/Fc

–

ns

ENEXT

Minimum possible width of

Overflow, Underflow, and CC

(Counter equals Compare

value) trigger outputs

TPWM

Output trigger pulse widths

1.5/Fc

EXT

Minimum time between

successive counts

SID.TCPWM.5A TC

Resolution of counter

PWM resolution

1/Fc

–

ns

RES

Minimum pulse width of PWM

output

SID.TCPWM.5B PWM

RES

Minimum pulse width between

Quadrature phase inputs.

Delays from pins should be

similar.

SID.TCPWM.5C

Q

Quadrature inputs resolution

2/Fc

–

ns

RES

Serial Communication Block (SCB)

Table 28. Serial Communication Block (SCB) Specifications

Spec ID#

Parameter

Description

Min Typ Max Units

Details / Conditions

2

Fixed I C DC Specifications

SID149

SID150

SID151

SID152

I

Block current consumption at 100 kHz

Block current consumption at 400 kHz

Block current consumption at 1 Mbps

–

30

80

µA

–

I2C1

I2C2

I2C3

I2C4

180

1.7

2

I C enabled in Deep Sleep mode

µA At 60°C.

2

Fixed I C AC Specifications

SID153

Fixed UART DC Specifications

F

Bit Rate

–

1

Mbps –

I2C1

SID160

SID161

I

Block current consumption at 100 kbps

Block current consumption at 1000 kbps

–

30

µA

–

UART1

UART2

180

Fixed UART AC Specifications

SID162A

SID162B

F

–

3

8

Mbps ULP Mode

LP Mode

UART1

UART2

Bit Rate

Fixed SPI DC Specifications

SID163

I

Block current consumption at 1 Mbps

–

220

µA

–

SPI1

Document Number: 002-28785 Rev. *I

Page 49 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 28. Serial Communication Block (SCB) Specifications (continued)

Spec ID#

SID164

Parameter

Description

Min Typ Max Units

Details / Conditions

I

Block current consumption at 4 Mbps

Block current consumption at 8 Mbps

Block current consumption at 25 Mbps

–

340

360

800

µA

–

SPI2

SID165

SPI3

SID165A

SP14

Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.

SPIOperatingfrequencyexternallyclocked

slave

12-MHz max for ULP (0.9 V)

mode

–

25

MHz

SID166

F

SPI

F

max is 100 MHz in LP

F_scb/4 MHz

scb

SPI operating frequency master (F

SPI clock).

is

scb

SID166B

(1.1 V) mode, 25 MHz in ULP

mode.

SPI_EXT

5 MHz max for ULP (0.9 V)

mode

–

15

MHz

SID166A

SPI slave internally clocked

SPI_IC

Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.

20 ns max for ULP (0.9 V)

mode

–

5

0

–

12

–

ns

SID167

SID168

SID169

T

MOSI valid after SClock driving edge

MISO valid before SClock capturing edge

MOSI data hold time

DMO

Full clock, late MISO

sampling

DSI

Referred to Slave capturing

edge

–

HMO

Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.

SID170

T

MOSI valid before Sclock capturing edge

5

–

ns

–

DMI

MISO valid after Sclock driving edge in Ext.

Clk. mode

35 ns max. for ULP (0.9 V)

mode

20

SID171A

T

DSO_EXT

–

T_{DSO_}ns

_EXT+3

* Tscb

MISO valid after Sclock driving edge in

Internally Clk. mode

Tscb is Serial Comm. Block

clock period.

SID171

T

DSO

T_{DSO_}ns

MISO Valid after Sclock driving edge in

Internally Clk. Mode with median filter

enabled.

+

Tscb is Serial Comm. Block

clock period.

EXT

SID171B

T

DSO

4 *

Tscb

SID172

Previous MISO data hold time

5

–

ns

–

HSO

SID172A

SID172B

TSSEL

SSEL Valid to first SCK valid edge

SSEL Hold after Last SCK valid edge

65

SCK1

SCK2

Document Number: 002-28785 Rev. *I

Page 50 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

LCD Specifications

Table 29. LCD Direct Drive DC Specifications

Spec ID#

Parameter

Description

Min

Typ Max Units

Details / Conditions

32×4 small display. 30-Hz.

µA PWM mode. Slow slew rate.

Operating current with 100-kHz LCD

block clock in ULP mode in Deep Sleep

SID154

I

–

90

50

–

LCDLOW1

460-k series resistors

32×4 small display. 30-Hz.

µA PWM mode. Slow slew rate.

460-k series resistors

Operating current with 32- kHz LCD block

clock in ULP mode in Deep Sleep

SID154A

–

LCDLOW2

LCD capacitance per segment/common

driver

SID155

SID156

SID157

C

–

500 5000 pF

–

LCDCAP

LCD

I

Long-term segment offset

20

–

mV

mA

OFFSET

PWM Mode current.

32 × 4 segments

50 Hz

0.6

LCDOP1

LCDOP2

3.3 V bias. 8 MHz IMO. 25 °C.

PWM Mode current.

32 × 4 segments

50 Hz

SID158

I

–

0.5

–

mA

3.3 V bias. 8 MHz IMO. 25 °C.

Table 30. LCD Direct Drive AC Specifications

Spec ID Parameter Description

SID159 LCD frame rate

Min

Typ Max Units

50 150 Hz

–

Details/Conditions

F

10

LCD

Document Number: 002-28785 Rev. *I

Page 51 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Memory

Table 31. Flash Specifications^[6]

Spec ID

Flash DC Specifications

SID173A IPE

Flash AC Specifications

Parameter

Description

Min Typ Max

Units

Details/Conditions

Erase and Program current

–

6

mA

SID174

SID175

SID176

SID178

SID179

SID178S

T

Row write time (erase and program)

Row erase time

–

16

11

5

ms

Row = 512 bytes

ROWWRITE

ROWERASE

ROWPROGRAM

BULKERASE

SECTORERASE

SSERIAE

–

Row program time after erase

Bulk erase time (512 KB)

Sector erase time (256 KB)

Subsector erase time

–

11

–

512 rows per sector

8 rows per subsector

Subsector write time; 1 erase plus 8

program times

SID179S

SID180S

T

–

51

ms

–

SSWRITE

SWRITE

Sector write time; 1 erase plus 512 program

times

2.6 seconds –

7.5 seconds –

SID180

SID181

T

F

Total device write time

Flash endurance

–

DEVPROG

END

100K

–

cycles

–

Flash retention. Ta  25 °C, 100K P/E

cycles

SID182

F

10

–

years

–

RET1

SID182A

SID182B

SID256

F

T

Flash retention. Ta  85 °C, 10K P/E cycles 10

Flash retention. Ta 55 °C, 20K P/E cycles 20

–

years

–

RET2

RET3

WS100

WS50

Number of Wait states at 100 MHz

Number of Wait states at 50 MHz

3

2

SID257

Note

4. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

Document Number: 002-28785 Rev. *I

Page 52 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

System Resources

Table 32. System Resources

Spec ID

Parameter

Description

Min Typ Max Units

Details/Conditions

Power-On-Reset with Brown-out DC Specifications

Precise POR (PPOR)

BOD trip voltage in Active and Sleep

modes. V

BOD reset guaranteed for levels

below 1.54 V

SID190

SID192

SID192A

V

1.54

–

V

FALLPPOR

FALLDPSLP

DDRAMP

.

DDD

BOD trip voltage in Deep Sleep. V

.

–

DDD

Maximum power supply ramp rate (any

supply)

100 mV/µs Active mode

POR with Brown-out AC Specification

Maximum power supply ramp rate (any

supply) in Deep Sleep

SID194A

V

–

10

mV/µs BOD operation guaranteed

DDRAMP_DS

Voltage Monitors DC Specifications

SID195

SID196

SID197

SID198

SID199

SID200

SID201

SID202

SID203

SID204

SID205

SID206

SID207

SID208

SID209

SID211

V

–

1.38 1.43 1.47

1.57 1.63 1.68

1.76 1.83 1.89

1.95 2.03 2.1

2.05 2.13 2.2

2.15 2.23 2.3

2.24 2.33 2.41

2.34 2.43 2.51

2.44 2.53 2.61

2.53 2.63 2.72

2.63 2.73 2.82

2.73 2.83 2.92

2.82 2.93 3.03

2.92 3.03 3.13

3.02 3.13 3.23

V

µA

–

HVDI1

HVDI2

HVDI3

HVDI4

HVDI5

HVDI6

HVDI7

HVDI8

HVDI9

HVDI10

HVDI11

HVDI12

HVDI13

HVDI14

HVDI15

–

LVI_IDD

Block current

–

5

15

Voltage Monitors AC Specification

SID212 Voltage monitor trip time

T

–

170

ns

–

MONTRIP

Document Number: 002-28785 Rev. *I

Page 53 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

SWD Interface

Table 33. SWD and Trace Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units Details / Conditions

SWD and Trace Interface

LP Mode.

MHz

SID214

F_SWDCLK2

F_SWDCLK2L

1.7 V  V

1.7 V V

 3.6 V

–

25

12

DDD

V

= 1.1 V.

CCD

ULP Mode.

SID214L

 3.6 V

MHz

DDD

V

–

= 0.9 V.

CCD

SID215

SID216

SID217

SID217A

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

0.25 * T

–

ns

0.25 * T

–

0.5 * T

–

1

With Trace Data setup/hold times of

2/1 ns respectively

SID214T

SID215T

SID216T

F_TRCLK_LP1

F_TRCLK_LP2

F_TRCLK_ULP

–

50

20

MHz LP Mode. V = 1.1 V.

DD

With Trace Data setup/hold times of

3/2 ns respectively

MHz LP Mode. V = 1.1 V.

DD

With Trace Data setup/hold times of

3/2 ns respectively

MHz ULP Mode. V = 0.9 V.

DD

Internal Main Oscillator

Table 34. IMO DC Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

–

9

15

µA

SID218

I

IMO operating current at 8 MHz

–

IMO1

Table 35. IMO AC Specifications

Spec ID

SID223

Parameter

Description

Min

–

Typ

–

Max

±2

–

Units

%

Details/Conditions

Frequency variation centered on

8 MHz

F

T

–

IMOTOL1

JITR

SID227

Cycle-to-Cycle and Period jitter

–

250

ps

Internal Low-Speed Oscillator

Table 36. ILO DC Specification

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID231

I

ILO operating current at 32 kHz

–

0.3

0.7

µA

–

ILO2

Table 37. ILO AC Specifications

Spec ID

Parameter

Description

ILO startup time

Min

Typ

Max

Units

Details/Conditions

Startup time to 95% of

final frequency

SID234

T

–

7

µs

STARTILO1

SID236

SID237

TLIODUTY

ILO Duty cycle

45

50

32

55

%

–

F

32 kHz trimmed frequency

28.8

35.2

kHz

10% variation

ILOTRIM1

Document Number: 002-28785 Rev. *I

Page 54 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Crystal Oscillator Specifications

Table 38. ECO Specifications

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

MHz ECO DC Specification

Max = 35 MHz,

Typ = 16 MHz

Block operating current with Cload up to

18 pF

SID316

MHz ECO AC Specification

SID317 F_MHz

I

–

800

1600

µA

DD_MHz

Some restrictions apply.

Refer to the device TRM.

Crystal frequency range

16

–

35

MHz

kHz ECO DC Specification

SID318

I

Block operating current with 32-kHz crystal

Equivalent series resistance

Drive level

–

0.38

80

–

1

–

1

µA

kΩ

–

DD_kHz

SID321E ESR32K

SID322E PD32K

µW

kHz ECO AC Specification

SID319

SID320

SID320E

F_kHz

32 kHz frequency

Startup time

–

32.768

–

kHz

ms

–

Ton_kHz

–

500

250

F

Frequency tolerance

50

ppm

TOL32K

External Clock Specifications

Table 39. External Clock Specifications

Spec ID

SID305

SID306

Parameter

Description

Min

0

Typ

–

Max

100

55

Units

MHz

%

Details/Conditions

EXTCLK

External clock input frequency

–

FREQ

DUTY

EXTCLK

Duty cycle; measured at V /2

45

–

DD

PLL Specifications

Table 40. PLL Specifications

Spec ID Parameter

Description

Input frequency to PLL block

Time to achieve PLL lock

Output frequency from PLL block

PLL current

Min

Typ

–

Max

64

Units

MHz

µs

Details/Conditions

SID304P PLL_IN

4

SID305P PLL_LOCK

SID306P PLL_OUT

SID307P PLL_IDD

–

16

–

35

–

10.625

150

1.1

150

MHz

–

0.55

–

mA Typ. at 100 MHz out.

ps

100-MHz output

frequency

SID308P PLL_JTR

Period jitter

Table 41. Clock Source Switching Time

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

Clock switching from clk1 to clk2 in clock

periods; for example, from IMO (clk1) to FLL

(clk2).

4 clk1 +

3 clk2

SID262

TCLK

–

periods –

SWITCH

[5]

Note

5. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 3) then clk1 is the IMO and clk2 is the FLL.

Document Number: 002-28785 Rev. *I

Page 55 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

FLL Specifications

Table 42. Frequency Locked Loop (FLL) Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

Frequency Locked Loop (FLL) Specifications

0.001

–

100

MHz

Lower limit allows lock to

USB SOF signal (1 kHz).

Upper limit is for External

input.

SID450

SID451

FLL_RANGE

Input frequency range.

Output frequency range.

V_CCD= 1.1 V

24.00

–

100.00

50.00

MHz

Output range of FLL

divided-by-2 output

FLL_OUT_DIV2

Output frequency range.

V_CCD= 0.9 V

Output range of FLL

divided-by-2 output

SID451A

SID452

FLL_DUTY_DIV2 Divided-by-2 output; High or Low

47.00

–

53.00

7.50

%

–

µs

With IMO input, less than

10 °C change in

temperaturewhileinDeep

Sleep, and Fout ≥ 50 MHz.

Time from stable input clock to 1%

of final value on Deep Sleep

wakeup

SID454

FLL_WAKEUP

–

35.00

5.50

ps

50 ps at 48 MHz, 35 ps at

100 MHz

SID455

SID456

FLL_JITTER

Period jitter (1 sigma) at 100 MHz

CCO + Logic current

FLL_CURRENT

µA/MHz –

USB

Table 43. USB Specifications (USB requires LP Mode 1.1-V internal supply)

Spec ID

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

USB Block Specifications

SID322U V_{USB_3.3}

Device supply for USB operation

3.15

2.85

–

3.6

–

V

USB Configured

V_DDD= 3.3 V

Device supply for USB operation

(functional operation only)

SID323U V_{USB_3}

SID325U Iusb_config

Block supply current in Active mode

8

mA

Block supply current in suspend

mode

V_DDD= 3.3 V, Device

connected

SID328

SID329

Iusb_suspend

–

0.5

–

Block supply current in suspend

mode

V_DDD= 3.3 V, Device

disconnected

–

0.3

–

mA

Series resistors are on

chip

SID330U USB_Drive_Res

USB driver impedance

28

–

44

Ω

SID332U USB_Pullup_Idle Idle mode range

SID333U USB_Pullup Active mode

900

1575

3090

Bus idle

Upstream device trans-

mitting

1425

Document Number: 002-28785 Rev. *I

Page 56 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 44. QSPI Specifications

Spec ID# Parameter

SMIF QSPI Specifications. All specs with 15-pF load. Measured from 50% to 50% waveform transitions.

Description

Min

Typ

Max

Units Details / Conditions

SID390Q

Fsmifclock

SMIF QSPI output clock frequency

–

80

MHz LP mode (1.1 V)

ULP mode (0.9 V).

MHz

SID390QU

Fsmifclocku

SMIF QSPI output clock frequency

–

50

Guaranteed by Char.

SID399Q

SID397Q

SID398Q

Clk_dutycycle Clock duty cycle (high or low time)

45

–

55

%

Idd_qspi

Block current in LP mode (1.1 V)

Block current in ULP mode (0.9 V)

1900

590

µA

LP mode (1.1 V)

Idd_qspi_u

–

ULP mode (0.9 V)

Input data set-up time with respect to

clock capturing falling edge

SID391Q

SID392Q

SID393Q

SID394Q

SID395Q

SID396Q

Tsetup

4.5

–

ns

–

Input data hold time with respect to

clock capturing falling edge

Tdatahold

Tdataoutvalid

Tholdtime

Tseloutvalid

Tselouthold

1

Output data valid time with respect to

clock falling edge

7.5-ns max for ULP

mode (0.9 V)

–

3.7

–

Output data hold time with respect to

clock rising edge

3

–

OutputSelectvalid time with respect to

clock rising edge

15-ns max for ULP

mode (0.9 V)

7.5

–

Output Select hold time with respect to

clock rising edge

Tsclk = Fsmifclk cycle

time

Tsclk/2

Smart I/O

Table 45. Smart I/O Specifications

Spec ID#

SID420

SID421

Parameter

SMIO_BYP

SMIO_LUT

Description

Smart I/O bypass delay

Smart I/O LUT prop delay

Min

–

Typ

–

Max

2

Units Details/Conditions

ns

–

8

–

SD Host Controller and eMMC

Table 46. SD Host Controller and eMMC Specifications

Spec ID# Parameter Description

Min

Typ

Max

Units Details / Conditions

SD Host Controller and eMMC Specifications (SD Host clock (see the Clocking Diagram) must be divided by 2 or more

when used as source in DDR modes. Specs are Guaranteed by Design.)

drive_sel = '01' for all

modes

SID_SD390

SD_DS

SD_TR

I/O drive select

4

–

4

3

mA

ns

SID_SD391

SD:DS Timing

SID_SD392

SID_SD393

SID_SD394

SID_SD395

Input transition time

0.7

–

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

–

25

8

MHz (40-ns period)

MHz (125-ns period)

SD_DCMD_CL I/O loading at DATA/CMD pins

30

–

pF

–

SD_CLK_CL

I/O loading at CLK pins

–

Output: Setup time of CMD/DATprior to

CLK

SID_SD396

SD_TS_OUT

5.1

–

ns

–

Document Number: 002-28785 Rev. *I

Page 57 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 46. SD Host Controller and eMMC Specifications (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units Details / Conditions

Output: Hold time of CMD/DAT after

CLK

SID_SD397

SD_HLD_OUT

5.1

–

ns

–

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

SID_SD398

SID_SD399

SD_TS_IN

24

–

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

SD_TS_IN

109

0

–

ns

–

SID_SD400

SD:HS Timing

SID_SD401

SID_SD402

SID_SD403

SID_SD404

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

–

45

16

–

MHz (22.5-ns period)

MHz (62.5-ns period)

SD_DCMD_CL I/O loading at DATA/CMD pins

30

pF

–

SD_CLK_CL

I/O loading at CLK pins

–

Output: Setup time of CMD/DATprior to

CLK

SID_SD405

SID_SD406

SID_SD407

SD_TS_OUT

6.1

2.1

8

–

ns

–

Output: Hold time of CMD/DAT after

CLK

SD_HLD_OUT

SD_TS_IN

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

SID_SD408

SID_SD409

SD_TS_IN

48.3

–

ns

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 2.5

SD:SDR-12 Timing

SID_SD410

SID_SD411

SID_SD412

SID_SD413

SID_SD414

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

Duty cycle of output CLK

–

25

8

MHz (40-ns period)

MHz (125-ns period)

SD_CLK

SD_CLK_DC

30

–

70

–

%

pF

–

SD_DCMD_CL I/O loading at DATA/CMD pins

30

SD_CLK_CL

I/O loading at CLK pins

–

Output: Setup time of CMD/DATprior to

CLK

SID_SD415

SID_SD416

SID_SD417

SD_TS_OUT

3.1

0.9

24

–

ns

–

Output: Hold time of CMD/DAT after

CLK

SD_HLD_OUT

SD_TS_IN

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

SID_SD418

SID_SD419

SD_TS_IN

109

–

ns

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 1.5

SD:SDR-25 Timing

SID_SD420

SID_SD421

SID_SD422

SID_SD423

SID_SD424

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

Duty cycle of output CLK

–

50

16

70

–

MHz (20-ns period)

MHz (62.5-ns period)

SD_CLK

SD_CLK_DC

30

–

%

pF

–

SD_DCMD_CL I/O loading at DATA/CMD pins

SD_CLK_CL I/O loading at CLK pins

30

–

Document Number: 002-28785 Rev. *I

Page 58 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 46. SD Host Controller and eMMC Specifications (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units Details / Conditions

Output: Setup time of CMD/DATprior to

CLK

SID_SD425

SD_TS_OUT

3.1

–

ns

–

Output: Hold time of CMD/DAT after

CLK

SID_SD426

SID_SD427

SD_HLD_OUT

SD_TS_IN

0.9

5.8

–

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

SID_SD428

SID_SD429

SD_TS_IN

48.3

–

ns

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 1.5

SD:SDR-50 Timing

SID_SD430

SID_SD431

SID_SD432

SID_SD433

SID_SD434

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

Duty cycle of output CLK

–

80

32

70

–

MHz (12.5-ns period)

MHz (31.25-ns period)

SD_CLK

SD_CLK_DC

30

–

%

pF

–

SD_DCMD_CL I/O loading at DATA/CMD pins

20

SD_CLK_CL

I/O loading at CLK pins

–

Output: Setup time of CMD/DATprior to

CLK

SID_SD435

SID_SD436

SID_SD437

SD_TS_OUT

3.1

0.9

5

–

ns

–

Output: Hold time of CMD/DAT after

CLK

SD_HLD_OUT

SD_TS_IN

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

SID_SD438

SID_SD439

SD_TS_IN

23.6

–

ns

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 1.5

SD:DDR-50 Timing

SID_SD440

SID_SD441

SID_SD442

SID_SD443

SID_SD444

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

Duty cycle of output CLK

–

40

16

55

–

MHz (25-ns period).

MHz (62.5-ns period)

SD_CLK

SD_CLK_DC

45

–

%

pF

ns

–

SD_DCMD_CL I/O loading at DATA/CMD pins

30

–

SD_CLK_CL

I/O loading at CLK pins

–

Output: Setup time of CMD/DATprior to

CLK

3.1

–

SID_SD445

SID_SD446

SID_SD447

SD_TS_OUT

–

Output: Hold time of CMD/DAT after

CLK

0.9

5.7

24

–

ns

SD_HLD_OUT

SD_TS_IN

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

SID_SD448

SID_SD449

SD_TS_IN

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 1.5

eMMC:BWC Timing

SID_SD450

SID_SD451

SID_SD452

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

–

26

8

MHz (38.4-ns period)

MHz (125-ns period)

SD_DCMD_CL I/O loading at DATA/CMD pins

30

–

pF

–

Document Number: 002-28785 Rev. *I

Page 59 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 46. SD Host Controller and eMMC Specifications (continued)

Spec ID#

Parameter

Description

Min

–

Typ

30

–

Max

–

Units Details / Conditions

SID_SD453

SD_CLK_CL

I/O loading at CLK pins

pF

ns

–

Output: Setup time of CMD/DATprior to

CLK

3.1

–

SID_SD454

SID_SD455

SID_SD456

SD_TS_OUT

SD_HLD_OUT

SD_TS_IN

–

Output: Hold time of CMD/DAT after

CLK

3.1

9.7

–

ns

–

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

96.3

SID_SD457

SID_SD458

SD_TS_IN

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 8.3

eMMC:SDR Timing

SID_SD459

SID_SD460

SID_SD461

SID_SD462

SD_CLK

Interface clock period (LP mode)

Interface clock period (ULP mode)

–

52

16

–

MHz (19.2-ns period)

MHz (62.5-ns period)

SD_DCMD_CL I/O loading at DATA/CMD pins

–

30

–

pF

ns

–

SD_CLK_CL

I/O loading at CLK pins

–

Output: Setup time of CMD/DATprior to

CLK

3.1

–

SID_SD463

SID_SD464

SID_SD465

SD_TS_OUT

–

Output: Hold time of CMD/DAT after

CLK

3.1

5.3

–

ns

SD_HLD_OUT

SD_TS_IN

Input: Setup time of CMD/DAT prior to

CLK (LP mode)

Input: Setup time of CMD/DAT prior to

CLK (ULP mode)

48.6

SID_SD466

SID_SD467

SD_TS_IN

–

SD_HLD_IN

Input: Hold time of CMD/DAT after CLK 2.5

SD Host Block Current Specs

SD Host block current consumption at

100 MHz

SID400SD

SID401SD

IDD_SD_1

IDD_SD_2

–

4.65

3.75

5

mA

SDR-50

SD Host block current consumption at

50 MHz

–

4.3

mA SDR-25

JTAG Boundary Scan

Table 47. JTAG Boundary Scan

Spec ID#

Parameter

Min

Typ Max Units Details / Conditions

JTAG Boundary Scan Parameters

JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:

SID468

SID469

SID470

SID471

SID472

TCKLOW

TCKHIGH

TCK_TDO

TSU_TCK

TCk_THD

TCK LOW

52

10

–

ns

–

TCK HIGH

TCK falling edge to output valid

Input valid to TCK rising edge

Input hold time to TCK rising edge

40

–

12

10

40

–

TCK falling edge to output valid (High-Z

to Active).

–

SID473

SID474

TCK_TDOV

TCK_TDOZ

–

TCK falling edge to output valid (Active

to High-Z).

40

–

ns

Document Number: 002-28785 Rev. *I

Page 60 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Table 47. JTAG Boundary Scan (continued)

Spec ID#

Parameter

Min

Typ Max Units Details / Conditions

JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:

SID468A

SID469A

SID470A

SID471A

SID472A

TCKLOW

TCKHIGH

TCK_TDO

TSU_TCK

TCk_THD

TCK low

102

20

–

ns

–

TCK high

TCK falling edge to output valid

Input valid to TCK rising edge

Input hold time to TCK rising edge

80

–

22

20

80

–

TCK falling edge to output valid (high-Z

to active).

–

SID473A

SID474A

TCK_TDOV

TCK_TDOZ

–

TCK falling edge to output valid (active

to high-Z).

80

–

ns

Document Number: 002-28785 Rev. *I

Page 61 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Ordering Information

Table 51 lists the CYB06445LQI-S3D42 part numbers and features. See also the product selector guide.

Table 48. Ordering Information

Arm CM4 and CM0+, DC-DC

converter, 12-bit SAR ADC, 2

LPCOMPs, 7 SCBs, 12 TCPWMs,

SD Host Controller, USB-FS

64

CYB06445LQI-S3D42

512

256

Y

1

Y

53

68-QFN

Document Number: 002-28785 Rev. *I

Page 62 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

PSoC 6 MPN Decoder

CY XX 6 A B C DD E - FF G H I JJ K L

Field

Description Values

Meaning

Cypress

Field

Description

Values

Meaning

Consumer

CY

Cypress

CY

8C

B0

C

I

Standard

E

Temperature Range

Industrial

“Secure Boot” v1

Q

Extended Industrial

XX

6

Firmware

Architecture

“Standard Secure” -

AWS

S0

Cypress internal

FF

Feature Code

6

0

1

2

3

4

2

3

4

PSoC 6

S2-S6

Value

BL

F

Integrated Bluetooth LE

Single Core

Dual Core

Feature set

31-50

Programmable

Performance

Connectivity

Secured

G

H

CPU Core

A

B

Line

D

Attributes Code

0–9

1

100 MHz

2

51-70

I

GPIO count

Speed

150 MHz

3

71-90

150/50 MHz

4

91-110

Engineering sample

(optional)

Engineering samples or

not

0-3

Reserved

JJ

K

ES

4

5

256K/128K

512K/256K

Base

Die Revision

(optional)

A1-A9 Die revision

Tape/Reel Shipment

(optional)

Memory Size

(Flash/SRAM)

6

512K/128K

L

T

Tape and Reel shipment

C

7

8

9

A

1024K/288K

1024K/512K

Reserved

2048K/1024K

AZ, AX TQFP

LQ

BZ

FM

QFN

BGA

DD

Package

M-CSP

FN, FD,

FT

WLCSP

Document Number: 002-28785 Rev. *I

Page 63 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Packaging

This product line is offered in a 68-QFN package.

Table 49. Package Dimensions

Spec ID# Package

PKG_1 68-QFN

Description

Package Dwg #

68-QFN package

001-96836

Table 50. Package Characteristics

Parameter Description

Conditions

Min

–40

–

Typ

25

–

Max

85

100

–

Units

°C

T

Operating ambient temperature

Operating junction temperature

–

A

°C

J

Package  (68-QFN)

15.4

2

°C/watt

JA

JC

JA

Package  (68-QFN)

–

JC

Table 51. Solder Reflow Peak Temperature

Package

Maximum Peak Temperature

Maximum Time at Peak Temperature

68-QFN

260°C

30 seconds

Table 52. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

MSL

68 QFN

MSL 3

Document Number: 002-28785 Rev. *I

Page 64 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Figure 18. 68-QFN Package Diagram

001-96836 *A

Document Number: 002-28785 Rev. *I

Page 65 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Acronyms

Acronym

ECC

Description

error correcting code

Acronym

3DES

Description

triple DES (data encryption standard)

analog-to-digital converter

ECC

ECO

elliptic curve cryptography

external crystal oscillator

ADC

advanced DMA version 3, a Secure Digital data

transfer mode

ADMA3

AES

electrically erasable programmable read-only

memory

EEPROM

advanced encryption standard

EMI

electromagnetic interference

embedded MultiMediaCard

electrostatic discharge

embedded trace macrocell

first-in, first-out

AMBA(advanced microcontroller bus architecture)

high-performance bus, an Arm data transfer bus

eMMC

ESD

ETM

FIFO

FLL

AHB

AMUX

AMUXBUS

API

analog multiplexer

analog multiplexer bus

application programming interface

advanced RISC machine, a CPU architecture

ball grid array

frequency locked loop

floating-point unit

®

Arm

FPU

FS

BGA

full-speed

BOD

brown-out detect

GND

Ground

BREG

BWC

CAD

backup registers

general-purpose input/output, applies to a PSoC

GPIO

backward compatibility (eMMC data transfer mode)

computer aided design

HMAC

HSIOM

I/O

Hash-based message authentication code

high-speed I/O matrix

CCO

current controlled oscillator

a stream cipher

ChaCha

CM0+

CM4

input/output, see also GPIO, DIO, SIO, USBIO

Inter-Integrated Circuit, a communications protocol

inter-IC sound

2

Cortex-M0+, an Arm CPU

Cortex-M4, an Arm CPU

I C, or IIC

2

I S

CMAC

cypher-based messge authentication code

IC

integrated circuit

IDAC

IDE

ILO

current DAC, see also DAC, VDAC

integrated development environment

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input output subsystem

complementary metal-oxide-semicondutor, a

process technology for IC fabrication

CMOS

CMRR

CPU

common-mode rejection ratio

central processing unit

IMO

INL

cyclic redundancy check, an error-checking

protocol

CRC

IOSS

IoT

CSD

CSV

CapSense Sigma-Delta

clock supervisor

internet of things

IPC

IRQ

ISR

ITM

JTAG

LCD

inter-processor communication

interrupt request

Cypress mutual capacitance sensing method. See

also CSD

CSX

interrupt service routine

CTI

cross trigger interface

instrumentation trace macrocell

Joint Test Action Group

DAC

DAP

DDR

DES

DFT

DMA

DNL

DSI

digital-to-analog converter, see also IDAC, VDAC

debug access port

liquid crystal display

double data rate

Local Interconnect Network, a communications

protocol

data encryption standard

design for test

LIN

LP

low power

direct memory access, see also TD

differential nonlinearity, see also INL

digital system interconnect

data unit

LS

low-speed

LUT

LVD

LVI

lookup table

low-voltage detect, see also LVI

low-voltage interrupt

low-voltage transistor-transistor logic

DU

DW

data wire, a DMA implementation

LVTTL

Document Number: 002-28785 Rev. *I

Page 66 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Acronym

MAC

Description

multiply-accumulate

Acronym

SAR

Description

successive approximation register

SAR ADC multiplexer bus

MCU

MISO

MMIO

MOSI

MPU

MSL

Msps

MTB

MUL

NC

microcontroller unit

SARMUX

SC/CT

SCB

master-in slave-out

switched capacitor/continuous time

serial communication block

memory-mapped input output

master-out slave-in

2

SCL

I C serial clock

memory protection unit

moisture sensitivity level

million samples per second

micro trace buffer

SD

Secure Digital

2

SDA

I C serial data

SDHC

SDR

Secure Digital host controller

single data rate

multiplier

Sflash

SHA

supervisory flash

no connect

secure hash algorithm

signal to noise and distortion ratio

shared memory protection unit

signal-to-noise ration

start of frame

NMI

nonmaskable interrupt

nested vectored interrupt controller

nonvolatile latch, see also WOL

one-time programmable

over voltage protection

overvoltage tolerant

SINAD

SMPU

SNR

NVIC

NVL

OTP

OVP

OVT

PASS

PCB

PCM

PDM

PHY

PICU

PLL

SOF

silicon-oxide-nitride-oxide-silicon, a flash memory

technology

SONOS

SPI

Serial Peripheral Interface, a communications

protocol

programmable analog subsystem

printed circuit board

SRAM

SROM

SRSS

SWD

SWJ

static random access memory

supervisory read-only memory

system resources subsystem

serial wire debug, a test protocol

serial wire JTAG

pulse code modulation

pulse density modulation

physical layer

port interrupt control unit

phase-locked loop

SWO

SWV

TCPWM

TDM

single wire output

PMIC

POR

PPU

PRNG

power management integrated circuit

power-on reset

single-wire viewer

timer, counter, pulse-width modulator

time division multiplexed

total harmonic distortion

thin quad flat package

peripheral protection unit

pseudo random number generator

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

quadrature decoder

THD

®

PSoC

PSRR

PWM

QD

TQFP

TRM

technical reference manual

true random number generator

transmit

TRNG

TX

QSPI

RAM

RISC

RMS

ROM

quad serial peripheral interface

random-access memory

reduced-instruction-set computing

root-mean-square

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

ULP

ultra-low power

USB

Universal Serial Bus

watch crystal oscillator

watchdog timer

read-only memory

WCO

WDT

WIC

Rivest–Shamir–Adleman, a public-key cryptog-

raphy algorithm

RSA

wakeup interrupt controller

wafer level chip scale package

execute-in-place

RTC

RWW

RX

real-time clock

read-while-write

receive

WLCSP

XIP

XRES

external reset input pin

S/H

sample and hold

Document Number: 002-28785 Rev. *I

Page 67 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Document Conventions

Table 53. Units of Measure (continued)

Units of Measure

Table 53. Units of Measure

Symbol

µH

Unit of Measure

microhenry

microsecond

microvolt

Symbol

°C

Unit of Measure

µs

degrees Celsius

decibel

µV

µW

mA

ms

mV

nA

ns

dB

microwatt

milliampere

millisecond

millivolt

fF

femto farad

Hz

hertz

KB

1024 bytes

kbps

khr

kilobits per second

kilohour

nanoampere

nanosecond

nanovolt

kHz

k

kilohertz

nV

W

kilo ohm

ohm

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

pF

picofarad

ppm

ps

parts per million

picosecond

second

s

mega-ohm

sps

sqrtHz

V

samples per second

square root of hertz

volt

megasamples per second

microampere

microfarad

µF

Document Number: 002-28785 Rev. *I

Page 68 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Errata

This section describes the errata for the CYB06445LQI-S3D42 product line. Details include errata trigger conditions, scope of impact,

available workarounds, and silicon revision applicability. Compare this document to the device's datasheet for a complete functional

description.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

Device Characteristics

CYB06445LQI-S3D42

CYB06445LQI-S3D42 Product Line

Qualification Status

Engineering Samples

Errata Summary

This table defines the errata applicability to available PSoC 6 CYB06445LQI-S3D42 devices.

PSoC

CYB06445LQI-S3D42

Items

Silicon Revision

Fix Status

[1.] DMA controllers are not available

All

Production silicon Resolution planned by Q4 '22

1. DMA controllers are not available

The 32- and 29-channel DMA controllers are not available. Register access to these controllers is not

available. The 2-channel controller is available; there are no USB or audio connections to it.

Problem Definition

Parameters Affected

Trigger Condition(s)

Scope of Impact

Workaround

The 32- and 29-channel DMA controllers

Attempt to use the 32- or the 29-channel DMA controller, by accessing their registers

CPU exceptions are generated

Use the 2-channel controller for DMA operations

Investigation underway. Fix planned by Q3’21.

Fix Status

Document Number: 002-28785 Rev. *I

Page 69 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Revision History

Description Title: PSoC 6 MCU: CYB06445LQI-S3D42 Datasheet

Document Number: 002-28785

Submission

Revision

ECN

Description of Change

Date

**

6711017

10/22/2019 New datasheet.

Updated Features.

Updated Blocks and Functionality and Functional Description.

Updated Pinouts and Power Supply Considerations.

*A

6776273

01/16/2020

04/10/2020

Updated Packaging.

Updated Features.

Updated Functional Description.

Updated Pinouts.

*B

*C

6851682

6894902

Updated PSoC 6 MPN Decoder.

Updated Development Ecosystem, GPIO, and LCD sections.

06/16/2020 Added External Crystal Oscillators.

Updated Revision History

Updated Flexible Clocking Options, Block Diagram, and CPUs.

Updated list of application notes and links and the kit link in PSoC 6 MCU Resources.

Updated the amount of available SRAM in Features, Blocks and Functionality, Memory, Table 3,

and Ordering Information. Updated the PSoC 64 Security section.

Updated ModusToolbox Software.

Updated Quad-SPI (QSPI)/Serial Memory Interface (SMIF).

Added InterProcessor Communication (IPC).

Updated Analog Subsystem diagram.

*D

6981432

11/16/2020

Updated Direct Memory Access (DMA) Controllers.

Updated VDDA bullet in Power Supply Considerations.

Updated the XRES bullet in Reset, SID15 Description and Conditions, and System Resources

(Power-On-Reset specifications)

Updated SID7A conditions, SID7D description, and SID8 conditions.

Updated SD Host Controller and eMMC Specifications.

Integrated ECO erratum into External Crystal Oscillators. Added ECO Usage Guidelines table.

Added Errata items.

Updated Security terminology to Infineon standards.

Changed BLE references to Bluetooth LE.

*E

*F

7139142

7231613

05/13/2021 Added Table 14 and Figure 33 in Electrical Specifications.

Removed SIDDS1 and SIDDS1_B and updated Typ values for SIDDS2 and SIDDS2_B

Added “DMA controllers are not available” errata item.

Updated SIDDS2 - Corrected Deep Sleep current values.

08/20/2021

Removed "System Deep Sleep power higher than specification" errata item.

Removed Preliminary tag from the datasheet.

Updated Figure 6.

Added note regarding unused USB pins in USB Full-Speed Device Interface, Power Supply

Considerations, and Pinouts.

*G

*H

7487079

7758801

12/03/2021

Updated SIDC1 description.

Updated details/conditions for SID7A.

Updated SID325U, SID328, and SID329 description.

Updated Errata.

05/05/2022 Corrected typo in Figure 14 and Figure 15.

Document Number: 002-28785 Rev. *I

Page 70 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Description Title: PSoC 6 MCU: CYB06445LQI-S3D42 Datasheet

Document Number: 002-28785

Added device identification and revision information in Features.

Added spec SID304P.

Updated PLL Specifications and Clock System.

Updated Protection Units.

*I

7788568

10/26/2022

Document Number: 002-28785 Rev. *I

Page 71 of 72

PSoC 6 MCU: CYB06445LQI-S3D42

Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Memory

cypress.com/support

cypress.com/memory

cypress.com/mcu

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

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Document Number: 002-28785 Rev. *I

Revised October 26, 2022

Page 72 of 72


型号：	CYB06445LQI-S3D42
厂家：	Infineon
描述：	32-位PSoC™ 6 Arm® Cortex®-M4 / M0+
文件：	总73页 (文件大小：1094K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYB06445LQI-S3D42 [INFINEON]

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CYBL10462-56LQXI

CYBL10471-56LQXI

CYBL10473-56LQXI

CYBL10473-56LQXIT

CYBL10563-56LQXI

CYBL10563-68FNXI