CYPAP111A3-10SXQT [INFINEON]
PG-DSO-10 tape and reel packing primary side startup controller with non-x-cap mode and pulse-transformer feedback for USB PD charger and adapters;
| 型号： | CYPAP111A3-10SXQT |
| 厂家： | 
Infineon |
| 描述： | PG-DSO-10 tape and reel packing primary side startup controller with non-x-cap mode and pulse-transformer feedback for USB PD charger and adapters 光电二极管 |
| 文件： | 总17页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EZ-PD™ PAG1P
Primary side startup controller
General description
EZ-PD™ PAG1P (Power Adapter Generation 1 Primary) is Infineon’s primary-side start-up controller for AC/DC
applications targeting the mobile power adapter segment. EZ-PD™ PAG1P interfaces directly with either the AC
mains in an X-cap discharge mode or the DC output of a bridge rectifier. EZ-PD™ PAG1P is available in a 10-pin
SOIC package.
EZ-PD™ PAG1P is designed for a secondary controlled AC/DC flyback converter topology. In this topology, voltage
and current regulation is performed by the secondary controller. EZ-PD™ PAG1P is responsible for providing the
start-up function, driving the primary side FET as well as responding to fault conditions.
Features
• Works across universal AC mains input 85 VAC to 265 VAC
• Low-side gate driver to drive primary side FET
• Line undervoltage protection (UVP) and line overvoltage protection
• Overcurrent protection (OCP)
• Overvoltage protection (OVP) during soft-start
• Programmable soft-start configurable with external capacitor
• Fixed auto-restart timer for fault recovery
• Supports X-cap discharge mode to obtain better efficiency
• Integrated high-voltage start-up and shunt regulator
• Synchronizes to PWM from secondary side using a pulse edge Transformer
Functional block diagram
LINE_OV
OVP
OSCILLATOR AND Rx
REF
REF
7.5V
VIN
(Rectified Output from AC Mains)
RT
LINE_UV
VDD700
Free
Running
Oscillator
UVLO
PWM
Generator
7.5V
REF
7.5V
Flyback
Transformer
AUXIN
Optional
Regulator
LDO
GND
REF
Discharge
GND
(7-20)V
AUX_UV
POR
OVP
REF
AUX_OV
1V
OVP_AUX
To
Blank
START
STOP
Secondary
Controller
PULSEIN
SS
GATE
DRIVER
From
Secondary
GD
CS
-1V
Pulse Edge
Transformer
LEB
TURN OFF GD
RSENSE
Vth1
CURRENT
SENSE
GND
GND
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 17
002-25572 Rev. *F
2022-05-18
Primary side startup controller
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Functional block diagram...................................................................................................................1
Table of contents...............................................................................................................................2
1 Pinout............................................................................................................................................3
2 Application overview ......................................................................................................................5
3 Functional description ....................................................................................................................7
3.1 Soft-start .................................................................................................................................................................7
3.2 X-cap mode .............................................................................................................................................................7
3.3 Secondary synchronization....................................................................................................................................7
3.4 Power circuit ...........................................................................................................................................................7
3.5 Overcurrent and overvoltage fault protection ......................................................................................................7
3.6 Auto-restart timer ...................................................................................................................................................8
3.7 Protection and fault condition...............................................................................................................................8
4 Electrical specifications.................................................................................................................11
5 Ordering information ....................................................................................................................14
5.1 Ordering code definitions.....................................................................................................................................14
6 Packaging ....................................................................................................................................15
Revision history ..............................................................................................................................16
Datasheet
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Primary side startup controller
Pinout
1
Pinout
1
2
VDD700
NC
OVP_AUX
AUX_IN
10
9
3
4
RT
GD
CS
8
7
PULSEIN
SS
5
GND
6
Figure 1
Table 1
Pin map
EZ-PD™ PAG1P pin description
Pin number Pin name
Description
Start-up power supply input. VDD700 is the power supply source during the
start-up phase. This pin can be connected to either the bridge rectifier output as
shown in Figure 2, or directly to the AC mains through a diode as shown in
Figure 3. This pin has a maximum voltage rating of 500 V.
1
VDD700
2
3
NC
RT
No connect
Timing resistor. The RT pin is used to connect to an external timing resistor of
499 k which determines the free running oscillator frequency FOSC. Oscillator
frequency is typically 30 kHz.
Pulse Edge Transformer (PET) input. Once the start-up phase is successfully
complete, EZ-PD™ PAG1P synchronizes to the secondary side pulses received at
the PULSEIN input. The secondary controller provides PWM control information to
the primary using a PET. The pulse amplitude shall not exceed V_PULSEINNEGAMP
and V_PULSEINPOSAMP and the pulse width shall be in the T_PULSEINPW range.
Soft-start pin. Connect a 0.1-µF capacitor to GND. The soft-start time is provided
in the specification section (Table 13). This pin also connects to the other end of
the pulse transformer. The external capacitor connected to the SS pin determines
the soft-start time. The duty cycle of the gate drive gradually increases to provide
a smooth transfer of power to the secondary side.
4
5
PULSEIN
SS
6
7
GND
CS
Ground
Primary side current sense input. Current sense input is used to monitor the
overcurrent fault scenario. Overcurrent fault is detected with the voltage between
this input and ground exceeds V_CSTH1 threshold.
Primary FET gate driver. EZ-PD™ PAG1P integrates a low side gate driver to drive
the gate of an external FET.
8
GD
Datasheet
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Primary side startup controller
Pinout
Table 1
EZ-PD™ PAG1P pin description (continued)
Pin number Pin name
Description
Auxiliary supply input. AUX_IN serves as the power supply source after the start-up
phase. This pin should be connected to the output of auxiliary winding through a
rectifier or a regulator depending on whether the maximum voltage on the output
of the auxiliary winding exceeds 22 V. EZ-PD™ PAG1P switches its power supply
source to AUX_IN once the secondary side provides power.
9
AUX_IN
Auxiliary winding overvoltage detection. EZ-PD™ PAG1P monitors this pin for
overvoltage condition on the secondary side, using an external resistor divider. Any
voltage exceeding V_OVPAUXRISE on this pin is treated as an overvoltage fault
condition. The overvoltage condition is monitored only during open loop
operation. A Schottky diode to GND should be connected to ensure negative
voltage is not seen when the gate driver is ON.
10
OVP_AUX
Datasheet
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2
Application overview
EZ-PD™ PAG1P works with Infineon's secondary side controller EZ-PD™ PAG1S. Figure 2 shows the application diagram of a USB Power Delivery power
adapter solution with ‘EZ-PD™ PAG1P + EZ-PD™ PAG1S’. In this system, once the start-up phase is complete, the primary FET control is completely
synchronized to the PWM pulses received from the secondary side. The PWM pulses are transmitted over an isolation barrier using a PET. EZ-PD™ PAG1P
takes over control of the primary FET only during power-up and system fault scenarios.
Full-bridge
Snubber
VBU S_TypeC
VBU S_IN
Rectifier
Optional
Regulator
EMI
Filter
CC_COMP_GPIO2
GD
CS
AUXIN
CC1
CC2
VDD700
EA_OUT
DP_GPIO5
DM_GPIO4
EZ-PD™
PAG1P
EZ-PD™ PAG1S
RT
PULSEIN
SS
FB
PWM_DRV_GPIO1
GPIO0
GND
Temperature
Sensor
Primary Side
Secondary Side
Figure 2
Type-C based mobile phone power adapter with EZ-PD™ PAG1P (CYPAP111xx) and EZ-PD™ PAG1S in a secondary controlled flyback
topology configuration
Figure 3 shows the application diagram for a power adapter where EZ-PD™ PAG1P is powered directly from the AC mains before the full bridge rectifier.
This topology enables discharging the X cap using EZ-PD™ PAG1P instead of using a passive resistor thereby improving efficiency.
Full-bridge
Snubber
VBUS_TypeC
VBUS_IN
Rectifier
Optional
Regulator
EMI
Filter
CC_COMP_GPIO2
GD
CS
AUXIN
CC1
CC2
VDD700
EA_OUT
DP_GPIO5
DM_GPIO4
EZ-PD™
PAG1P
EZ-PD™ PAG1S
RT
PULSEIN
SS
FB
PWM_DRV_GPIO1
GPIO0
GND
Temperature
Sensor
Primary Side
Secondary Side
Figure 3
Type-C based mobile phone power adapter with EZ-PD™ PAG1P (CYPAP112xx) used in X-cap discharge configuration
Primary side startup controller
Functional description
3
Functional description
3.1
Soft-start
The Soft-start feature allows EZ-PD™ PAG1P to gradually increase the output voltage of the flyback converter till
the secondary side takes control of the regulation. Soft-start is used during initial start-up sequence and fault
condition. The duration of the soft-start is controlled by an external capacitor connected to the SS pin and the
frequency of the soft-start is determined by an external resistor connected to the RT pin. An internal current
source of 5 µA charges the external capacitor and the maximum amplitude for the soft-start ramp is 3.75 V. 3.75 V
dictates the maximum duty cycle. Under Soft-start, the maximum ON time of the primary FET is limited to 19 µs
which is equivalent to 70% duty cycle at 30 kHz. When the secondary side takes control, the maximum ON time
is limited to 25 µs.
3.2
X-cap mode
In EZ-PD™ PAG1P X-cap part, X-cap mode is detected when 3 V_VDD700UVRISE transitions occur within 64 ms. A
flag is set indicating the part is operating in X-cap mode. When 3 V_VDD700UVRISE transitions are not detected
within 64 ms after the flag is set, a line disconnect is detected and an internal discharge path is turned ON to
discharge the X-capacitor.
3.3
Secondary synchronization
During the start-up phase, if EZ-PD™ PAG1P sees appropriate input pulses at the PULSEIN pin, then it synchro-
nizes the primary FET control to the secondary pulses. The PWM control signal from the secondary side is coupled
to the primary side using a Pulse Edge Transformer (PET). The PET is an important component to ensure proper
frequency response and should have just an adequate Q-factor to avoid excessive overshoot. The positive pulse
from the PET is treated as primary FET turn-on signal and the negative pulse from the PET is treated as primary
FET turn-off signal. The pulse amplitude shall not exceed V_PULSEINNEGAMP and V_PULSEINPOSAMP and the
pulse width shall be within T_PULSEINPW range.
The synchronization path between the secondary and primary through the PET is also used for communication
of shutdown condition. Three consecutive negative pulses from the secondary side is treated as a shutdown
signal. On receiving such three consecutive negative pulses, EZ-PD™ PAG1P will shutdown after 200 ms.
3.4
Power circuit
EZ-PD™ PAG1P integrates a high voltage start-up regulator. During power-up, EZ-PD™ PAG1P shall be powered
from the line input via the VDD700 pin. Once voltage on the auxiliary winding is available from the secondary side,
EZ-PD™ PAG1P switches its power supply input to AUX_IN pin and no power will be sourced from the VDD700 pin.
3.5
Overcurrent and overvoltage fault protection
EZ-PD™ PAG1P implements overcurrent protection. When the CS pin voltage exceeds V_CSTH1, EZ-PD™ PAG1P
limits the primary current by turning OFF the primary FET.
EZ-PD™ PAG1P provides three types of voltage protection – protection against line undervoltage/overvoltage and
secondary overvoltage. The line undervoltage/overvoltage monitoring is via VDD700 pin and the respective
thresholds are V_VDDUVRISE and V_VDDOVRISE. Gate pulses are turned off until fault is removed. Once the
voltage on VDD700 is within operating range, EZ-PD™ PAG1P does an auto-restart.
In addition, EZ-PD™ PAG1P monitors the voltage on OVP_AUX pin for detecting overvoltage condition on the
secondary side. The voltage on the OVP_AUX pin is a scaled-down version of the secondary side voltage. When
voltage on OVP_AUX exceeds V_OVPAUXRISE, the gate driver is turned off. Once the voltage on OVP_AUX goes
below the fault range, EZ-PD™ PAG1P does an auto-restart. EZ-PD™ PAG1P monitors secondary overvoltage only
during start-up phase or during fault condition after auto-restart.
The flow chart in Figure 4 and the Functional block diagram show the operation of the chip.
Datasheet
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2022-05-18
Primary side startup controller
Functional description
3.6
Auto-restart timer
A fixed timer of TAR sec is available for various fault conditions. The timer is operated from a free running oscil-
lator inside EZ-PD™ PAG1P. Free running oscillator will be running at FOSC.
3.7
Protection and fault condition
Primarily there are four types of protection actions used in various fault conditions.
1. Autorestart: In this mode, EZ-PD™ PAG1P will wait TAR sec before doing a soft start. This sequence is repeated
continuously (see Figure 5).
2. Latch or shutdown: No auto-restart timer or soft start is implemented. Shuts the IC immediately and power to
the IC needs to be removed to unlatch.
3. Gate OFF: This only turns OFF the gate drive pulse and waits for the fault condition to pass before the IC
functions normally.
4. Max duty cycle: Gate driver will be ON for 19 µs (maximum) during soft-start. When secondary is in control, gate
drive will be ON for 25 µs (maximum).
Datasheet
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Primary side startup controller
Functional description
Table 2 provides the fault conditions and protection action.
Table 2
Sl#
Faults conditions and protection action
Fault
Action
Gate driver output is low. When VDD700 exceeds
V_VDD700UVRISE, do a soft-start followed by Autore-
start.
Gate driver output is low during fault condition
followed by Autorestart.
VDD700 pin is under threshold voltage
V_VDD700UVRISE
1
2
3
VDD700 pin exceeds threshold voltage
V_VDD700OVRISE
Gate driver output is low during fault condition
followed by Autorestart. This is valid only when
EZ-PD™ PAG1P is operating in open loop.
OVP_AUX pin exceeds threshold voltage
V_OVPAUXRISE
Gate driver output is low during fault condition. In
open loop, do the Autorestart after fault condition is
removed. In closed loop, wait for the next pulse from
secondary side.
4
CS pin exceeds threshold voltage V_CSTH1
Stop command from Secondary side
Receive no pulses from Secondary side for TAR sec
after last stop pulse
6
7
Shutdown after 200 ms.
Autorestart
Keep gate driver ON for 25 µs. EZ-PD™ PAG1P will wait
for TAR sec before doing Autorestart.
8
Start pulse and no Stop pulse from Secondary side
Datasheet
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Primary side startup controller
Functional description
START
(Non X-cap)
START
(X-cap)
YES
NO
GD
OFF
GD
OFF
Detect 3 line
UV in 64ms
Below
Above
V_VDD700OVRI
NO
V_VDD700UVRI
SE?
NO
SE?
YES
Set X-cap
flag
YES
3 Line UV not
detected in
64ms
YES
Start Free Running PWM with soft-
start. Soft-start duration is set by
external capacitor.
NO
Discharge X-cap
Start Free Running PWM with
softstart. Soft-start duration is set
by external capacitor.
Pulse from
Secondary
available
NO
YES
PWM from EZ-PD·
PAG1P control gate
driver.
PWM from EZ‐PD™
PAG1S controls gate
driver.
Pulse from
Secondary
available
NO
NO
YES
PWM from EZ‐PD™
PAG1P control gate
driver.
PWM from EZ‐PD™
PAG1S controls gate
driver.
Open loop
Closed loop
Fault detected
NO
YES
Open loop
Closed loop
Refer to Table 2
Fault detected
YES
Refer to Table 2
Figure 4
EZ-PD™ PAG1P operation flow chart
SS
SS
SS
TAR
TAR
TAR
Figure 5
Auto-restart
Datasheet
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Primary side startup controller
Electrical specifications
4
Electrical specifications
Table 3
Absolute maximum ratings
Description Min
Typ
Max
500
1
Unit
V
A
Details/conditions
Voltage on VDD700
Output current on GD
Voltage on AUX_IN
Voltage on CS, SS, OVP_AUX
Voltage on RT
Voltage on PULSEIN
Operating junction temperature
Storage temperature
Ambient temperature
0
1
0
0.3
0
5
40
55
40
22
8.25
8.25
8.25
125
150
105
V
°C
V
Electrostatic discharge human body
model
Electrostatic discharge charged
device model
2000
500
Except for SS and OVP_AUX.
For SS and OVP_AUX, use
0.5 V.
For RT, negative injection is
not recommended.
Pin current for latch-up
100
100
mA
Table 4
Spec ID
SID.VDD700.1 VDD700
Silicon power specifications
Parameter Description
High voltage supply 120
Min Typ Max Unit
Details/conditions
380
20
V
SID.AUXIN.1
V_AUXIN
Auxiliary supply
13
Current from
VDD700 (VDD700 =
325 V)
Current from
VDD700 (VDD700 =
325 V)
EZ-PD™ PAG1P is in
shutdown.
SID.PWR.1
I_VDD700_LATCH
50
All circuits active except
gate driver not toggling
SID.PWR.2
I_VDD700_NOGD
350
Current from
VDD700 (VDD700 =
325 V)
Current from AUXIN
(AUXIN = 12 V)
All circuits active including
gate driver toggling at
30 kHz; CL = 1 nF.
All circuits active except
gate driver not toggling
All circuits active including
gate driver toggling at
30 kHz; CL = 1 nF.
µA
SID.PWR.3
SID.PWR.4
SID.PWR.5
I_VDD700_ACTIVE
I_AUXIN_NOGD
I_AUXIN_ACTIVE
800
350
800
Current from AUXIN
(AUXIN = 12 V)
Current from
SID.PWR.6
SID.PWR.7
I_VDD700_STARTUP VDD700 when
starting up
10
VDD700 = 325 V; AUXIN = 0 V
mA
Current from
I_XCAP_DISCHARGE VDD700 while
discharging X-cap
0.48 1.7
2
Datasheet
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Primary side startup controller
Electrical specifications
Table 5
Spec ID
Undervoltage and overvoltage on VDD700
Parameter
Description
Min Typ Max Unit
Details/conditions
Undervoltage rising
threshold
Undervoltage falling
threshold
Overvoltage rising
threshold
SID.VDD700.2 V_VDD700UVRISE
SID.VDD700.3 V_VDD700UVFALL
SID.VDD700.4 V_VDD700OVRISE
SID.VDD700.5 V_VDD700OVFALL
SID.VDD700.6 T_VDD700UVDB
90 100 115
81 90 110
V
400 430 490
Overvoltage falling
threshold
Debounce time
undervoltage falling
395 420 480
30
ms
Table 6
Spec ID
Overvoltage on AUXIN
Parameter
Description
Min Typ Max Unit Details/conditions
Overvoltage
threshold on
OVP_AUX
SID.OVPAUX.1 V_OVPAUXRISE
1.1
1.2
1.26
V
Blanking time on
OVP_AUX when GD
output goes high to
low
T_OVPAUXBLK
SID.OVPAUX.3
0.9
1.1
1.3
µs
Table 7
Spec ID
Gate driver
Parameter
Description
Min Typ Max Unit Details/conditions
GDLowLevelOutput
voltage
GD High Level
Output voltage
SID.GD.1
SID.GD.2
V_GDVOL
V_GDVOH
1
2
AUXIN = 12 V and
sinking 200 mA
V
8
10
SID.GD.3
SID.GD.4
T_GDTR
T_GDTF
Rise time
Fall time
25
20
60
37
Delay time from
PULSEIN to GD,
rising edge
Delay time from
PULSEIN to GD,
falling edge
SID.GD.5
SID.GD.6
T_GDPDR
T_GDPDF
90
70
125
100
ns CL = 1 nF, AUXIN = 12 V
Table 8
Current sense fault protection
Parameter Description
V_CSTH1
Spec ID
Min Typ Max Unit Details/conditions
Threshold voltage
pulse-by-pulse
SID.CS.1
SID.CS.3
SID.CS.4
430
500
550
160
300
mV
Delay time from CS
to GD
T_CSPD
CL = 1 nF
ns
Leading edge
blanking time
T_CSLEB
150
250
Datasheet
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Primary side startup controller
Electrical specifications
Table 9
Spec ID
PULSEIN
Parameter
Description
Min Typ Max Unit Details/conditions
Minimum negative
SID.PULSEIN.1 V_PULSEINNEGAMP going pulse
amplitude
4
2
V
Maximum positive
SID. PULSEIN.2 V_PULSEINPOSAMP going pulse
amplitude
2
4
SID. PULSEIN.3 T_PULSEINPW
Pulse Width
25
200
ns
Table 10
Spec ID
Free running oscillator
Parameter
Description
Min Typ Max Unit Details/conditions
F
OSC = (I_RTCURR) *
SID.OSC.1
FOSC
Frequency
27
30
38
kHz (1/5 pF) * (1/4 V) =
30 kHz
SID.OSC.2
SID.OSC.3
DCMIN
DCMAX
Minimum duty cycle
Maximum duty cycle
3
%
70
Table 11
Spec ID
Timing resistor
Parameter
Description
Min Typ Max Unit Details/conditions
499
SID.RT.1
SID.RT.2
RT
Timing resistor
k
1%
2.4
5%
I_RTCURR
Current through RT
µA
Table 12
Spec ID
Auto-restart time
Parameter
Description
Min Typ Max Unit Details/conditions
Seco
nds
SID.AR.1
TAR
Auto-restart time
2
Table 13
Spec ID
Soft-start capacitor charging current
Parameter
Description
Min Typ Max Unit Details/conditions
Soft-start time =
I/C V/s; Maximum
µA soft-start voltage is
3.75 V and start of
soft-start is 1 V.
Current for charging
soft-start capacitor
SID.SS.1
I_SSCURR
4.8
6
Datasheet
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Primary side startup controller
Ordering information
5
Ordering information
Table 14
Ordering part number
MPN
Mode
Package type
Silicon revision
CYPAP111A3-10SXQ
CYPAP111A3-10SXQT
CYPAP112A3-10SXQ
CYPAP112A3-10SXQT
Non X-cap
10-pin SOIC
A3
X-cap
5.1
CY
Ordering code definitions
-
X
XX XX
XX
X
X
PA
P
X
X
XX
T = Tape and reel
ES (Optional field) = Pre-production Engineering Samples Only. Non orderable.
Temperature grade: Q = Extended industrial (-40°C to +105°C)
X = Pb-free
Package type: S = SOIC
Number of pins in the package
Si Rev
Application and feature combination designation
Product type: 1 = First-generation product family
Product type: P = Primary side controller
Marketing code: PA = Power adapter
Company ID: CY = Infineon
Datasheet
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Primary side startup controller
Packaging
6
Packaging
002-26358 **
Figure 6
10-pin SOIC package outline
Datasheet
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Primary side startup controller
Revision history
Revision history
Document
Date of release
version
Description of changes
Changed datasheet status to final
*D
2019-12-10
Updated SID.OSC.1 parameter min value from 24 to 27 and max value from 36 to
38 in Table 10
*E
2020-06-18
Updated to Infineon template
Changed part numbers from CYPAP111A3-10SXQES and CYPAP112A3-10SXQES
to CYPAP111A3-10SXQT and CYPAP112A3-10SXQT in “Ordering information”
on page 14
*F
2022-05-18
Datasheet
16 of 17
002-25572 Rev. *F
2022-05-18
Please read the Important Notice and Warnings at the end of this document
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IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-05-18
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
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concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
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document?
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Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
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Document reference
002-25572 Rev. *F
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
相关型号：
CYPAP112A3-10SXQ
PG-DSO-10 tray packing primary side startup controller with x-cap mode and pulse-transformer feedback for USB PD charger and adapters
INFINEON
CYPAP112A3-10SXQT
PG-DSO-10 tape and reel packing primary side startup controller with x-cap mode and pulse-transformer feedback for USB PD charger and adapters
INFINEON
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