CYPM1211-40LQXIT [INFINEON]
EZ-PD™ PMG1-S2 CYPM1211-40LQXIT是PMG1-S2的卷带封装类型选项，它支持双角色端口（DRP）USB-C PD应用并集成了一个USB全速设备控制器。;
| 型号： | CYPM1211-40LQXIT |
| 厂家： | 
Infineon |
| 描述： | EZ-PD™ PMG1-S2 CYPM1211-40LQXIT是PMG1-S2的卷带封装类型选项，它支持双角色端口（DRP）USB-C PD应用并集成了一个USB全速设备控制器。 控制器 光电二极管 |
| 文件： | 总46页 (文件大小：1548K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYPM1211
M-S2 Datasheet Power Delivery Microcontroller Gen1
EZ-PD™ PMG1-S2 Power Delivery MCU
EZ-PD™ PMG1 family general description
EZ-PD™ PMG1 (Power Delivery Microcontroller Gen1) is a family of high-voltage USB-C Power Delivery (PD)
microcontrollers (MCU). These chips include an Arm® Cortex®-M0/M0+ CPU and USB-C PD controller along with
analog and digital peripherals. EZ-PD™ PMG1 is targeted for any embedded system that provides/consumes
powers to/from a high-voltage USB-C PD port and leverages the microcontroller to provide additional control
capability. Figure 1 shows the EZ-PD™ PMG1 family segmentation.
Feature
Flash / RAM
USB, Crypto, LDO,
EZ-PD™
PMG1-S3 MCU
2x PD Sink/Source,
28V VBUS,
EZ-PD™
PMG1-S3 MCU
1x PD Sink/Source,
28V VBUS,
NFET Gate Drivers,
CAPSENSE™ , 12-bit ADC,
SCB, TCPWM
256 KB /
32 KB
97BGA
48QFN
EZ-PD™
PMG1-S2 MCU
1x PD Sink/Source,
21.5V VBUS,
USB, Crypto, LDO,
NFET Gate Drivers, 8-bit
ADC, SCB, TCPWM
128 KB /
8 KB
40QFN/42CSP
EZ-PD™
PMG1-S1 MCU
1x PD Sink/Source,
21.5V VBUS,
40QFN
LDO,
128 KB /
12 KB
PFET Gate Drivers,
8-bit ADC, SCB, TCPWM
EZ-PD™
PMG1-S0 MCU
1x PD Sink,
21.5V VBUS,
24QFN
LDO,
64 KB /
8 KB
PFET Gate Drivers, 8-bit
ADC, SCB, TCPWM
< 30
GPIO#
< 55
< 15
< 20
M0
< 25
M0+
Figure 1
EZ-PD™ PMG1 family segmentation
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
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EZ-PD™ PMG1-S2 Power Delivery MCU
EZ-PD™ PMG1 family general description
Table 1 shows the comparison of features of different MCUs of the EZ-PD™ PMG1 family.
Table 1
Comparison of features of different EZ-PD™ PMG1 family MCUs
Subsystem
or range
EZ-PD™
EZ-PD™
EZ-PD™
EZ-PD™
Item
PMG1-S0
PMG1-S1
PMG1-S2
PMG1-S3
CPU &
Memory
Core
Max Freq (MHz)
Flash (KB)
SRAM (KB)
Power Delivery
Ports
Arm®Cortex®-M0 Arm®Cortex®-M0 Arm®Cortex®-M0 Arm® Cortex®-M0+
48
64
8
48
128
12
1
48
128
8
48
256
32
Subsystem
Power
Delivery
1
1
1 port for 48-QFN
2 ports for 97-BGA
Role
Sink
DRP
DRP
DRP
MOSFET Gate
Drivers
1x PFET
2x PFET
2x NFET
Flexible 2x NFET
Fault Protections
VBUS OVP and
UVP
VBUS OVP, UVP, VBUS OVP, UVP,
VBUS OVP, UVP,
and OCP
SCP and RCP
(for Source
Configuration
only)
and OCP
SCP and RCP
(for Source
Configuration
only)
and OCP
USB
Integrated Full
Speed
No
No
Yes
Yes
USB 2.0 Device
with Billboard
Class support
Voltage
Range
Supply (V)
VDDD (2.7 - 5.5)
VBUS (4 - 21.5)
VSYS (2.75 - 5.5)
VBUS (4 - 21.5)
VSYS (2.7 - 5.5)
VBUS (4 - 21.5)
VSYS (2.8–5.5)
VBUS (4–28)
IO (V)
SCB (configurable
as I2C/UART/SPI)
1.71 - 5.5
2
1.71 - 5.5
4
1.71 - 5.5
4
1.71 – 5.5
Digital
7 for 48-QFN (out of
which only 5 can be
configured as SPI
and UART)
8 for 97-BGA
TCPWM Block
(configurable as
timer, counter or
pulse width
4
2
4
7 for 48-QFN
8 for 97-BGA
modulator)
Hardware
Authentication
Block (Crypto)
No
No
Yes
Yes (AES-128,
(AES-128/192/25 SHA2-256, TRNG,
6, SHA1,
SHA2-224,
SHA2-256, PRNG,
CRC)
Vector Unit)
Analog
ADC
2x 8-bit SAR
Yes
1x 8-bit SAR
Yes
2x 8-bit SAR
2x 8-bit SAR
1x 12-bit SAR
On-chip
Temperature
Sensor
Yes
Yes
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
EZ-PD™ PMG1 family general description
Table 1
Comparison of features of different EZ-PD™ PMG1 family MCUs (continued)
Subsystem
or range
EZ-PD™
EZ-PD™
EZ-PD™
EZ-PD™
Item
PMG1-S0
PMG1-S1
PMG1-S2
PMG1-S3
Direct
Memory
Access
(DMA)
DMA
No
No
No
Yes
GPIO
Max # of I/O
12(10+2 OVT)
17(15+2 OVT)
20(18+2 OVT)
26 (24+2 OVT) for
48-QFN
50 (48+2 OVT) for
97-BGA
Charging
Charging Source
Charging Sink
ESD Protection
-
BC 1.2, AC
BC 1.2, AC
BC 1.2, AC
BC 1.2, AC
BC 1.2, AC, AFC and
Quick Charge 3.0
Standards
BC 1.2, Apple
Charging (AC)
BC 1.2, AC
ESD
Protection
Yes (Up to ± 8-kV
contact
Yes (HBM and
CDM)
Yes (Up to ± 8-kV Yes (HBM and CDM)
contact
discharge, up to
±15-kV air
discharge, up to
±15-kV air
discharge,human
body model
discharge,
Human body
model and
(HBM), and
charged device
model (CDM))
charged device
model)
Packages
Package Options 24-QFN (4x4 mm, 40-QFN (6×6 mm, 40-QFN(6×6 mm, 48-QFN (6x6 mm,
0.5-mm pitch) 0.5-mm pitch) 0.5-mm pitch) 0.5-mm pitch)
42-CSP(2.63x3.18 97-BGA (6x6 mm,
mm, 0.4 mm
pitch)
0.5 mm and
0.65 mm pitch)
The rest of this document discusses the EZ-PD™ PMG1-S2 device in detail.
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
EZ-PD™ PMG1-S2 general description
EZ-PD™ PMG1-S2 general description
EZ-PD™ PMG1-S2 has 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a crypto engine for
authentication, a 20V-tolerant regulator, and a pair of FETs to switch a 5 V (VCONN) supply. EZ-PD™ PMG1-S2 also
integrates two pairs of gate drivers to control external VBUS FETs and system level ESD protection. EZ-PD™
PMG1-S2 is available in 40-QFN and 42-CSP package.
Features
• Type-C and USB PD support
- Supports one USB Type-C port
- Integrated USB Power Delivery 3.0 support
- Integrated USB PD BMC transceiver
- Integrated VCONN FETs
- Configurable resistors RP and RD
- Dead battery detection support
- Integrated fast role swap and extended data messaging
- Integrated hardware based overcurrent protection (OCP) and overvoltage protection (OVP)
• 32-bit MCU subsystem
- 48-MHz ARM® Cortex®-M0 CPU
- 128-KB Flash
- 8-KB SRAM
• Integrated digital blocks
- Hardware crypto block enables authentication
- Full-Speed USB device controller supporting Billboard Device Class
- Integrated timers and counters to meet response times required by the USB PD protocol
- Four run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART func-
tionality
• Clocks and oscillators
- Integrated oscillator eliminating the need for external clock
• Power
- VSYS(2.7 V–5.5 V)
- VBUS (4.0 V–21.5 V)
- 2x integrated dual-output gate drivers for external VBUS FET switch control
- Independent supply voltage pin for GPIO that allows 1.71 V to 5.5 V signaling on the I/Os
- Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
• System-level ESD protection
- On CC, SBU, USBDP, USBDM, and VBUS pins
- ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based on IEC61000-4-2 level 4C
• Packages
- 40-pin QFN and 42-ball CSP
- Supports industrial temperature range (–40°C to +105°C)
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
Block diagram
Block diagram
Color Key:Power Modes
Active/Sleep
EZ-PD™ PMG1-S2 MCU
CYPM1211-40LQXI
Deep Sleep
System Resources
Power
Clocks
ILO IMO
Sleep Control
Clock Control
WDT
POR
REF
PWRSYS
Authentication
WIC
Test
Test Mode Entry
Digital DFT
Reset
Reset Control
USB PD Subsystem
XRES
Analog DFT
CPU Subsystem
VBUS Under Voltage/
Over Voltage
SWD/TC
Cortex M0
48 MHz
FAST MUL
NVIC, IRQMUX
SPCIF
Flash
128 KB
Read Accelerator
SRAM
8 KB
SRAM Controller
FS
PHY
ROM
8 KB
ROM Controller
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EZ-PD™ PMG1-S2 Power Delivery MCU
Table of contents
Table of contents
EZ-PD™ PMG1 family general description.............................................................................................1
EZ-PD™ PMG1-S2 general description ..................................................................................................4
Features ...........................................................................................................................................4
Block diagram...................................................................................................................................5
Table of contents...............................................................................................................................6
1 Development support .....................................................................................................................8
1.1 Documentation .......................................................................................................................................................8
1.2 Online ......................................................................................................................................................................8
1.3 Tools ........................................................................................................................................................................8
1.4 Eclipse IDE for ModusToolbox™ .............................................................................................................................9
2 Functional overview .....................................................................................................................10
2.1 CPU and memory subsystem ...............................................................................................................................10
2.1.1 CPU .....................................................................................................................................................................10
2.1.2 Flash ...................................................................................................................................................................10
2.1.3 SROM ..................................................................................................................................................................10
2.2 Crypto block..........................................................................................................................................................10
2.3 Integrated billboard device..................................................................................................................................10
2.4 USB PD subsystem (USB PD SS)...........................................................................................................................10
2.5 Full-speed USB subsystem ...................................................................................................................................11
2.6 Peripherals ............................................................................................................................................................11
2.6.1 Serial communication blocks (SCB)..................................................................................................................11
2.6.2 Timer/counter/PWM block (TCPWM) ................................................................................................................12
2.7 GPIO.......................................................................................................................................................................12
3 Power systems overview ...............................................................................................................13
4 Pinouts ........................................................................................................................................14
5 Application diagrams ....................................................................................................................18
6 Electrical specifications.................................................................................................................21
6.1 Absolute maximum ratings ..................................................................................................................................21
6.2 Pin based absolute maximum ratings .................................................................................................................22
6.3 Device-level specifications ...................................................................................................................................24
6.3.1 I/O .......................................................................................................................................................................26
6.3.2 XRES....................................................................................................................................................................28
6.4 Digital peripherals.................................................................................................................................................28
6.4.1 Pulse width modulation (PWM) for GPIO pins..................................................................................................28
6.4.2 I2C .......................................................................................................................................................................29
6.5 System resources..................................................................................................................................................30
6.5.1 Power-on reset (POR) with brown out SWD interface......................................................................................30
6.5.2 Internal main oscillator .....................................................................................................................................32
6.5.3 Internal low-speed oscillatorpower down .......................................................................................................33
6.5.4 Gate driver specifications..................................................................................................................................34
6.5.5 SBU .....................................................................................................................................................................35
6.5.6 Charger detect ...................................................................................................................................................35
6.5.7 Analog to digital converter................................................................................................................................36
6.5.8 Memory...............................................................................................................................................................38
7 Ordering information ....................................................................................................................39
7.1 Ordering code definitions.....................................................................................................................................39
8 Packaging ....................................................................................................................................40
9 Acronyms.....................................................................................................................................42
10 Document conventions................................................................................................................44
10.1 Units of measure .................................................................................................................................................44
Datasheet
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Table of contents
Revision history ..............................................................................................................................45
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
Development support
1
Development support
The EZ-PD™ PMG1 family has a rich set of documentation, development tools, and online resources to assist you
during your development process. Visit EZ-PD™ PMG1 MCU webpage to find out more.
1.1
Documentation
A suite of documentation supports the EZ-PD™ PMG1 family to ensure that you can find answers to your questions
quickly. This section contains a list of some of the key documents.
Software user guide: A step-by-step guide for using ModusToolbox™ software. The software user guide shows
you how ModusToolbox™ software build process works in detail, how to use source control with ModusToolbox™
software, and much more.
Component datasheets: The flexibility of EZ-PD™ PMG1 allows the creation of new peripherals (components)
long after the device has gone into production. Component data sheets provide all the information needed to
select and use a particular component, including functional description, API documentation, example codes, and
AC/DC specifications.
Application notes: This includes the getting started application note and the hardware design guidelines.
Technical reference manual: The technical reference manual (TRM) contains all the technical detail you need
to use a EZ-PD™ PMG1 device, including a complete description of all EZ-PD™ PMG1 registers. The TRM is available
in the Documentation section at EZ-PD™ PMG1 MCU webpage.
1.2
Online
In addition to print documentation, the EZ-PD™ PMG1 MCU forums connect you with fellow users and experts
in PMG1 from around the world, 24 hours a day, 7 days a week.
1.3
Tools
With industry standard cores, programming, and debugging interfaces, the EZ-PD™ PMG1 family is part of a devel-
opment tool ecosystem.
Visit us at ModusToolbox™ software for the latest information on the revolutionary, easy to use Eclipse IDE for
ModusToolbox™, supported third party compilers, programmers, debuggers, and development kits.
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Development support
1.4
Eclipse IDE for ModusToolbox™
ModusToolbox™ is an Eclipse-based development environment on Windows, macOS, and Linux platforms that
includes the Eclipse IDE for ModusToolbox™. The Eclipse IDE for ModusToolbox™ brings together several device
resources, middleware, and firmware to build an application. Using ModusToolbox™ software, you can enable
and configure device resources and middleware libraries, write C/C++/assembly source code, and program and
debug the device.
For additional details on using the ModusToolbox™ software, refer to AN232553 - Getting started with EZ-PD™
PMG1 MCU on ModusToolbox™ software and the documentation and help integrated into ModusToolbox™
software. As Figure 2 shows, with the Eclipse IDE for ModusToolbox™, you can:
1. Create a new application based on a list of template applications, filtered by kit or device, or browse the col-
lection of code examples online.
2. Configure device resources in Device Configurator to build your hardware system design in the workspace.
3. Add software components or middleware.
4. Develop your application firmware.
Figure 2
Eclipse IDE for ModusToolbox™ and middleware
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EZ-PD™ PMG1-S2 Power Delivery MCU
Functional overview
2
2.1
2.1.1
Functional overview
CPU and memory subsystem
CPU
The Cortex®-M0 CPU in EZ-PD™ PMG1-S2 is part of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2
instruction set. The Infineon implementation includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a
Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing
power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex®-M0 CPU
provides a nonmaskable interrupt (NMI) input, which is made available to the user when it is not in use for system
functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configu-
ration used for EZ-PD™ PMG1-S2 has four break-point (address) comparators and two watchpoint (data) compar-
ators.
2.1.2
Flash
The EZ-PD™ PMG1-S2 device has a flash module with two banks of 64 KB flash, a flash accelerator, tightly coupled
to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1
wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85%
of single-cycle SRAM access performance on average.
2.1.3
SROM
A supervisory ROM that contains boot and configuration routines is provided.
2.2
Crypto block
EZ-PD™ PMG1-S2 integrates a crypto block for hardware assisted authentication of firmware images. It also
supports field upgradeability of firmware in a trusted ecosystem. The EZ-PD™ PMG1-S2 crypto block provides
cryptography functionality. It includes hardware acceleration blocks for advanced encryption standard (AES)
block cipher, secure hash algorithm (SHA-1 and SHA-2), cyclic redundancy check (CRC) and pseudo random
number generation.
2.3
Integrated billboard device
EZ-PD™ PMG1-S2 integrates a complete full speed USB 2.0 device controller capable of functioning as a Billboard
class device. The USB 2.0 device controller can also support other device classes.
2.4
USB PD subsystem (USB PD SS)
The USB PD subsystem contains all of the blocks related to USB Type-C and Power Delivery. The subsystem
consists of the following:
• Biphase marked coding (BMC) PHY: USB PD Transceiver with fast role swap (FRS) transmit and detect
• VCONN power FETs for the CC lines
• Analog crossbar to switch between the SBU1/SBU2 and AUX_P/AUX_N pins
• Programmable pull-up and pull-down termination on the AUX_P/AUX_N pins
• Hot plug detect (HPD) processor
• VBUS_C regulator (20V LDO)
• Power switch between VSYS supply and VBUS_C regulator output
• VBUS_C overvoltage (OV) and undervoltage (UV) detectors
• Current sense amplifier (CSA) for overcurrent detection
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EZ-PD™ PMG1-S2 Power Delivery MCU
Functional overview
• Gate drivers for VBUS_P and VBUS_C external Power FETs
• VBUS_C discharge switch
• Charger detection/Emulation for USB BC1.2 and other proprietary protocols
• Two instances of 8-bit SAR ADCs
• 8-kV IEC ESD Protection on the following pins: VBUS_C, CC1, CC2, SBU1, SBU2, USBDP, USBDM
The EZ-PD™ PMG1-S2 USB PD subsystem interfaces to the pins of a USB Type-C connector. It includes a USB
Type-C baseband transceiver and physical-layer logic. This transceiver performs the BMC and the 4b/5b encoding
and decoding functions as well as integrating the 1.2-V analog front end (AFE). This subsystem integrates the
required terminations to identify the role of the EZ-PD™ PMG1-S2 device, including RP and RD for UFP/DFP roles.
It also integrates power FETs for supplying VCONN power to the CC1/CC2 pins from the VCONN_Source pin. The
analog crossbar enables connecting either of the SBU1/SBU2 pins to either of the AUX_P/AUX_N pins to support
DisplayPort sideband signaling. The integrated HPD processor can be used to control or monitor the HPD signal
of a DisplayPort source or sink.
The overvoltage/undervoltage (OV/UV) block monitors the VBUS_C supply for programmable overvoltage and
undervoltage conditions. The CSA amplifies the voltage across an external sense resistor, which is proportional
to the current being drawn from the external DC-DC VBUS supply converter. The CSA output can either be
measured with an ADC or configured to detect an overcurrent condition. The VBUS_P and VBUS_C gate drivers
control the gates of external power FETs for the VBUS_C and VBUS_P supplies. The gate drivers can be configured
to support both P and N type external power FETs. The gate drivers are configured by default for nFET devices.
In applications using pFETs, the gate drivers must be appropriately configured. The OV/UV and CSA blocks can
generate interrupts to automatically turn off the power FETs for the programmed overvoltage and overcurrent
conditions. The VBUS_C discharge switch allows for discharging the VBUS_C line through an external resistor.
The USB PD subsystem also contains two 8-bit 125 ksps successive approximation register (SAR) ADCs for analog
to digital conversions. The voltage reference for the ADCs is generated from the VDDD supply. Each ADC includes
an 8-bit DAC and a comparator. The DAC output forms the positive input of the comparator. The negative input
of the comparator is from a 4-input multiplexer. The four inputs of the multiplexer are a pair of global analog
multiplex buses, an internal bandgap voltage and an internal voltage proportional to the absolute temperature.
Each GPIO pin can be connected to the global analog multiplex buses through a switch, which allows either ADC
to sample the pin voltage. When sensing the GPIO pin voltage with an ADC, the pin voltage must not exceed the
VDDIO supply value.
2.5
Full-speed USB subsystem
The FSUSB subsystem contains a full-speed USB device controller as described in the Integrated billboard
device section.
2.6
Peripherals
2.6.1
Serial communication blocks (SCB)
EZ-PD™ PMG1-S2 has four SCBs, which can be configured to implement an I2C, SPI, or UART interface. The
hardware I2C blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the
SPI mode, the SCB blocks can be configured to act as master or slave.
In the I2C mode, the SCB blocks are capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and have
flexible buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I2C
that creates a mailbox address range in the memory of EZ-PD™ PMG1-S2 and effectively reduce I2C communi-
cation to reading from and writing to an array in memory. In addition, the blocks support 128-deep FIFOs for
receive and transmit which, by increasing the time given for the CPU to read data, greatly reduce the need for
clock stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode, Fast Mode, and Fast Mode Plus devices as
defined in the NXP I2C-bus specification and user manual (UM10204).
The I2C bus I/Os are implemented with GPIO in open-drain modes.
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Functional overview
The I2C port on SCB 1-3 blocks of EZ-PD™ PMG1-S2 are not completely compliant with the I2C specification in the
following aspects:
• The GPIO cells for SCB 1's I2C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or
powered up independently of the rest of the I2C system.
• Fast Mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA
IOL with a VOL maximum of 0.6 V.
• Fast Mode and Fast Mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong
mode can help meet this spec depending on the bus load.
2.6.2
Timer/counter/PWM block (TCPWM)
EZ-PD™ PMG1-S2 has four TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator
(PWM), and quadrature decoder functionality.
2.7
GPIO
EZ-PD™ PMG1-S2 has up to 20 GPIOs (these GPIOs can be configured for GPIOs, SCB, SBU, and Aux signals) and
SWD pins, which can also be used as GPIOs. The I2C pins from SCB 0 are overvoltage-tolerant.
The GPIO block implements the following:
• Seven drive strength modes:
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL)
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode)
• Selectable slew rates for dV/dt related noise control to improve EMI
During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or
cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
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Power systems overview
3
Power systems overview
Figure 3 shows an overview of the EZ-PD™ PMG1-S2 power system requirement. EZ-PD™ PMG1-S2 shall be able
to operate from two possible external supply sources VBUS (4.0 V–21.5 V) or VSYS (2.7 V–5.5 V). The VBUS supply
is regulated inside the chip with a low-dropout regulator (LDO) down to 3.3-V level. The chip’s internal VDDD rail
is intelligently switched between the output of the VBUS regulator and unregulated VSYS. The switched supply,
VDDD is either used directly inside some analog blocks or further regulated down to VCCD which powers majority
of the core using regulators. Besides Reset mode, EZ-PD™ PMG1-S2 has three different power modes: Active,
Sleep and Deep Sleep, transitions between which are managed by the Power System. A separate power domain
VDDIO is provided for the GPIOs. The VDDD and VCCD pins, both the output of regulators are brought out for
connecting a 1-µF capacitor for the regulator stability only. These pins are not supported as power supplies.
When EZ-PD™ PMG1-S2 is powered from VSYS that is greater than 3.3 V, the dedicated USB regulator allows USB
operation.
VSYS
VBUS
Switch
LDO
OVP
1 uF
1 uF
VBUS_DISCHARGE
VBUS_C_CTRL
CSP/VBUS_P
CSN
Gate Driver
OCP
Gate Driver
VDDD
1 uF
VBUS_P_CTRL
USB Regulator
Regulator
Core
FX-USB
TX/RX
USBDP, USBDM
VCCD
1 uF
VDDIO
CC
Tx/Rx
CC1, CC2
VSS
GPIO
VSS
EZ-PD™ PMG1 - S2
Figure 3
EZ-PD™ PMG1-S2 power system block diagram
Table 2
EZ-PD™ PMG1-S2 power modes
Mode
Description
RESET
Power is valid and XRES is not asserted. An internal reset source is asserted or
SleepController is sequencing the system out of reset.
ACTIVE
SLEEP
Power is valid and CPU is executing instructions.
Power is valid and CPU is not executing instructions. All logic that is not operating
is clock gated to save power.
DEEP SLEEP
Main regulator and most hard-IP are shut off. Deep Sleep regulator powers logic,
but only low-frequency clock is available.
Datasheet
13
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Pinouts
4
Pinouts
Table 3
EZ-PD™ PMG1-S2 pin description for CYPM1211-40LQXI
40-pin
42-ball
CSP
Group
Pin name
Description
QFN
7
8
F6
D5
P1.0/UART_2_TX/SPI_2_MISO
P1.1/UART_2_RX/SPI_2_SEL
GPIO/UART_2_TX/SPI_2_MISO
GPIO/UART_2_RX/SPI_2_SEL
P1.2/UART_0_RX/
UART_3_CTS/SPI_3_MOSI/
I2C_3_SCL
P1.3/UART_0_TX/
UART_3_RTS/SPI_3_CLK/
I2C_3_SDA
GPIO/UART_0_RX/UART_3_CTS/SPI_3_MO
SI/I2C_3_SCL
9
E5
G6
GPIO/UART_0_TX/UART_3_RTS/SPI_3_CLK
/I2C_3_SDA
10
P1.6/AUX_P/UART_1_TX/
SPI_1_MISO
P1.4/SBU1/UART_3_TX/
SPI_3_MISO
P1.5/SBU2/UART_3_RX/
SPI_3_SEL
P1.7/AUX_N/UART_1_RX/
SPI_1_SEL
DisplayPort AUX_P
11
12
13
14
15
E4
F5
G5
G4
F4
signal/GPIO/UART_1_TX/SPI_1_MISO
USB Type-C SBU1
signal/GPIO/UART_3_TX/SPI_3_MISO
USB Type-C SBU2
signal/GPIO/UART_3_RX/SPI_3_SEL
DisplayPort AUX_N
signal/GPIO/UART_1_RX/SPI_1_SEL
P2.0/SWD_IO/UART_1_CTS/
SPI_1_CLK/I2C_1_SCL
GPIO / SWD_IO/UART_1_CTS/SPI_1_CLK/
I2C_1_SCL
GPIOs
and serial
interface
P2.1/SWD_CLK/UART_1_RTS/
SPI_1_MOSI/I2C_1_SDA
P2.4
GPIO/SWD_CLK/
16
23
G3
E2
UART_1_RTS/SPI_1_MOSI/ I2C_1_SDA
GPIO
24
25
D3
D2
P2.5/UART_0_TX/SPI_0_MOSI
P2.6/UART_0_RX/SPI_0_CLK
GPIO/UART_0_TX/SPI_0_MOSI
GPIO/UART_0_RX/SPI_0_CLK
P0.0/GPIO_OVT/ UART_0_CTS/
SPI_0_SEL/I2C_0_SDA
P0.0/GPIO_OVT/UART_0_CTS/SPI_0_SEL/I
2C_0_SDA/TCPWM_line_0
27
C3
P0.1/GPIO_OVT/
P0.1/GPIO_OVT/UART_0_RTS/SPI_0_MISO/
I2C_0_SCL/TCPWM_line_1
28
C2
UART_0_RTS/SPI_0_MISO/
I2C_0_SCL
34
35
A2
B2
P3.2
P3.3
GPIO/TCPWM_line_0
GPIO/TCPWM_line_1
P3.4/ UART_2_CTS/SPI_2_MOSI/
I2C_2_SDA
P3.5/ UART_2_RTS/SPI_2_CLK/
I2C_2_SCL
GPIO/UART_2_CTS/SPI_2_MOSI/I2C_2_SD
A/TCPWM_line_2
GPIO/UART_2_RTS/SPI_2_CLK/I2C_2_SCL/
TCPWM_line_3
36
37
B3
A3
38
21
22
B4
F1
E1
P3.6
GPIO
USB 2.0 DP
USB 2.0 DM
USB PD connector detect/Configuration
Channel 2
USB PD connector detect/Configuration
Channel 1
USBDP
USBDM
CC2
USB FS
3
5
B6, C5
C6, D6
USB
Type-C
CC1
Datasheet
14
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Pinouts
Table 3
Group
EZ-PD™ PMG1-S2 pin description for CYPM1211-40LQXI (continued)
40-pin
QFN
42-ball
CSP
Pin name
Description
VBUS_P_CTRL1
VBUS Gate Driver Control 1 for Producer
Switch
VBUS Gate Driver Control 0 for Producer
Switch
VBUS Gate Driver Control 1 for Consumer
Switch
VBUS Gate Driver Control 0 for Consumer
Switch
1
A5
A6
C1
C4
VBUS_P_CTRL0
VBUS_C_CTRL1
VBUS_C_CTRL0
2
VBUS
29
30
32
39
A1
A4
VBUS_DISCHARGE
CSN
CSP/VBUS_P
VBUS Discharge Control output
Current Sense Negative Input
VBUS producer input. Connect this pin to a
higher potential compared to CSN pin.
External Reset Input. Internally pulled-up to
VDDIO.
VBUS
OCP/SCP/
RCP
40
26
B5
D1
XRES
Reset
VCONN_Source
Input Supply Voltage for VCONN FETs
VCON_Source = 5.0 V–5.5 V to supply
VCONN > 4.75 V @ 1.5W VCONN_Source =
3.5 V – 5.5 V to supply VCONN > 3.00 V @ 1W
4
D4
17
18
G2
F3
VDDD
VDDIO
VDDD supply Input/Output (2.7 V–5.5 V)
1.71 V–5.5 V supply for I/Os. This supply also
powers the global analog multiplex buses.
Power
19
20
31
33
F2
G1
B1
VCCD
VSYS
VBUS
1.8-V regulator output for filter capacitor
System power supply (2.7 V–5.5 V)
VBUS Input
GND
NC
E3
E6
VSS
NC
Ground Supply (GND)
Not connected
EPAD
6
Datasheet
15
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Pinouts
Table 4
SCBs and their functionality
40-pin QFN 42-ball CSP
Port
Pin
SCB function
SPI
Pin #
27
28
7
Pin #
C3
C2
F6
D5
UART
I2C
P0.0
P0.1
P1.0
P1.1
P1.2
UART_0_CTS
UART_0_RTS
UART_2_TX
UART_2_RX
SPI_0_SEL
SPI_0_MISO
SPI_2_MISO
SPI_2_SEL
SPI_3_MOSI
I2C_0_SDA
I2C_0_SCL
-
-
8
9
E5
UART_0_RX
UART_3_CTS
I2C_3_SCL
P1.3
10
G6
UART_0_TX
UART_3_RTS
SPI_3_CLK
I2C_3_SDA
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.5
P2.6
P3.4
P3.5
12
13
11
14
15
16
24
25
36
37
F5
G5
E4
G4
F4
G3
D3
D2
B3
A3
UART_3_TX
UART_3_RX
UART_1_TX
UART_1_RX
UART_1_CTS
UART_1_RTS
UART_0_TX
UART_0_RX
UART_2_CTS
UART_2_RTS
SPI_3_MISO
SPI_3_SEL
SPI_1_MISO
SPI_1_SEL
SPI_1_CLK
SPI_1_MOSI
SPI_0_MOSI
SPI_0_CLK
SPI_2_MOSI
SPI_2_CLK
-
-
-
-
I2C_1_SCL
I2C_1_SDA
-
-
I2C_2_SDA
I2C_2_SCL
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
VBUS_P_CTRL1
VBUS_P_CTRL0
CC2
VBUS_C_CTRL0
VBUS_C_CTRL1
GPIO_OVT
GPIO_OVT
XRES
VCONN_Source
CC1
EPAD
NC
GPIO
GPIO
GPIO
GPIO
GPIO
USBDM
GPIO
10
USBDP
GPIO
Figure 4
Pinout of 40-QFN package (top view)
Datasheet
16
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Pinouts
6
5
4
3
2
1
VBUS_P_CT VBUS_P_CT
GPIO
P3.5
GPIO
P3.2
VBUS_DISC
HARGE
A
B
C
D
E
F
CSN
RL0
RL1
CSP/
VBUS_P
GPIO
P3.6
GPIO
P3.4
GPIO
P3.3
CC2
VBUS
VBUS_C_CT GPIO_OVT
GPIO_OVT VBUS_C_CT
CC1
CC1
NC
CC2
RL0
P0.0
P0.1
RL1
GPIO
P1.1
VCONN_Sou
rce
GPIO
P2.5
GPIO
P2.6
XRES
P1.6/
AUX_P
GPIO
P1.2
GPIO
P2.4
VSS
USBDM
USBDP
VSYS
GPIO
P1.0
GPIO
P2.0
VDDIO
VCCD
VDDD
P1.4/SBU1
P1.5/SBU2
P1.7/
AUX_N
GPIO
P1.3
GPIO
P2.1
G
Figure 5
Pinout of 42-WLCSP bottom (balls up) view
Datasheet
17
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Application diagrams
5
Application diagrams
Figure 6 shows a Power Sink application using EZ-PD™ PMG1-S2. In this application, the Type-C receptacle is
used for consuming power. The EZ-PD™ PMG1-S2 device negotiates power contracts with the source device
connected to the Type-C receptacle. The device also controls and drives the consumer path FETs and monitors
overvoltage/undervoltage conditions on the Type-C VBUS line.
Type-C Receptacle
VBUS
IRF7907TRPbF
Consumer Path
VBUS
Load
S
D
D
S
G
G
10F
10M
10M
100
X
29
39
VBUS_C_CTRL1
VBUS_C_CTRL0
CSN
30
32
40
CSP/VBUS_P
X
4
VCONN_Source
VBUS_DISCHARGE
CC2
X
3
5
CC2
CC1
VBUS
CC1
390pF
31
20
390pF
VBUS
VSYS
X
21
22
CYPM1211-40LQXI
USBDP
USBDM
D+ Top/Bottom
D- Top/Bottom
17
18
19
VDDD
VDDIO
VCCD
1
VBUS_P_CTRL1
VBUS_P_CTRL0
X
2
0.1uF
0.1uF
1uF
X
1.3F
26
33
XRES
8, 9, 10, 15, 16, 23, 24, 25, 27,
GND
28, 34, 35, 36, 37, 38
X
0.1F
EPAD
GPIO
SBU1 SBU2 P1.0
12 13
AUX_P AUX_N
11
14
7
X
X
X
X
X
P1.0 indicates FET type in design. Floating condition
indicates NFETs and connected to GND indicates
PFETs in provider path.
GND
Figure 6
EZ-PD™ PMG1-S2 based sink application diagram
Figure 7 illustrates the application diagram of a power source using EZ-PD™ PMG1-S2 device. In this application,
EZ-PD™ PMG1-S2 is used as DFP (power provider) only. The maximum power profile that can be supported in
power source applications is up to 20 V, 100 W. EZ-PD™ PMG1-S2 can drive both types of FETs and the state of
GPIO P1.0 (floating or grounded) indicates the type of FET (N-MOS or P-MOS FET) being used in the power
provider path. To ensure quick discharge of VBUS when the power adapter cable is detached, a discharge path
is provided with a resistor connected to the VBUS_DISCHARGE pin of the EZ-PD™ PMG1-S2 device.
The VBUS voltage on the Type-C port is monitored using internal circuits to detect under-voltage and overvoltage
conditions. VBUS overcurrent can also be detected by sensing the current through the 10-mΩ sense resistor
connected between "CSN" and "CSP/VBUS_P" pins. Any of these faults on the VBUS line can further be used to
turn off the VBUS provider path using the provider path FETs which are controlled by high-voltage gate driver
outputs (VBUS_P_CTRL0 and VBUS_P_CTRL1 pins).
The EZ-PD™ PMG1-S2 device is also capable of supporting proprietary charging protocols over the D+ and D- lines
of the Type-C receptacle. By providing a 5-V source at the VCONN_Source pin of the EZ-PD™ PMG1-S2 device, the
device also becomes capable of delivering VCONN supply over either the CC1 or CC2 pins of the Type-C connector.
Datasheet
18
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Application diagrams
Type-C Receptacle
DC/DC
VBUS_OC
VBUS_IN
VBUS_OUT
OR
IRF7907TRPbF
VBUS
AC-DC
Secondary
(5-20V)
S
S
D
D
10 m
G
G
Provider Path
10F
10M
10M
100
39
2
CSN
VBUS_P_CTRL0
VBUS_P_CTRL1
1
40
31
CSP/VBUS_P
VBUS
32
29
VBUS_DISCHARGE
VBUS_C_CTRL1
X
1F
50V
30
VBUS_C_CTRL0
X
5V
21
USBDP
USBDM
D+ Top/Bottom
4
22
VCONN_Source
VSYS
D- Top/Bottom
CC2
1 µF
20
X
3
5
CC2
CC1
CYPM1211-40LQXI
17
18
19
VDDD
CC1
VBUS_OUT
390pF
390pF
VDDIO
VCCD
100K
1uF
23
0.1F
1.3F
P2.4
26
33
XRES
GND
10K
0.1F
EPAD
GPIO
X
8, 9, 10, 15, 16, 24, 25, 27, 28,
34, 35, 36, 37, 38
SBU1 SBU2 P1.0
12 13
AUX_P AUX_N
11 14
7
X
X
X
X
X
P1.0 indicates FET type in design. Floating condition
indicates NFETs and connected to GND indicates
PFETs in provider path.
GND
Figure 7
EZ-PD™ PMG1-S2 based source application diagram
Datasheet
19
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Application diagrams
Figure 8 illustrates a DRP application diagram using EZ-PD™ PMG1-S2 device. The Type-C port can be used as a
power provider or a power consumer.
VINT20
IRF7907TRPbF
Consumer Path
Load
D
S
S
D
G
G
10M
10M
VBUS
VBUS_SUPPLY
Provider Path
1uF
IRF7907TRPbF
DC/DC
S
D
D
S
10 m
10uF
G
G
10M
10M
2
1
39
CSN
VBUS_P_CTRL0 VBUS_P_CTRL1
VBUS_C_CTRL1
VBUS
29
Type-C Receptacle
VBUS
31
VBUS
40
V3P3 and V5P0 are 3.3V and 5V supplies coming
from the board/kit.
CSP/VBUS_P
V3P3
20
VSYS
100
8, 9, 10, 15, 16, 23, 24, 25, 27,
30
32
0.1uF
0.1uF
1uF
VBUS_C_CTRL0
28, 34, 35, 36, 37, 38
GPIO
X
VBUS_DISCHARGE
CC2
VDDD
3
5
17
CC2
CC1
VDDD
CYPM1211-40LQXI
CC1
V5P0
18
4
VDDIO
0.1uF
0.1uF
1uF
VCONN_Source
390pF
1 µF
390pF
12
SBU1
SBU2
X
13
X
21
USBDP
D+ Top/Bottom
D- Top/Bottom
22
26
11
USBDM
XRES
AUX_P
AUX_N
X
14
X
0.1uF
33
GND
P1.0
VCCD
19
GND
EPAD
7
X
1uF
P1.0 indicates FET type in design. Floating condition
indicates NFETs and connected to GND indicates
PFETs in provider path.
Figure 8
EZ-PD™ PMG1-S2 based DRP application diagram
Datasheet
20
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6
Electrical specifications
6.1
Table 5
Absolute maximum ratings
Absolute maximum ratings[1]
Parameter
VSYS_MAX
Description
Min Typ
Max
Units
Details/conditions
Digital supply relative to VSS
–
–
–
–
6
6
V[2] Absolute max
V
VCONN_SOURCE_MAX Max supply voltage relative to
VSS
VBUS_MAX_ON
Max supply voltage relative to
VSS, VBUS regulator enabled
–
–
–
–
26
V
V
VBUS_MAX_OFF
Max supply voltage relative to
VSS, VBUS regulator enabled
100% of the time
24.5
Max supply voltage relative to
–
–
–
26
6
V
V
V
SS, VBUS regulator enabled 25%
of the time
VDDIO_MAX
Max supply voltage relative to
VSS
–
VGPIO_ABS
VGPIO_OVT_ABS
IGPIO_ABS
GPIO voltage
–0.5[3]
–0.5
–25
–
–
–
–
–
VDDIO + 0.5
V
V
OVT GPIO voltage
Maximum current per GPIO
6
25
6
mA
V
VCC_ABS
Max voltage on CC1 and CC2
pins
IGPIO_INJECTION
ESD_HBM
GPIO injection current, Max for –0.5
VIH > VDDD, and Min for VIL < VSS
–
–
–
0.5
–
mA Absolute max, current
injected per pin
Electrostatic discharge human 2200
body model (ESD-HBM)
V
–
ESD_CDM
Electrostatic discharge charged 500
device model (ESD-CDM)
–
V
–
LU
Pin current for latch-up
–100
8000
–
–
100
–
mA Tested at 125°C
ESD_IEC_CON
Electrostatic discharge
IEC61000-4-2
V
Contact discharge on CC1,
CC2, VBUS, USBDP,
USBDM, SBU1 and SBU2
pins
ESD_IEC_AIR
Electrostatic discharge
IEC61000-4-2
15000
–
–
V
Air discharge for CC1, CC2,
VBUS, USBDP, USBDM,
SBU1 and SBU2 pins
Notes
1. Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device.
Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The
maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the
device may not operate to specification.
2. All voltages are relative to Ground unless otherwise specified.
3. In a system, if the negative spike exceeds the minimum voltage specified here, it is recommended to add
Schottky diode to clamp the negative spike.
Datasheet
21
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.2
Pin based absolute maximum ratings
Table 6
Pin based absolute maximum ratings
Absolute Absolute
Pin
Pin
S. No.
Name minimum maximum
Remarks
(40 QFN) (42 CSP)
(V)
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
–
(V)
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
26
1
2
3
4
5
6
7
8
7
8
9
F6
D5
E5
G6
E4
P1.0
P1.1
P1.2
P1.3
P1.6
P1.4
P1.5
P1.7
P2.0
P2.1
P2.4
P2.5
P2.6
P0.0
P0.1
P3.2
P3.3
P3.4
P3.5
P3.6
USBDP
USBDM
CC2
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
Maximum voltage cannot exceed VDDIO + 0.5
–
10
11
12
13
14
15
16
23
24
25
27
28
34
35
36
37
38
21
22
3
F5
G5
G4
F4
G3
E2
D3
D2
C3
C2
A2
B2
B3
A3
B4
F1
E1
B6, C5
C6, D6
A5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
5
1
CC1
VBUS_P
_CTRL1
–
-0.5
–
–
26
27
28
29
2
A6
C1
C4
A1
VBUS_P
_CTRL0
VBUS_C
_CTRL1
VBUS_C
_CTRL0
VBUS_-
DISCHA
RGE
-0.5
-0.5
-0.5
–
26
26
26
26
–
–
–
–
29
30
32
30
31
39
40
A4
B5
CSN
–
–
26
26
–
–
CSP/VB
US_P
32
26
D1
XRES
-0.5
6
Maximum voltage cannot exceed VDDIO + 0.5
Datasheet
22
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 6
S. No.
33
Pin based absolute maximum ratings (continued)
Absolute Absolute
Pin
Pin
Name minimum maximum
Remarks
(40 QFN) (42 CSP)
(V)
(V)
4
D4
VCONN
_Source
–
6
–
34
35
36
37
38
39
40
41
17
18
19
20
31
33
EPAD
6
G2
F3
F2
G1
B1
VDDD
VDDIO
VCCD
VSYS
VBUS
VSS
–
–
–
–
–
–
–
–
6
VDDD
1.95
6
26
–
This is an output only pin
–
This is an output only pin
–
–
–
–
–
E3
E6
VSS
NC
–
–
Datasheet
23
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.3
Device-level specifications
All specifications are valid for –40°C TA 105°C and TJ 120°C, except where noted.
Table 7 DC specifications
Spec ID
SID.PWR#1
Parameter
VSYS
SID.PWR#1_A VSYS
SID.PWR#23 VCONN
Description
Min Typ Max Units
Details/conditions
UFP Mode.
DFP/DRP or Gate Driver Modes
–
–
–
2.7
3
–
–
–
5.5
5.5
5.5
V
V
V
Power supply
input voltage
2.7
SID.PWR#13 VDDIO
IO supply voltage 1.71
–
1.8
5.5[4]
–
V
V
2.7 V < VDDD < 5.5 V
–
SID.PWR24
VCCD
Output voltage for
core logic
–
SID.PWR#4
IDD
Supply current
–
25
–
mA From VSYS or VBUS
VBUS = 5 V,
TA = 25°C / VSYS = 5 V, TA = 25°C
FS USB, CC IO in Tx or Rx, no I/O
sourcing current, 2 SCBs at 1
Mbps, CPU at 24 MHz.
SID.PWR#1_B VSYS
SID.PWR#1_C VSYS
SID.PWR#1_D VSYS
Power supply for
USB operation
Power supply for
USB operation
Power supply for
charger
detect/emulation
operation
4.5
–
–
–
5.5
3.45
5.5
V
V
V
USB configured, USB Regulator
enabled
USB configured, USB Regulator
disabled
3.15
3.15
–40°C to +85°C TA
SID.PWR#27 VBUS
SID.PwR#28 VBUS
Power supply
input voltage
Power supply
input voltage for
USB operation
3.5
4.5
–
–
21.5
21.5
V
V
FS USB disabled. Total current
consumption from VBUS <15 mA.
FS USB configured, USB Regulator
disabled
SID.PWR#30 VBUS_P
SID.PWR#15 Cefc
Power supply
input voltage
External regulator
voltage bypass for
VCCD
Power supply
decoupling
capacitor for VSYS
4.00
1
–
21.5
1.6
V
–
1.3
µF X5R ceramic or better
µF X5R ceramic or better
SID.PWR#16 Cexc
0.8
1
–
Sleep Mode. VSYS = 2.7 V to 5.5 V. Typical values measured at VDD = 3.3 V and TA = 25°C.
SID25A
IDD20A
CC, I2C, WDT
wakeup on.
IMO at 48 MHz.
–
3.5
–
mA VSYS = 3.3 V, TA = 25°C, All blocks
except CPU are on, CC IO on, USB
in Suspend Mode, no I/O sourcing
current
Deep Sleep Mode
Note
4. If VDDIO > VDDD, GPIO P2.4 cannot be used. It must be left unconnected. See Table 3 for pin numbers.
Datasheet
24
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 7
Spec ID
DC specifications (continued)
Parameter
Description
Min Typ Max Units
Details/conditions
SID_DS
IDD_DS
VSYS = 3.0 to 3.6 V.
–
30
–
µA Power Source = VSYS, DFP Mode,
Type-C Not Attached. CC Attach,
I2C and WDT enabled for Wakeup.
CC Attach, I2C,
WDT Wakeup on.
XRES Current
SID307
IDD_XR
Supply current
while XRES
asserted.
–
30
–
µA Power Source = VSYS = 3.3 V,
Type-C device not attached,
TA = 25°C
This does not
include current
drawn due to the
XRES internal
pull-up resistor.
Table 8
AC specifications (guaranteed by characterization)
Spec ID
SID.CLK#4
SID.PWR#20 TSLEEP
SID.PWR#21 TDEEPSLEEP
SID.XRES#5 TXRES
Parameter
FCPU
Description
CPU input frequency
Wakeup from sleep mode
Wakeup from Deep Sleep mode
External reset pulse width
Min Typ Max Units Details/conditions
DC
–
–
0
–
–
5
48
–
MHz All VDDD
µs
µs
–
–
–
5
35
–
µs All VDDIO
ms
SYS.FES#1
T_PWR_RDY
Power-up to “Ready to accept
–
25
–
I2C/CC command”
Datasheet
25
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.3.1
I/O
Table 9
I/O DC specifications
Details/
Spec ID
Parameter
Description
Min
Typ Max
Units
conditions
Input voltage HIGH
threshold
Input voltage LOW
threshold
LVTTL input,
VDDIO < 2.7 V
LVTTL input,
VDDIO < 2.7 V
LVTTL input,
VDDIO 2.7 V
LVTTL input,
VDDIO 2.7 V
0.7 ×
SID.GIO#37 VIH_CMOS
SID.GIO#38 VIL_CMOS
SID.GIO#39 VIH_VDDIO2.7-
SID.GIO#40 VIL_VDDIO2.7-
SID.GIO#41 VIH_VDDIO2.7+
SID.GIO#42 VIL_VDDIO2.7+
SID.GIO#33 VOH_3V
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
V
V
V
CMOS input
VDDIO
0.3 ×
VDDIO
–
CMOS input
–
0.7 ×
VDDIO
–
0.3 ×
VDDIO
–
–
–
–
2.0
–
–
0.8
–
VDDIO –
0.6
VDDIO –
0.5
IOH = 4 mA at
3 V VDDIO
IOH = 1 mA at
1.8 V VDDIO
IOL = 4 mA at
1.8 V VDDIO
Output voltage HIGH level
Output voltage HIGH level
Output voltage LOW level
SID.GIO#34 VOH_1.8V
SID.GIO#35 VOL_1.8V
–
–
0.6
I
OL = 4 mA at
SID.GIO#36 VOL_3V
Output voltage LOW level
–
–
0.6
V
3 V VDDIO for SBU
and AUX pins
SID.GIO#5
SID.GIO#6
RPU
RPD
Pull-up resistor value
Pull-down resistor value
3.5
3.5
5.6
5.6
8.5
8.5
kΩ +25°C TA, all VDDIO
kΩ +25°C TA, all VDDIO
+25°C TA, all
Input leakage current
(absolute value)
VDDIO.
SID.GIO#16 IIL
–
–
2
nA
Guaranteed by
characterization.
All VDDIO, all
packages, all I/Os
except SBU and
SID.GIO#17 CPIN
Max pin capacitance
–
3.0
7
pF
AUX.
Guaranteed by
characterization.
All VDDIO, all
packages, SBU
pF pins only.
Guaranteed by
characterization.
All VDDIO, all
packages, AUX
pF pins only.
Guaranteed by
characterization.
SID.GIO#17A CPIN_SBU
SID.GIO#17B CPIN_AUX
Max pin capacitance
Max pin capacitance
–
–
16
12
18
14
Datasheet
26
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 9
Spec ID
I/O DC specifications (continued)
Details/
Parameter
Description
Min
Typ Max
Units
conditions
Input hysteresis, LVTTL
Guaranteed by
SID.GIO#43 VHYSTTL
SID.GIO#44 VHYSCMOS
15
40
–
–
–
mV
VDDIO 2.7 V
characterization
VDDIO < 4.5 V.
mV Guaranteed by
characterization.
0.05 ×
VDDIO
Input hysteresis CMOS
Current through
protection diode to
VDDIO/Vss
Maximum total sink chip
current
Guaranteed by
SID69
IDIODE
–
–
–
–
100
85
µA characterization
Guaranteed by
mA
SID.GIO#45 ITOT_GPIO
OVT
characterization
Input current when Pad >
VDDIO for OVT inputs
Per I2C
µA
SID.GIO#46 IIHS
–
–
10.00
specification
Table 10
I/O AC specifications
(guaranteed by characterization)
Spec ID
SID70
SID71
Parameter
TRISEF
TFALLF
Description
Rise time in Fast Strong mode
Fall time in Fast Strong mode
Min Typ Max Units
Details/conditions
2
2
–
–
12
12
ns 3.3 V VDDIO, Cload = 25 pF
ns 3.3 V VDDIO, Cload = 25 pF
6.3.2
XRES
Table 11
XRES DC specifications
Details/
Units
Spec ID
Parameter Description
Min
Typ
–
Max
conditions
Input voltage HIGH
threshold on XRES pin
Input voltage LOW
threshold on XRES pin
Input capacitance on
XRES pin
Input voltage hysteresis
on XRES pin
0.7 ×
VDDIO
SID.XRES#1 VIH_XRES
SID.XRES#2 VIL_XRES
SID.XRES#3 CIN_XRES
SID.XRES#4 VHYSXRES
–
V
V
CMOS input
CMOS input
0.3 ×
VDDIO
–
–
–
–
Guaranteed by
–
7
–
pF
mV
characterization
0.05 ×
VDDIO
Guaranteed by
characterization
6.4
Digital peripherals
The following specifications apply to the timer/counter/PWM peripherals in the timer mode.
6.4.1
Pulse width modulation (PWM) for GPIO pins
Table 12
PWM AC specifications
(guaranteed by characterization)
Spec ID
SID.TCPWM.3
SID.TCPWM.4
Parameter
Description
Min Typ Max Units
Details/conditions
Fc max = CLK_SYS.
Maximum = 48 MHz.
TCPWMFREQ Operating frequency
–
–
–
Fc MHz
TPWMENEXT Input trigger pulse width 2/Fc
–
ns For all trigger events
Datasheet
27
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 12
PWM AC specifications
(guaranteed by characterization) (continued)
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.5
TPWMEXT
Output trigger pulse width 2/Fc
–
–
ns
Minimum time between
successive counts
Minimum pulse width of
PWM output
SID.TCPWM.5A TCRES
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
ns
ns
SID.TCPWM.5B PWMRES
Minimum pulse width
Quadrature inputs
resolution
SID.TCPWM.5C QRES
1/Fc
–
–
ns between
quadrature-phase inputs
Datasheet
28
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.4.2
Table 13
I2C
Fixed I2C DC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
conditions
SID149
SID150
SID151
SID152
II2C1
II2C2
II2C3
II2C4
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
I2C enabled in Deep Sleep mode
–
–
–
–
–
–
–
–
60
185
390
1.4
µA
µA
µA
µA
–
–
–
–
Table 14
Fixed I2C AC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
Mbps
conditions
SID153
FI2C1
Bit rate
–
–
1
–
Table 15
Fixed UART DC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
conditions
SID160
SID161
IUART1
IUART2
Block current consumption at 100 Kb/s
Block current consumption at 1000 Kb/s
–
–
–
–
125
312
µA
µA
–
–
Table 16
Fixed UART AC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
Mbps
conditions
SID162
FUART
Bit rate
–
–
1
–
Table 17
Fixed SPI DC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
conditions
SID163
SID164
SID165
ISPI1
ISPI2
ISPI3
Block current consumption at 1 Mb/s
Block current consumption at 4 Mb/s
Block current consumption at 8 Mb/s
–
–
–
–
–
–
360
560
600
µA
µA
µA
–
–
–
Table 18
Fixed SPI AC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
MHz
conditions
SPI operating frequency
(Master; 6X oversampling)
SID166
FSPI
–
–
8
–
Datasheet
29
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 19
Fixed SPI master mode AC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ Max Units
conditions
SID167
SID168
TDMO
TDSI
MOSI Valid after SClock driving edge
MISO Valid before SClock capturing
edge
–
–
–
15
–
ns
ns
–
Full clock, late MISO
sampling
20
Referred to slave
capturing edge
SID169
THMO
Previous MOSI data hold time
0
–
–
ns
Table 20
Fixed SPI slave mode AC specifications
(guaranteed by characterization)
Details/
Spec ID Parameter
Description
Min Typ
Max
Units
ns
ns TCPU = 1/FCPU
conditions
MOSI valid before Sclock capturing
edge
SID170 TDMI
40
–
–
–
–
–
–
42 + 3 ×
TCPU
SID171 TDSO
SID171A TDSO_EXT
MISO valid after Sclock driving edge
MISO valid after Sclock driving edge
in Ext Clk mode
–
48
ns
–
SID172 THSO
SID172A TSSELSCK
Previous MISO data hold time
SSEL valid to first SCK Valid edge
0
100
–
–
–
–
ns
ns
–
–
6.5
System resources
6.5.1
Power-on reset (POR) with brown out SWD interface
Table 21
Imprecise power-on reset (IPOR)
(guaranteed by characterization)
Spec ID Parameter
Description
Min Typ Max Units
Details/conditions
Power-on Reset (POR) rising trip
voltage
POR falling trip voltage
SID185
SID186
VRISEIPOR
VFALLIPOR
0.80
0.70
–
–
1.50
1.4
V
V
–
–
Table 22
Precise power-on reset (POR)
(guaranteed by characterization)
Spec ID Parameter
Description
Min Typ Max Units
Details/conditions
Brown-out detect (BOD) trip
voltage in active/sleep modes
BOD trip voltage in Deep Sleep
mode
SID190
SID192
VFALLPPOR
VFALLDPSLP
1.48
1.1
–
–
1.62
1.5
V
V
–
–
Datasheet
30
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 23
Spec ID
SWD interface specifications
Parameter
Description
Min
Typ Max Units Details/conditions
SWDCLK 1/3 CPU
SID.SWD#1
SID.SWD#2
SID.SWD#3
SID.SWD#4
SID.SWD#5
SID.SWD#6
F_SWDCLK1
3.3 V VDDIO 5.5 V
1.8 V VDDIO 3.3 V
–
–
–
–
–
–
–
14
7
MHz
MHz
ns
clock frequency
SWDCLK 1/3 CPU
clock frequency
Guaranteed by
characterization
Guaranteed by
characterization
Guaranteed by
characterization
F_SWDCLK2
–
0.25 × T
0.25 × T
–
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
–
–
ns
0.50 × T ns
ns
Guaranteed by
characterization
1
–
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.5.2
Internal main oscillator
Table 24
IMO DC specifications
(guaranteed by design)
Spec ID Parameter
Description
IMO operating current at 48 MHz
Min Typ Max Units
1000 µA
Details/conditions
SID218
IIMO1
–
–
–
Table 25
IMO AC specifications
Spec ID Parameter
Description
Min Typ Max Units
Details/conditions
Frequency variation at 24, 36,
and 48 MHz (trimmed)
–25°C TA 85°C,
SID.CLK#13 FIMOTOL
–
–
–
–
±2
7
%
µs
ps
all VDDD
Guaranteed by
characterization
Guaranteed by
characterization
SID226
TSTARTIMO IMO start-up time
TJITRMSIMO2 RMS jitter at 24 MHz
SID229
–
145
–
–
SID.CLK#1 FIMO
IMO frequency
24
48 MHz All VDDD
Datasheet
32
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.5.3
Internal low-speed oscillatorpower down
Table 26
ILO DC specifications
(guaranteed by design)
Spec ID Parameter
Description
ILO operating current
ILO leakage current
Min Typ Max Units
Details/conditions
SID231
SID233
IILO1
IILOLEAK
–
–
0.3 1.05 µA
15 nA
–
–
2
Table 27
ILO AC specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
Guaranteed by
SID234
TSTARTILO1 ILO start-up time
–
–
2
ms
%
characterization
Guaranteed by
characterization
SID238
TILODUTY
FILO
ILO duty cycle
ILO frequency
40
20
50
40
60
SID.CLK#5
80 kHz
–
Table 28
Spec ID
PD DC specifications
Parameter
Description
Min Typ Max Units
64 80 96 µA
Details/conditions
DFP CC termination for
default USB Power
SID.PD.1
SID.PD.2
RP_std
–
DFP CC termination for 1.5 A
power
RP_1.5A
166 180 194.4 µA
304 330 356.4 µA
–
DFP CC termination for 3.0 A
power
UFP CC termination
SID.PD.3
SID.PD.4
RP_3.0A
RD
–
–
4.59 5.1 5.61
kΩ
UFP Dead Battery CC
termination on CC1 and
CC2. For Default RP
UFP Dead Battery CC termi-
nation on CC1 and CC2, valid
for 1.5 A and 3.0 A RP termi-
nation values
SID.PD.5
RD_DB
4.08 5.1 6.12
kΩ termination, the
voltage on CC1 and CC2
is guaranteed to be
<1.32 V.
Relative to the remote
BMC transmitter.
Guaranteed by
Ground offset tolerated by
BMC receiver
SID.PD.15 Vgndoffset
–400
–
400
mV
characterization.
Table 29
Spec ID
CSA specifications
Parameter
Description
Min Typ Max Units Details/conditions
Overall error at Av = 15
Guaranteed by
SID.CSA.1 Out_E_Trim_15_DS using deep sleep
reference
–7.00
–4.50
–
–
–
7.00
4.50
%
%
%
characterization.
Overall error at Av = 15
Guaranteed by
characterization.
SID.CSA.2 Out_E_Trim_15_BG
using bandgap reference
Overall error at Av = 100
SID.CSA.3 Out_E_Trim_100
using either bandgap or –24.50
deep sleep reference
24.50
–
Datasheet
33
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2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 30
UV/OV specifications
Description
Voltage threshold accuracy,
BUS 16 V
Voltage threshold accuracy,
BUS 16 V
Spec ID Parameter
Min Typ Max Units
Details/conditions
Tested at VBUS = 3.75 V,
4.5 V, 5.25 V, 12 V, 16 V
SID.UVOV.1 VTHUVOV1
SID.UVOV.2 VTHUVOV2
–6
6
%
%
V
–10
10
Tested at VBUS = 20 V
V
6.5.4
Gate driver specifications
Table 31
Gate driver DC specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
1. Gate driver supply voltage
5 V, where gate driver supply
voltage = VBUS _P for
VBUS_P_CTRL_ outputs, and
VBUS_C for VBUS_C_CTRL_
outputs.
Gate to source
overdrive
DC.NGDO.1 VGS1
5
–
16.5
V
2. Gate driver current = 0
3. Gate driver configuration =
NFET
4. Gate driver pump clock
divider = 1
1. Gate driver supply voltage
3.75 V, where Gate driver
supply voltage = VBUS _P for
VBUS_P_CTRL_ outputs, and
VBUS_C for VBUS_C_CTRL_
outputs.
2. Gate driver current = 0
3. Gate driver configuration =
NFET
Gate to source
overdrive
DC.NGDO.2 VGS2
DC.NGDO.6 RPD
3.75
–
–
16.5
V
4. Gate driver pump clock
divider = 1
Resistance when
“pull down” enabled
–
5
kΩ
–
Datasheet
34
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 32
Gate driver AC specifications
Description
Spec ID Parameter
Min Typ Max Units
Details/conditions
1. Gate driver configura-
tion = NFET
2. Load = The gate of a
SI9936 MOSFET
Gate turn-on time to
gate_driver_supply_voltage +
5 V for supply voltage 5 V and
VBUS * 2 for supply voltage < 5 V
AC.NGDO.1 TON
–
–
1
ms
6.5.5
SBU
Table 33
Analog crossbar switch specifications
Details/
Spec ID Parameter
Description
Switch ON resistance
Min Typ Max Units
conditions
Voltage input
from 0 V to 3.6 V
SID.SBU.1 Ron_sw
–
–
10
Ω
SID.SBU.2 Rpu_aux_1 AUX_P/N pull-up resistance – 100k
SID.SBU.3 Rpu_aux_2 AUX_P/N pull-up resistance – 1M
SID.SBU.4 Rpd_aux_1 AUX_P/N pull-down resistance – 100k
SID.SBU.5 Rpd_aux_2 AUX_P/N pull-down resistance – 1M
SID.SBU.6 Rpd_aux_3 AUX_P/N pull-down resistance – 470k
80
0.8
80
0.8
329
–
–
–
–
–
–
120
1.2
120
1.2
611
6.11
kΩ
MΩ
kΩ
MΩ
kΩ
–
–
–
–
–
–
SID.SBU.7 Rpd_aux_4 AUX_P/N pull-down resistance – 4.7M 3.29
MΩ
6.5.6
Charger detect
Table 34
Charger detect specifications
Details/
Spec ID Parameter
SID.CD.1 VDAT_REF
SID.CD.2 VDM_SRC
SID.CD.3 VDP_SRC
Description
Min Typ Max Units
conditions
BC1.2 Data detect voltage
threshold
–
250
500
500
–
–
–
400
700
700
mV
mV
mV
With current sink of
25 µA–175 µA
With current sink of
25 µA–175 µA
BC1.2 DM voltage source
BC1.2 DP voltage source
SID.CD.4 IDM_SINK
SID.CD.5 IDP_SINK
SID.CD.6 IDP_SRC
SID.CD.7 RDP_UP
SID.CD.8 RDM_UP
BC1.2 DM current sink
BC1.2 DP current sink
BC1.2 DP DCD current source
USB FS DP pull-up termination
USB FS DM pull-up termination
25
25
7
0.9
0.9
–
–
–
–
–
–
–
175
175
13
1.575
1.575
24.8
24.8
µA
µA
µA
kΩ
kΩ
kΩ
kΩ
–
–
–
–
–
–
–
SID.CD.9 RDP_DWN USB FS DP pull-down termination 14.25
SID.CD.10 RDM_DWN USB FS DM pull-down termination 14.25
The charger detect
function and data
line leakage is
enabled.
DP/DM data line leakage
termination
SID.CD.11 RDAT_LKG
300
–
500
kΩ
BC1.2 DCP port resistance between
DP and DM
USB FS logic threshold
–
SID.CD.12 RDCP_DAT
SID.CD.13 VSETH
–
–
–
40
Ω
1.26
1.54
V
–
Datasheet
35
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EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.5.7
Analog to digital converter
Table 35
ADC DC specifications
(guaranteed by characterization)
Spec ID Parameter
SID.ADC.1 Resolution ADC resolution
Description
Min
–
–1.5
–2.5
–1
Typ
8
–
–
–
Max Units Details/conditions
–
Bits
LSB
LSB
LSB
–
–
–
–
SID.ADC.2 INL
SID.ADC.3 DNL
Integral non-linearity
Differential non-linearity
1.5
2.5
1
SID.ADC.4 Gain Error Gain error
Table 36 ADC AC specifications
(guaranteed by design)
Spec ID Parameter
SID.ADC.5 SLEW_Max
Description
Rate of change of sampled
voltage signal
Min
Typ Max Units
V/ms
Details/conditions
–
–
3
–
Table 37
Spec ID
VBUS_C regulator DC specifications
Parameter
Description
Min Typ Max Units
Details/conditions
VBUS regulator output
voltage measured at
VDDD for VBUS = 4.5 V
to 21.5 V
VBUS regulator output
voltage measured at
VDDD for VBUS = 3.5 V
to 21.5 V
VBUS = 4.5 V - 21.5 V range.
VDDD voltage measured
with no load and a load of
30 mA.
VBUS = 4.5 V - 21.5 V range.
VDDD voltage measured
with no load and a load of
15 mA.
SID.20vreg.1 VBUSREG
SID.20vreg.2 VBUSREG2
3
3
–
–
3.6
3.6
V
V
VBUS supply varied from
4.5 V to 21.5 V and the
change in the VDDD
measured.
VBUS regulator line
SID.20vreg.6 VBUSLINREG regulation for VBUS
from 4.5 V to 21.5 V
–
–
–
–
0.5
%/V
Guaranteed by
characterization.
Supply of 4.5 V - 21.5 V
applied on VBUS and the
load current swept from 0
VBUS regulator load
SID.20vreg.8 VBUSLOADREG regulation for VBUS
from 4.5 V to 21.5 V
0.2 %/mA to 30 mA. The change in
VDDD is measured.
Guaranteed by
characterization.
Table 38
(guaranteed by characterization)
Spec ID Parameter
VBUS_C regulator AC specifications
Description
Min Typ Max Units
Details/conditions
Apply VBUS and measure start
time on VDDD pin.
AC.20vreg.1 TSTART
Regulator start-up time
–
–
120
µs
Time from assertion of an
internal disable signal to for
load current on VDDD to
Regulator power down
time
AC.20vreg.2 TSTOP
–
–
1
µs
decrease from 30 mA to 10 µA.
Datasheet
36
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EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
Table 39
Spec ID
VSYS switch specification
Parameter Description
Min Typ Max Units
Details/conditions
Resistance from VSYS
supply input to the output
supply VDDD
Measured with a load current of
5 mA - 10 mA on VDDD.
SID.vddsw.1 Res_sw
–
–
1.5
Ω
Datasheet
37
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EZ-PD™ PMG1-S2 Power Delivery MCU
Electrical specifications
6.5.8
Memory
Table 40
Flash AC specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
SID.MEM#3 FLASH_ERASE
SID.MEM#4 FLASH_WRITE
Row erase time
–
–
15.5 ms
–
–
Row (Block) write time
(erase and program)
–
–
20 ms
Row program time after
erase
–
–
SID.MEM#8 FLASH_ROW_PGM
–
–
–
–
–
–
7
ms
SID178
SID180
TBULKERASE
TDEVPROG
Bulk erase time (64k bytes)
35 ms
Guaranteed by
characterization
Total device program time
7.5
–
s
Flash retention, TA ≤ 55°C,
100 K P/E cycles
Guaranteed by
characterization
SID182
FRET1
FRET2
FRET3
20
10
3
–
–
–
years
years
years
Flash retention, TA ≤ 85°C,
10 K P/E cycles
Guaranteed by
characterization
SID182A
SID182B
–
Flash retention, TA ≤ 105°C,
10 K P/E cycles
Guaranteed by
characterization
–
Datasheet
38
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EZ-PD™ PMG1-S2 Power Delivery MCU
Ordering information
7
Ordering information
Table 41 lists the EZ-PD™ PMG1-S2 part numbers and features.
Table 41 EZ-PD™ PMG1-S2 Ordering information
MPN
Application
Termination resistor
Role
Package
Si ID
CYPM1211-40LQXI
CYPM1211-40LQXIT
40-pin QFN 1D20
42-ball CSP 1D21
[7]
DRP applications
RP[6], RD[5], RD_DB
DRP
CYPM1211-42FNXIT
7.1
Ordering code definitions
The part numbers are of the form CYPM1ABC-DEFGHIJ where the fields are defined as follows.
Table 42 EZ-PD™ PMG1-S2 ordering code definitions
Field
CY
PM
1
Description
Cypress prefix
Marketing code
MCU Family generation
Family
Values
Meaning
Company ID
PM = Power Delivery MCU family
CY
PM
1
Product family generation
A
0
S0
1
S1
2
S2
3
1
S3
1-PD port
B
PD Ports
2
2-PD port
C
DE
FG
Application specific
Pin
X
Application specific
Number of pins in the package
QFN
XX
LQ
BZ
FN
X
Package code
BGA
CSP
Lead: X = Pb-free
Industrial
Tape and reel
H
I
J
Lead free
Temperature range
Only for T&R
I
T
Notes
5. Termination resistor denoting an upstream facing port.
6. Termination resistor denoting a downstream facing port.
7. Termination resistor denoting dead battery termination.
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
Packaging
8
Packaging
Table 43
Package characteristics
Description
Parameter
Conditions
Industrial
Extended Industrial
Industrial
Extended Industrial
Min
Typ
Max
85
105
100
125
17
2
34
0.3
Units
Operating ambient
temperature
TA
TJ
–40
25
°C
Operating junction
temperature
–40
25
TJA
TJC
TJA
TJC
Package JA (40-pin QFN)
Package JC (40-pin QFN)
Package JA (42-pin CSP)
Package JC (42-pin CSP)
–
–
–
–
–
–
–
–
–
–
–
–
°C/W
Table 44
Package
Solder reflow peak temperature
Maximum peak temperature
Maximum time within 5°C of peak tem-
perature
40-pin QFN
42-ball CSP
260°C
30 seconds
Table 45
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
MSL
MSL 3
MSL 1
40-pin QFN
42-ball CSP
001-80659 *A
Figure 9
40-pin QFN package outline, 001-80659
Datasheet
40
002-31598 Rev. *D
2022-07-04
EZ-PD™ PMG1-S2 Power Delivery MCU
Packaging
002-04062 *A
Figure 10
42-ball CSP package outline, 002-04062
Datasheet
41
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EZ-PD™ PMG1-S2 Power Delivery MCU
Acronyms
9
Acronyms
Table 46
Acronyms used in this document
Acronym
Description
ADC
AES
analog-to-digital converter
advanced encryption standard
AHB
API
AMBA (advanced microcontroller bus architecture) high-performance bus
application programming interface
advanced RISC machine, a CPU architecture
Biphase Mark Code
Arm®
BMC
CC
configuration channel
CPU
CRC
CS
central processing unit
cyclic redundancy check, an error-checking protocol
current sense
DFP
DIO
DRP
EEPROM
downstream facing port
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
dual role port
electrically erasable programmable read-only memory
electronically marked cable assembly, a USB cable that includes an IC that reports
cable characteristics (e.g., current rating) to the Type-C ports
EMCA
EMI
ESD
FS
electromagnetic interference
electrostatic discharge
full-speed
GPIO
HPD
IC
general-purpose input/output
hot plug detect
integrated circuit
IDE
integrated development environment
Inter-Integrated Circuit, a communications protocol
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output subsystem
input/output, see also GPIO
low-dropout regulator
low-voltage detect
I2C, or IIC
ILO
IMO
IOSS
I/O
LDO
LVD
LVTTL
MCU
MMIO
NC
low-voltage transistor-transistor logic
microcontroller unit
memory mapped input/output
no connect
NMI
nonmaskable interrupt
NVIC
opamp
OCP
nested vectored interrupt controller
operational amplifier
overcurrent protection
Datasheet
42
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EZ-PD™ PMG1-S2 Power Delivery MCU
Acronyms
Table 46
Acronyms used in this document (continued)
Acronym
Description
OVP
OVT
PCB
PD
overvoltage protection
over voltage tolerant
printed circuit board
power delivery
PGA
PHY
POR
PRES
PRNG
PWM
RAM
RCP
RISC
RMS
RTC
RX
programmable gain amplifier
physical layer
power-on reset
precise power-on reset
pseudo random number generation
pulse-width modulator
random-access memory
reverse current protection, supported in Source Configuration only
reduced-instruction-set computing
root-mean-square
real-time clock
receive
SAR
SCB
SCL
successive approximation register
serial communication block
I2C serial clock
SCP
SDA
S/H
short circuit protection, supported in Source Configuration only
I2C serial data
sample and hold
SHA
SPI
secure hash algorithm
Serial Peripheral Interface, a communications protocol
static random access memory
serial wire debug, a test protocol
timer/counter pulse-width modulator
true random number generation
transmit
SRAM
SWD
TCPWM
TRNG
TX
a new standard with a slimmer USB connector and a reversible cable, capable of
sourcing up to 100 W of power
Type-C
UART
USB
Universal Asynchronous Transmitter Receiver, a communications protocol
Universal Serial Bus
USB PD
USB-FS
USBIO
USB PD SS
UVP
USB Power Delivery
USB Full-Speed
USB input/output, PMG1-S2 pins used to connect to a USB port
USB PD subsystem
under voltage protection
VDM
vendor defined messages
XRES
external reset I/O pin
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
Document conventions
10
Document conventions
10.1
Units of measure
Table 47
Units of measure
Symbol
Unit of measure
°C
degrees Celsius
hertz
Hz
KB
kHz
kΩ
Mbps
MHz
MΩ
Msps
µA
1024 bytes
kilohertz
kiloohm
megabits per second
megahertz
megaohm
megasamples per second
microampere
microfarad
microsecond
microvolt
µF
µs
µV
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
Ω
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
V
samples per second
volt
Datasheet
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EZ-PD™ PMG1-S2 Power Delivery MCU
Revision history
Revision history
Document
Date
Description of change
revision
**
2020-10-23
New datasheet.
Updated EZ-PD™ PMG1 family general description.
Updated Eclipse IDE for ModusToolbox™.
Updated Application diagrams.
*A
2021-02-25
Added footnotes 1, 2, and 3.
Removed VCONN_MAX parameter from Table 5.
Removed Preliminary status of the datasheet.
Updated Table 3.
Updated Acronyms.
*B
*C
2021-06-11
2022-05-18
Added Pin based absolute maximum ratings.
Migrated to IFX template.
Updated Figure 1.
Added Figure 5 and Figure 10.
*D
2022-07-04
Updated Table 1, Table 3, Table 4, Table 6, Table 41, Table 43, Table 44,
Table 45.
Updated Block diagram.
Datasheet
45
002-31598 Rev. *D
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Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-07-04
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
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a written document signed by
Do you have a question about this
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Document reference
002-31598 Rev. *D
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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