CYS0644ABZI-S2D44T [INFINEON]
32-位PSoC™ 6 Arm® Cortex®-M4 / M0+;
| 型号： | CYS0644ABZI-S2D44T |
| 厂家： | 
Infineon |
| 描述： | 32-位PSoC™ 6 Arm® Cortex®-M4 / M0+ |
| 文件： | 总88页 (文件大小：1468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
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The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
PSoC 64 "Standard Secure" MCU-AWS
General Description
PSoC® 6 MCU is a high-performance, ultra-low-power, and secured MCU platform, purpose-built for IoT applications. The PSoC 64
product line, based on the PSoC 6 MCU platform, features out-of-box security functionality, providing an isolated root-of-trust with true
attestation and provisioning services. In addition, it delivers a pre-configured, PSA level-2 compliant secured execution environment,
which is custom-built to support theAmazon FreeRTOS ecosystem. PSoC 64 also includes a rich execution environment for application
development, with Amazon FreeRTOS support that communicates with the secured execution environment.
Features
32-bit Dual CPU Subsystem
Immutable “Secure Boot” Support
Note: In PSoC 64 the Cortex M0+ is reserved for system
functions, and is not available for applications.
■ Flexible chain of trust can use different signatures for different
images
■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle
■ ECC-based image signature validation
multiply, floating point, and memory protection unit (MPU)
Cypress Bootloader
■ Open Source MCUBoot[1] based bootloader optimized for
PSoC 64
■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply
and MPU
■ User-selectable core logic operation at either 1.1 V or 0.9 V
■ Pre-built bootloader binary capable of validating, launching and
updating signed user application images
■ Active CPU current slope with 1.1-V core operation
❐ Cortex-M4: 40 µA/MHz
❐ Cortex-M0+: 28 µA/MHz
■ Tightly integrated with provisioned debug and boot policies to
inherit and implement security policies
■ Active CPU current slope with 0.9-V core operation
❐ Cortex-M4: 27 µA/MHz
❐ Cortex-M0+: 20 µA/MHz
Low-Power 1.7-V to 3.6-V Operation
■ Six power modes for fine-grained power management
■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention
■ On-chip DC-DC buck converter, <1 µA quiescent current
■ Backup domain with 64 bytes of memory and real-time clock
■ Three DMA controllers
Memory Subsystem
■ 1856-KB application flash, 32-KB auxiliary flash (AUXflash),
and 32-KB supervisory flash (SFlash); read-while-write (RWW)
support. Two 8-KB flash caches, one for each CPU
Flexible Clocking Options
■ 8-MHz internal main oscillator (IMO) with ±2% accuracy
■ Ultra-low-power 32-kHz internal low-speed oscillator (ILO)
■ On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
■ 944-KB SRAM with three independent blocks for power and
data retention control
■ One-time-programmable (OTP) 1-Kb eFuse array
■ Two phase-locked loops (PLLs) for multiplying clock
frequencies
Amazon FreeRTOS PSA Integration
■ Out-of-box solution forenablingAmazon FreeRTOS (AFR) with
Arm Platform Service Architecture (PSA) Level-2 Compliance
■ Frequency-locked loop (FLL) for multiplying IMO frequency
■ Integer and fractional peripheral clock dividers
■ Pre-built Trusted Firmware-M (TF-M) Secure Processing
Environment (SPE) binary built for this product line
Quad-SPI (QSPI)/Serial Memory Interface (SMIF)
■ Execute-In-Place (XIP) from external quad SPI flash
■ On-the-fly encryption and decryption
■ Amazon FreeRTOS API-level integration for TLS, firmware
update, and secured storage
Hardware-Based Root-of-Trust (RoT)
■ 4-KB cache for greater XIP performance with lower power
■ RoTbasedonimmutableboot-upcode, flashcontenthash, and
Cypress public key that ensures firmware integrity prior to provi-
sioning
■ Supports single, dual, quad, dual-quad, and octal interfaces
with throughput up to 640 Mbps
Segment LCD Drive
■ Supports trusted RoT handover to maintain chain of trust and
establish OEM trust anchor for secured boot
■ Supports up to 101 segments and up to 8 commons
■ Device generates a unique device ID and a device secret key
during the provisioning process, which can be used for attes-
tation and signing
Note
1. For details, refer to https://mcuboot.com/.
Cypress Semiconductor Corporation
Document Number: 002-28690 Rev. *I
•
198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised October 26, 2022
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Serial Communication
Profiler
■ 13 run-time configurable serial communication blocks (SCBs)
❐ Eight SCBs: configurable as SPI, I2C, or UART
❐ Four SCBs: configurable as I2C or UART
■ Eight counters provide event or duration monitoring of on-chip
resources
Packages
❐ One Deep Sleep SCB: configurable as SPI or I2C
124-BGA and 100-WLCSP
■ USB Full-Speed device interface
■ Two independent SD Host Controller/eMMC/SD controllers
Device Identification and Revisions
■ Product Line ID (12-bit): 0x102
Audio Subsystem
■ Two pulse density modulation (PDM) channels and two I2S
■ Major/Minor Die Revision ID: 1/2
channels with time division multiplexed (TDM) mode
■ Firmware Revisions: Rom Boot: 7.1, Flash Boot: 4.0.2.1842
(see Boot Code section)
Timing and Pulse-Width Modulation
This product line has a JTAG ID which is available through the
SWJ interface. It is a 32-bit ID, where:
■ Thirty-two timer/counter/pulse-width modulators (TCPWMs)
■ Center-aligned, edge, and pseudo-random modes
■ Comparator-based triggering of kill signals
■ The most significant digit is the device revision, based on the
Major Die Revision
Programmable Analog
■ The next four digits correspond to the part number, for example
"E4B0" as a hexadecimal number
■ 12-bit 2-Msps SAR ADC with differential and single-ended
modes and 16-channel sequencer with result averaging
■ The three least significant digits are the manufacturer ID, in this
case "069" as a hexadecimal number
■ Two low-power comparators available in system Deep Sleep
and Hibernate modes
The Silicon ID system call can be used by firmware to get Silicon
ID and ROM Boot data. For more information, see the technical
reference manual (TRM).
■ Built-in temperature sensor connected to ADC
Up to 100 Programmable GPIOs
The Flash Boot version can be read directly from designated
addresses 0x1600 2004 and 0x1600 2018. For more
information, see the technical reference manual (TRM).
■ Two Smart I/O™ ports (16 I/Os) enable Boolean operations on
GPIO pins; available during system Deep Sleep
■ Programmable drive modes, strengths, and slew rates
■ Six overvoltage-tolerant (OVT) pins
Capacitive Sensing
■ CypressCapSense® sigma-delta(CSD)providesbest-in-class
signal-to-noise ratio (SNR), liquid tolerance, and proximity
sensing
■ Enables dynamic usage of both self and mutual sensing
■ Automatic hardware tuning (SmartSense™)
Cryptography Accelerator
■ Hardware acceleration for symmetric and asymmetric
cryptographic methods and hash functions
■ True random number generator (TRNG) function
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Contents
General Description ......................................................... 1
Features............................................................................. 1
32-bit Dual CPU Subsystem ........................................1
Memory Subsystem .....................................................1
Amazon FreeRTOS PSA Integration ...........................1
Hardware-Based Root-of-Trust (RoT) .........................1
Immutable “Secure Boot” Support ...............................1
Cypress Bootloader ....................................................1
Low-Power 1.7-V to 3.6-V Operation ..........................1
Flexible Clocking Options ............................................1
Quad-SPI (QSPI)/Serial Memory Interface (SMIF) .....1
Segment LCD Drive ....................................................1
Serial Communication .................................................2
Audio Subsystem ........................................................2
Timing and Pulse-Width Modulation ............................2
Programmable Analog .................................................2
Capacitive Sensing ......................................................2
Cryptography Accelerator ............................................2
Profiler .........................................................................2
Packages .....................................................................2
Device Identification and Revisions .............................2
Contents............................................................................ 3
Development Ecosystem................................................. 4
PSoC 6 MCU Resources .............................................4
ModusToolbox Software ..............................................5
Blocks and Functionality................................................. 6
Functional Description..................................................... 8
CPU and Memory Subsystem .....................................8
System Resources ....................................................12
Programmable Analog Subsystems ..........................14
Programmable Digital ................................................16
Fixed-Function Digital ................................................16
GPIO .........................................................................18
Special-Function Peripherals ....................................18
PSoC 64 Security ......................................................22
Pinouts ............................................................................ 28
Power Supply Considerations....................................... 42
Electrical Specifications ................................................ 47
Absolute Maximum Ratings .......................................47
Device-Level Specifications ......................................47
Analog Peripherals ....................................................56
Digital Peripherals .....................................................62
Memory .....................................................................65
System Resources ....................................................66
Ordering Information...................................................... 76
PSoC 6 MPN Decoder ..............................................77
Packaging........................................................................ 78
Acronyms........................................................................ 81
Document Conventions ................................................. 83
Units of Measure .......................................................83
Errata ............................................................................... 84
Revision History ............................................................. 85
Sales, Solutions, and Legal Information ...................... 87
Worldwide Sales and Design Support .......................87
Products ....................................................................87
PSoC® Solutions ......................................................87
Cypress Developer Community .................................87
Technical Support .....................................................87
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Development Ecosystem
PSoC 6 MCU Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated list of resources for PSoC 6 MCU:
■ Overview: PSoC Portfolio, PSoC Roadmap
■ Product Selectors: PSoC 6 MCU
■ PSoC 6 MCU Programming Specification provides the infor-
mation necessary to program PSoC 6 MCU nonvolatile
memory
■ Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
❐ AN22174: Getting Started with PSoC 6 MCU
■ Development Tools
❐ ModusToolbox® software enables cross platform code de-
velopment with a robust suite of tools and software libraries
❐ AN218241: PSoC 6 MCU Hardware Design Guide
❐ AN213924: PSoC 6 MCU Device Firmware Update Guide
❐ AN219528: PSoC 6 MCU Power Reduction Techniques
❐ AN85951: PSoC 4, PSoC 6 MCU CapSense Design Guide
❐ “Secure Boot” SDK includes all required libraries, tools, and
sample code to provision and develop applications for
PSoC 64 MCUs.
❐ CY8CKIT-064S0S2-4343W[2] PSoC 64 “Standard Secure”
Prototyping Kit: a low-cost hardware platform that enables
design and debug of this product line.
■ CodeExamplesdemonstrateproductfeaturesandusage,and
are also available on Cypress GitHub repositories.
❐ PSoC 6 CAD libraries provide footprint and schematic sup-
port for common tools. BSDL files and IBIS models are also
available.
■ Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 6 MCU architecture and registers.
■ Training Videos are available on a wide range of topics
including the PSoC 6 MCU 101 series
Note
2. The link will be provided in a later revision.
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
ModusToolbox Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive
development experience for creating converged MCU and wireless systems. It is:
■ Comprehensive - it has the resources you need
■ Flexible - you can use the resources in your own workflow
■ Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub. This includes:
■ Board Support Packages (BSPs) aligned with Cypress kits
■ Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL)
■ Middleware enabling industry-leading features such as CapSense®, Bluetooth Low Energy, and mesh networks
■ An extensive set of thoroughly tested code example applications
Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Cypress MCUs. It is a generic
interface that can be used across multiple product families. For example, it wraps the PSoC 6 PDL with a simplified API, but the PDL
exposes all low-level peripheral functionality. You can leverage the HAL's simpler and more generic interface for most of an application,
even if one portion requires finer-grained control.
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a
project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox. For
information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and AN228571: Getting Started
with PSoC 6 MCU on ModusToolbox.
Figure 1. ModusToolbox Software Tools
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Blocks and Functionality
Figure 2 shows the major subsystems and a simplified view of their interconnections. The color coding shows the lowest power mode
where the particular block is still functional (for example, the SRAM is functional down to system Deep Sleep mode).
Figure 2. Block Diagram
Color Key:
Power Modes and
PSoC 64 “Standard Secure” MCU
CYS0644xxxI-S2D4x
Domains
Programmable Analog
System LP/ULP Mode
SAR ADC 12 bit
System Resources
CPUs Active/Sleep
Power
Clocks
Temperature
Sensor
OVP
POR
LVD
IMO
FLL
ECO
BOD
2x PLL
System
Deep Sleep Mode
Buck Regulator
XRES Reset
Backup Regs
2x MCWDT
ILO
WDT
WCO
RTC
System
Hibernate Mode
PMIC Control
Backup
Domain
CPU Subsystem
SCB
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
Audio Subsystem
3x DMA
Controller
Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator
Flash
2048 KB + 32 KB + 32 KB
8 KB cache for each CPU
SRAM0
512 KB
USB
PHY
SRAM1
256 KB
SRAM2
256 KB
ROM
64 KB
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
This product line has up to 2 MB of flash; however 192 KB is reserved for system usage, leaving 1856 KB for applications. It also has
up to 1 MB of SRAM; however 80 KB is reserved for system usage, leaving 944 KB for applications.
The PSoC 64 devices offer an immutable, RoT-based boot-up process, which allows only signed applications to be booted up. In
addition, user assets such as keys and debug policies can be provisioned on the device in an HSM environment and made immutable.
PSoC 64 also allows for root-of-trust based cryptography services which can be accessed using system calls.
There are three debug access ports, one each for CM4 and CM0+, and a system port. All debug and test interfaces can be permanently
disabled during final production provisioning to avoid any malicious reprogramming or reading of flash and register contents.
PSoC 6 MCU devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All
device interfaces can be permanently disabled for applications concerned about a reprogrammed device or starting and interrupting
flash programming sequences. All programming, debug, and test interfaces can be disabled.
Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does
not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required
to fully support debug.
The Eclipse IDE for ModusToolbox provides fully integrated programming and debug support for these devices. The SWJ (SWD and
JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust
flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, PSoC 6
provides multiple levels of device security.
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Functional Description
The following sections provide an overview of the features,
capabilities and operation of each functional block identified in
the block diagram in Figure 2. For more detailed information,
refer to the following documentation:
CPU and Memory Subsystem
PSoC 6 has multiple bus masters, as Figure 2 shows. They are:
CPUs, DMA controllers, QSPI, USB, SD Host Controllers, and a
Crypto block. Generally, all memory and peripherals can be
accessed and shared by all bus masters through multi-layer Arm
AMBA high-performance bus (AHB) arbitration. Accesses
between CPUs can be synchronized using an inter-processor
communication (IPC) block.
■ Board Support Package (BSP) Documentation
BSPs are available on GitHub. They are aligned with Cypress
kits and provide files for basic device functionality such as
hardware configuration files, startup code, and linker files.
The BSP also includes other libraries that are required to sup-
port a kit. Each BSP has its own documentation, but typically
includes an API reference such as the example here. This
search link finds all currently available BSPs on the Cypress
GitHub site.
CPUs
There are two Arm Cortex CPUs:
The Cortex-M4 (CM4) has single-cycle multiply, a floating-point
unit (FPU), and a memory protection unit (MPU). It can run at up
to 150 MHz. This is the main CPU, designed for a short interrupt
response time, high code density, and high throughput.
■ Hardware Abstraction Layer API Reference Manual
The Cypress Hardware Abstraction Layer (HAL) provides a
high-level interface to configure and use hardware blocks on
Cypress MCUs. It is a generic interface that can be used
across multiple product families. You can leverage the HAL's
simpler and more generic interface for most of an application,
even if one portion requires finer-grained control. The HAL
API Reference provides complete details. Example applica-
tions that use the HAL download it automatically from the
GitHub repository.
CM4 implements a version of the Thumb instruction set based
on Thumb-2 technology (defined in the Armv7-M Architecture
Reference Manual).
The Cortex-M0+ (CM0+) has single-cycle multiply, and an MPU.
It can run at up to 100 MHz; however, for CM4 speeds above
100 MHz, CM0+ and bus peripherals are limited to half the speed
of CM4. Thus, for CM4 running at 150 MHz, CM0+ and
peripherals are limited to 75 MHz.
In PSoC 64, the initial CM0+ frequency is set according to a
provisioned security policy (see PSoC 64 Security). The
frequency ranges from 8 MHz to 50 MHz. For more information,
see the Architecture and Registers TRM.
■ Peripheral Driver Library (PDL) Application Programming
Interface (API) Reference Manual
The Peripheral Driver Library (PDL) integrates device header
files and peripheral drivers into a single package and supports
all PSoC 6 MCU product lines. The drivers abstract the hard-
ware functions into a set of easy-to-use APIs. These are fully
documented in the PDLAPI Reference. Example applications
that use the PSoC 6 PDL download it automatically from the
GitHub repository.
CM0+ is the secondary CPU; it is used to implement system calls
and device-level safety and protection features. CM0+ provides
a secured, uninterruptible boot function. This helps ensure that
post boot, system integrity is checked and memory and
peripheral access privileges are enforced.
CM0+ implements the Armv6-M Thumb instruction set (defined
in the Armv6-M Architecture Reference Manual).
■ Architecture Technical Reference Manual (TRM)
The architecture TRM provides a detailed description of each
resource in the device. This is the next reference to use if it is
necessary to understand the operation of the hardware below
the software provided by PDL. It describes the architecture
and functionality of each resource and explains the operation
of each resource in all modes. It provides specific guidance
regarding the use of associated registers.
The CPUs have the following power draw, at VDDD = 3.3 V and
using the internal buck regulator:
Table 1. Active Current Slope at VDDD = 3.3 V Using the
Internal Buck Regulator
System Power Mode
ULP
LP
■ Register Technical Reference Manual
Cortex-M0+
Cortex-M4
20 A/MHz 28 A/MHz
27 A/MHz 40 A/MHz
The register TRM provides a complete list of all registers in
the device. It includes the breakdown of all register fields,
their possible settings, read/write accessibility, and default
states. All registers that have a reasonable use in typical ap-
plications have functions to access them from within PDL.
Note that ModusToolbox and PDL may provide software de-
fault conditions for some registers that are different from and
override the hardware defaults.
CPU
The CPUs can be selectively placed in their Sleep and Deep
Sleep power modes as defined by Arm.
Both CPUs have nested vectored interrupt controllers (NVIC) for
rapid and deterministic interrupt response, and wakeup interrupt
controllers (WIC) for CPU wakeup from Deep Sleep power
mode.
The CPUs have extensive debug support. PSoC 6 has a debug
access port (DAP) that acts as the interface for device
programming and debug. An external programmer or debugger
(the “host”) communicates with the DAP through the device
serial wire debug (SWD) or Joint Test Action Group (JTAG)
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Datasheet
interface pins. Through the DAP (and subject to restrictions), the
host can access the device memory and peripherals as well as
the registers in both CPUs.
descriptors for DMA channels can be in SRAM or flash.
Therefore, the number of descriptors is limited only by the size
of the memory. Each descriptor can transfer data in two nested
loops with configurable address increments to the source and
destination. The size of data transfer per descriptor varies based
on the type of DMA channel. Refer to the technical reference
manual for details.
Each CPU offers debug and trace features as follows:
■ CM4 supports six hardware breakpoints and four watchpoints,
4-bit embedded trace macrocell (ETM), serial wire viewer
(SWV), and printf()-style debugging through the single wire
output (SWO) pin.
Cryptography Accelerator (Crypto)
This subsystem consists of hardware implementation and
acceleration of cryptographic functions and random number
generators.
■ CM0+ supports four hardware breakpoints and two watch-
points, and a micro trace buffer (MTB) with 4-KB dedicated
RAM.
The Crypto subsystem supports the following:
PSoC 6 also has an Embedded Cross Trigger for synchronized
debugging and tracing of both CPUs.
■ Encryption/Decryption Functions
❐ Data Encryption Standard (DES)
❐ Triple DES (3DES)
Interrupts
This product line has 168 system and peripheral interrupt
sources, and supports interrupts and system exceptions on both
CPUs. CM4 has 168 interrupt request lines (IRQ), with the
interrupt source ‘n’ directly connected to IRQn. CM0+ has eight
interrupts IRQ[7:0] with configurable mapping of one or more
interrupt sources to any of the IRQ[7:0]. CM0+ also supports
eight internal (software only) interrupts.
❐ Advanced Encryption Standard (AES) (128-, 192-, 256-bit)
❐ Elliptic Curve Cryptography (ECC)
❐ RSA cryptography functions
■ Hashing functions
❐ Secure Hash Algorithm (SHA)
❐ SHA-1
Each interrupt supports configurable priority levels (eight levels
for CM4 and four levels for CM0+). Up to four system interrupts
can be mapped to each of the CPUs' non-maskable interrupts
(NMI). Up to 39 interrupt sources are capable of waking the
device from Deep Sleep power mode using the WIC. Refer to the
technical reference manual for details.
❐ SHA-224/-256/-384/-512
■ Message authentication functions (MAC)
❐ Hashed message authentication code (HMAC)
❐ Cipher-based message authentication code (CMAC)
■ 32-bit cyclic redundancy code (CRC) generator
InterProcessor Communication (IPC)
■ Random number generators
In addition to the Arm SEV and WFE instructions, a hardware
InterProcessor Communication (IPC) block is included. It
includes 16 IPC channels and 16 IPC interrupt structures. The
IPC channels can be used to implement data communication
between the processors. Each IPC channel also implements a
locking scheme which can be used to manage shared resources.
The IPC interrupts let one processor interrupt the other, signaling
an event. This is used to trigger events such as notify and release
of the corresponding IPC channels. Some IPC channels and
other resources are reserved, as Table 2 shows:
❐ Pseudo random number generator (PRNG)
❐ True random number generator (TRNG)
Protection Units
This product line has multiple types of protection units to control
erroneous or unauthorized access to memory and peripheral
registers. CM4 and CM0+ have Arm MPUs for protection at the
bus master level. Other bus masters use additional MPUs.
Shared memory protection units (SMPUs) help implement
protection for memory resources that are shared among multiple
bus masters. Peripheral protection units (PPU) are similar to
SMPUs but are designed for protecting the peripheral register
space.
Table 2. Distribution of IPC Channels and Other Resources
Resources Available Resources Consumed
IPC channels,
16 available
13 reserved
Protection units support memory and peripheral access
attributes including address range, read/write, code/data,
privilege level, secured/non-secured, and protection context.
Some protection unit resources are reserved for system usage;
see the technical reference manual for details.
IPC interrupts,
16 available
13 reserved
Other interrupts
CM0+ NMI
1 reserved
Reserved
Up to eight protection contexts (boot is in protection context 0)
allow access privileges for memory and system resources to be
set by the boot process per protection context by bus master and
code privilege level.
Other resources:
clock dividers, DMA
channels, etc.
4 CM0+ interrupt mux
Direct Memory Access (DMA) Controllers
This product line has three DMA controllers, which support
CPU-independent accesses to memory and peripherals. Two of
them have 29 channels each and the third has 4 channels. The
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In PSoC 64, multiple protection contexts are used to isolate the
different security levels within the device. The CM0+ makes use
of several of them during the boot sequence, bootloading,
system calls, etc. Protection context 6 is used for the user
application code that runs on the CM4 CPU. The SMPUs are set
up by default and cannot be modified by the user. See section 8
in the Architecture TRM for the protection context assignment.
■ eFuse
A one-time-programmable (OTP) eFuse array consists of
1024 bits, all of which are reserved for system use. The bits
are used for storing hash values, unique IDs, or other similar
PSoC 64 parameters.
Each fuse is individually programmed; once programmed (or
“blown”), its state cannot be changed. Blowing a fuse transi-
tions it from the default state of 0 to 1. To program an eFuse,
Memory
VDDIO0 must be at 2.5 V ±5%, at 14 mA.
PSoC 6 contains flash, SRAM, ROM, and eFuse memory blocks.
Because blowing an eFuse is an irreversible process, pro-
gramming is recommended only in mass production under
controlled factory conditions. For more information, see
PSoC 6 MCU Programming Specifications.
■ Flash
There is up to 2 MB of flash; however 192 KB is reserved for
system usage, leaving 1856 KB for applications, organized in
256-KB sectors.
Boot Code
There are also two 32-KB flash sectors:
❐ Auxiliary flash (AUXflash), typically used for EEPROM emu-
lation
❐ Supervisory flash (Sflash). Data stored in Sflash includes de-
vice trim values, Flash Boot code, and encryption keys. After
the device transitions into the “Secure” lifecycle stage, Sflash
can no longer be changed.
Two blocks of code, ROM Boot and Flash Boot, are
pre-programmed into the device and work together to provide
device startup and configuration, basic security features,
lifecycle stage management and other system functions.
■ ROM Boot
On a device reset, the boot code in ROM is the first code to
execute. This code performs the following:
❐ Integrity checks of flash boot code
❐ Device trim setting (calibration)
❐ Setting the device protection units
The flash has 128-bit-wide accesses to reduce power. Write
operations can be performed at the row level. A row is
512 bytes. Read operations are supported in both Low Power
and Ultra-Low Power modes, however write operations may
not be performed in Ultra-Low Power mode.
❐ Settingdeviceaccessrestrictionsfor“Secure”lifecyclestates
The flash controller has two caches, one for each CPU. Each
cache is 8 KB, with 4-way set associativity.
ROM cannot be changed and acts as the root of trust in a
secured system.
■ SRAM
■ Flash Boot
There is 944 KB of SRAM available for applications. The re-
maining 80 KB is reserved for system usage. SRAM is provid-
ed in three banks of 432 KB, 256 KB, and 256 KB. Each
SRAM bank provides control over power modes to manage
power consumption. For Bank 0 (432 KB), power control and
retention granularity are configurable in thirteen 32-KB re-
gions. For banks 1 and 2 (256 KB each) power control is on
a per bank basis. For normal operation, the banks can be
enabled or disabled to save power. For Deep Sleep mode, the
banks can also be configured to retain data.
Flash boot is firmware stored in SFlash that ensures that only
a validated application may run on the device. It also ensures
that the firmware image has not been modified, such as by a
malicious third party.
Flash boot:
❐ Is validated by ROM Boot
❐ Runs after ROM Boot and before the user application
❐ Enables system calls
❐ Enables provisioning and device policy features
❐ Implements RoT-based services for cryptography
❐ Provides secured storage for keys and certificates
❐ Validates and launches first image based on policies
provisioned in the device
■ ROM
The 64-KB ROM, also referred to as the supervisory ROM
(SROM), provides code (ROM Boot) for several system func-
tions. The ROM contains device initialization, flash write, se-
curity, eFuse programming, and other system-level routines.
ROM code is executed only by the CM0+ CPU, in protection
context 0. A system function can be initiated by either CPU,
or through the DAP. This causes an NMI in CM0+, which
causes CM0+ to execute the system function.
❐ Uses mbed TLS v2.24
If the user application cannot be validated, then flash boot
ensures that the device is transitioned into a safe state. Refer
to the PSoC 64 Security section for more details.
Document Number: 002-28690 Rev. *I
Page 10 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Memory Map
Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided
into the Arm-defined regions shown in Table 3. Note that code can be executed from the Code and External RAM regions.
Table 3. Address Map for CM4 and CM0+
Address Range
Name
Code
Use
Program code region. Data can also be placed here. It includes
the exception vector table, which starts at address 0.
0x0000 0000 – 0x1FFF FFFF
0x2000 0000 – 0x3FFF FFFF
0x4000 0000 – 0x5FFF FFFF
SRAM
Data region. This region is not supported in PSoC 6.
All peripheral registers. Code cannot be executed from this
region. CM4 bit-band in this region is not supported in PSoC 6.
Peripheral
External
RAM
SMIF or Quad SPI, (see the Quad-SPI/Serial Memory Interface
(SMIF) section). Code can be executed from this region.
0x6000 0000 – 0x9FFF FFFF
0xA000 0000 – 0xDFFF FFFF
External
Device
Not used.
Private
Peripheral
Bus
0xE000 0000 – 0xE00F FFFF
0xE010 0A000 – 0xFFFF FFFF
Provides access to peripheral registers within the CPU core.
Device-specific system registers.
Device
The device memory map shown in Table 4 applies to both CPUs. That is, the CPUs share access to all PSoC 6 MCU memory and
peripheral registers.
Table 4. Internal Memory Address Map for CM4 and CM0+
Address Range
Memory Type
Size
0x0000 0000 – 0x0000 FFFF
ROM
64 KB
0x0800 0000 – 0x080E BFFF
0x080E C000 - 0x080F FFFF
Application SRAM
System SRAM
Up to 944 KB
80 KB
0x1000 0000 – 0x101C FFFF
0x101D 0000 - 0x101F FFFF
Application flash
Secured code flash
Used for secured boot, secured boot-
loader, and system calls
Up to 1856 KB
192 KB
Auxiliary flash, can be used for EE-
PROM emulation
0x1400 0000 – 0x1400 7FFF
0x1600 0000 – 0x1600 7FFF
32 KB
Supervisory flash, for secured access 32 KB
Note that PSoC 6 SRAM is located in the Arm Code region for both CPUs (see Table 3). There is no physical memory located in the
CPUs’ Arm SRAM regions.
Document Number: 002-28690 Rev. *I
Page 11 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
■ CPU Sleep – CPU code execution is halted in system LP or
ULP mode
System Resources
Power System
■ CPU Deep Sleep – CPU code execution is halted and system
The power system provides assurance that voltage levels are as
required for each respective mode and will either delay mode
entry (on power-on reset (POR), for example) until voltage levels
are as required for proper function or generate resets (brown-out
detect (BOD)) when the power supply drops below specified
levels. The design guarantees safe chip operation between
power supply voltage dropping below specified levels (for
example, below 1.7 V) and the reset occurring. There are no
voltage sequencing requirements.
Deep Sleep is requested in system LP or ULP mode
■ System Deep Sleep – Only low-frequency peripherals are
available after both CPUs enter CPU Deep Sleep mode
■ System Hibernate – Device and I/O states are frozen and the
device resets on wakeup
CPU Active, Sleep, and Deep Sleep are standard Arm-defined
power modes supported by the Arm CPU instruction set
architecture (ISA). System LP, ULP, Deep Sleep and Hibernate
modes are additional low-power modes supported by PSoC 6
MCU.
The VDDD supply (1.7 to 3.6 V) powers an on-chip buck regulator
or a low-dropout regulator (LDO), selectable by the user. In
addition, both the buck and the LDO offer a selectable (0.9 or
1.1 V) core operating voltage (VCCD). The selection lets users
choose between two system power modes:
Clock System
Figure 3 shows that the clock system of this product line consists
of the following:
■ System Low Power (LP) operates VCCD at 1.1 V and offers high
performance, with no restrictions on device configuration.
■ Internal main oscillator (IMO)
■ Internal low-speed oscillator (ILO)
■ Watch crystal oscillator (WCO)
■ External MHz crystal oscillator (ECO)
■ External clock input
■ System Ultra Low Power (ULP) operates VCCD at 0.9 V for
exceptional low power, but imposes limitations on clock
speeds.
In addition, a backup domain adds an “always on” functionality
using a separate power domain supplied by a backup supply
(VBACKUP) such as a battery or supercapacitor. It includes a
real-time clock (RTC) with alarm feature, supported by a
■ Two phase-locked loops (PLLs)
■ One frequency-locked loop (FLL)
32.768-kHz
watch
crystal
oscillator
(WCO),
and
power-management IC (PMIC) control. Refer to Power Supply
Considerations for more details.
Clocks may be buffered and brought out to a pin on a smart I/O
port.
Power Modes
The default clocking when the application starts is CLK_HF[0]
being driven by the IMO and the FLL. CLK_HF[0], clk_fast,
clk_peri, and clk_slow are all either 50 MHz (LP mode) or 25 MHz
(ULP mode). All other clocks, including all peripheral clocks, are
off.
PSoC 6 MCU can operate in four system and three CPU power
modes. These modes are intended to minimize the average
power consumption in an application. For more details on power
modes and other power-saving configuration options, see the
application note, AN219528: PSoC 6 MCU Low-Power Modes
and Power Reduction Techniques. Contact your local Cypress
sales representative for the latest technical reference manual.
Internal Main Oscillator (IMO)
The IMO is the primary source of internal clocking. It is trimmed
at the factory to achieve the specified accuracy. The IMO
frequency is 8 MHz and tolerance is ± 2%.
Power modes supported by PSoC 6 MCUs, in order of
decreasing power consumption, are:
■ System Low Power (LP) – All peripherals and CPU power
modes are available at maximum speed
Internal Low-speed Oscillator (ILO)
The ILO is a very low power oscillator, nominally 32 kHz, which
operates in all power modes. The ILO can be calibrated against
a higher accuracy clock for better accuracy.
■ System Ultra Low Power (ULP) – All peripherals and CPU
power modes are available, but with limited speed
■ CPUActive – CPU is executing code in system LPor ULPmode
Document Number: 002-28690 Rev. *I
Page 12 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 3. Clocking Diagram
Yellow multiplexers
are glitch safe
Root mux
Path Mux
(FLL/PLL)
FLL
Divider
Divider
CM4
CLK_HF[0]
Predivider
(1/2/4/8)
Peripheral
clocks
IMO
clk_peri
Divider
Peripheral
Clock Dividers
TCPWM
SCB
EXTCLK
Predivider
(1/2/4/8)
CLK_HF[1]
CLK_HF[2]
CLK_HF[3]
PLL 0
Audio
CM0+
AHB
ECO
CapSense
LCD
QSPI/SMIF,
SD Host [1]
Predivider
(1/2/4/8)
PLL 1
DMA
Analog
Subsystem
CLK_PATH3
eFuse
MMIO
PPU
Predivider
(1/2/4/8)
USB
Smart I/O
CLK_PATH4
CLK_PATH5
Predivider
(1/2/4/8)
CLK_HF[4]
CLK_HF[5]
SD Host[0]
clk_ext
Crypto
Predivider
(1/2/4/8)
System LP/ULP Domain
System Deep Sleep /
Hibernate Domain
ILO
CLK_LF
WCO
External Crystal Oscillators
See also Table 6 for additional restrictions for general analog
subsystem use.
Figure 4 shows all of the external crystal oscillator circuits for this
product line. The component values shown are typical; check
ECO Specifications for the crystal values, and the crystal
datasheet for the load capacitor values. The ECO and WCO
require balanced external load capacitors. For more information,
see the TRM and AN218241, PSoC 6 MCU Hardware Design
Considerations.
Table 5. ECO Usage Guidelines
Drive
Strength for
VDDD ≤ 2.7 V
Drive Strength
for VDDD ≤ 2.7 V
Ports
Max Frequency
Port 11
60MHzforSMIF DRIVE_SEL 2 DRIVE_SEL 3
(QSPI)
Figure 4. Oscillator Circuits
PSoC 6
Ports12and Slow slew rate No restrictions No restrictions
13 setting
Watchdog Timers (WDT, MCWDT)
PSoC 6 MCU has one WDT and two multi-counter WDTs
(MCWDT). The WDT has a 16-bit free-running counter. Each
MCWDT has two 16-bit counters and one 32-bit counter, with
multiple operating modes. All of the 16-bit counters can generate
a watchdog device reset. All of the counters can generate an
interrupt on a match event.
The WDT is clocked by the ILO. It can generate interrupt/wakeup
in system LP/ULP, Deep Sleep, and Hibernate power modes.
The MCWDTs are clocked by LFCLK (ILO or WCO). It can
generate periodic interrupt / wakeup in system LP/ULP and Deep
Sleep power modes.
MHz XTAL
32.768 kHz XTAL
CL / 2
CL / 2
CL / 2
CL / 2
Clock Dividers
Integer and fractional clock dividers are provided for peripheral
use and timing purposes. There are:
If the ECO is used, note that its performance is affected by GPIO
switching noise. GPIO ports should be used as Table 5 shows.
■ Eight 8-bit clock dividers
■ Sixteen 16-bit integer clock dividers
■ Four 16.5-bit fractional clock dividers
■ One 24.5-bit fractional clock divider
Document Number: 002-28690 Rev. *I
Page 13 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Trigger Routing
Programmable Analog Subsystems
PSoC 6 MCU contains a trigger multiplexer block. This is a
collection of digital multiplexers and switches that are used for
routing trigger signals between peripheral blocks and between
GPIOs and peripheral blocks.
12-bit SAR ADC
The 12-bit, 2-Msps SAR ADC can operate at a maximum clock
rate of 36 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion. One of three internal
reference voltages may be used for an ADC reference voltage.
The references are, VDD, VDD/2, and VREF (nominally 1.2 V and
trimmed to ±1%). An external reference may also be used, by
either driving the VREF pin or routing an external reference to
GPIO pin P9.7. These reference options allow ratio-metric
readings or absolute readings at the accuracy of the reference
used. The input range of the ADC is the full supply voltage
between VSS and VDDA/VDDIOA. The SAR ADC may be
configured with a mix of single-ended and differential signals in
the same configuration.
There are two types of trigger routing. Trigger multiplexers have
reconfigurability in the source and destination. There are also
hardwired switches called “one-to-one triggers”, which connect
a specific source to a destination. The user can enable or disable
the route.
Reset
PSoC 6 MCU can be reset from a variety of sources:
■ Power-on reset (POR) to hold the device in reset while the
power supply ramps up to the level required for the device to
function properly. POR activates automatically at power-up.
■ Brown-out detect (BOD) reset to monitor the digital voltage
supply VDDD and generate a reset if VDDD falls below the
minimum required logic operating voltage.
The SAR ADC’s sample-and-hold (S/H) aperture is
programmable to allow sufficient time for signals with a high
impedance to settle sufficiently, if required. System performance
is 65 dB for true 12-bit precision provided appropriate references
are used and system noise levels permit it. To improve
performance in noisy conditions, an external bypass capacitor
for the internal reference amplifier (through the fixed “VREF”
pin), may be added.
■ External reset dedicated pin (XRES) to reset the device using
an external source. The XRES pin is active low. It can be
connected either to a pull-up resistor to VDDD, or to an active
drive circuit, as Figure 5 shows. If a pull-up resistor is used,
select its value to minimize current draw when the pin is pulled
low; 4.7 kΩ is typical.
The SAR is connected to a fixed set of pins through an input
multiplexer. The multiplexer cycles through the selected
channels autonomously (sequencer scan) and does so with zero
switching overhead (that is, the aggregate sampling bandwidth
is equal to 2 Msps whether it is for a single channel or distributed
over several channels). The result of each channel is buffered,
so that an interrupt may be triggered only when a full scan of all
channels is complete. Also, a pair of range registers can be set
to detect and cause an interrupt if an input exceeds a minimum
and/or maximum value. This allows fast detection of out-of-range
values without having to wait for a sequencer scan to be
completed and the CPU to read the values and check for
out-of-range values in software. The SAR can also be
connected, under firmware control, to most other GPIO pins via
the Analog Multiplexer Bus (AMUXBUS). The SAR is not
available in system Deep Sleep and Hibernate modes as it
requires a high-speed clock (up to 36 MHz). The SAR operating
range is 1.71 to 3.6 V.
Figure 5. XRES Connection Diagram
1.7 to 3.6 V
PSoC 6
VDDD
4.7 kΩ typ.
XRES
XRES
drive
■ Watchdog timer (WDT or MCWDT) to reset the device if
firmware fails to service it within a specified timeout period.
■ Software-initiated reset to reset the device on demand using
firmware.
Temperature Sensor
An on-chip temperature sensor is part of the SAR and may be
scanned by the SAR ADC. It consists of a diode, which is biased
by a current source that can be disabled to save power. The
temperature sensor may be connected directly to the SAR ADC
as one of the measurement channels. The ADC digitizes the
temperature sensor’s output and a Cypress-supplied software
function may be used to convert the reading to temperature
which includes calibration and linearization.
■ Logic-protectionfaultcantrigger aninterruptorresetthedevice
if unauthorized operating conditions occur; for example,
reaching a debug breakpoint while executing privileged code.
■ Hibernate wakeup reset to bring the device out of the system
Hibernate power mode.
Reset events are asynchronous and guarantee reversion to a
known state. Some of the reset sources are recorded in a
register, which is retained through reset and allows software to
determine the cause of the reset.
Low-Power Comparators
Two low-power comparators are provided, which can operate in
all power modes. This allows other analog system resources to
be disabled while retaining the ability to monitor external voltage
levels during system Deep Sleep and Hibernate modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator-switch event.
Document Number: 002-28690 Rev. *I
Page 14 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 6 shows an overview of the analog subsystem. This diagram is a high-level abstraction. See the TRM for detailed connectivity
information.
Figure 6. Analog Subsystem
AMUXBUSA
Red dots indicate
AMUXBUS splitter
switches
AMUXBUSB
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
CSD
LPCOMP0
inp
inn
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
shield_pad
vref_ext
csh
cmod
amuxbusa
amuxbusb
LPCOMP1
inp
inn
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P4.0
P4.1
P4.2
P4.3
P14.0
P14.1
P9.7
P9.6
P9.5
P9.4
P9.3
P9.2
P9.1
P9.0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
AREF, 1.2 V
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
SAR ADC
vplus
vminus
vref
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
SARREF
VDDA
VDDA / 2
TEMP
temp
VSS
To VREF pin, for bypass capacitor
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
Document Number: 002-28690 Rev. *I
Page 15 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
In this device there are:
■ Eight 32-bit TCPWMs
■ Twenty-four 16-bit TCPWMs
Programmable Digital
Smart I/O
Smart I/O is a programmable logic fabric that enables Boolean
operations on signals traveling from device internal resources to
the GPIO pins or on signals traveling into the device from
external sources. A Smart I/O block sits between the GPIO pins
and the high-speed I/O matrix (HSIOM) and is dedicated to a
single port.
Serial Communication Blocks (SCB)
This product line has 13 SCBs:
■ Eight can implement either I2C, UART, or SPI.
■ Four can implement either I2C or UART.
■ One SCB (SCB #8) can operate in system Deep Sleep mode
with an external clock; this SCB can be either SPI slave or I2C
slave.
There are two Smart I/O blocks: one on Port 8 and one on Port 9.
When Smart I/O is not enabled, all signals on Port 8 and Port 9
bypass the Smart I/O hardware.
I2C Mode: The SCB can implement a full multi-master and slave
interface (it is capable of multimaster arbitration). This block can
operate at speeds of up to 1 Mbps (Fast Mode Plus). It also
supports EZI2C, which creates a mailbox address range and
effectively reduces I2C communication to reading from and
writing to an array in memory. The SCB supports a 256-byte
FIFO for receive and transmit.
The I2C peripheral is compatible with I2C standard-mode, Fast
Mode, and Fast Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
Smart I/O supports:
■ System Deep Sleep operation
■ Boolean operations without CPU intervention
■ Asynchronous or synchronous (clocked) operation
Each Smart I/O block contains a data unit (DU) and eight lookup
tables (LUTs).
The DU:
■ Performs unique functions based on a selectable opcode.
■ Can source input signals from internal resources, the GPIO
port, or a value in the DU register.
UART Mode: This is a full-feature UART operating at up to
8 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows the
addressing of peripherals connected over common Rx and Tx
lines. Common UART functions such as parity error, break
detect, and frame error are supported. A 256-byte FIFO allows
much greater CPU service latencies to be tolerated.
Each LUT:
■ Has three selectable input sources. The input signals may be
sourced from another LUT, an internal resource, an external
signal from a GPIO pin, or from the DU.
■ Acts as a programmable Boolean logic table.
■ Can be synchronous or asynchronous.
Fixed-Function Digital
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure
Simple Pairing (SSP) (essentially adds a start pulse that is used
to synchronize SPI Codecs), and National Microwire (half-duplex
form of SPI). The SPI block supports an EZSPI mode in which
the data interchange is reduced to reading and writing an array
in memory. The SPI interface operates with a 25-MHz clock.
Timer/Counter/Pulse-width Modulator (TCPWM)
■ The TCPWM supports the following operational modes:
❐ Timer-counter with compare
❐ Timer-counter with capture
❐ Quadrature decoding
USB Full-Speed Device Interface
❐ Pulse width modulation (PWM)
❐ Pseudo-random PWM
❐ PWM with dead time
This product line incorporates a full-speed USB device interface.
The device can have up to eight endpoints. A 512-byte SRAM
buffer is provided and DMA is supported.
■ Up, down, and up/down counting modes
■ Clock prescaling (division by 1, 2, 4, ... 64, 128)
■ Double buffering of compare/capture and period values
■ Underflow, overflow, and capture/compare output signals
■ Supports interrupt on:
❐ Terminal count – Depends on the mode; typically occurs on
overflow or underflow
❐ Capture/compare – The count is captured to the capture reg-
ister or the counter value equals the value in the compare
register
Note: If the USB pins are not used, connect VDDUSB to ground
and leave the P14.0/USBDP and P14.1/USBDM pins
unconnected.
Quad-SPI/Serial Memory Interface (SMIF)
A serial memory interface is provided, running at up to 80 MHz.
It supports single, dual, quad, dual-quad and octal SPI
configurations, and supports up to four external memory devices.
It supports two modes of operation:
■ Memory-mapped I/O (MMIO), a command mode interface that
provides data access via registers and FIFOs
■ Complementary output for PWMs
■ Execute in Place (XIP), in which AHB reads and writes are
directly translated to SPI read and write transfers.
■ Selectable start, reload, stop, count, and capture event signals
for each TCPWM; with rising edge, falling edge, both edges,
and level trigger options. The TCPWM has a Kill input to force
outputs to a predetermined state.
Document Number: 002-28690 Rev. *I
Page 16 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
In XIP mode, the external memory is mapped into the PSoC 6
MCU internal address space, enabling code execution directly
from the external memory. To improve performance, a 4-KB
cache is included. XIP mode also supports AES-128 on-the-fly
encryption and decryption, enabling secured storage and access
of code and data in the external memory.
For eMMC, the supported modes are:
■ BWC (backward compatibility)
■ SDR
Maximum clock restrictions and capacitive loads apply to some
modes, and are also dependent on system power mode
(LP/ULP). Refer to the SD Host Controller and eMMC
Specifications for details.
LCD
This block drives LCD commons and segments; routing is
available to most of the GPIOs. One to eight of the GPIOs must
be used for commons, the rest can be used for segments.
The SD Host Controller complies with the following standards.
Refer to the specifications documents for more information on
the protocol and operations.
The LCD block has two modes of operation: high speed (8 MHz)
and low speed (32 kHz). Both modes operate in system LP and
ULP modes. Low-speed mode operates with reduced contrast in
system Deep Sleep mode - review the number of common and
segment lines, viewing angle requirements, and prototype
performance before using this mode.
■ SD Specifications Part 1 Physical Layer Specification Version
6.00, supporting card capacities for SDSC (up to 2 GB), SDHC
(up to 32 GB) and SDXC (up to 2 TB).
■ SD Specifications Part A2 SD Host Controller Standard Speci-
fication Version 4.20
SD Host Controllers
■ SD Specifications Part E1 SDIO Specifications Version 4.10
■ Embedded Multi-Media Card (eMMC) Electrical Standard 5.1
This product line contains two Secure Digital (SD) host
controllers. They provide communication with IoT connectivity
devices such as Bluetooth, Bluetooth Low-Energy and WiFi
radios, as well as combination devices. The controller also
supports embedded MultiMediaCards (eMMC) and Secure
Digital (SD) cards.
The SD Host Controller is configured as a master. To be fully
compatible with features provided in the driver software for
speed and efficiency, it supports advanced DMA version 3
(ADMA3), defined by the SDIO standard, and has a 1-KB Rx/Tx
FIFO allowing double buffering of 512-byte blocks.
Several bus speed modes under the SD specification are
supported:
■ DS (default speed)
■ HS (high speed)
■ SDR12 (single data rate)
■ SDR25
■ SDR50
■ DDR50 (double data rate)
Document Number: 002-28690 Rev. *I
Page 17 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
The port 1 pins are capable of overvoltage-tolerant (OVT)
GPIO
operation, where the input voltage may be higher than VDDD
.
This product line has up to 100 GPIOs, which implement the
following:
OVT pins are commonly used with I2C, to allow powering the
chip OFF while maintaining a physical connection to an
operating I2C bus without affecting its functionality.
■ Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
GPIO pins can be ganged to source or sink higher values of
current. GPIO pins, including OVT pins, may not be pulled up
higher than the absolute maximum; see Electrical Specifications.
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
During power-on and reset, the pins are forced to the analog
input drive mode, with input and output buffers disabled, so as
not to crowbar any inputs and/or cause excess turn-on current.
A multiplexing network known as the high-speed I/O matrix
(HSIOM) is used to multiplex between various peripheral and
analog signals that may connect to an I/O pin.
■ Input threshold select (CMOS or LVTTL)
■ Hold mode for latching previous state (used for retaining the
I/O state in system Hibernate mode)
Analog performance is affected by GPIO switching noise. In
order to get the best analog performance, the following
frequency and drive mode constraints must be applied. The
DRIVE_SEL values (refer to Table 6) represent drive strengths
Architecture and Register TRMs . Contact your local Cypress
sales representative for the latest TRM.
■ Selectable slew rates for dV/dt-related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
up to 8 pins in width. Data output and pin state registers store,
respectively, the values to be driven on the pins and the input
states of the pins.
See also Table 5 for additional restrictions for ECO use.
Every pin can generate an interrupt if enabled; each port has an
interrupt request (IRQ) associated with it.
Table 6. DRIVE_SEL Values
Ports
Ports 0, 1
Port 2
Max Frequency
8 MHz
Drive Strength for VDDD ≤ 2.7 V Drive Strength for VDDD > 2.7 V
DRIVE_SEL 2
DRIVE_SEL 1
DRIVE_SEL 2
DRIVE_SEL 1
DRIVE_SEL 3
DRIVE_SEL 2
DRIVE_SEL 3
DRIVE_SEL 2
50 MHz
Ports 3 to 10
Ports 11 to 13
16 MHz; 25 MHz for SPI
80 MHz for SMIF (QSPI).
The PDM-to-PCM decoder implements a single hardware Rx
FIFO that decodes a stereo or mono 1-bit PDM input stream to
PCM data output. The following features are supported:
Special-Function Peripherals
Audio Subsystem
This subsystem consists of the following hardware blocks:
■ Programmable data output word length – 16/18/20/24 bits
■ Two Inter-IC Sound (I2S) interfaces
■ Programmable gain amplifier (PGA) for volume control – from
■ Two PDM to PCM decoder channels
–12 dB to +10.5 dB in 1.5 dB steps
Each of the I2S interfaces implements two independent
hardware FIFO buffers – Tx and Rx, which can operate in master
or slave mode. The following features are supported:
■ Configurable PDM clock generation. Range from 384 kHz to
3.072 MHz
■ Droop correction and configurable decimation rate for
sampling; up to 48 ksps
■ Multiple data formats – I2S, left-justified, Time Division Multi-
plexed (TDM) mode A, and TDM mode B
■ Programmable high-pass filter gain
■ Programmable channel/word lengths – 8/16/18/20/24/32 bits
■ Internal/external clock operation up to 192 ksps
■ Interrupt mask events – not empty, overflow, trigger, underflow
■ Configurable FIFO trigger level with DMA support
■ Interrupt mask events – trigger, not empty, full, overflow,
underflow, watchdog
The PDM-to-PCM decoder is commonly used to connect to
digital PDM microphones. Up to two microphones can be
connected to the same PDM Data line.
■ Configurable FIFO trigger level with DMA support
The I2S interface is commonly used to connect with audio
codecs, simple DACs, and digital microphones.
Document Number: 002-28690 Rev. *I
Page 18 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
CapSense Subsystem
IDAC
CapSense is supported in PSoC 6 MCU through a CapSense
sigma-delta (CSD) hardware block. It is designed for
high-sensitivity self-capacitance and mutual-capacitance
measurements, and is specifically built for user interface
solutions.
The CSD block has two programmable current sources, which
offer the following features:
■ 7-bit resolution
■ Sink and source current modes
■ A current source programmable from 37.5 nA to 609 A
In addition to CapSense, the CSD hardware block supports three
general-purpose functions. These are available when CapSense
is not being used. Alternatively, two or more functions can be
time-multiplexed in an application under firmware control. The
four functions supported by the CSD hardware block are:
■ Two IDACs that can be used in parallel to form one 8-bit IDAC
Comparator
The CapSense subsystem comparator operates in the system
Low Power and Ultra-Low Power modes. The inverting input is
connected to an internal programmable reference voltage and
the non-inverting input can be connected to any GPIO via the
AMUXBUS.
■ CapSense
■ 10-bit ADC
■ Programmable current sources (IDAC)
■ Comparator
CapSense Hardware Subsystem
CapSense
Figure 7 shows the high-level hardware overview of the
CapSense subsystem, which includes a delta sigma converter,
internal clock dividers, a shield driver, and two programmable
current sources.
Capacitive touch sensors are designed for user interfaces that
rely on human body capacitance to detect the presence of a
finger on or near a sensor. Cypress CapSense solutions bring
elegant, reliable, and simple capacitive touch sensing functions
to applications including IoT, industrial, automotive, and home
appliances.
The inputs are managed through analog multiplexed buses
(AMUXBUS A/B). The input and output of all functions offered by
the CSD block can be provided on any GPIO or on a group of
GPIOs under software control, with the exception of the
comparator output and external capacitors that use dedicated
GPIOs.
The Cypress-proprietary CapSense technology offers the
following features:
■ Best-in-class signal-to-noise ratio (SNR) and robust sensing
under harsh and noisy conditions
Self-capacitance is supported by the CSD block using
AMUXBUS A, an external modulator capacitor, and a GPIO for
each sensor. There is a shield electrode (optional) for
self-capacitance sensing. This is supported using AMUXBUS B
and an optional external shield tank capacitor (to increase the
drive capability of the shield driver) should this be required.
Mutual-capacitance is supported by the CSD block using
AMUXBUS A, two external integrated capacitors, and a GPIO for
transmit and receive electrodes.
■ Self-capacitance (CSD) and mutual-capacitance (CSX)
sensing methods
■ Support for various widgets, including buttons, matrix buttons,
sliders, touchpads, and proximity sensors
■ High-performance sensing across a variety of materials
■ Best-in-class liquid tolerance
The ADC does not require an external component. Any GPIO
that can be connected to AMUXBUS A can be an input to the
ADC under software control. The ADC can accept VDDA as an
input without needing GPIOs (for applications such as battery
voltage measurement).
■ SmartSense™ auto-tuning technology that helps avoid
complex manual tuning processes
■ Superior immunity against external noise
■ Spread-spectrum clocks for low radiated emissions
■ Gesture and built-in self-test libraries
■ Ultra-low power consumption
The two programmable current sources (IDACs) in
general-purpose mode can be connected to AMUXBUS A or B.
They can therefore connect to any GPIO pin. The comparator
resides in the delta-sigma converter. The comparator inverting
input can be connected to the reference. Both comparator inputs
can be connected to any GPIO using AMUXBUS B; see
Figure 7. The reference has a direct connection to a dedicated
GPIO; see Table 9.
■ An integrated graphical CapSense tuner for real-time tuning,
testing, and debugging
ADC
The CapSense subsystem slope ADC offers the following
features:
The CSD block can operate in active and sleep CPU power
modes, and seamlessly transition between system LP and ULP
modes. It can be powered down in system Deep Sleep and
Hibernate modes. Upon wakeup from Hibernate mode, the CSD
block requires re-initialization. However, operation can be
resumed without re-initialization upon exit from Deep Sleep
mode, under firmware control.
■ Selectable 8- or 10-bit resolution
■ Selectable input range: GND to VREF and GND to VDDA on any
GPIO input
■ MeasurementofVDDA against aninternal referencewithoutthe
use of GPIO or external components
Document Number: 002-28690 Rev. *I
Page 19 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 7. CapSense Hardware Subsystem
AMUXBUS
A
B
GPIO Pin
GPIO
Cell
CSD Sensor1
Clock Input
C
S1
GPIO Pin
GPIO
Cell
CSD Sensor 2
C
S2
CSD Hardware Block
C
Pin
MOD
C
Sense clock
MOD
Clock
Generator
C
_
SH TANK
GPIO Pin
( optional
)
Shield Drive
Circuit
Modulator
Clock
GPIO Pin
GPIO
Cell
Compensation
IDAC
C
Shield Electrode
SHIELD
Modulator
IDAC
GPIO Pin
IDAC control
Tx
GPIO
Cell
CSX Sensor3
C
S3
Raw
Count
Sigma Delta
Converter
GPIO Pin
Rx
GPIO
Cell
V
REF
C
Pin
INTA
GPIO
Cell
C
INTA
C
INTB
C
Pin
INTB
GPIO
Cell
ADC Input
IDAC Outputs
Comp Input
Document Number: 002-28690 Rev. *I
Page 20 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 8 shows the high-level software overview. Cypress
provides middleware libraries for CapSense, ADC, and IDAC on
GitHub to enable quick integration. The Board Support Package
for any kit with CapSense capabilities automatically includes the
CapSense library in any application that uses the BSP.
CapSense and ADC middleware use the CSD interrupt to
implement non-blocking sensing and A-to-D conversion.
Therefore, interrupt service routines are a defined part of the
middleware, which must be initialized by the application.
Middleware and drivers can operate on either CPU. Cypress
recommends using the middleware only in one CPU. If both
CPUs must access the CSD driver, memory access should be
managed in the application.
User applications interact only with middleware to implement
functions of the CSD block. The middleware interacts with
underlying drivers to access hardware as necessary. The CSD
driver facilitates time-multiplexing of the CSD hardware if more
than one piece of CSD-related middleware is present in a project.
It prevents access conflicts in this case.
Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design
Guide for more details on CSX sensing, CSD sensing, shield
electrode usage and its benefits, and capacitive system design
guidelines.
ModusToolbox Software provides a CapSense configurator to
enable fast library configuration. It also provides a tuner for
performance evaluation and real-time tuning of the system. The
tuner requires an EZI2C communication interface in the
application to enable real-time tuning capability. The tuner can
update configuration parameters directly in the device as well as
in the configurator.
Refer to theAPI reference guides for CapSense, ADC, and IDAC
available on GitHub.
Figure 8. CapSense Software/Firmware Subsystem
Application Program
Middleware
Software
Configurator
Tuner
SCB Driver (EZI 2C)
CSD Driver
GPIO / Clock Drivers
SCB
CSD Block
GPIOs / Clock
Hardware and Drivers
Document Number: 002-28690 Rev. *I
Page 21 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
The first step in using a PSoC 64 device is to inject the following
information into the device - a process called provisioning:
PSoC 64 Security
All PSoC 64 “Secure” MCU product lines feature enhanced
security functionality. They provide an isolated root of trust (RoT)
with true attestation and provisioning services. Cypress also
provides a “Secure Boot” SDK User Guide, which includes all
required libraries, tools, and sample code to provision PSoC 64
devices. The SDK also provides provisioning scripts with sample
keys and policies, a pre-built bootloader image, and tools for
signing firmware images. For more information, see the “Secure
Boot” SDK User Guide.
■ A set of cryptographic public keys, which are used to:
❐ Transfer the RoT from Cypress to the user/OEM, as Figure 9
shows
❐ Validate applications
■ A set of security policies that define how the device should
behave
■ Certificates (optional) used to bind device identity or provide a
The “Secure Boot” SDK also includes entrance exam scripts. An
entrance exam can optionally be run on PSoC 64 devices before
provisioning to ensure that no device tampering has occurred.
chain of trust to a higher certifying authority
■ The Cypress Bootloader
Provisioning is done before an application is programmed into
the device.
Figure 9. PSoC 64 Usage Processes
Program
Manufacture
Take Over Root-of-Trust
Setup chip security
Application
User RoT
User RoT
OEM RoT
Public Key
Cy RoT
Public Key
Public Key
Public Key
Unique Device
Identity
Unique Device
Identity
Unique Device
Identity
PSoC 64
Keys, Security
Policies, Certificates
Keys, Security
Policies, Certificates
PSoC 64
Cypress Bootloader
Cypress Bootloader
PSoC 64
User Application
PSoC 64
Provisioning is done using a hardware security module (HSM). An HSM is a physical computing device, placed in a secured facility,
that safeguards and manages digital keys for strong authentication, and provides cryptographic processing.
After the device is provisioned, it can be programmed with signed applications. The signature and authenticity of the application is
verified before control is transferred to it.
Document Number: 002-28690 Rev. *I
Page 22 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 10 shows a simplified flash memory map of PSoC 64 assets and immutable sections. As noted in Memory, a portion of device
SRAM is also reserved for system usage.
Figure 10. PSoC 64 “Secure” MCU Asset Memory Map
0x1000:0000
User Application Space
Typically immutable, can be
0x101D:0000
updated if allowed by security
Cypress Bootloader
policy during provisioning
0x101E:0000
“Secure Flash Boot”
Immutable after Cypress
Manufacturing
OEM Asset storage
0x101F:BF00
0x101F:FFFF
Typically immutable, can be
partially updated if allowed by
security policy during provisioning
User Flash
0x1600:7FFF
“Secure Flash Boot” +
Cypress Public Key
0x1600:0000
0x0001:FFFF
Supervisory Flash
Boot ROM
ROM
Immutable after Cypress
Manufacturing
0x0000:0000
Document Number: 002-28690 Rev. *I
Page 23 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Cypress Bootloader
The Cypress Bootloader supports external memory over the
PSoC 64 Serial Memory Interface (SMIF). The bootloader
currently supports only external memory vendors who support
the Serial Flash Discovery Protocol (SFDP).
The Cypress Bootloader is a port of the open source MCUBoot
library. For more details about this library, refer to MCUBoot
Bootloader design. The current version of the Cypress
Bootloader for this device does not support the swap-based
images feature as documented in the MCUBoot design
document.
The Cypress Bootloader enforces protection contexts for the
bootloader code, so code running in another protection context
may be prohibited from overwriting/tampering with the
bootloader code. Figure 11 shows the launch sequence of the
Cypress Bootloader:
The Cypress Bootloader is included in the “Secure Boot” SDK as
a pre-built hex image. This image acts as the first image
launched by the PSoC 64 boot code. It parses the provisioned
Boot&Upgrade policy to launch an application image.
Figure 11. Bootloader Launch Sequence
Reads for setting
access policies
Boot ROM +
“Secure Flash Boot”
Address of Bootloader image
and key for verification
Verifies & Launches
Verifies & Launches
Debug Policy
Cypress Bootloader
Boot Policy
Bootloader Certificate
Address of User image
and key for verification
Provisioned Policies
First User Image
Signed with OEM Pvt key
Figure 12 shows a typical application update scenario using the Cypress Bootloader:
Figure 12. Bootloader Application Update Sequence
New image available
Bootloader verifies new image
Bootloader updates current
image
Immutable Boot Code
Cypress Bootloader
Immutable Boot Code
Immutable Boot Code
Cypress Bootloader
Keys, Policies
Cypress Bootloader
Keys, Policies
Keys, Policies
Update image,
launches
New Image
Customer
Verifies new
Application v2
Customer Application v1
Signed with User Privkey
Customer Application v2
Signed with User Privkey
image content
and signature
with provisioned
keys
Customer Application v1
Signed with User Privkey
Signed with User
Privkey
Image
Written
Slot#0
Slot#0
Slot#0
Customer Application v2
Signed with User Privkey
Slot#1, empty
Slot#1, empty
Slot#1
Internal (or) External flash
Internal (or) External flash
Internal (or) External flash
Document Number: 002-28690 Rev. *I
Page 24 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Amazon FreeRTOS PSA
this binary against the Amazon FreeRTOS ecosystem. Cypress
adds a layer in the Amazon FreeRTOS side that uses the TF-M
binary using standard PSA calls.
Note: This product line has been tested with FreeRTOS version
202007.00.
Platform Security Architecture (PSA). The goal of PSA is to
design security into IoT devices right from the start with specific
hardware requirements. This gives vendors a direction and
confidence in providing secured IoT devices. The PSA
certification program allows OEM vendors to declare they have
followed the recommendations to make their device secured. For
consumers, the PSA certification gives them confidence in
buying a secured device from a vendor. Depending on the level
of security sought, PSA provides three levels of certification
where each level has more stringent testing.
The PSoC 64 “Standard Secure” AWS product line provides a
platform security architecture (PSA) level-2 certified method to
connect to Amazon Web Services. PSA is a set of threat models,
security analysis, hardware and firmware architecture
specifications, open source firmware reference implementation,
and independent evaluation and certification. PSA provides the
following:
■ A hardware and firmware architecture based on a set of speci-
fications such as the Security Model (PSA-SM) and Firmware
Framework (PSA-FF)
PSA is currently supported on Cortex-M based IoT solutions.
PSA provides a reference implementation of PSA FF that allows
vendors to quickly implement a PSA compliant system. The
reference implementation for Cortex-M based solutions is called
Trusted Firmware M.
■ Documents pertaining to boot and upgrade requirements
■ Defined isolation levels that compartmentalize software and
services
■ An outline of a certification process that helps identify the level
of security. Currently it has three levels of certification: L1, L2,
and L3.
TF-M is a reference implementation of PSA. This reference
implementation is governed by Linaro and hosted on
trustedfirmware.org. Arm and partner companies including
Cypress contribute to this open source project.
■ An API for secured services such as crypto, secured storage,
As indicated in the name, TF-M is a solution for Cortex-M based
solutions. TF-M implements the necessary framework as well as
the following services.
and attestation
■ A reference implementation for Cortex-M class processors
called Trusted Firmware M (TF-M)
■ PSA Cryptography, to provide crypto functionality
Amazon FreeRTOS is an Amazon-supported embedded
ecosystem that provides a development environment for IoT
devices including WiFi connectivity. The PSoC 64 “Standard
Secure” AWS provides a pre-built TF-M layer to Amazon
FreeRTOS, as well as all the required AWS FreeRTOS
enhancements.
■ PSAProtected Storage, used to provide security in storing data
in external flash
■ PSA Internal Trusted Storage, used to provide trusted storage
in internal flash
PSA Attestation, to provide a method for a server to verify the
authenticity of a device that is connected.
The TF-M binary delivered in this product line is based on code
maintained in trustedfirmware.org. Cypress tests and validates
Document Number: 002-28690 Rev. *I
Page 25 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Amazon FreeRTOS and AWS “Standard Secure”
Amazon FreeRTOS is an Amazon supported ecosystem that provides an IoT development environment for IoT devices including WiFi
connectivity. The intention is to help users/OEMs create IoT devices that connect to Amazon AWS. AWS “Standard Secure” provides
an SPE and PSA compliance. Figure 13 depicts the overall AWS “Standard Secure” Solution.
Figure 13. AWS “Standard Secure” Solution Diagram
NSPE
SPE
AFR API
Root of
Trust
PKCS#11
I
I
PSA
API
P P
C C
FreeRTOS
WHD
FW
Update
mbedTLS
LWIP
SPM
As shown, the system has two separate processing
environments. Amazon FreeRTOS runs in the NSPE. The SPE
used in AWS “Standard Secure” is Trusted Firmware M.
PKCS#11: The PKCS#11 API is used by Amazon FreeRTOS for
secured storage of certificates/keys and for asymmetric
cryptography using these keys. PKCS#11 integration uses the
“Secure” Storage and Crypto in the SPE.
In this model, Amazon FreeRTOS is free to execute without
accessing any features or APIs provided by the SPE. However,
the idea of the integration is to allow Amazon FreeRTOS to
provide secured storage, device identity, and cryptography by
using the secured services made available by SPE.
Mbed TLS: Amazon FreeRTOS uses Mbed TLS for symmetric
cryptography.
OTA: Although OTA requires authentication of the incoming
upgrade package, no specific PSA integration is currently
implemented in the SPE layer. The Cypress Bootloader meets
the requirements set out by PSA on boot requirements. An OTA
upgrade package in AWS “Standard Secure” consists of either
one or both of the SPE and NSPE images. The SPE and NSPE
images are individually signed and can be authenticated with
Cypress Bootloader. In this case, the bootloader and PSoC 64's
secured boot and provisioning procedure provides the secured
upgrade. If the authentication fails, the bootloader does not
perform the upgrade.
Communication between NSPE and SPE is accomplished using
the PSoC 6 InterProcessor Communication (IPC), as Figure 13
shows.
The SPE implementation provides a library of source and header
files ("PSA API" in Figure 13) that is included in the NSPE to
access the services provided by the SPE. PSA can then be
integrated into Amazon FreeRTOS.
PSA Integration: PSA Integration redirects security sensitive
functionality to the SPE. This is done using the PSA API. PSA
Integration is done in Amazon FreeRTOS in the following areas;
note that this list is constantly evolving. Please check the
https://github.com/aws/amazon-freertos for the latest details.
This upgrade package is double-signed with an Amazon OTA
verification key. The OTA agent has a verification certificate built
into the image that is used to initially authenticate the incoming
package. If the verification key pair needs to be upgraded, that
can be accomplished by upgrading the NSPE image with a new
verification certificate.
TRNG: True Random Number Generation is accomplished using
the PSoC 6 Crypto block, which is exclusively controlled by the
SPE.
Document Number: 002-28690 Rev. *I
Page 26 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Arm PSA Certification Level 2
This product line is certified PSA Level 2. Retaining the
certification in an end system requires several constraints on the
use of the product:
for cryptographic purposes without thoroughly understanding
the potential security weaknesses.
The features that are present in the product but fall outside of the
secured configuration are:
■ OEMs must follow the direction in the “Secure Boot” SDK User
Guide for transferring root of trust and signing the images with
the OEM RoT private key
■ Symmetric Algorithms
❐ DES
■ The Debug Access Port (DAP) must be disabled for the CM0+
Secured Processing Environment
❐ Triple DES
❐ RC4
■ Use cryptographic algorithms that are within the scope of the
PSA L2 certification such as the ones defined in the PSA
Platform Security Boot Guide
❐ RSA – with 2048 key lengths or higher and the RSA-PSS
scheme
■ Symmetric Modes
❐ CBC
❐ CBCMAC
■ Hashes
❐ MD2
❐ MD4
❐ ECC and ECDSA – with 256-bit key lengths or higher with
NIST P-256 curves
❐ Hashing – Secure Hash Algorithm 2 (at least 256 bits)
❐ MD5
❐ RIPEMD160
❐ SHA_1
■ Avoid use of legacy cryptographic algorithms that are outside
the scope of the PSA L2 certification and only provided for
compatibility. The use of these algorithms is not recommended
Document Number: 002-28690 Rev. *I
Page 27 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Pinouts
Power supplies and ports correspond as follows:
■ P0: VBACKUP
■ P1: VDDD. Port 1 pins are overvoltage tolerant (OVT).
■ P2, P3, P4: VDDIO2
■ P5, P6, P7, P8: VDDIO1
■ P9, P10: VDDIO, VDDA (VDDIOA and VDDA must be connected together on the PCB)
■ P11, P12, P13: VDDIO0
■ P14: VDDUSB
Table 7. Packages and Pin Information
Packages
Pin
124-BGA
100-WLCSP
VDDD
VCCD
VDDA
VDDIOA
VDDIO0
VDDIO1
VDDIO2
VBACKUP
VDDUSB
VSS
A1
D14
A2
C15
A12
J1
A13
-
C4
A11
K12
K2
L4
M10
D1
C17
M1
J17
B12, C3, D4, D10, K4, K10
D2, E13, J13, L1
VDD_NS
VIND1
XRES
VREF
P0.0
J1
J2
J15
H16
E17
C3
F1
B13
E3
E2
E1
F3
F2
G3
G2
G1
H3
H2
H1
J3
F14
G13
D16
E15
G11
F16
H12
G15
-
P0.1
P0.2
P0.3
P0.4
P0.5
P1.0
P1.1
P1.2
P1.3
-
P1.4
H14
G17
L17
K12
L15
P1.5
P2.0
M2
N2
L3
P2.1
P2.2
Document Number: 002-28690 Rev. *I
Page 28 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 7. Packages and Pin Information (continued)
Packages
Pin
124-BGA
100-WLCSP
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P4.0
P4.1
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
P8.4
M3
N3
L13
L11
M16
M14
M12
-
N1
M4
N4
L5
M5
-
N5
-
L6
-
M6
-
N6
-
L7
-
M7
-
N7
M8
K10
J11
H10
L9
M6
G9
G7
M4
L7
L5
K8
J9
L3
M2
K4
K6
J7
J3
H8
-
L8
M8
N8
L9
M9
N9
N10
M10
L10
L11
M11
N11
M12
N12
M13
L13
L12
K13
N13
K11
J13
J12
J11
H13
H12
H11
G13
G12
-
-
G1
H2
J5
H6
H4
F2
Document Number: 002-28690 Rev. *I
Page 29 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 7. Packages and Pin Information (continued)
Packages
Pin
124-BGA
100-WLCSP
P8.5
P8.6
G11
F13
F12
E11
E12
E13
F11
D13
D12
D11
C13
C12
A11
B11
C11
A10
B10
C10
A9
-
-
P8.7
-
P9.0
E1
G3
G5
F4
E3
-
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
-
P9.7
C1
F6
E5
B2
D4
C5
B4
A3
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
F8
E9
B9
C9
D6
A8
E7
B8
A7
C8
B6
A7
A5
B7
C7
C7
B8
A6
A9
B6
D8
C6
A13
B10
C9
A5
B5
C5
B12
C11
D10
B14
A15
C13
D12
E11
A4
B4
B1
A3
B3
B2
C2
Document Number: 002-28690 Rev. *I
Page 30 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 7. Packages and Pin Information (continued)
Packages
Pin
124-BGA
100-WLCSP
F10
C1
D3
D2
L2
L1
P13.5
P13.6
F12
P13.7
B16
P14.0/ USBDP
P14.1/ USBDM
K14
K16
Note: Balls K2 and K3 are connected together internally in the 124-BGA package.
Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins unconnected.
Note
3. DNC means Do Not Connect. Do Not Connect anything to these pins.
Document Number: 002-28690 Rev. *I
Page 31 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Each port pin has multiple alternate functions. These are defined in Table 8. The columns ACT #x and DS #y denote active (System LP/ULP) and Deep Sleep mode signals
respectively.
The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there is more than one signal for
a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the
fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize use of on-chip resources.
Table 8. Multiple Alternate Functions
Port/
Pin
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P0.0
tcpwm[0].
line[0]:0
tcpwm[1]
.line[0]:0
csd.csd
_tx:0
csd.csd
_tx_n:0
srss.e
xt_clk:
0
scb[0].
spi_se
lect1:0
peri.tr
_io_in
put[0]:
0
P0.1
tcpwm[0].
line_com
pl[0]:0
tcpwm[1]
.line_co
mpl[0]:0
csd.csd
_tx:1
csd.csd
_tx_n:1
scb[0].
spi_se
lect2:0
peri.tr
_io_in
put[1]:
0
P0.2
P0.3
P0.4
P0.5
P1.0
tcpwm[0].
line[1]:0
tcpwm[1]
.line[1]:0
csd.csd
_tx:2
csd.csd
_tx_n:2
scb[0]
.uart_
rx:0
scb[0].
i2c_scl
:0
scb[0].
spi_m
osi:0
tcpwm[0].
line_com
pl[1]:0
tcpwm[1]
.line_co
mpl[1]:0
csd.csd
_tx:3
csd.csd
_tx_n:3
scb[0]
.uart_
tx:0
scb[0].
i2c_sd
a:0
scb[0].
spi_mi
so:0
tcpwm[0].
line[2]:0
tcpwm[1]
.line[2]:0
csd.csd
_tx:4
csd.csd
_tx_n:4
scb[0]
.uart_
rts:0
scb[0].
spi_cl
k:0
peri.tr_io_
output[0]:2
tcpwm[0].
line_com
pl[2]:0
tcpwm[1]
.line_co
mpl[2]:0
csd.csd
_tx:5
csd.csd
_tx_n:5
srss.e
xt_clk:
1
scb[0]
.uart_
cts:0
scb[0].
spi_se
lect0:0
peri.tr_io_
output[1]:2
tcpwm[0].
line[3]:0
tcpwm[1]
.line[3]:0
csd.csd
_tx:6
csd.csd
_tx_n:6
scb[7]
.uart_
rx:0
scb[7].
i2c_scl
:0
scb[7].
spi_m
osi:0
peri.tr
_io_in
put[2]:
0
P1.1
tcpwm[0].
line_com
pl[3]:0
tcpwm[1]
.line_co
mpl[3]:0
csd.csd
_tx:7
csd.csd
_tx_n:7
scb[7]
.uart_
tx:0
scb[7].
i2c_sd
a:0
scb[7].
spi_mi
so:0
peri.tr
_io_in
put[3]:
0
P1.2
P1.3
tcpwm[0].
line[4]:4
tcpwm[1]
.line[12]:
1
csd.csd
_tx:8
csd.csd
_tx_n:8
scb[7]
.uart_
rts:0
scb[7].
spi_cl
k:0
tcpwm[0].
line_com
pl[4]:4
tcpwm[1]
.line_co
mpl[12]:1
csd.csd
_tx:9
csd.csd
_tx_n:9
scb[7]
.uart_
cts:0
scb[7].
spi_se
lect0:0
Document Number: 002-28690 Rev. *I
Page 32 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P1.4
P1.5
P2.0
tcpwm[0].
line[5]:4
tcpwm[1]
.line[13]:
1
csd.csd
_tx:10
csd.csd
_tx_n:1
0
scb[7].
spi_se
lect1:0
tcpwm[0].
line_com
pl[5]:4
tcpwm[1]
.line_co
mpl[14]:1
csd.csd
_tx:11
csd.csd
_tx_n:1
1
scb[7].
spi_se
lect2:0
tcpwm[0].
line[6]:4
tcpwm[1]
.line[15]:
1
csd.csd
_tx:12
csd.csd
_tx_n:1
2
scb[1]
.uart_
rx:0
scb[1].
i2c_scl
:0
scb[1].
spi_m
osi:0
peri.tr
_io_in
put[4]:
0
sdhc[0].
card_da
t_3to0[0
]
P2.1
P2.2
P2.3
tcpwm[0].
line_com
pl[6]:4
tcpwm[1]
.line_co
mpl[15]:1
csd.csd
_tx:13
csd.csd
_tx_n:1
3
scb[1]
.uart_
tx:0
scb[1].
i2c_sd
a:0
scb[1].
spi_mi
so:0
peri.tr
_io_in
put[5]:
0
sdhc[0].
card_da
t_3to0[1
]
tcpwm[0].
line[7]:4
tcpwm[1]
.line[16]:
1
csd.csd
_tx:14
csd.csd
_tx_n:1
4
scb[1]
.uart_
rts:0
scb[1].
spi_cl
k:0
sdhc[0].
card_da
t_3to0[2
]
tcpwm[0].
line_com
pl[7]:4
tcpwm[1]
.line_co
mpl[16]:1
csd.csd
_tx:15
csd.csd
_tx_n:1
5
scb[1]
.uart_
cts:0
scb[1].
spi_se
lect0:0
sdhc[0].
card_da
t_3to0[3
]
P2.4
P2.5
P2.6
P2.7
tcpwm[0].
line[0]:5
tcpwm[1]
.line[17]:
1
csd.csd
_tx:16
csd.csd
_tx_n:1
6
scb[9]
.uart_
rx:0
scb[9].
i2c_scl
:0
scb[1].
spi_se
lect1:0
sdhc[0].
card_c
md
tcpwm[0].
line_com
pl[0]:5
tcpwm[1]
.line_co
mpl[17]:1
csd.csd
_tx:17
csd.csd
_tx_n:1
7
scb[9]
.uart_
tx:0
scb[9].
i2c_sd
a:0
scb[1].
spi_se
lect2:0
sdhc[0].
clk_card
tcpwm[0].
line[1]:5
tcpwm[1]
.line[18]:
1
csd.csd
_tx:18
csd.csd
_tx_n:1
8
scb[9]
.uart_
rts:0
scb[1].
spi_se
lect3:0
sdhc[0].
card_de
tect_n
tcpwm[0].
line_com
pl[1]:5
tcpwm[1]
.line_co
mpl[18]:1
csd.csd
_tx:19
csd.csd
_tx_n:1
9
scb[9]
.uart_
cts:0
sdhc[0].
card_m
ech_writ
e_prot
P3.0
P3.1
tcpwm[0].
line[2]:5
tcpwm[1]
.line[19]:
1
csd.csd
_tx:20
csd.csd
_tx_n:2
0
scb[2]
.uart_
rx:1
scb[2].
i2c_scl
:1
scb[2].
spi_m
osi:1
peri.tr
_io_in
put[6]:
0
sdhc[0].i
o_volt_s
el
tcpwm[0].
line_com
pl[2]:5
tcpwm[1]
.line_co
mpl[19]:1
csd.csd
_tx:21
csd.csd
_tx_n:2
1
scb[2]
.uart_
tx:1
scb[2].
i2c_sd
a:1
scb[2].
spi_mi
so:1
peri.tr
_io_in
put[7]:
0
sdhc[0].
card_if_
pwr_en
Document Number: 002-28690 Rev. *I
Page 33 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P3.2
P3.3
P3.4
P3.5
P4.0
tcpwm[0].
line[3]:5
tcpwm[1]
.line[20]:
1
csd.csd
_tx:22
csd.csd
_tx_n:2
2
scb[2]
.uart_
rts:1
scb[2].
spi_cl
k:1
tcpwm[0].
line_com
pl[3]:5
tcpwm[1]
.line_co
mpl[20]:1
csd.csd
_tx:23
csd.csd
_tx_n:2
3
scb[2]
.uart_
cts:1
scb[2].
spi_se
lect0:1
tcpwm[0].
line[4]:5
tcpwm[1]
.line[21]:
1
csd.csd
_tx:24
csd.csd
_tx_n:2
4
scb[2].
spi_se
lect1:1
tcpwm[0].
line_com
pl[4]:5
tcpwm[1]
.line_co
mpl[21]:1
csd.csd
_tx:25
csd.csd
_tx_n:2
5
scb[2].
spi_se
lect2:1
tcpwm[0].
line[5]:5
tcpwm[1]
.line[22]:
1
csd.csd
_tx:26
csd.csd
_tx_n:2
6
scb[7]
.uart_
rx:1
scb[7].
i2c_scl
:1
scb[7].
spi_m
osi:1
peri.tr
_io_in
put[8]:
0
P4.1
tcpwm[0].
line_com
pl[5]:5
tcpwm[1]
.line_co
mpl[22]:1
csd.csd
_tx:27
csd.csd
_tx_n:2
7
scb[7]
.uart_
tx:1
scb[7].
i2c_sd
a:1
scb[7].
spi_mi
so:1
peri.tr
_io_in
put[9]:
0
P4.2
P4.3
P5.0
tcpwm[0].
line[6]:5
tcpwm[1]
.line[23]:
1
csd.csd
_tx:28
csd.csd
_tx_n:2
8
scb[7]
.uart_
rts:1
scb[7].
spi_cl
k:1
tcpwm[0].
line_com
pl[6]:5
tcpwm[1]
.line_co
mpl[23]:1
csd.csd
_tx:29
csd.csd
_tx_n:2
9
scb[7]
.uart_
cts:1
scb[7].
spi_se
lect0:1
tcpwm[0].
line[4]:0
tcpwm[1]
.line[4]:0
csd.csd
_tx:30
csd.csd
_tx_n:3
0
scb[5]
.uart_
rx:0
scb[5].
i2c_scl
:0
scb[5].
spi_m
osi:0
peri.tr
_io_in
put[10
]:0
audioss
[0].clk_i
2s_if:0
P5.1
tcpwm[0].
line_com
pl[4]:0
tcpwm[1]
.line_co
mpl[4]:0
csd.csd
_tx:31
csd.csd
_tx_n:3
1
scb[5]
.uart_
tx:0
scb[5].
i2c_sd
a:0
scb[5].
spi_mi
so:0
peri.tr
_io_in
put[11
]:0
audioss
[0].tx_s
ck:0
P5.2
P5.3
P5.4
tcpwm[0].
line[5]:0
tcpwm[1]
.line[5]:0
csd.csd
_tx:32
csd.csd
_tx_n:3
2
scb[5]
.uart_
rts:0
scb[5].
spi_cl
k:0
audioss
[0].tx_w
s:0
tcpwm[0].
line_com
pl[5]:0
tcpwm[1]
.line_co
mpl[5]:0
csd.csd
_tx:33
csd.csd
_tx_n:3
3
scb[5]
.uart_
cts:0
scb[5].
spi_se
lect0:0
audioss
[0].tx_s
do:0
tcpwm[0].
line[6]:0
tcpwm[1]
.line[6]:0
csd.csd
_tx:34
csd.csd
_tx_n:3
4
scb[1
0].uar
t_rx:0
scb[10
].i2c_s
cl:0
scb[5].
spi_se
lect1:0
audioss
[0].rx_s
ck:0
Document Number: 002-28690 Rev. *I
Page 34 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P5.5
tcpwm[0].
line_com
pl[6]:0
tcpwm[1]
.line_co
mpl[6]:0
csd.csd
_tx:35
csd.csd
_tx_n:3
5
scb[1
0].uar
t_tx:0
scb[10
].i2c_s
da:0
scb[5].
spi_se
lect2:0
audioss
[0].rx_w
s:0
P5.6
tcpwm[0].
line[7]:0
tcpwm[1]
.line[7]:0
csd.csd
_tx:36
csd.csd
_tx_n:3
6
scb[1
0].uar
t_rts:
0
scb[5].
spi_se
lect3:0
audioss
[0].rx_s
di:0
P5.7
P6.0
P6.1
tcpwm[0].
line_com
pl[7]:0
tcpwm[1]
.line_co
mpl[7]:0
csd.csd
_tx:37
csd.csd
_tx_n:3
7
scb[1
0].uar
t_cts:
0
scb[3].
spi_se
lect3:0
tcpwm[0].
line[0]:1
tcpwm[1]
.line[8]:0
csd.csd
_tx:38
csd.csd
_tx_n:3
8
scb[8].
i2c_scl
:0
scb[3]
.uart_
rx:0
scb[3].
i2c_scl
:0
scb[3].
spi_m
osi:0
cpuss.faul
t_out[0]
scb[8]
.spi_
mosi:
0
tcpwm[0].
line_com
pl[0]:1
tcpwm[1]
.line_co
mpl[8]:0
csd.csd
_tx:39
csd.csd
_tx_n:3
9
scb[8].
i2c_sd
a:0
scb[3]
.uart_
tx:0
scb[3].
i2c_sd
a:0
scb[3].
spi_mi
so:0
cpuss.faul
t_out[1]
scb[8]
.spi_
miso:
0
P6.2
P6.3
tcpwm[0].
line[1]:1
tcpwm[1]
.line[9]:0
csd.csd
_tx:40
csd.csd
_tx_n:4
0
scb[3]
.uart_
rts:0
scb[3].
spi_cl
k:0
scb[8]
.spi_c
lk:0
tcpwm[0].
line_com
pl[1]:1
tcpwm[1]
.line_co
mpl[9]:0
csd.csd
_tx:41
csd.csd
_tx_n:4
1
scb[3]
.uart_
cts:0
scb[3].
spi_se
lect0:0
scb[8]
.spi_s
elect0
:0
P6.4
P6.5
P6.6
P6.7
tcpwm[0].
line[2]:1
tcpwm[1]
.line[10]:
0
csd.csd
_tx:42
csd.csd
_tx_n:4
2
scb[8].
i2c_scl
:1
scb[6]
.uart_
rx:2
scb[6].
i2c_scl
:2
scb[6].
spi_m
osi:2
peri.tr
_io_in
put[12
]:0
peri.tr_io_
output[0]:1
cpuss.
swj_s
wo_td
o
scb[8]
.spi_
mosi:
1
tcpwm[0].
line_com
pl[2]:1
tcpwm[1]
.line_co
mpl[10]:0
csd.csd
_tx:43
csd.csd
_tx_n:4
3
scb[8].
i2c_sd
a:1
scb[6]
.uart_
tx:2
scb[6].
i2c_sd
a:2
scb[6].
spi_mi
so:2
peri.tr
_io_in
put[13
]:0
peri.tr_io_
output[1]:1
cpuss.
swj_s
wdoe_
tdi
scb[8]
.spi_
miso:
1
tcpwm[0].
line[3]:1
tcpwm[1]
.line[11]:
0
csd.csd
_tx:44
csd.csd
_tx_n:4
4
scb[6]
.uart_
rts:2
scb[6].
spi_cl
k:2
cpuss.
swj_s
wdio_t
ms
scb[8]
.spi_c
lk:1
tcpwm[0].
line_com
pl[3]:1
tcpwm[1]
.line_co
mpl[11]:0
csd.csd
_tx:45
csd.csd
_tx_n:4
5
scb[6]
.uart_
cts:2
scb[6].
spi_se
lect0:2
cpuss.
swj_s
wclk_t
clk
scb[8]
.spi_s
elect0
:1
Document Number: 002-28690 Rev. *I
Page 35 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P7.0
tcpwm[0].
line[4]:1
tcpwm[1]
.line[12]:
0
csd.csd
_tx:46
csd.csd
_tx_n:4
6
scb[4]
.uart_
rx:1
scb[4].
i2c_scl
:1
scb[4].
spi_m
osi:1
peri.tr
_io_in
put[14
]:0
cpuss.tr
ace_clo
ck
P7.1
tcpwm[0].
line_com
pl[4]:1
tcpwm[1]
.line_co
mpl[12]:0
csd.csd
_tx:47
csd.csd
_tx_n:4
7
scb[4]
.uart_
tx:1
scb[4].
i2c_sd
a:1
scb[4].
spi_mi
so:1
peri.tr
_io_in
put[15
]:0
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
tcpwm[0].
line[5]:1
tcpwm[1]
.line[13]:
0
csd.csd
_tx:48
csd.csd
_tx_n:4
8
scb[4]
.uart_
rts:1
scb[4].
spi_cl
k:1
tcpwm[0].
line_com
pl[5]:1
tcpwm[1]
.line_co
mpl[13]:0
csd.csd
_tx:49
csd.csd
_tx_n:4
9
scb[4]
.uart_
cts:1
scb[4].
spi_se
lect0:1
tcpwm[0].
line[6]:1
tcpwm[1]
.line[14]:
0
csd.csd
_tx:50
csd.csd
_tx_n:5
0
scb[4].
spi_se
lect1:1
cpuss.tr
ace_da
ta[3]:2
tcpwm[0].
line_com
pl[6]:1
tcpwm[1]
.line_co
mpl[14]:0
csd.csd
_tx:51
csd.csd
_tx_n:5
1
scb[4].
spi_se
lect2:1
cpuss.tr
ace_da
ta[2]:2
tcpwm[0].
line[7]:1
tcpwm[1]
.line[15]:
0
csd.csd
_tx:52
csd.csd
_tx_n:5
2
scb[4].
spi_se
lect3:1
cpuss.tr
ace_da
ta[1]:2
tcpwm[0].
line_com
pl[7]:1
tcpwm[1]
.line_co
mpl[15]:0
csd.csd
_tx:53
csd.csd
_tx_n:5
3
scb[3].
spi_se
lect1:0
cpuss.
clk_fm
_pum
p
cpuss.tr
ace_da
ta[0]:2
P8.0
P8.1
P8.2
P8.3
tcpwm[0].
line[0]:2
tcpwm[1]
.line[16]:
0
csd.csd
_tx:54
csd.csd
_tx_n:5
4
scb[4]
.uart_
rx:0
scb[4].
i2c_scl
:0
scb[4].
spi_m
osi:0
peri.tr
_io_in
put[16
]:0
tcpwm[0].
line_com
pl[0]:2
tcpwm[1]
.line_co
mpl[16]:0
csd.csd
_tx:55
csd.csd
_tx_n:5
5
scb[4]
.uart_
tx:0
scb[4].
i2c_sd
a:0
scb[4].
spi_mi
so:0
peri.tr
_io_in
put[17
]:0
tcpwm[0].
line[1]:2
tcpwm[1]
.line[17]:
0
csd.csd
_tx:56
csd.csd
_tx_n:5
6
lpcom
p.dsi_
comp
0:0
scb[4]
.uart_
rts:0
scb[4].
spi_cl
k:0
tcpwm[0].
line_com
pl[1]:2
tcpwm[1]
.line_co
mpl[17]:0
csd.csd
_tx:57
csd.csd
_tx_n:5
7
lpcom
p.dsi_
comp
1:0
scb[4]
.uart_
cts:0
scb[4].
spi_se
lect0:0
Document Number: 002-28690 Rev. *I
Page 36 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P8.4
P8.5
P8.6
tcpwm[0].
line[2]:2
tcpwm[1]
.line[18]:
0
csd.csd
_tx:58
csd.csd
_tx_n:5
8
scb[1
1].uar
t_rx:0
scb[11
].i2c_s
cl:0
scb[4].
spi_se
lect1:0
tcpwm[0].
line_com
pl[2]:2
tcpwm[1]
.line_co
mpl[18]:0
csd.csd
_tx:59
csd.csd
_tx_n:5
9
scb[1
1].uar
t_tx:0
scb[11
].i2c_s
da:0
scb[4].
spi_se
lect2:0
tcpwm[0].
line[3]:2
tcpwm[1]
.line[19]:
0
csd.csd
_tx:60
csd.csd
_tx_n:6
0
scb[1
1].uar
t_rts:
0
scb[4].
spi_se
lect3:0
P8.7
P9.0
P9.1
tcpwm[0].
line_com
pl[3]:2
tcpwm[1]
.line_co
mpl[19]:0
csd.csd
_tx:61
csd.csd
_tx_n:6
1
scb[1
1].uar
t_cts:
0
scb[3].
spi_se
lect2:0
tcpwm[0].
line[4]:2
tcpwm[1]
.line[20]:
0
csd.csd
_tx:62
csd.csd
_tx_n:6
2
scb[2]
.uart_
rx:0
scb[2].
i2c_scl
:0
scb[2].
spi_m
osi:0
peri.tr
_io_in
put[18
]:0
cpuss.tr
ace_da
ta[3]:0
audioss
[0].clk_i
2s_if:1
tcpwm[0].
line_com
pl[4]:2
tcpwm[1]
.line_co
mpl[20]:0
csd.csd
_tx:63
csd.csd
_tx_n:6
3
scb[2]
.uart_
tx:0
scb[2].
i2c_sd
a:0
scb[2].
spi_mi
so:0
peri.tr
_io_in
put[19
]:0
cpuss.tr
ace_da
ta[2]:0
audioss
[0].tx_s
ck:1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
P10.0
tcpwm[0].
line[5]:2
tcpwm[1]
.line[21]:
0
csd.csd
_tx:64
csd.csd
_tx_n:6
4
scb[2]
.uart_
rts:0
scb[2].
spi_cl
k:0
audioss
[0].tx_w
s:1
cpuss.tr
ace_da
ta[1]:0
tcpwm[0].
line_com
pl[5]:2
tcpwm[1]
.line_co
mpl[21]:0
csd.csd
_tx:65
csd.csd
_tx_n:6
5
scb[2]
.uart_
cts:0
scb[2].
spi_se
lect0:0
audioss
[0].tx_s
do:1
cpuss.tr
ace_da
ta[0]:0
tcpwm[0].
line[7]:5
tcpwm[1]
.line[0]:2
csd.csd
_tx:66
csd.csd
_tx_n:6
6
scb[2].
spi_se
lect1:0
audioss
[0].rx_s
ck:1
tcpwm[0].
line_com
pl[7]:5
tcpwm[1]
.line_co
mpl[0]:2
csd.csd
_tx:67
csd.csd
_tx_n:6
7
scb[2].
spi_se
lect2:0
audioss
[0].rx_w
s:1
tcpwm[0].
line[0]:6
tcpwm[1]
.line[1]:2
csd.csd
_tx:68
csd.csd
_tx_n:6
8
scb[2].
spi_se
lect3:0
audioss
[0].rx_s
di:1
tcpwm[0].
line_com
pl[0]:6
tcpwm[1]
.line_co
mpl[1]:2
csd.csd
_tx:69
csd.csd
_tx_n:6
9
tcpwm[0].
line[6]:2
tcpwm[1]
.line[22]:
0
csd.csd
_tx:70
csd.csd
_tx_n:7
0
scb[1]
.uart_
rx:1
scb[1].
i2c_scl
:1
scb[1].
spi_m
osi:1
peri.tr
_io_in
put[20
]:0
cpuss.tr
ace_da
ta[3]:1
Document Number: 002-28690 Rev. *I
Page 37 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P10.1
tcpwm[0].
line_com
pl[6]:2
tcpwm[1]
.line_co
mpl[22]:0
csd.csd
_tx:71
csd.csd
_tx_n:7
1
scb[1]
.uart_
tx:1
scb[1].
i2c_sd
a:1
scb[1].
spi_mi
so:1
peri.tr
_io_in
put[21
]:0
cpuss.tr
ace_da
ta[2]:1
P10.2
P10.3
P10.4
tcpwm[0].
line[7]:2
tcpwm[1]
.line[23]:
0
csd.csd
_tx:72
csd.csd
_tx_n:7
2
scb[1]
.uart_
rts:1
scb[1].
spi_cl
k:1
cpuss.tr
ace_da
ta[1]:1
tcpwm[0].
line_com
pl[7]:2
tcpwm[1]
.line_co
mpl[23]:0
csd.csd
_tx:73
csd.csd
_tx_n:7
3
scb[1]
.uart_
cts:1
scb[1].
spi_se
lect0:1
cpuss.tr
ace_da
ta[0]:1
tcpwm[0].
line[0]:3
tcpwm[1]
.line[0]:1
csd.csd
_tx:74
csd.csd
_tx_n:7
4
scb[1].
spi_se
lect1:1
audios
s[0].p
dm_cl
k:0
P10.5
tcpwm[0].
line_com
pl[0]:3
tcpwm[1]
.line_co
mpl[0]:1
csd.csd
_tx:75
csd.csd
_tx_n:7
5
scb[1].
spi_se
lect2:1
audios
s[0].p
dm_d
ata:0
P10.6
P10.7
P11.0
tcpwm[0].
line[1]:6
tcpwm[1]
.line[2]:2
csd.csd
_tx:76
csd.csd
_tx_n:7
6
scb[1].
spi_se
lect3:1
tcpwm[0].
line_com
pl[1]:6
tcpwm[1]
.line_co
mpl[2]:2
csd.csd
_tx:77
csd.csd
_tx_n:7
7
tcpwm[0].
line[1]:3
tcpwm[1]
.line[1]:1
csd.csd
_tx:78
csd.csd
_tx_n:7
8
smif.
spi_s
elect
2
scb[5]
.uart_
rx:1
scb[5].
i2c_scl
:1
scb[5].
spi_m
osi:1
audioss
[1].clk_i
2s_if:1
peri.tr
_io_in
put[22
]:0
P11.1
P11.2
P11.3
P11.4
tcpwm[0].
line_com
pl[1]:3
tcpwm[1]
.line_co
mpl[1]:1
csd.csd
_tx:79
csd.csd
_tx_n:7
9
smif.
spi_s
elect
1
scb[5]
.uart_
tx:1
scb[5].
i2c_sd
a:1
scb[5].
spi_mi
so:1
audioss
[1].tx_s
ck:1
peri.tr
_io_in
put[23
]:0
tcpwm[0].
line[2]:3
tcpwm[1]
.line[2]:1
csd.csd
_tx:80
csd.csd
_tx_n:8
0
smif.
spi_s
elect
0
scb[5]
.uart_
rts:1
scb[5].
spi_cl
k:1
audioss
[1].tx_w
s:1
tcpwm[0].
line_com
pl[2]:3
tcpwm[1]
.line_co
mpl[2]:1
csd.csd
_tx:81
csd.csd
_tx_n:8
1
smif.
spi_
data
3
scb[5]
.uart_
cts:1
scb[5].
spi_se
lect0:1
audioss
[1].tx_s
do:1
peri.tr_io_
output[0]:0
tcpwm[0].
line[3]:3
tcpwm[1]
.line[3]:1
csd.csd
_tx:82
csd.csd
_tx_n:8
2
smif.
spi_
data
2
scb[5].
spi_se
lect1:1
audioss
[1].rx_s
ck:1
peri.tr_io_
output[1]:0
Document Number: 002-28690 Rev. *I
Page 38 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P11.5
tcpwm[0].
line_com
pl[3]:3
tcpwm[1]
.line_co
mpl[3]:1
csd.csd
_tx:83
csd.csd
_tx_n:8
3
smif.
spi_
data
1
scb[5].
spi_se
lect2:1
audioss
[1].rx_w
s:1
P11.6
csd.csd
_tx:84
csd.csd
_tx_n:8
4
smif.
spi_
data
0
scb[5].
spi_se
lect3:1
audioss
[1].rx_s
di:1
P11.7
P12.0
smif.
spi_c
lk
tcpwm[0].
line[4]:3
tcpwm[1]
.line[4]:1
csd.csd
_tx:85
csd.csd
_tx_n:8
5
smif.
spi_
data
4
scb[6]
.uart_
rx:0
scb[6].
i2c_scl
:0
scb[6].
spi_m
osi:0
peri.tr
_io_in
put[24
]:0
sdhc[1].
card_e
mmc_re
set_n
P12.1
P12.2
P12.3
P12.4
P12.5
tcpwm[0].
line_com
pl[4]:3
tcpwm[1]
.line_co
mpl[4]:1
csd.csd
_tx:86
csd.csd
_tx_n:8
6
smif.
spi_
data
5
scb[6]
.uart_
tx:0
scb[6].
i2c_sd
a:0
scb[6].
spi_mi
so:0
peri.tr
_io_in
put[25
]:0
sdhc[1].
card_de
tect_n
tcpwm[0].
line[5]:3
tcpwm[1]
.line[5]:1
csd.csd
_tx:87
csd.csd
_tx_n:8
7
smif.
spi_
data
6
scb[6]
.uart_
rts:0
scb[6].
spi_cl
k:0
sdhc[1].
card_m
ech_writ
e_prot
tcpwm[0].
line_com
pl[5]:3
tcpwm[1]
.line_co
mpl[5]:1
csd.csd
_tx:88
csd.csd
_tx_n:8
8
smif.
spi_
data
7
scb[6]
.uart_
cts:0
scb[6].
spi_se
lect0:0
sdhc[1].l
ed_ctrl
tcpwm[0].
line[6]:3
tcpwm[1]
.line[6]:1
csd.csd
_tx:89
csd.csd
_tx_n:8
9
smif.
spi_s
elect
3
scb[6].
spi_se
lect1:0
audios
s[0].p
dm_cl
k:1
sdhc[1].
card_c
md
tcpwm[0].
line_com
pl[6]:3
tcpwm[1]
.line_co
mpl[6]:1
csd.csd
_tx:90
csd.csd
_tx_n:9
0
scb[6].
spi_se
lect2:0
audios
s[0].p
dm_d
ata:1
sdhc[1].
clk_card
P12.6
P12.7
P13.0
tcpwm[0].
line[7]:3
tcpwm[1]
.line[7]:1
csd.csd
_tx:91
csd.csd
_tx_n:9
1
scb[6].
spi_se
lect3:0
sdhc[1].
card_if_
pwr_en
tcpwm[0].
line_com
pl[7]:3
tcpwm[1]
.line_co
mpl[7]:1
csd.csd
_tx:92
csd.csd
_tx_n:9
2
sdhc[1].i
o_volt_s
el
tcpwm[0].
line[0]:4
tcpwm[1]
.line[8]:1
csd.csd
_tx:93
csd.csd
_tx_n:9
3
scb[6]
.uart_
rx:1
scb[6].
i2c_scl
:1
scb[6].
spi_m
osi:1
peri.tr
_io_in
put[26
]:0
sdhc[1].
card_da
t_3to0[0
]
audioss
[1].clk_i
2s_if:0
Document Number: 002-28690 Rev. *I
Page 39 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 8. Multiple Alternate Functions (continued)
Port/
ACT ACT ACT ACT
ACT ACT
ACT
#10
ACT
#12
ACT
#14
ACT
#15
ACT #0 ACT #1 ACT #2 ACT #3 DS #2 DS #3
Pin
ACT #13
DS #5 DS #6
#4
#5
#6
#7
#8
#9
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
tcpwm[0].
line_com
pl[0]:4
tcpwm[1]
.line_co
mpl[8]:1
csd.csd
_tx:94
csd.csd
_tx_n:9
4
scb[6]
.uart_
tx:1
scb[6].
i2c_sd
a:1
scb[6].
spi_mi
so:1
peri.tr
_io_in
put[27
]:0
sdhc[1].
card_da
t_3to0[1
]
audioss
[1].tx_s
ck:0
tcpwm[0].
line[1]:4
tcpwm[1]
.line[9]:1
csd.csd
_tx:95
csd.csd
_tx_n:9
5
scb[6]
.uart_
rts:1
scb[6].
spi_cl
k:1
sdhc[1].
card_da
t_3to0[2
]
audioss
[1].tx_w
s:0
tcpwm[0].
line_com
pl[1]:4
tcpwm[1]
.line_co
mpl[9]:1
csd.csd
_tx:96
csd.csd
_tx_n:9
6
scb[6]
.uart_
cts:1
scb[6].
spi_se
lect0:1
sdhc[1].
card_da
t_3to0[3
]
audioss
[1].tx_s
do:0
tcpwm[0].
line[2]:4
tcpwm[1]
.line[10]:
1
csd.csd
_tx:97
csd.csd
_tx_n:9
7
scb[1
2].uar
t_rx:0
scb[12
].i2c_s
cl:0
scb[6].
spi_se
lect1:1
sdhc[1].
card_da
t_7to4[0
]
audioss
[1].rx_s
ck:0
tcpwm[0].
line_com
pl[2]:4
tcpwm[1]
.line_co
mpl[10]:1
csd.csd
_tx:98
csd.csd
_tx_n:9
8
scb[1
2].uar
t_tx:0
scb[12
].i2c_s
da:0
scb[6].
spi_se
lect2:1
sdhc[1].
card_da
t_7to4[1
]
audioss
[1].rx_w
s:0
tcpwm[0].
line[3]:4
tcpwm[1]
.line[11]:
1
csd.csd
_tx:99
csd.csd
_tx_n:9
9
scb[1
2].uar
t_rts:
0
scb[6].
spi_se
lect3:1
sdhc[1].
card_da
t_7to4[2
]
audioss
[1].rx_s
di:0
tcpwm[0].
line_com
pl[3]:4
tcpwm[1]
.line_co
mpl[11]:1
csd.csd
_tx:100
csd.csd
_tx_n:1
00
scb[1
2].uar
t_cts:
0
sdhc[1].
card_da
t_7to4[3
]
Document Number: 002-28690 Rev. *I
Page 40 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Analog and Smart I/O alternate port pin functionality is provided in Table 9.
Table 9. Port Pin Analog, Digital, and Smart I/O Functions
Table 9. Port Pin Analog, Digital, and Smart I/O Functions
Port/Pin
Digital
Port/Pin
P0.0
Analog
P0.4
pmic_wakeup_in
hibernate_wakeup[1]
hibernate_wakeup[0]
pmic_wakeup_out
SMARTIO
wco_in
P0.1
wco_out
P1.4
P0.5
P5.6
lpcomp.inp_comp0
lpcomp.inn_comp0
lpcomp.inp_comp1
lpcomp.inn_comp1
P5.7
Port/Pin
P6.2
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
smartio[8].io[0]
smartio[8].io[1]
smartio[8].io[2]
smartio[8].io[3]
smartio[8].io[4]
smartio[8].io[5]
smartio[8].io[6]
smartio[8].io[7]
smartio[9].io[0]
smartio[9].io[1]
smartio[9].io[2]
smartio[9].io[3]
smartio[9].io[4]
smartio[9].io[5]
smartio[9].io[6]
smartio[9].io[7]
P6.3
P6.6
P6.7
swd_data
swd_clk
P7.2
P7.3
P7.7
csd.csh_tank
csd.vref_ext
csd.shield
P9.7
aref_ext_vref
sarmux_pads[0]
sarmux_pads[1]
sarmux_pads[2]
sarmux_pads[3]
sarmux_pads[4]
sarmux_pads[5]
sarmux_pads[6]
sarmux_pads[7]
eco_in
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P12.6
P12.7
eco_out
Document Number: 002-28690 Rev. *I
Page 41 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Power Supply Considerations
The following power system diagrams show typical connections for power pins for all supported packages and with and without usage
of the buck regulator.
In these diagrams, the package pin is shown with the pin name, for example "VDDA, A12". For VDDx pins, the I/O port that is powered
by that pin is also shown, for example "VDDD, A1; I/O port P1".
Figure 14. 124-BGA Power Connection Diagram124-BGA Power Connection Diagram
1.7 to 3.6 V
CYS0644xxxI-S2D4x, 124-BGA package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
VDDD, A1; I/O port P1
VDD_NS, J1
VIND1, J2
VCCD, A2
10 µF
1 µF
1 µF
1 µF
1 µF
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
10 µF
VBACKUP, D1; I/O port P0
2.2 µH
VDDIO0, C4; I/O ports P11, P12, P13
VDDIO1, K12; I/O ports P5, P6, P7, P8
VDDIO2, L4; I/O ports P2, P3, P4
VDDUSB, M1; I/O port P14
4.7 µF
1 KΩ at
100 MHz
VDDA, A12
VDDIOA, A13; I/O ports P9, P10
B12, C3, D4, D10, K4, K10
VSS
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Page 42 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 15. 124-BGA (No Buck) Power Connection Diagram
1.7 to 3.6 V
CYS0644xxxI-S2D4x, 124-BGA package
1 KΩ at
100 MHz
VDDD, A1; I/O port P1
VDD_NS, J1
10 µF
1 µF
1 µF
1 µF
1 µF
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VBACKUP, D1; I/O port P0
VIND1, J2
VCCD, A2
VDDIO0, C4; I/O ports P11, P12, P13
VDDIO1, K12; I/O ports P5, P6, P7, P8
VDDIO2, L4; I/O ports P2, P3, P4
VDDUSB, M1; I/O port P14
4.7 µF
1 KΩ at
100 MHz
VDDA, A12
VDDIOA, A13; I/O ports P9, P10
B12, C3, D4, D10, K4, K10
VSS
Document Number: 002-28690 Rev. *I
Page 43 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 16. 100-WLCSP Power Connection Diagram
1.7 to 3.6 V
CYS0644xxxI-S2D4x, 100-WLCSP package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
VDDD, D14; I/O port P1
VDD_NS, J15
VIND1, H16
VCCD, C15
10 µF
1 µF
1 µF
1 µF
1 µF
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
10 µF
VBACKUP, C17; I/O port P0
2.2 µH
VDDIO0, A11; I/O ports P11, P12, P13
VDDIO1, K2; I/O ports P5, P6, P7, P8
VDDIO2, M10; I/O port P2
4.7 µF
VDDUSB, J17; I/O port P14
1 KΩ at
100 MHz
VDDA, J1; I/O ports P9, P10
D2, E13, J13, L1
VSS
Document Number: 002-28690 Rev. *I
Page 44 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 17. 100-WLCSP (No Buck) Power Connection Diagram
1.7 to 3.6 V
CYS0644xxxI-S2D4x, 100-WLCSP package
1 KΩ at
100 MHz
VDDD, D14; I/O port P1
VDD_NS, J15
10 µF
1 µF
1 µF
1 µF
1 µF
1 µF
10 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
V
V
V
V
BACKUP, C17; I/O port P0
V
IND1, H16
DDIO0, A11; I/O ports P11, P12, P13
DDIO1, K2; I/O ports P5, P6, P7, P8
DDIO2, M10; I/O port P2
V
CCD, C15
4.7 µF
VDDUSB, J17; I/O port P14
VDDA, J1; I/O ports P9, P10
1 KΩ at
100 MHz
D2, E13, J13, L1
VSS
There are as many as eight VDDx supply pins, depending on the
package, and multiple VSS ground pins. The power pins are:
as 1.4 V, for battery or supercapacitor backup, as Figure 18
shows, otherwise it is connected to VDDD. It powers I/O port 0.
■ VDDD: the main digital supply. It powers the low dropout (LDO)
regulators and I/O port 1
Figure 18. Separate Battery Connection to VBACKUP
1.7 to 3.6 V
■ VCCD: the main LDO output. It requires a 4.7-µF capacitor for
regulation. The LDO can be turned off when VCCD is driven
from the switching regulator (see below). For more information,
see the power system block diagram in the device technical
reference manual (TRM).
VDDD
10 µF
1 µF
0.1 µF
0.1 µF
■ VDDA: the supply for the analog peripherals. Voltage must be
applied to this pin for correct device initialization and boot up.
VBACKUP
■ VDDIOA: the supply for I/O ports 9 and 10. It must be connected
1.4 to 3.6 V
to VDDA
.
■ VDDIO0: the supply for I/O ports 11, 12, and 13.
■ VDDIO1: the supply for I/O ports 5, 6, 7, and 8.
■ VDDIO2: the supply for I/O ports 2, 3, and 4.
■ VDDUSB: the supply for the USB peripheral and the USBDPand
USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If
USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can
be used as limited-capability GPIOs on I/O port 14.
■ VBACKUP: the supply for the backupdomain, which includes the
32-kHz WCO and the RTC. It can be a separate supply as low
Document Number: 002-28690 Rev. *I
Page 45 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 10 shows a summary of the I/O port supplies:
No external load should be placed on VCCD, or VIND1, whether
or not these pins are used.
Table 10. I/O Port Supplies
There are no power pin sequencing requirements; power
supplies may be brought up in any order. The power
management system holds the device in reset until all power pins
are at the voltage levels required for proper operation.
Port
0
Supply
VBACKUP
VDDD
Alternate Supply
VDDD
1
-
Note: If a battery is installed on the PCB first, VDDD must be
cycled for at least 50 µs. This prevents premature drain of the
battery during product manufacture and storage.
2, 3, 4
5, 6, 7, 8
9, 10
11, 12, 13
14
VDDIO2
VDDIO1
VDDIOA
VDDIO0
VDDUSB
-
-
VDDA
Bypass capacitors must be connected to a common ground from
the VDDx and other pins, as indicated in the diagrams. Typical
practice for systems in this frequency range is to use a 10-µF or
1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and
bypass capacitor parasitic should be simulated for optimal
bypassing.
-
-
Note: If the USB pins are not used, connect VDDUSB to ground
and leave the P14.0/USBDP and P14.1/USBDM pins unconnect-
ed.
All capacitors and inductors should be ±20% or better. The
recommended inductor value is 2.2 µH ±20% (for example, TDK
MLP2012H2R2MT0S1).
Voltage must be applied to the VDDD pin, and the VDDA pin as
noted above, for correct device initialization and operation. If an
I/O port is not being used, applying voltage to the corresponding
V
DDx pin is optional.
It is good practice to check the datasheets for your bypass
capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can
decrease considerably when the applied voltage is a significant
percentage of the rated working voltage.
■ VSS: ground pins for the above supplies.All ground pins should
be connected together to a common ground.
In addition to the LDO regulator, a switching regulator is
included. The regulator pins are:
For more information on pad layout, refer to PSoC 6 CAD
libraries.
■ VDD_NS: the regulator supply.
■ VIND1: the regulator output. It is typically used to drive VCCD
through an inductor.
The VDD power pins are not connected on chip. They can be
connected off chip, in one or more separate nets. If separate
power nets are used, they can be isolated from noise from the
other nets using optional ferrite beads, as indicated in the
diagrams.
Document Number: 002-28690 Rev. *I
Page 46 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Electrical Specifications
All specifications are valid for –40 °C ≤ TA ≤ 85 °C and for 1.71 V to 3.6 V except where noted.
Note: These are preliminary and subject to change.
Absolute Maximum Ratings
Table 11. Absolute Maximum Ratings[4]
Spec ID#
SID1
Parameter
Description
Min
Typ
Max Units
Details / Conditions
Analog or digital supply relative to VSS
VDD_ABS
–0.5
–
4
V
V
V
(VSSD = VSSA
)
Direct digital core voltage input relative to
VSSD
SID2
SID3
VCCD_ABS
–0.5
–0.5
–
–
1.2
VDD
0.5
+
VGPIO_ABS
IGPIO_ABS
GPIO voltage; VDDD or VDDA
Current per GPIO
SID4
SID5
–25
–
–
25
mA
mA
IGPIO_injection GPIO injection current per pin
–0.5
0.5
Electrostatic discharge Human Body
SID3A
ESD_HBM
Model
2200
–
–
–
V
Electrostatic discharge Charged Device
SID4A
SID5A
ESD_CDM
Model
500
–
–
V
LU
Pin current for latchup-free operation
–100
100
mA
Device-Level Specifications
Table 14 provides detailed specifications of CPU current. Table 12 summarizes these specifications, for rapid review of CPU currents
under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to
generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz.
Table 12. CPU Current Specifications Summary
Condition
Range
Typ Range
Max Range
LP Mode, V
= 3.3 V, V
= 1.1 V, with buck regulator
DDD
CCD
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
0.9–7.35 mA
0.8–4.4 mA
0.7–1.55 mA
0.7–1.3 mA
0.64–0.85 mA
2–9.5 mA
2–5.8 mA
1.3–2.2 mA
1.3–2 mA
1.2–1.5 mA
Across CPUs clock ranges: 8 – 150/100 MHz;
Dhrystone with flash cache enabled
Minimum regulator current mode
ULP Mode, V = 3.3 V, V
Across CM4/CM0+ CPU active/sleep modes
= 0.9 V, with buck regulator
CCD
DDD
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
0.65–1.85 mA
0.55–1 mA
1.2–2.5 mA
0.95–1.5 mA
0.9–1.2 mA
0.72–1.2 mA
1–1 mA
-
Across CPUs clock ranges: 8–50/25 MHz; Dhrystone
with flash cache enabled
0.45–0.85 mA
0.41–0.62 mA
0.4–0.55 mA
7–9 µA
Minimum regulator current mode
Deep Sleep
Across CM4/CM0+ CPU active/sleep modes
Across SRAM retention
Hibernate
Across V
300–2100 nA
-
DDD
Note
4. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-28690 Rev. *I
Page 47 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 19. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode
8
7
6
5
4
3
2
1
0
CM4 Active, CM0+ Sleep 1/2 CM4
CM4 Active, CM0+ Sleep same as CM4
CM0+ Active, CM4 Sleep
0
25
50
75
100
125
150
CPU Clock, MHz
Power Supplies
Table 13. Power Supply DC Specifications
Spec ID# Parameter Description
SID6 VDDD
Min
Typ
Max
Units
Details / Conditions
Internal regulator and Port 1 GPIO supply 1.7
–
3.6
V
–
Analog power supply voltage. Shorted to
VDDIOA on PCB.
Internally unregulated
supply
SID7
VDDA
1.7
–
3.6
V
Must be ≥ VDDA if the
CapSense (CSD) block is
used in the application
SID7A
VDDIO1
GPIO supply for ports 5 to 8 when present 1.7
–
3.6
V
GPIO supply for ports 11 to 13 when
present
SID7B
SID7C
VDDIO0
VDDIO2
VDDIOA
1.7
–
–
3.6
3.6
V
V
–
–
GPIO supply for ports 2 to 4 when present 1.7
GPIO supply for ports 9 and 10 when
present. Must be connected to VDDA on
PCB.
SID7D
SID7F
1.7
–
–
3.6
3.6
V
V
–
Supply for port 14 (USB or GPIO) when
present
Min supply is 2.85 V for
USB
VDDUSB
VBACKUP
VCCD1
1.7
Backup power and GPIO Port 0 supply
when present
Min is 1.4 V when VDDD is
removed
SID6B
SID8
1.7
–
–
3.6
–
V
V
Output voltage (for core logic bypass)
1.1
0.9
System LP mode
ULP mode. Valid for –20 to
85 °C.
SID9
VCCD2
Output voltage (for core logic bypass)
–
–
X5R ceramic or better.
Value for 0.8 to 1.2 V.
SID10
SID11
CEFC
CEXC
External regulator voltage (VCCD) bypass 3.8
Power supply decoupling capacitor
4.7
10
5.6
–
µF
–
µF X5R ceramic or better
Document Number: 002-28690 Rev. *I
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PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
CPU Current and Transition Times
Table 14. CPU Current and Transition Times
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
LP RANGE POWER SPECIFICATIONS (for VCCD = 1.1 V with Buck and LDO)
Cortex-M4. Active Mode
Execute with Cache Disabled (Flash)
VDDD=3.3V, BuckON, Max
at 60 °C
2.85
4.5
Execute from Flash; CM4 Active 50 MHz,
CM0+ Sleep 25 MHz. With IMO & FLL.
While(1).
VDDD=1.8V, BuckON, Max
at 60 °C
SIDF1
SIDF2
IDD1
IDD2
–
–
4.1
6.8
0.9
1.2
2.4
5.1
10
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
2.1
2.2
5.5
Execute from Flash; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz.With IMO. While(1).
VDDD=1.8V, BuckON, Max
at 60 °C
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
Execute with Cache Enabled
VDDD=3.3V, BuckON, Max
at 60 °C
7.35
12
9.5
14.5
21
Execute from Cache;CM4Active150 MHz,
CM0+ Sleep 75 MHz. IMO & PLL.
Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
SIDC1
SIDC2
SIDC3
SIDC4
IDD3
IDD4
IDD5
IDD6
–
–
–
–
mA
mA
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
18
VDDD=3.3V, BuckON, Max
at 60 °C
5.4
6.8
10
Execute from Cache;CM4Active100 MHz,
CM0+ Sleep 100 MHz. IMO & FLL.
Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
8.95
13.8
2.65
4.25
6.8
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
17
VDDD=3.3V, BuckON, Max
at 60 °C
3.8
5.3
10
Execute from Cache;CM4 Active 50 MHz,
CM0+ Sleep 25 MHz. IMO & FLL.
Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
0.9
2
Execute from Cache;CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. IMO. Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
1.27
2.3
2.1
5.5
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
Document Number: 002-28690 Rev. *I
Page 49 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
VDDD=3.3V, BuckON, Max
at 60 °C
2.6
3.9
6.5
0.8
1.1
2.2
4
Execute from Flash;CM4Off, CM0+Active
50 MHz. With IMO & FLL. While (1).
VDDD=1.8V, BuckON, Max
at 60 °C
SIDF3
SIDF4
IDD7
IDD8
–
5
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
10
1.5
2
VDDD=3.3V, BuckON, Max
at 60 °C
Execute from Flash;CM4Off, CM0+Active
8 MHz. With IMO. While (1).
VDDD=1.8V, BuckON, Max
at 60 °C
–
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
5.5
Execute with Cache Enabled
VDDD=3.3V, BuckON, Max
at 60 °C
4.40
7.35
11.5
0.8
5.8
8.5
14.5
2
Execute from Cache;CM4 Off, CM0+
Active 100 MHz. With IMO & FLL.
Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
SIDC5
SIDC6
IDD9
–
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
Execute from Cache;CM4 Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
IDD10
1.2
2
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
2.2
5.5
Cortex M4. Sleep Mode
VDDD=3.3V, BuckON, Max
at 60 °C
1.55
2.4
2.2
3.5
7.2
2
CM4 Sleep 100 MHz, CM0+ Sleep 25
MHz. With IMO & FLL.
VDDD=1.8V, BuckON, Max
at 60 °C
SIDS1
SIDS2
SIDS3
IDD11
IDD12
IDD13
–
–
–
mA
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
4.2
VDDD=3.3V, BuckON, Max
at 60 °C
1.2
CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.
With IMO & FLL.
VDDD=1.8V, BuckON, Max
at 60 °C
1.75
3.2
2.7
6.3
1.3
1.8
5
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
0.7
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz.
With IMO.
VDDD=1.8V, BuckON, Max
at 60 °C
0.96
1.7
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
Document Number: 002-28690 Rev. *I
Page 50 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
Cortex M0+. Sleep Mode
VDDD=3.3V, BuckON, Max
at 60 °C
1.3
2.05
3.6
2
CM4 Off, CM0+ Sleep 50 MHz. With IMO
& FLL.
VDDD=1.8V, BuckON, Max
at 60 °C
SIDS4
SIDS5
IDD14
IDD15
–
3
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
6.8
1.3
1.5
5
VDDD=3.3V, BuckON, Max
at 60 °C
0.7
VDDD=1.8V, BuckON, Max
at 60 °C
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
–
0.95
1.7
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
Cortex M4. Minimum Regulator Current Mode
VDDD=3.3V, BuckON, Max
at 60 °C
0.85
1.18
2.2
1.8
2
Execute from Flash; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. While (1).
VDDD=1.8V, BuckON, Max
at 60 °C
SIDLPA1
SIDLPA2
IDD16
IDD17
–
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
5.5
1.5
2
VDDD=3.3V, BuckON, Max
at 60 °C
0.9
Execute from Cache; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
1.27
2.2
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
5.5
Cortex M0+. Minimum Regulator Current Mode
VDDD=3.3V, BuckON, Max
at 60 °C
0.8
1.14
2.1
1.5
2
Execute from Flash; CM4 Off, CM0+
Active 8 MHz. With IMO. While (1).
VDDD=1.8V, BuckON, Max
at 60 °C
SIDLPA3
SIDLPA4
IDD18
IDD19
–
–
mA
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
5.5
1.5
2
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.8
Execute from Cache; CM4 Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
VDDD=1.8V, BuckON, Max
at 60 °C
1.15
2.1
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
5.5
Cortex M4. Minimum Regulator Current Mode
VDDD=3.3V, BuckON, Max
at 60 °C
0.65
0.95
1.6
1.2
1.7
5
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz.
With IMO.
VDDD=1.8V, BuckON, Max
at 60 °C
SIDLPS1
IDD20
–
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
Document Number: 002-28690 Rev. *I
Page 51 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter Description
Cortex M0+. Minimum Regulator Current Mode
Min
Typ
Max Units
Details / Conditions
VDDD=3.3V, BuckON, Max
at 60 °C
0.64
0.93
1.6
1.2
VDDD=1.8V, BuckON, Max
at 60 °C
SIDLPS3
IDD22
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
–
1.7
5
mA
VDDD = 1.8 to 3.3 V, LDO,
max at 60 °C
ULP Range Power Specifications (for VCCD = 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C.
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
VDDD=3.3V, BuckON, Max
at 60 °C
2.15
2.85
0.65
0.8
2.9
3.4
1.2
1.4
Execute from Flash; CM4 Active 50 MHz,
CM0+ Sleep 25 MHz. With IMO & FLL.
While(1).
SIDF5
SIDF6
IDD3
IDD4
–
–
mA
mA
VDDD=1.8V, BuckON, Max
at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
Execute from Flash; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. While (1).
VDDD=1.8V, BuckON, Max
at 60 °C
Execute with Cache Enabled
Execute from Cache; CM4Active 50 MHz,
VDDD=3.3V, BuckON, Max
at 60 °C
1.85
2.9
2.5
3.5
1.2
1.3
SIDC8
IDD10
CM0+ Sleep 25 MHz. With IMO & FLL.
Dhrystone.
–
–
mA
mA
VDDD=1.8V, BuckON, Max
at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
0.65
0.8
Execute from Cache; CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. Dhrystone.
SIDC9
IDD11
VDDD=1.8V, BuckON, Max
at 60 °C
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
VDDD=3.3V, BuckON, Max
at 60 °C
1.1
1.5
2.2
1.2
1.4
Execute from Flash; CM4 Off, CM0+
Active 25 MHz. With IMO & FLL. Write(1).
SIDF7
SIDF8
IDD16
IDD17
–
–
mA
mA
VDDD=1.8V, BuckON, Max
at 60 °C
1.55
0.55
0.73
VDDD=3.3V, BuckON, Max
at 60 °C
Execute from Flash; CM4 Off, CM0+
Active 8 MHz. With IMO. While(1).
VDDD=1.8V, BuckON, Max
at 60 °C
Execute with Cache Enabled
Execute from Cache; CM4 Off, CM0+
VDDD = 3.3 V, Buck ON,
Max at 60 °C
1
1.5
2
SIDC10
IDD18
Active 25 MHz. With IMO & FLL.
Dhrystone.
–
mA
VDDD = 1.8 V, Buck ON,
Max at 60 °C
1.5
Document Number: 002-28690 Rev. *I
Page 52 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
Description
Min
Typ
Max Units
Details / Conditions
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.55
0.95
mA
1.3
Execute from Cache; CM4 Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
SIDC11
IDD19
–
VDDD = 1.8 V, Buck ON,
Max at 60 °C
0.73
Cortex M4. Sleep Mode
CM4 Sleep 50 MHz, CM0+ Sleep 25 MHz.
With IMO & FLL.
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.85
1.2
1.2
mA
1.8
SIDS7
SIDS8
IDD21
IDD22
–
–
VDDD = 1.8 V, Buck ON,
Max at 60 °C
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.45
0.59
0.9
mA
1
CM4 Sleep 8 MHz, CM0+ Sleep 8 MHz.
With IMO.
VDDD = 1.8 V, Buck ON,
Max at 60 °C
Cortex M0+. Sleep Mode
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.62
0.88
0.41
0.58
1.2
mA
1.5
CM4 Off, CM0+ Sleep 25 MHz. With IMO
& FLL.
SIDS9
IDD23
IDD24
–
–
VDDD = 1.8 V, Buck ON,
Max at 60 °C
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.72
mA
1.3
SIDS10
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
VDDD = 1.8 V, Buck ON,
Max at 60 °C
Cortex M4. Minimum Regulator Current Mode °
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.65
0.8
1.2
mA
1.4
Execute from Flash. CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. While(1).
SIDLPA5
SIDLPA6
IDD25
IDD26
–
–
VDDD = 1.8 V, Buck ON,
Max at 60 °C
VDDD = 3.3 V, Buck ON,
Max at 60 °C
0.6
1
Execute from Cache. CM4 Active 8 MHz,
CM0+ Sleep 8 MHz. With IMO. Dhrystone.
mA
1.4
VDDD = 1.8 V, Buck ON,
Max at 60 °C
0.78
Cortex M0+. Minimum Regulator Current Mode
VDDD=3.3V, BuckON, Max
at 60 °C
0.55
0.75
0.5
1
Execute from Flash. CM4 Off, CM0+
Active 8 MHz. With IMO. While (1).
SIDLPA7
SIDLPA8
IDD27
IDD28
–
–
mA
1.4
VDDD=1.8V, BuckON, Max
at 60 °C
VDDD=3.3V, BuckON, Max
at 60 °C
1
Execute from Cache. CM4 Off, CM0+
Active 8 MHz. With IMO. Dhrystone.
mA
1.4
VDDD=1.8V, BuckON, Max
at 60 °C
0.7
Document Number: 002-28690 Rev. *I
Page 53 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter Description
Cortex M4. Minimum Regulator Current Mode
Min
Typ
Max Units
Details / Conditions
VDDD=3.3V, BuckON, Max
at 60 °C
0.45
0.57
1
CM4 Sleep 8 MHz, CM0 Sleep 8 MHz.
With IMO.
SIDLPS5
IDD29
–
mA
1.1
VDDD=1.8V, BuckON, Max
at 60 °C
Cortex M0+. Minimum Regulator Current Mode
VDDD=3.3V, BuckON, Max
at 60 °C
0.4
1
SIDLPS7
IDD31
CM4 Off, CM0+ Sleep 8 MHz. With IMO.
–
–
mA
1.1
VDDD=1.8V, BuckON, Max
at 60 °C
0.56
Deep Sleep Mode
SIDDS2 IDD33B
Hibernate Mode
With internal Buck enabled and 256-KB
SRAM retention.
20
–
µA
SIDHIB1
SIDHIB2
IDD34
IDD34A
VDDD = 1.8 V
VDDD = 3.3 V
–
–
300
–
–
nA No clocks running
nA No clocks running
2100
Power Mode Transition Times
Minimum Regulator Current to LP
transition time.
SID12
TLPACT_ACT
–
–
35
µs
Including PLL lock time
SID13
SID14
TDS_LPACT Deep Sleep to LP transition time
THIB_ACT Hibernate to LP transition time
–
–
–
21
–
µs
µs
Guaranteed by design
Including PLL lock time
1000
XRES
Table 15. XRES DC Specifications
Spec ID#
SID17
Parameter
TXRES_IDD
TXRES_IDD_1
VIH
Description
IDD when XRES asserted
IDD when XRES asserted
Input voltage HIGH threshold
Input voltage LOW threshold
Input capacitance
Min
Typ
300
2100
–
Max
Units
Details / Conditions
–
500
nA VDDD = 1.8 V
nA VDDD = 3.3 V
SID17A
SID77
–
10500
0.7 * VDD
–
V
V
CMOS input
SID78
VIL
–
–
–
–
–
0.3 * VDD
CMOS input
SID80
CIN
3
–
–
pF
mV
µA
–
–
SID81
VHYSXRES
Input voltage hysteresis
100
–
Current through protection diode to
VDD/VSS
100
SID82
IDIODE
–
Document Number: 002-28690 Rev. *I
Page 54 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 16. XRES AC Specifications
Spec ID#
SID15
Parameter
TXRES_ACT
TXRES_PW
Description
Min
Typ
Max
Units
Details / Conditions
POR or XRES release to Active
transition time
–
1000
–
µs Normal mode, 50-MHz
CM0+.
SID16
XRES pulse width
5
–
–
µs
–
GPIO
Table 17. GPIO DC Specifications
Spec ID# Parameter
SID57 VIH
Description
Min
Typ
–
Max
–
Units
V
Details / Conditions
Input voltage HIGH threshold
0.7 * VDD
–
CMOS Input
Per I2C Spec
Input current when Pad > VDDIO
for OVT inputs
–
10
µA
SID57A
IIHS
SID58
VIL
Input voltage LOW threshold
LVTTL input, VDD < 2.7 V
LVTTL input, VDD < 2.7 V
LVTTL input, VDD ≥ 2.7 V
LVTTL input, VDD ≥ 2.7 V
Output voltage HIGH level
Output voltage LOW level
Pull-up resistor
–
–
–
0.3 * VDD
V
V
CMOS Input
SID241
SID242
SID243
SID244
SID59
VIH
0.7 * VDD
–
–
VIL
–
–
0.3 * VDD
V
–
VIH
2.0
–
–
V
–
VIL
–
–
0.8
–
V
–
VOH
VDD – 0.5
–
V
IOH = 8 mA
SID62A
SID63
VOL
–
–
0.4
8.5
8.5
2
V
IOL = 8 mA
RPULLUP
RPULLDOWN
3.5
3.5
–
5.6
5.6
–
kΩ
kΩ
nA
–
–
SID64
Pull-down resistor
Input leakage current (absolute
value)
SID65
SID66
SID67
SID68
SID69
IIL
25 °C, VDD = 3.0 V
CIN
Input capacitance
–
–
0
5
–
pF
–
–
–
–
Input hysteresis LVTTL VDD
2.7 V
>
100
mV
VHYSTTL
VHYSCMOS
IDIODE
Input hysteresis CMOS
0.05 * VDD
–
–
–
–
mV
Current through protection diode
to VDD/VSS
100
µA
Maximum total source or sink
chip current
–
–
200
mA
SID69A
ITOT_GPIO
–
Table 18. GPIO AC Specifications
Spec ID# Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Rise time in Fast Strong Mode.
–
–
2.5
ns Cload = 15 pF, 8-mA drive
strength
SID70
TRISEF
10% to 90% of VDD
Fall time in Fast Strong Mode.
10% to 90% of VDD
Rise time in Slow Strong Mode.
10% to 90% of VDD
.
–
–
–
–
2.5
142
102
ns Cload = 15 pF, 8-mA drive
strength
SID71
SID72
TFALLF
.
52
48
ns Cload = 15 pF, 8-mA drive
TRISES_1
.
strength, VDD 2.7 V
ns Cload = 15 pF, 8-mA drive
Rise time in Slow Strong Mode.
10% to 90% of VDD
SID72A
TRISES_2
strength, 2.7 V < VDD
3.6 V
.
Document Number: 002-28690 Rev. *I
Page 55 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 18. GPIO AC Specifications (continued)
Spec ID#
SID73
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Fall time in Slow Strong Mode.
44
–
211
ns Cload = 15 pF, 8-mA drive
TFALLS_1
10% to 90% of VDD
.
strength, VDD 2.7 V
42
–
93
ns Cload = 15 pF, 8-mA drive
Fall time in Slow Strong Mode.
10% to 90% of VDD
SID73A
TFALLS_2
strength, 2.7 V < VDD
3.6 V
.
Fall time (30% to 70% of VDD) in 20 *VDDIO
/
–
–
–
–
–
–
250
100
1.5
ns Cload = 10 pF to 400 pF,
8-mA drive strength
SID73G
SID74
TFALL_I2C
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
FGPIOIN
5.5
Slow Strong mode.
–
MHz 90/10%,15-pFload,60/40
duty cycle
GPIO Fout. Fast Strong mode.
–
–
–
–
MHz 90/10%,15-pFload,60/40
duty cycle
SID75
GPIO Fout; Slow Strong mode.
GPIO Fout; Fast Strong mode.
GPIO Fout; Slow Strong mode.
100
1.3
MHz 90/10%,25-pFload,60/40
duty cycle
SID76
MHz 90/10%,25-pFload,60/40
duty cycle
SID245
SID246
GPIO input operating frequency;
100
MHz
90/10% VIO
1.71 V VDD 3.6 V
Analog Peripherals
Low-Power (LP) Comparator
Table 19. LP Comparator DC Specifications
Spec ID#
Parameter
Description
Min Typ
–10
Max
Units
Details/Conditions
Input offset voltage. Normal power
mode.
SID84
V
V
V
V
V
V
V
V
–
10
25
25
60
80
mV
mV
mV
mV
mV
V
–
–
–
–
–
–
–
–
–
OFFSET1
Input offset voltage. Low-power
mode.
SID85A
SID85B
SID86
–25 ±12
–25 ±12
OFFSET2
OFFSET3
HYST1
HYST2
ICM1
Input offset voltage. Ultra
low-power mode.
Hysteresis when enabled in
Normal mode
–
–
–
–
–
–
–
–
Hysteresis when enabled in
Low-power mode
SID86A
SID87
Input common mode voltage in
Normal mode
0
VDDIO1 – 0.1
VDDIO1 – 0.1
VDDIO1 – 0.1
–
InputcommonmodevoltageinLow
power mode
SID247
SID247A
SID88
0
V
ICM2
Input common mode voltage in
Ultra low power mode
0
V
ICM3
Common mode rejection ratio in
Normal power mode
CMRR
50
dB
SID89
I
Block current, Normal mode
–
–
–
–
150
10
µA
µA
–
–
CMP1
SID248
I
Block current, Low-power mode
CMP2
Block current in Ultra low-power
mode
SID259
SID90
I
–
0.3
–
0.85
–
µA
–
–
CMP3
ZCMP
DC input impedance of comparator 35
MΩ
Document Number: 002-28690 Rev. *I
Page 56 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 20. LP Comparator AC Specifications
Spec ID#
Parameter
Description
Min Typ
Max
Units
Details/Conditions
Response time, Normal mode, 100
mV overdrive
SID91
T
T
T
–
–
–
–
–
–
100
ns
–
–
–
RESP1
Response time, Low power mode,
100 mV overdrive
SID258
SID92
1000
20
ns
µs
RESP2
RESP3
Response time, Ultra-low power
mode, 100 mV overdrive
SID92E
SID92F
T_CMP_EN1
T_CMP_EN2
Time from Enabling to operation
Time from Enabling to operation
–
–
–
–
10
50
µs Normal and low-power modes
µs Ultra-low-power mode
Temperature Sensor
Table 21. Temperature Sensor Specifications
Spec ID
SID93
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
T
Temperature sensor accuracy
–5
±1
5
°C –40 to +85 °C
SENSACC
Internal Reference
Table 22. Internal Reference Specification
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID93R
V
–
1.188
1.2
1.212
V
–
REFBG
SAR ADC
Table 23. 12-bit SAR ADC DC Specifications
Spec ID
SID94
SID95
SID96
SID97
SID98
SID99
Parameter
Description
SAR ADC resolution
Min
–
Typ
Max Units
Details/Conditions
A_RES
–
–
–
–
–
–
12
16
8
bits
–
A_CHNLS_S Number of channels - single-ended
–
8 full speed.
A-CHNKS_D
A-MONO
Number of channels - differential
Monotonicity
–
–
Diff inputs use neighboring I/Os
Yes.
–
-
–
A_GAINERR
A_OFFSET
Gain error
–
±0.2
2
%
With external reference.
Input offset voltage
–
mV Measured with 1-V reference
At 1 Msps. External reference
mode
1.05
mA
SID100
A_ISAR_1
Current consumption at 1 Msps
Current consumption at 1 Msps
Current consumption at 2 Msps
–
–
–
–
–
–
SID100A A_ISAR_2
1.3
mA At 1 Msps. Internal reference mode
At 2 Msps. External reference
mode
1.65
mA
SID1002
A_ISAR_3
SID1003
SID101
SID102
SID103
SID104
A_ISAR_4
A_VINS
Current consumption at 2 Msps
Input voltage range - single-ended
Input voltage range - differential
Input resistance
–
VSS
VSS
–
–
–
–
1
5
2.15
VDDA
VDDA
–
mA At 2 Msps. Internal reference mode
V
V
A_VIND
A_INRES
A_INCAP
KΩ
pF
Input capacitance
–
–
Document Number: 002-28690 Rev. *I
Page 57 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 24. 12-bit SAR ADC AC Specifications
Spec ID
SID106
Parameter
A_PSRR
Description
Min
70
Typ
–
Max Units
Details/Conditions
Power supply rejection ratio
–
–
dB
dB Measured at 1 V
SID107
A_CMRR
Common mode rejection ratio
Sample rate with external reference
With bypass cap
66
–
SID1081
SID1082
A_SAMP_1
A_SAMP_1
–
–
–
–
–
–
–
–
–
–
2
1
Msps
Msps
Msps
Msps
Msps
ksps
V
V
V
V
2.7–3.6
1.7–3.6
2.7–3.6
1.7–3.6
DDA
DDA
DDA
DDA
Sample rate with external reference
With bypass cap
Sample rate with V reference;
DD
SID108A1 A_SAMP_2
SID108A2 A_SAMP_2
SID108B A_SAMP_3
SID108C A_SAMP_4
–
2
No Bypass Cap
Sample rate with V Reference;
DD
–
1
No Bypass Cap
Sample rate with internal reference;
With Bypass Cap.
–
1
Sample rate with internal reference.
No Bypass Cap
–
200
–
Signal-to-noise and distortion ratio
(SINAD).
SID109
A_SINAD
A_INL
64
–2
dB Fin = 10 kHz
Integral non-linearity.
Up to 1 Msps
SID111A
2
LSB All reference modes
External reference or V
DDA
Reference Mode, V
≥ 2 V.
SID111B
A_INL
Integral non-linearity. 2 Msps.
–2.5
–1
–
–
2.5
1.5
LSB
REF
V
= 2.7 V to 3.6 V
DDA
SID112A A_DNL
SID112B A_DNL
Differential non-linearity. Up to 1 Msps
LSB All reference modes
External reference or V
DDA
≥ 2 V.
Differential non-linearity. 2 Msps.
Total harmonic distortion. 1 Msps.
–1
–
–
–
1.6
-65
LSB Reference Mode, V
REF
V
= 2.7 to 3.6V
DDA
SID113
A_THD
dB
F
= 10 kHz. V
= 2.7–3.6 V
IN
DDA
CSD
Table 25. CapSense Sigma-Delta (CSD) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
CSD V2 Specifications
Max allowed ripple on power supply,
DC to 10 MHz
V
> 2 V (with ripple), 25 °C
DDA
SYS.PER#3
V
–
–
–
–
±50
mV
DD_RIPPLE
T , sensitivity = 0.1 pF
A
V
> 1.75 V (with ripple),
DDA
25 °C T ,
Max allowed ripple on power supply,
DC to 10 MHz
A
SYS.PER#16
V
I
±25
mV
DD_RIPPLE_1.8
Parasitic capacitance (C ) <
20 pF, Sensitivity ≥ 0.4 pF
P
SID.CSD.BLK
SID.CSD#15
Maximum block current
–
–
4500
µA
V
–
CSD
VDDA
0.6
–
Voltage reference for CSD and
Comparator
V
0.6
1.2
V
V
– V
– V
≥ 0.6 V
≥ 0.6 V
REF
DDA
REF
REF
External Voltage reference for CSD
and Comparator
VDDA
0.6
–
SID.CSD#15A
V
I
0.6
–
V
REF_EXT
DDA
SID.CSD#16
SID.CSD#17
SID308
IDAC1 (7-bits) block current
IDAC2 (7-bits) block current
Voltage range of operation
–
–
–
–
–
1900
1900
3.6
µA
µA
V
–
–
DAC1IDD
DAC2IDD
I
V
1.7
1.71–3.6 V
CSD
Document Number: 002-28690 Rev. *I
Page 58 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)
Spec ID#
SID308A
Parameter
Description
Min
0.6
–1
Typ
–
Max
Units
V
Details / Conditions
– V ≥ 0.6 V
VDDA
0.6
–
V
I
Voltage compliance range of IDAC
V
–
COMPIDAC
DDA
REF
SID309
SID310
SID311
SID312
DNL
INL
–
1
3
1
3
LSB
LSB
LSB
LSB
DAC1DNL
DAC1INL
DAC2DNL
DAC2INL
If V
< 2 V then for LSB of
DDA
I
I
I
–3
–
2.4 µA or less
DNL
INL
–1
–
–
If V
< 2 V then for LSB of
DDA
–3
–
2.4 µA or less
SNRC of the following is Ratio of counts of finger to noise. Measured typical devices at room temperature using Dual IDAC + PRS
Clock Mode. Best performance is when using the PASS reference and the PLL.
SRSS Reference. IMO + FLL Clock
Source. 0.1-pF sensitivity.
SID313_1A
SID313_1B
SID313_1C
SID313_2A
SID313_2B
SID313_2C
SID313_3A
SID313_3B
SID313_3C
SID314
SNRC_1
SNRC_2
SNRC_3
SNRC_4
SNRC_5
SNRC_6
SNRC_7
SNRC_8
SNRC_9
IDAC
5
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ratio 9.5-pF max. capacitance
Ratio 31-pF max. capacitance
Ratio 61-pF max. capacitance
Ratio 12-pF max. capacitance
Ratio 47-pF max. capacitance
Ratio 86-pF max. capacitance
Ratio 25-pF max. capacitance
Ratio 86-pF max. capacitance
Ratio 168-pF Max. capacitance
µA LSB = 37.5-nA typ.
SRSS Reference. IMO + FLL Clock
Source. 0.3-pF sensitivity.
SRSS Reference. IMO + FLL Clock
Source. 0.6-pF sensitivity.
5
–
PASS Reference. IMO + FLL Clock
Source. 0.1-pF sensitivity.
5
–
PASS Reference. IMO + FLL Clock
Source. 0.3-pF sensitivity.
5
–
PASS Reference. IMO + FLL Clock
Source. 0.6-pF sensitivity.
5
–
PASS Reference. IMO + PLL Clock
Source. 0.1-pF sensitivity.
5
–
PASS Reference. IMO + PLL Clock
Source. 0.3-pF sensitivity.
5
–
PASS Reference. IMO + PLL Clock
Source. 0.6-pF sensitivity.
5
–
Output current of IDAC1 (7 bits) in
low range
4.2
33.7
270
8
5.7
45.6
365
11.4
91
730
5.7
45.6
365
1CRT1
Output current of IDAC1 (7 bits) in
medium range
SID314A
IDAC
IDAC
IDAC
IDAC
IDAC
IDAC
IDAC
IDAC
µA LSB = 300-nA typ.
1CRT2
1CRT3
1CRT12
1CRT22
1CRT32
2CRT1
2CRT2
2CRT3
Output current of IDAC1 (7 bits) in
high range
SID314B
µA LSB = 2.4-µA typ.
Output current of IDAC1 (7 bits) in
low range, 2X mode
LSB = 37.5-nA typ. 2X output
stage
SID314C
µA
Output current of IDAC1 (7 bits) in
medium range, 2X mode
LSB = 300-nA typ. 2X output
stage
SID314D
67
540
4.2
33.7
270
µA
Output current of IDAC1 (7 bits) in
LSB = 2.4-µA typ. 2X output
stage
SID314E
µA
high range, 2X mode. V
> 2 V
DDA
Output current of IDAC2 (7 bits) in
low range
SID315
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
Output current of IDAC2 (7 bits) in
medium range
SID315A
Output current of IDAC2 (7 bits) in
high range
SID315B
Document Number: 002-28690 Rev. *I
Page 59 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 25. CapSense Sigma-Delta (CSD) Specifications (continued)
Spec ID#
SID315C
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Output current of IDAC2 (7 bits) in
low range, 2X mode
LSB = 37.5-nA typ. 2X output
stage
IDAC
8
–
11.4
µA
2CRT12
2CRT22
2CRT32
3CRT13
3CRT23
3CRT33
Output current of IDAC2 (7 bits) in
medium range, 2X mode
LSB = 300-nA typ. 2X output
stage
SID315D
SID315E
SID315F
SID315G
SID315H
IDAC
IDAC
IDAC
IDAC
IDAC
67
540
8
–
–
–
–
–
91
730
11.4
91
µA
µA
Output current of IDAC2 (7 bits) in
LSB = 2.4-µA typ. 2X output
stage
high range, 2X mode. V
> 2V
DDA
Output current of IDAC in 8-bit mode
in low range
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
Output current of IDAC in 8-bit mode
in medium range
67
Output current of IDAC in 8-bit mode
540
730
µA LSB = 2.4-µA typ.
in high range. V
> 2V
DDA
SID320
SID321
IDAC
IDAC
IDAC
All zeroes input
–
–
–
–
1
LSB Polarity set by source or sink
OFFSET
GAIN
Full-scale error less offset
±15
%
LSB = 2.4-µA typ.
Mismatch between IDAC1 and
IDAC2 in Low mode
MIS-
SID322
–
–
–
–
–
–
–
–
9.2
6
LSB LSB = 37.5-nA typ.
LSB LSB = 300-nA typ.
LSB LSB = 2.4-µA typ.
MATCH1
IDAC
Mismatch between IDAC1 and
IDAC2 in Medium mode
MIS-
MATCH2
SID322A
SID322B
SID323
IDAC
Mismatch between IDAC1 and
IDAC2 in High mode
MIS-
5.8
10
MATCH3
Settling time to 0.5 LSB for 8-bit
IDAC
Full-scale transition. No
external load.
IDAC
µs
SET8
Settling time to 0.5 LSB for 7-bit
IDAC
Full-scale transition. No
external load.
SID324
SID325
IDAC
–
–
–
10
–
µs
SET7
CMOD
External modulator capacitor.
2.2
nF 5-V rating, X7R or NP0 cap.
Table 26. CSD ADC Specifications
Spec ID# Parameter
CSDv2 ADC Specifications
Description
Min Typ Max Units
Details / Conditions
Auto-zeroing is required every milli-
second
SIDA94
A_RES
Resolution
–
–
10
bits
SID95
A_CHNLS_S
A-MONO
Number of channels - single ended
Monotonicity
–
–
–
–
–
16
–
–
SIDA97
Yes
V
mode
REF
Reference source: SRSS
(V
(V
= 1.20 V, V
= 1.6 V, 2.2 V < V
< 2.2 V),
DDA
REF
SIDA98
A_GAINERR_VREF Gain error
–
–
0.6
0.2
–
–
%
%
<
REF
DDA
2.7 V), (V
2.7 V)
= 2.13 V, V
>
REF
DDA
Reference source: SRSS
(V
(V
=1.20 V, V
=1.6 V,
< 2.2V),
DDA
REF
SIDA98A A_GAINERR_VDDA Gain error
REF
2.2 V < V
< 2.7 V),
DDA
(V
= 2.13 V, V
> 2.7 V)
REF
DDA
Document Number: 002-28690 Rev. *I
Page 60 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 26. CSD ADC Specifications (continued)
Spec ID#
Parameter
Description
Min Typ Max Units
Details / Conditions
After ADC calibration, Ref. Src =
SRSS, (V
2.2 V),
= 1.20 V, V
<
REF
DDA
SIDA99
A_OFFSET_VREF
Input offset voltage
–
–
0.5
0.5
–
–
LSB
LSB
(V
= 1.6 V, 2.2 V < V
<
DDA
REF
2.7 V), (V
2.7 V)
= 2.13 V, V
>
REF
DDA
After ADC calibration, Ref. Src =
SRSS, (V
2.2 V),
= 1.20 V, V
<
REF
DDA
SIDA99A A_OFFSET_VDDA
Input offset voltage
(V
= 1.6 V, 2.2 V < V
<
DDA
REF
2.7 V),
(V = 2.13 V, V
> 2.7 V)
DDA
REF
SIDA100 A_ISAR_VREF
SIDA100A A_ISAR_VDDA
Current consumption
Current consumption
–
–
0.3
0.3
–
–
mA CSD ADC Block current
mA CSD ADC Block current
(V
(V
2.7 V),
= 1.20 V, V
< 2.2 V),
DDA
REF
= 1.6 V, 2.2 V < V
<
REF
DDA
SIDA101 A_VINS_VREF
SIDA101A A_VINS_VDDA
Input voltage range - single ended
Input voltage range - single ended
VSSA
–
–
VREF
V
V
(V
= 2.13 V, V
> 2.7 V)
< 2.2 V),
REF
DDA
DDA
(V
(V
= 1.20 V, V
REF
= 1.6 V, 2.2 V < V
<
DDA
RE F
VSSA
VDDA
2.7 V),
(V
= 2.13 V, V
> 2.7 V)
DDA
REF
SIDA103 A_INRES
SIDA104 A_INCAP
SIDA106 A_PSRR
Input charging resistance
Input capacitance
–
–
–
15
41
60
–
–
–
kΩ
pF
dB
–
–
Power supply rejection ratio (DC)
–
Measured with 50-Ω source
impedance. 10 µs is default
software driver acquisition time
setting. Settling to within 0.05%.
SIDA107 A_TACQ
Sample acquisition time
–
10
–
µs
Conversion time for 8-bit resolution at
conversion rate = Fhclk / (2"(N + 2)).
Clock frequency = 50 MHz.
SIDA108 A_CONV8
SIDA108A A_CONV10
–
–
25
60
–
–
µs Does not include acquisition time.
µs Does not include acquisition time.
Conversion time for 10-bit resolution at
conversion rate = Fhclk / (2"(N + 2)).
Clock frequency = 50 MHz.
Signal-to-noise and Distortion ratio
(SINAD)
Measured with 50-Ω source
impedance
SIDA109 A_SND_VRE
SIDA109A A_SND_VDDA
–
–
–
–
–
–
57
52
–
–
–
2
2
1
1
dB
Signal-to-noise and Distortion ratio
(SINAD)
Measured with 50-Ω source
impedance
dB
Measured with 50-Ω source
impedance
SIDA111
SIDA111A A_INL_VDDA
SIDA112 A_DNL_VREF
SIDA112A A_DNL_VDDA
A_INL_VREF
Integral non-linearity. 11.6 ksps
Integral non-linearity. 11.6 ksps
Differential non-linearity. 11.6 ksps
Differential non-linearity. 11.6 ksps
LSB
Measured with 50-Ω source
impedance
–
LSB
Measured with 50-Ω source
impedance
–
LSB
Measured with 50-Ω source
impedance
–
LSB
Document Number: 002-28690 Rev. *I
Page 61 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Digital Peripherals
Timer/Counter/PWM
Table 27. Timer/Counter/PWM (TCPWM) Specifications
Spec ID#
SID.TCPWM.1
SID.TCPWM.2
SID.TCPWM.2A
Parameter
Description
Min Typ Max Units
Details/Conditions
I
I
I
Block current consumption at 8 MHz
Block current consumption at 24 MHz
Block current consumption at 50 MHz
–
–
–
–
–
–
70
µA All modes (TCPWM)
µA All modes (TCPWM)
µA All modes (TCPWM)
TCPWM1
TCPWM2
TCPWM3
180
270
SID.TCPWM.2B
SID.TCPWM.3
I
Block current consumption at 100 MHz
Operating frequency
–
–
–
–
540
µA All modes (TCPWM)
TCPWM4
TCPWM
100 MHz Maximum = 100 MHz
FREQ
Trigger events can be Stop,
Start, Reload, Count, Capture,
or Kill depending on which
mode of operation is selected.
Fc is counter operating
frequency.
Input trigger pulse width for all trigger
events
SID.TCPWM.4
SID.TCPWM.5
TPWM
2/Fc
–
–
–
–
ns
ENEXT
Minimum possible width of
Overflow, Underflow, and CC
ns (Counter equals Compare
value) trigger outputs. Fc is
counter operating frequency.
TPWM
Output trigger pulse widths
1.5/Fc
EXT
Minimum time between
ns successive counts. Fc is
counter operating frequency.
SID.TCPWM.5A TC
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
RES
Minimum pulse width of PWM
ns output. Fc is counter operating
frequency.
SID.TCPWM.5B PWM
RES
Minimum pulse width between
Quadrature phase inputs.
ns Delays from pins should be
similar. Fc is counter operating
frequency.
SID.TCPWM.5C
Q
Quadrature inputs resolution
2/Fc
–
–
RES
Serial Communication Block (SCB)
Table 28. Serial Communication Block (SCB) Specifications
Spec ID#
Parameter
Description
Min Typ
Max Units
Details / Conditions
2
Fixed I C DC Specifications
SID149
SID150
SID151
SID152
I
I
I
I
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
–
–
–
–
–
–
–
–
30
80
µA
µA
µA
–
–
–
I2C1
I2C2
I2C3
I2C4
180
1.7
2
I C enabled in Deep Sleep mode
µA At 60 °C.
2
Fixed I C AC Specifications
SID153
Fixed UART DC Specifications
F
Bit rate
–
–
1
Mbps –
I2C1
SID160
SID161
I
I
Block current consumption at 100 kbps
Block current consumption at 1000 kbps
–
–
–
–
30
µA
µA
–
–
UART1
UART2
180
Fixed UART AC Specifications
SID162A
SID162B
F
–
–
–
–
3
8
Mbps ULP Mode
LP Mode
UART1
UART2
Bit Rate
F
Document Number: 002-28690 Rev. *I
Page 62 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 28. Serial Communication Block (SCB) Specifications (continued)
Spec ID#
Parameter
Description
Min Typ
Max Units
Details / Conditions
Fixed SPI DC Specifications
SID163
SID164
SID165
SID165A
I
I
I
I
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
Block current consumption at 25 Mbps
–
–
–
–
–
–
–
–
220
340
360
800
µA
µA
µA
µA
–
–
–
–
SPI1
SPI2
SPI3
SP14
Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SPIOperatingfrequencyexternallyclocked
slave
12-MHz max for ULP (0.9 V)
mode
SID166
F
F
F
–
–
–
–
–
–
25
MHz
SPI
F
max is 100 MHz in LP
scb
SPI operating frequency master (F
SPI clock).
is
scb
SID166B
Fscb/4 MHz (1.1 V) mode, 25 MHz in ULP
mode.
SPI_EXT
SPI_IC
5 MHz max for ULP (0.9 V)
mode
SID166A
SPI slave internally clocked
15
MHz
Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
20-ns max for ULP (0.9 V)
mode
SID167
SID168
SID169
T
T
T
MOSI valid after SClock driving edge
MISO valid before SClock capturing edge
MOSI data hold time
–
5
0
–
–
–
12
–
ns
ns
ns
DMO
Full clock, late MISO
sampling
DSI
Referred to Slave capturing
edge
–
HMO
Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID170
T
MOSI valid before Sclock capturing edge
5
–
–
–
–
ns
ns
–
DMI
MISO valid after Sclock driving edge in Ext.
Clk. mode
35-ns max. for ULP (0.9 V)
mode
SID171A
T
20
DSO_EXT
TDSO_
EXT + 3 * ns
TSCB
MISO valid after Sclock driving edge in
Internally Clk. mode
SID171
T
–
–
–
–
T
T
is SCB clock period.
is SCB clock period.
DSO
SCB
SCB
TDSO_E
XT + 4 * ns
TSCB
MISO Valid after Sclock driving edge in
Internally Clk. Mode with median filter
enabled.
SID171B
T
T
DSO
SID172
Previous MISO data hold time
5
–
–
–
–
–
–
ns
ns
ns
–
–
–
HSO
SID172A
SID172B
TSSEL
TSSEL
SSEL Valid to first SCK valid edge
SSEL Hold after Last SCK valid edge
65
65
SCK1
SCK2
Document Number: 002-28690 Rev. *I
Page 63 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
LCD Specifications
Table 29. LCD Direct Drive DC Specifications
Spec ID#
SID155
Parameter
Description
Min
–
Typ Max Units
Details / Conditions
LCD capacitance per segment/common
driver
C
500 5000 pF
–
–
LCDCAP
SID156
SID157
LCD
I
Long-term segment offset
–
20
–
–
mV
mA
OFFSET
PWM Mode current.
32 × 4 segments
50 Hz
–
0.6
LCDOP1
LCDOP2
3.3 V bias. 8 MHz IMO. 25 °C.
PWM Mode current.
32 × 4 segments
50 Hz
SID158
I
–
0.5
–
mA
3.3 V bias. 8 MHz IMO. 25 °C.
Table 30. LCD Direct Drive AC Specifications
Spec ID Parameter Description
SID159 LCD frame rate
Min
Typ Max Units
50 150 Hz
Details/Conditions
F
10
–
LCD
Document Number: 002-28690 Rev. *I
Page 64 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Memory
Table 31. Flash Specifications[5]
Spec ID
Flash DC Specifications
SID173A IPE
Flash AC Specifications
Parameter
Description
Min Typ Max
Units
Details/Conditions
Erase and program current
–
–
6
mA
–
SID174
SID175
SID176
SID178
SID179
SID178S
TROWWRITE
TROWERASE
Row write time (erase and program)
Row erase time
–
–
–
–
–
–
–
–
–
–
–
–
16
11
5
ms
ms
ms
ms
ms
ms
Row = 512 bytes
–
TROWPROGRAM Row program time after erase
TBULKERASE Bulk erase time (2048 KB)
TSECTORERASE Sector erase time (256 KB)
–
11
11
11
–
512 rows per sector
8 rows per subsector
TSSERIAE
Subsector erase time
Subsector write time; 1 erase plus 8
program times
SID179S
SID180S
TSSWRITE
–
–
–
–
51
ms
–
Sector write time; 1 erase plus 512
program times
TSWRITE
2.6 seconds –
SID180
SID181
TDEVPROG
FEND
Total device write time
Flash endurance
–
–
–
30
–
seconds –
100K
cycles
–
Flash retention. TA 25 °C, 100K P/E
cycles
SID182
FRET1
FRET2
FRET3
10
10
20
–
–
–
–
–
–
years
–
Flash retention. TA 85 °C, 10K P/E
cycles
SID182A
SID182B
years
years
–
–
Flash retention. TA 55 °C, 20K P/E
cycles
SID256
SID257
TWS100
TWS50
Number of Wait states at 100 MHz
Number of Wait states at 50 MHz
3
2
–
–
–
–
LP mode. VCCD = 1.1 V
ULP mode. VCCD = 0.9 V
Note
5. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 002-28690 Rev. *I
Page 65 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
System Resources
Table 32. System Resources
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Power-On-Reset with Brown-out DC Specifications
Precise POR (PPOR)
BOD trip voltage in Active and Sleep
modes. VDDD
BOD reset guaranteed for
levels below 1.54 V
SID190
SID192
SID192A
VFALLPPOR
VFALLDPSLP
VDDRAMP
1.54
1.54
–
–
–
–
–
–
V
V
.
BOD trip voltage in Deep Sleep. VDDD
.
–
Maximum power supply ramp rate (any
supply)
100 mV/µs Active mode
POR with Brown-out AC Specification
Maximum power supply ramp rate (any
supply) in Deep Sleep
SID194A
VDDRAMP_DS
–
–
10
mV/µs BOD operation guaranteed
Voltage Monitors DC Specifications
SID195
SID196
SID197
SID198
SID199
SID200
SID201
SID202
SID203
SID204
SID205
SID206
SID207
SID208
SID209
SID211
VHVDI1
VHVDI2
VHVDI3
VHVDI4
VHVDI5
VHVDI6
VHVDI7
VHVDI8
VHVDI9
VHVDI10
VHVDI11
VHVDI12
VHVDI13
VHVDI14
VHVDI15
LVI_IDD
–
1.38 1.43 1.47
1.57 1.63 1.68
1.76 1.83 1.89
1.95 2.03 2.1
2.05 2.13 2.2
2.15 2.23 2.3
2.24 2.33 2.41
2.34 2.43 2.51
2.44 2.53 2.61
2.53 2.63 2.72
2.63 2.73 2.82
2.73 2.83 2.92
2.82 2.93 3.03
2.92 3.03 3.13
3.02 3.13 3.23
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Block current
–
5
15
Voltage Monitors AC Specification
SID212 TMONTRIP Voltage monitor trip time
–
–
170
ns
–
Document Number: 002-28690 Rev. *I
Page 66 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
SWD Interface
Table 33. SWD and Trace Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details / Conditions
SWD and Trace Interface
LP Mode.
MHz
SID214
F_SWDCLK2
F_SWDCLK2L
1.7 V V
1.7 V V
3.6 V
–
–
–
–
25
12
DDD
V
= 1.1 V.
CCD
ULP Mode.
SID214L
3.6 V
MHz
DDD
V
–
–
–
–
= 0.9 V.
CCD
SID215
SID216
SID217
SID217A
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
0.25 * T
–
–
–
–
–
ns
ns
ns
ns
0.25 * T
–
0.5 * T
–
–
1
With Trace Data setup/hold times of
2/1 ns respectively
SID214T
SID215T
SID216T
F_TRCLK_LP1
F_TRCLK_LP2
F_TRCLK_ULP
–
–
–
–
–
–
50
50
20
MHz LP Mode. V = 1.1 V.
DD
With Trace Data setup/hold times of
3/2 ns respectively
MHz LP Mode. V = 1.1 V.
DD
With Trace Data setup/hold times of
3/2 ns respectively
MHz ULP Mode. V = 0.9 V.
DD
Internal Main Oscillator
Table 34. IMO DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID218
I
IMO operating current at 8 MHz
–
9
15
µA
–
IMO1
Table 35. IMO AC Specifications
Spec ID
SID223
Parameter
Description
Min
–
Typ
–
Max
±2
–
Units
%
Details/Conditions
Frequency variation centered on
8 MHz
F
T
–
–
IMOTOL1
JITR
SID227
Cycle-to-cycle and period jitter
–
250
ps
Internal Low-Speed Oscillator
Table 36. ILO DC Specification
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID231
I
ILO operating current at 32 kHz
–
0.3
0.7
µA
–
ILO2
Table 37. ILO AC Specifications
Spec ID
Parameter
Description
ILO startup time
Min
Typ
Max
Units
Details/Conditions
Startup time to 95% of
final frequency
SID234
T
–
–
7
µs
STARTILO1
SID236
SID237
TLIODUTY
ILO duty cycle
ILO frequency
45
50
32
55
%
–
F
28.8
36.1
kHz
Factory trimmed
ILOTRIM1
Document Number: 002-28690 Rev. *I
Page 67 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Crystal Oscillator Specifications
Table 38. ECO Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
MHz ECO DC Specifications
Max = 35 MHz,
Typ = 16 MHz
Block operating current with Cload up to
18 pF
SID316
MHz ECO AC Specifications
SID317 F_MHz
I
–
800
1600
µA
DD_MHz
Some restrictions apply.
Refer to the device TRM.
Crystal frequency range
16
–
35
MHz
kHz ECO DC Specifications
SID318
I
Block operating current with 32-kHz crystal
Equivalent series resistance
Drive level
–
–
–
0.38
80
–
1
–
1
µA
kΩ
–
–
–
DD_kHz
SID321E ESR32K
SID322E PD32K
µW
kHz ECO AC Specifications
SID319
SID320
SID320E
F_kHz
32 kHz frequency
Startup time
–
–
–
32.768
–
kHz
ms
–
–
–
Ton_kHz
–
500
250
F
Frequency tolerance
50
ppm
TOL32K
External Clock Specifications
Table 39. External Clock Specifications
Spec ID
SID305
SID306
Parameter
Description
Min
0
Typ
–
Max
100
55
Units
MHz
%
Details/Conditions
EXTCLK
External clock input frequency
–
–
FREQ
DUTY
EXTCLK
Duty cycle; measured at V
45
–
DD/2
PLL Specifications
Table 40. PLL Specifications
Spec ID Parameter
Description
Input frequency to PLL block
Time to achieve PLL lock
Output frequency from PLL block
PLL current
Min
Typ
–
Max
64
Units
MHz
µs
Details/Conditions
SID304P PLL_IN
SID305P PLL_LOCK
SID306P PLL_OUT
SID307P PLL_IDD
4
–
10.625
–
16
–
35
–
–
150
1.1
MHz
0.55
mA Typ. at 100 MHz out.
100 MHz output
frequency
SID308P PLL_JTR
Period jitter
–
–
150
ps
Table 41. Clock Source Switching Time
Spec ID
Parameter
Description
Min
Typ
Max
Units
periods –
Details/Conditions
Clock switching from clk1 to clk2 in clock
periods; for example, from IMO (clk1) to FLL
4 clk1 +
3 clk2
SID262
TCLK
–
–
SWITCH
[6]
(clk2).
Note
6. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 3) then clk1 is the IMO and clk2 is the FLL.
Document Number: 002-28690 Rev. *I
Page 68 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
FLL Specifications
Table 42. Frequency Locked Loop (FLL) Specifications
Spec ID
Parameter
Description
Input frequency range.
Output frequency range.
Min
Typ
Max
Units
Details / Conditions
Lower limit allows lock to
USB SOF signal (1 kHz).
Upper limit is for External
input.
SID450
FLL_RANGE
0.001
–
100
MHz
Output range of FLL
divided-by-2 output
SID451
FLL_OUT_DIV2
24.00
–
100.00
MHz
V
= 1.1 V
CCD
Output frequency range.
= 0.9 V
Output range of FLL
divided-by-2 output
SID451A
SID452
FLL_OUT_DIV2
FLL_DUTY_DIV2
24.00
47.00
–
–
50.00
53.00
MHz
%
V
CCD
Divided-by-2 output; High or Low
–
With IMO input, less than
10 °C change in
temperature while in Deep
Sleep, and Fout ≥ 50 MHz.
Time from stable input clock to 1% of
final value on Deep Sleep wakeup
SID454
FLL_WAKEUP
–
–
7.50
µs
50 ps at 48 MHz, 35 ps at
100 MHz
SID455
SID456
FLL_JITTER
Period jitter (1 sigma) at 100 MHz
CCO + Logic current
–
–
–
–
35.00
5.50
ps
FLL_CURRENT
µA/MHz –
USB
Table 43. USB Specifications (USB requires LP Mode 1.1-V internal supply)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
USB Block Specifications
SID322U
SID323U
SID325U
SID328
Vusb_3.3
Device supply for USB operation
3.15
2.85
–
–
–
3.6
3.6
–
V
V
USB Configured
USB Configured
Device supply for USB operation
(functional operation only)
Vusb_3
Iusb_config
Iusb_suspend
Block supply current in Active mode
8
mA
mA
V
V
= 3.3 V
DDD
= 3.3 V, Device
DDD
Block supply current in suspend mode
–
0.5
–
connected
V
= 3.3 V, Device
DDD
SID329
Iusb_suspend
Block supply current in suspend mode
USB driver impedance
–
0.3
–
–
mA
Ω
disconnected
Series resistors are on
chip
SID330U
USB_Drive_Res
28
44
SID331U
SID332U
USB_Pulldown
USB pull-down resistors in Host mode
Idle mode range
14.25
900
–
–
24.8
kΩ
–
USB_Pullup_Idle
1575
Ω
Bus idle
Upstream device trans-
mitting
SID333U
USB_Pullup
Active mode
1425
–
3090
Ω
Document Number: 002-28690 Rev. *I
Page 69 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
QSPI
Table 44. QSPI Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details / Conditions
SMIF QSPI Specifications. All specs with 15-pF load. Measured from 50% to 50% waveform transitions.
SID390Q
Fsmifclock
SMIF QSPI output clock frequency
SMIF QSPI output clock frequency
–
–
–
–
80
50
MHz LP mode (1.1 V)
ULP mode (0.9 V).
MHz
SID390QU
Fsmifclocku
Guaranteed by Char.
SID397Q
SID398Q
Idd_qspi
Block current in LP mode (1.1 V)
Block current in ULP mode (0.9 V)
–
–
–
–
1900
590
µA
µA
LP mode (1.1 V)
ULP mode (0.9 V)
Idd_qspi_u
Input data set-up time with respect to
clock capturing falling edge
Guaranteed by charac-
terization
SID391Q
SID392Q
SID393Q
SID394Q
SID395Q
SID396Q
Tsetup
4.5
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
Input data hold time with respect to clock
capturing falling edge
Tdatahold
Tdataoutvalid
Tholdtime
Tseloutvalid
Tselouthold
1
–
Output data valid time with respect to
clock falling edge
7.5-ns max for ULP
mode (0.9 V)
–
3.7
–
Output data hold time with respect to
clock rising edge
3
–
–
Output Select valid time with respect to
clock rising edge
15-ns max for ULP
mode (0.9 V)
7.5
–
Output Select hold time with respect to
clock rising edge
Tsclk = Fsmifclk cycle
time
Tsclk/2
Audio Subsystem
Table 45. Audio Subsystem Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
PDM Specifications
PDM Active current, stereo
operation, 1-MHz clock
SID400P PDM_IDD1
–
–
175
600
–
–
µA
µA
16-bit audio at 16 ksps
24-bit audio at 48 ksps
PDM Active current, stereo
operation, 3-MHz clock
SID401
PDM_IDD2
[6]
[6]
SID402
SID403
PDM_JITTER
PDM_CLK
RMS jitter in PDM clock
PDM clock speed
–200
0.384
1.024
–
–
–
200
ps
–
–
–
3.072
49.152
MHz
MHz
[6]
SID403A PDM_BLK_CLK PDM block input clock
Data input set-up time to
PDM_CLK edge
[6]
SID403B PDM_SETUP
10
10
–
–
–
–
ns
ns
–
–
Data input hold time to PDM_CLK
edge
[6]
SID403C PDM_HOLD
[6]
SID404
SID405
PDM_OUT
PDM_WL
Audio sample rate
Word length
8
–
–
48
24
ksps
bits
–
–
[6]
[6]
16
Signal-to-Noise Ratio
(A-weighted)
PDM input, 20 Hz to 20 kHz
BW
SID406
SID407
SID408
PDM_SNR
PDM_DR
–
–
100
100
–
–
dB
dB
20 Hz to 20 kHz BW, -60 dB
FS
[6]
Dynamic range (A-weighted)
DC to 0.45f, DC Blocking
filter off.
[6]
[6]
PDM_FR
PDM_SB
Frequency response
Stop band
–0.2
–
–
0.2
–
dB
f
SID409
0.566
–
Note
6. Guaranteed by design, not production tested.
Document Number: 002-28690 Rev. *I
Page 70 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 45. Audio Subsystem Specifications (continued)
Spec ID#
Parameter
PDM_SBA
Description
Stop band attenuation
Adjustable gain
Min
–
Typ
60
–
Max
–
Units
dB
Details / Conditions
[6]
SID410
–
[6]
SID411
PDM_GAIN
PDM_ST
–12
–
10.5
–
dB
PDM to PCM, 1.5 dB/step
Word Select (WS) cycles
[6]
SID412
Startup time
48
I2S Specifications. The same for LP and ULP modes unless stated otherwise.
SID415
SID413
I2S_IDD
Block current
–
8
400
–
–
µA
I2S_WORD
Length of I2S Word
32
bits
12.288-MHz bit clock with
32-bit word
SID414
I2S_WS
Word clock frequency in LP mode
–
–
–
–
–
–
–
–
192
48
kHz
Word clock frequency in ULP
mode
3.072-MHz bit clock with
32-bit word
SID414M I2S_WS_U
kHz
Word clock frequency in TDM
mode for LP
SID414A I2S_WS_TDM
48
kHz Eight 32-bit channels
kHz Eight 32-bit channels
Word clock frequency in TDM
mode for ULP
SID414X I2S_WS_TDM_U
12
I2S Slave Mode
WS setup time to the following
rising edge of SCK for LP mode
SID430
TS_WS
5
–
–
–
–
–
–
ns
ns
ns
–
–
–
WS setup time to the following
rising edge of SCK for ULP mode
SID430U TS_WS_U
SID430A TH_WS
11
[7]
TMCLK_SOC
WS hold time to the following edge
of SCK
+5
Associated clock edge
depends on selected
polarity
-(TMCLK_SOC
+25)
Delay time of TX_SDO transition
from edge of TX_SCK for LP mode
TMCLK_S
OC+25
SID432
TD_SDO
–
–
–
–
ns
ns
ns
ns
Delay time of TX_SDO transition
from edge of TX_SCK for ULP
mode
Associated clock edge
depends on selected
polarity
-(TMCLK_SOC
+70)
TMCLK_S
OC+70
SID432U TD_SDO_U
RX_SDI setup time to the
following edge of RX_SCK in LP
mode
SID433
TS_SDI
5
–
–
–
–
RX_SDI setup time to the
following edge of RX_SCK in ULP
mode
SID433U TS_SDI_U
11
TMCLK_SOC
+
RX_SDI hold time to the rising
edge of RX_SCK
SID434
SID435
TH_SDI
–
–
–
ns
%
–
–
5
TSCKCY
TX/RX_SCK bit clock duty cycle
45
55
I2S Master Mode
WS transition delay from falling
edge of SCK in LP mode
SID437
TD_WS
–10
–10
–10
–10
–
–
–
–
20
40
20
40
ns
ns
ns
ns
–
–
–
–
WS transition delay from falling
edge of SCK in ULP mode
SID437U TD_WS_U
SDO transition delay from falling
edge of SCK in LP mode
SID438
TD_SDO
SDO transition delay from falling
edge of SCK in ULP mode
SID438U TD_SDO
Note
7. TMCLK_SOC is the internal I2S master clock period.
Document Number: 002-28690 Rev. *I
Page 71 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 45. Audio Subsystem Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
Associated clock edge
depends on selected
polarity
SDI setup time to the associated
edge of SCK
SID439
TS_SDI
5
–
–
ns
T is TX/RX_SCK Bit Clock
period. Associated clock
edge depends on selected
polarity.
SDI hold time to the associated
edge of SCK
TMCLK_SOC
+
SID440
TH_SDI
–
–
ns
%
5
SID443
SID445
TSCKCY
SCK bit clock duty cycle
45
–
–
55
–
MCLK_SOC frequency in LP
mode
FMCLK_SOC
1.024
98.304
MHz FMCLK_SOC = 8*Bit-clock
MCLK_SOC frequency in ULP
mode
FMCLK_SOC_U = 8 *
Bit-clock
SID445U FMCLK_SOC_U
1.024
–
24.576
MHz
SID446
SID447
TMCLKCY
TJITTER
MCLK_SOC duty cycle
MCLK_SOC input jitter
45
–
–
55
%
–
–
–100
100
ps
Smart I/O
Table 46. Smart I/O Specifications
Spec ID#
SID420
Parameter
SMIO_BYP
SMIO_LUT
Description
Smart I/O bypass delay
Smart I/O LUT prop delay
Min
–
Typ
Max
2
Units
ns
Details/Conditions
Details / Conditions
–
8
–
–
SID421
–
–
ns
SD Host Controller and eMMC
Table 47. SD Host Controller and eMMC Specifications
Spec ID# Parameter Description
Min
Typ
Max
Units
SD Host Controller and eMMC Specifications (SD Host clock (see the Clocking Diagram) must be divided by 2 or more
when used as source in DDR modes. Specifications are Guaranteed by Design.
SID_SD390
SID_SD391
SD:DS Timing
SID_SD392
SID_SD393
SID_SD394
SID_SD395
SD_DS
SD_TR
I/O drive select
4
–
–
4
3
mA
ns
drive_sel = '01' for all modes
–
Input transition time
0.7
SD_CLK
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
–
–
–
–
–
–
25
8
MHz (40-ns period)
MHz (125-ns period)
SD_DCMD_CL I/O loading at DATA/CMD pins
30
30
–
pF
pF
–
–
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD396
SID_SD397
SID_SD398
SID_SD399
SID_SD400
5.1
5.1
24
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
109
2.1
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
SD:HS Timing
SID_SD401
SID_SD402
SD_CLK
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
–
–
–
–
45
16
MHz (20-ns period)
MHz (62.5-ns period)
Document Number: 002-28690 Rev. *I
Page 72 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 47. SD Host Controller and eMMC Specifications (continued)
Spec ID#
SID_SD403
SID_SD404
Parameter
Description
Min
–
Typ
30
Max
–
Units
pF
Details / Conditions
SD_DCMD_CL I/O loading at DATA/CMD pins
–
–
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
30
–
pF
Output:Setup time ofCMD/DATprior
to CLK
SID_SD405
SID_SD406
SID_SD407
SID_SD408
SID_SD409
6.1
2.1
8
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
48
2.5
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
SD:SDR-12 Timing
SID_SD410
SID_SD411
SID_SD412
SID_SD413
SID_SD414
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
Duty cycle of output CLK
–
–
–
–
25
8
MHz (40-ns period)
MHz (125-ns period)
SD_CLK
SD_CLK_DC
30
–
–
70
–
%
pF
pF
–
–
–
SD_DCMD_CL I/O loading at DATA/CMD pins
30
30
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD415
SID_SD416
SID_SD417
SID_SD418
SID_SD419
3.1
0.9
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
24
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
109
1.85
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
SD:SDR-25 Timing
SID_SD420
SID_SD421
SID_SD422
SID_SD423
SID_SD424
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
Duty cycle of output CLK
–
–
–
–
50
16
70
–
MHz (20-ns period)
MHz (62.5-ns period)
SD_CLK
SD_CLK_DC
30
–
–
%
pF
pF
–
–
–
SD_DCMD_CL I/O loading at DATA/CMD pins
30
30
SD_CLK_CL
I/O loading at CLK pins
–
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD425
SID_SD426
SID_SD427
SID_SD428
SID_SD429
SD_TS_OUT
3.1
0.9
5.8
48
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
1.8
SD:SDR-50 Timing
SID_SD430 SD_CLK
Interface clock period (LP mode)
–
–
80
MHz (12.5-ns period)
Document Number: 002-28690 Rev. *I
Page 73 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 47. SD Host Controller and eMMC Specifications (continued)
Spec ID#
SID_SD431
SID_SD432
SID_SD433
SID_SD434
Parameter
SD_CLK
Description
Min
–
Typ
–
Max
32
70
–
Units
Details / Conditions
Interface clock period (ULP mode)
Duty cycle of output CLK
MHz (31.25-ns period)
SD_CLK_DC
30
–
–
%
pF
pF
–
–
–
SD_DCMD_CL I/O loading at DATA/CMD pins
20
20
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD435
SID_SD436
SID_SD437
SID_SD438
SID_SD439
3.1
0.9
5
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
23
1.8
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
SD:DDR-50 Timing
SID_SD440
SID_SD441
SID_SD442
SID_SD443
SID_SD444
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
Duty cycle of output CLK
–
–
–
–
40
16
55
–
MHz (25-ns period).
MHz (62.5-ns period)
SD_CLK
SD_CLK_DC
45
–
–
%
pF
pF
–
–
–
SD_DCMD_CL I/O loading at DATA/CMD pins
30
30
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD445
SID_SD446
SID_SD447
SID_SD448
SID_SD449
3.1
0.9
5.75
24
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
1.8
eMMC:BWC Timing
SID_SD450
SID_SD451
SID_SD452
SID_SD453
SD_CLK
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
–
–
–
–
–
–
26
8
MHz (38.4-ns period)
MHz (125-ns period)
SD_DCMD_CL I/O loading at DATA/CMD pins
30
30
–
pF
pF
–
–
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD454
SID_SD455
SID_SD456
SID_SD457
SID_SD458
3.1
3.1
9.7
96
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
8.3
Document Number: 002-28690 Rev. *I
Page 74 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Table 47. SD Host Controller and eMMC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
eMMC:SDR Timing
SID_SD459
SID_SD460
SID_SD461
SID_SD462
SD_CLK
SD_CLK
Interface clock period (LP mode)
Interface clock period (ULP mode)
–
–
–
–
–
–
52
16
–
MHz (19.2-ns period)
MHz (62.5-ns period)
SD_DCMD_CL I/O loading at DATA/CMD pins
30
30
pF
pF
–
–
SD_CLK_CL
SD_TS_OUT
I/O loading at CLK pins
–
Output:Setup time ofCMD/DATprior
to CLK
SID_SD463
SID_SD464
SID_SD465
SID_SD466
SID_SD467
3.1
3.1
5.3
48
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
Output: Hold time of CMD/DAT after
CLK
SD_HLD_OUT
SD_TS_IN
Input: Setup time of CMD/DAT prior
to CLK (LP mode)
Input: Setup time of CMD/DAT prior
to CLK (ULP mode)
SD_TS_IN
Input: Hold time of CMD/DAT after
CLK
SD_HLD_IN
2.5
SD Host Block Current Specs
SD Host block current consumption
at 100 MHz
SID_SD400SD IDD_SD_1
–
–
4.65
3.75
5
mA
mA
–
–
SD Host block current consumption
at 50 MHz
SID_SD401SD IDD_SD_2
4.3
JTAG Boundary Scan
Table 48. JTAG Boundary Scan
Spec ID#
Parameter
Description Min Typ Max
Units
JTAG Boundary Scan Parameters
JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:
SID468
SID469
SID470
SID471
SID472
TCKLOW
TCKHIGH
TCK_TDO
TSU_TCK
TCk_THD
TCK LOW
52
10
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
TCK HIGH
–
–
–
–
TCK falling edge to output valid
Input valid to TCK rising edge
Input hold time to TCK rising edge
40
–
12
10
–
TCK falling edge to output valid
(High-Z to Active).
SID473
SID474
TCK_TDOV
TCK_TDOZ
40
40
–
–
–
–
ns
ns
–
–
TCK falling edge to output valid
(Active to High-Z).
JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:
SID468A
SID469A
SID470A
SID471A
SID472A
TCKLOW
TCKHIGH
TCK_TDO
TSU_TCK
TCk_THD
TCK low
102
20
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
–
–
–
–
–
TCK high
TCK falling edge to output valid
Input valid to TCK rising edge
Input hold time to TCK rising edge
80
–
22
20
–
TCK falling edge to output valid
(high-Z to active).
SID473A
SID474A
TCK_TDOV
TCK_TDOZ
80
80
–
–
–
–
ns
ns
–
–
TCK falling edge to output valid
(active to high-Z).
Document Number: 002-28690 Rev. *I
Page 75 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Ordering Information
Table 49 lists the part numbers and features of this product line. See also the product selector guide.
Table 49. Ordering Information
Arm CM4/CM0+,
DC-DC converter,
12-bit SAR ADC,
2 LPCOMPs,
CYS0644ABZI-S2D44
CYS0644AFNI-S2D43T
150/50
150/50
100/25
100/25
FLEX
FLEX
2048
2048
1024
1024
Y
Y
Y
Y
100 124
BGA
82 100 WLCSP
64
13 SCBs, 32
TCPWMs, 2 I2S,
2 PDM, 2 SD Host
Controllers,
USB-FS
Document Number: 002-28690 Rev. *I
Page 76 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
PSoC 6 MPN Decoder
CY XX 6 A B C DD E - FF G H I JJ K L
Field
Description Values
Meaning
Cypress
Field
Description
Values
Meaning
Consumer
CY
Cypress
CY
8C
B0
S0
6
C
I
Standard
E
Temperature Range
Industrial
XX
6
Firmware
“Secure Boot” v1
“Standard Secure” - AWS
PSoC 6
Q
Extended Industrial
Cypress internal
Architecture
FF
Feature Code
S2-S6
0
Value
BL
F
Integrated Bluetooth LE
Single Core
Dual Core
Feature set
31-50
1
Programmable
Performance
Connectivity
Secured
G
H
CPU Core
A
B
Line
2
D
3
Attributes Code
0–9
1
4
2
100 MHz
2
51-70
I
GPIO count
Speed
3
150 MHz
3
71-90
4
150/50 MHz
4
91-110
Engineering samples or
not
Engineering sample
(optional)
0-3
Reserved
JJ
K
ES
4
5
256K/128K
512K/256K
Base
Die Revision
(optional)
A1-A9 Die revision
Tape and Reel shipment
Tape/ReelShipment
(optional)
Memory Size
(Flash/SRAM)
6
512K/128K
L
T
C
7
8
9
A
1024K/288K
1024K/512K
Reserved
2048K/1024K
AZ, AX TQFP
LQ
BZ
FM
QFN
BGA
DD
Package
M-CSP
FN, FD,
FT
WLCSP
Document Number: 002-28690 Rev. *I
Page 77 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Packaging
This product line is offered in 124-BGA and 100-WLCSP packages.
Table 50. Package Dimensions
Spec ID#
PKG_1
Package
Description
124 BGA, 9 mm × 9 mm × 1 mm height with 0.65-mm pitch
Package Dwg #
001-97718
124-BGA
PKG_2
100-WLCSP 100 WLCSP, 4.1 mm × 3.9 mm × 0.5 mm height with 0.5-mm pitch
002-23991
Table 51. Package Characteristics
Parameter Description
Conditions
Min
–40
–40
–
Typ
25
Max
85
100
–
Units
°C
T
T
T
T
T
T
Operating ambient temperature
Operating junction temperature
–
–
–
–
–
–
A
–
°C
J
Package (124-BGA)
31.9
11
°C/watt
°C/watt
°C/watt
°C/watt
JA
JC
JA
JC
JA
Package (124-BGA)
–
–
JC
Package (100-WLCSP)
–
19.1
0.12
–
JA
Package (100-WLCSP)
–
–
JC
Table 52. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All packages
260 °C
30 seconds
Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
124-BGA
MSL
MSL 3
MSL 1
100-WLCSP
Document Number: 002-28690 Rev. *I
Page 78 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 20. 124-BGA 9.0 × 9.0 ×1.0 mm
001-97718 *B
Document Number: 002-28690 Rev. *I
Page 79 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Figure 21. 100-WLCSP 4.1068 × 3.9025 × 0.467mm
002-23991 *A
Document Number: 002-28690 Rev. *I
Page 80 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Acronyms
Acronym
Description
electrostatic discharge
Acronym
Description
ESD
ETM
FIFO
FLL
3DES
ADC
triple DES (data encryption standard)
analog-to-digital converter
embedded trace macrocell
first-in, first-out
advanced DMA version 3, a Secure Digital data
transfer mode
ADMA3
AES
frequency locked loop
FPU
floating-point unit
advanced encryption standard
FS
full-speed
AMBA (advanced microcontroller bus architecture)
high-performance bus, an Arm data transfer bus
AHB
GND
GPIO
HMAC
HSIOM
Ground
general-purpose input/output, applies to a PSoC pin
Hash-based message authentication code
high-speed I/O matrix
AMUX
analog multiplexer
AMUXBUS analog multiplexer bus
API
application programming interface
®
I/O
2
input/output, see also GPIO, DIO, SIO, USBIO
Arm
advanced RISC machine, a CPU architecture
ball grid array
I C, or IIC Inter-Integrated Circuit, a communications protocol
BGA
2
I S
inter-IC sound
BOD
brown-out detect
IC
integrated circuit
BREG
BWC
CAD
backup registers
IDAC
IDE
ILO
current DAC, see also DAC, VDAC
integrated development environment
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input output subsystem
backward compatibility (eMMC data transfer mode)
computer aided design
CCO
current controlled oscillator
a stream cipher
IMO
INL
ChaCha
CM0+
CM4
Cortex-M0+, an Arm CPU
Cortex-M4, an Arm CPU
IOSS
IoT
internet of things
CMAC
cypher-based message authentication code
IPC
IRQ
ISR
ITM
JTAG
LCD
inter-processor communication
interrupt request
complementary metal-oxide-semiconductor, a
process technology for IC fabrication
CMOS
CMRR
CPU
CRC
CSD
CSV
common-mode rejection ratio
central processing unit
interrupt service routine
instrumentation trace macrocell
Joint Test Action Group
cyclic redundancy check, an error-checking protocol
CapSense Sigma-Delta
liquid crystal display
clock supervisor
Local Interconnect Network, a communications
protocol
LIN
Cypress mutual capacitance sensing method. See
also CSD
CSX
LP
low power
CTI
cross trigger interface
LS
low-speed
DAC
DAP
DDR
DES
DFT
DMA
DNL
DSI
digital-to-analog converter, see also IDAC, VDAC
debug access port
LUT
lookup table
LVD
low-voltage detect, see also LVI
low-voltage interrupt
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
double data rate
LVI
data encryption standard
design for test
LVTTL
MAC
MCU
MCWDT
MISO
MMIO
MOSI
MPU
MSL
Msps
MTB
MUL
direct memory access, see also TD
differential nonlinearity, see also INL
digital system interconnect
data unit
multi-counter watchdog timer
master-in slave-out
memory-mapped input output
master-out slave-in
memory protection unit
moisture sensitivity level
million samples per second
micro trace buffer
DU
ECC
ECC
ECO
error correcting code
elliptic curve cryptography
external crystal oscillator
electrically erasable programmable read-only
memory
EEPROM
EMI
electromagnetic interference
embedded MultiMediaCard
multiplier
eMMC
Document Number: 002-28690 Rev. *I
Page 81 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Acronym
NC
Description
Acronym
Description
silicon-oxide-nitride-oxide-silicon, a flash memory
technology
no connect
SONOS
SPI
NMI
nonmaskable interrupt
Serial Peripheral Interface, a communications
protocol
NVIC
NVL
nested vectored interrupt controller
nonvolatile latch, see also WOL
one-time programmable
over voltage protection
overvoltage tolerant
SRAM
SROM
SRSS
SWD
SWJ
static random access memory
supervisory read-only memory
system resources subsystem
serial wire debug, a test protocol
serial wire JTAG
OTP
OVP
OVT
PASS
PCB
PCM
PDM
PHY
PICU
PLL
programmable analog subsystem
printed circuit board
SWO
SWV
TCPWM
TDM
single wire output
pulse code modulation
single-wire viewer
pulse density modulation
physical layer
timer, counter, pulse-width modulator
time division multiplexed
total harmonic distortion
thin quad flat package
port interrupt control unit
phase-locked loop
THD
TQFP
TRM
PMIC
POR
PPU
PRNG
power management integrated circuit
power-on reset
technical reference manual
true random number generator
transmit
TRNG
TX
peripheral protection unit
pseudo random number generator
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
Universal Asynchronous Transmitter Receiver, a
communications protocol
®
UART
PSoC
PSRR
PWM
QD
UDB
ULP
universal digital block
ultra-low power
quadrature decoder
USB
Universal Serial Bus
watch crystal oscillator
watchdog timer
QSPI
RAM
RISC
RMS
ROM
quad serial peripheral interface
random-access memory
reduced-instruction-set computing
root-mean-square
WCO
WDT
WIC
wakeup interrupt controller
wafer level chip scale package
execute-in-place
WLCSP
XIP
read-only memory
Rivest–Shamir–Adleman, a public-key cryptography
algorithm
XRES
external reset input pin
RSA
RTC
real-time clock
RWW
RX
read-while-write
receive
S/H
sample and hold
SAR
successive approximation register
SAR ADC multiplexer bus
switched capacitor/continuous time
serial communication block
SARMUX
SC/CT
SCB
2
SCL
I C serial clock
SD
Secure Digital
2
SDA
I C serial data
SDR
Sflash
SHA
single data rate
supervisory flash
secure hash algorithm
signal to noise and distortion ratio
shared memory protection unit
signal-to-noise ratio
start of frame
SINAD
SMPU
SNR
SOF
Document Number: 002-28690 Rev. *I
Page 82 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Document Conventions
Table 54. Units of Measure (continued)
Units of Measure
Table 54. Units of Measure
Symbol
µH
Unit of Measure
microhenry
microsecond
microvolt
Symbol
°C
Unit of Measure
µs
degrees Celsius
decibel
µV
µW
mA
ms
mV
nA
ns
dB
microwatt
milliampere
millisecond
millivolt
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
khr
kilobits per second
kilohour
nanoampere
nanosecond
nanovolt
kHz
k
kilohertz
nV
W
kilo ohm
ohm
ksps
LSB
Mbps
MHz
M
Msps
µA
kilosamples per second
least significant bit
megabits per second
megahertz
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
mega-ohm
sps
sqrtHz
V
samples per second
square root of hertz
volt
megasamples per second
microampere
microfarad
µF
Document Number: 002-28690 Rev. *I
Page 83 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Errata
This section describes the errata for the CYS0644xxxI-S2D4x product line. Details include errata trigger conditions, scope of impact,
available workarounds, and silicon revision applicability. Compare this document to the device's datasheet for a complete functional
description.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
Device Characteristics
CYS0644xxxI-S2D4x
CYS0644xxxI-S2D4x Product Line
Qualification Status
Engineering Samples
Errata Summary
This table defines the errata applicability to available PSoC 6 CYS0644xxxI-S2D4x devices.
PSoC
CYS0644xxxI-S2D4x
Items
Silicon Revision
Fix Status
[1.]DMA controllers are not available
All
Production silicon Resolution planned by Q4 '22
1. DMA controllers are not available
The two 29-channel DMA controllers are not available. Register access to these controllers is not
available. The 4-channel controller is available; there are no USB or audio connections to it.
Problem Definition
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
The two 29-channel DMA controllers
Attempt to use either of the 29-channel DMA controllers, by accessing their registers
CPU exceptions are generated
Use the 4-channel controller for DMA operations
Investigation underway. Fix planned by Q3’21.
Fix Status
Document Number: 002-28690 Rev. *I
Page 84 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Revision History
Description Title: PSoC 6 MCU: CYS0644xxxI-S2D4x Datasheet
Document Number: 002-28690
Submission
Revision
ECN
Description of Change
Date
**
6710233
01/13/2020 New datasheet
Updated Features.
Updated Functional Description.
Updated SAR ADC 1 Msps references to 2 Msps.
Removed reference to e.MMC DDR mode
Updated Pinouts.
Updated Electrical Specifications.
*A
*B
6854009
6891487
04/16/2020
06/11/2020
Edited SAR Specs to split VDDA dependent specs into separate specs instead of having
qualifying comments. Also moved Supply Range specs from Description column to
Details/Conditions column.
Added SAR ADC 2 Msps supply current specs. Updated SAR ADC input impedance RC
values to support 9RC 2 Msps sampling.
Updated PSoC 6 MPN Decoder.
Updated Development Ecosystem, GPIO, and LCD sections.
Added External Crystal Oscillators.
Updated Flexible Clocking Options and Block Diagram.
Updated list of application notes and links in PSoC 6 MCU Resources.
Updated ModusToolbox Software.
Update amount of available SRAM in Features, Blocks and Functionality, Memory, Table 4,
and Ordering Information.
Updated Clocking Diagram.
Update the PSoC 64 Security section.
Updated Amazon FreeRTOS PSA.
Deleted the "Ports 9 and 10" row from Table 6. Change the # of GPIOs from 102 to 100 and
updated the block diagram to reflect this.
*C
6973720
10/09/2020 Updated Power Supply Considerations.
Updated CPUs and added InterProcessor Communication (IPC).
Updated Analog Subsystem diagram.
Update the XRES bullet in Reset, SID15 Description and Conditions, and System
Resources (Power-On-Reset specifications).
Updated SD Host Controllers and SD Host Controller and eMMC Specifications.
Updated SID7A conditions, SID7C description, and SID8 conditions.
Integrated ECO erratum into External Crystal Oscillators. Added ECO Usage Guidelines
table.
Added footnote to TMCLK_SOC specs.
Added four Errata items.
*D
*E
7052508
7147463
12/23/2020 Added Arm PSA Certification Level 2 section.
Updated Security terminology to Infineon standards.
Changed BLE references to Bluetooth LE.
Added Table 12 and Figure 19 in Electrical Specifications.
Removed SIDDS1 and SIDDS1_B and updated Typ values for SIDDS2 and SIDDS2_B.
05/28/2021
Corrected typo in Ordering Information.
Errata: Added "DMA controllers are not available" and deleted erratum "Cryptographic
SysCall API version". Deleted "Specify the FreeRTOS Version that works with this product
line" and integrated it into Amazon FreeRTOS PSA.
Updated SIDDS2 - Corrected Deep Sleep current values
08/18/2021
*F
7231613
Removed "System Deep Sleep power higher than specification" errata item.
Document Number: 002-28690 Rev. *I
Page 85 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Description Title: PSoC 6 MCU: CYS0644xxxI-S2D4x Datasheet
Document Number: 002-28690
Removed Preliminary tag from the datasheet.
Updated SIDC1 description.
11/24/2021 Updated details/conditions for SID7A.
Updated SID325U, SID328, and SID329 description.
*G
7469751
Updated Errata.
Updated MPN from CYS0644xxZI-S2D44 to CYS0644xxxI-S2D4x.
03/15/2022 Added CYS0644AFNI-S2D43T in Ordering Information.
Added 100-WLCSP package information.
*H
*I
7727645
7787179
Added device identification and revision information in Features.
Added spec SID415 and SID304P.
10/26/2022 Added footnote "Guaranteed by design, not production tested" for specs SID402 - SID412.
Updated Clock System and PLL Specifications.
Updated Protection Units.
Document Number: 002-28690 Rev. *I
Page 86 of 87
PSoC 6 MCU: CYS0644xxxI-S2D4x
Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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cypress.com/arm
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
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Community | Code Examples | Projects | Video | Blogs | Training
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Technical Support
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© Cypress Semiconductor Corporation, 2020-2022. This document is the property of Cypress Semiconductor Corporation, an Infineon Technologies company, and its affiliates ("Cypress"). This
document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates, and its directors, officers, employees, agents, distributors, and assigns
harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use
of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited
extent that (i) Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written
authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of
Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-28690 Rev. *I
Revised October 26, 2022
Page 87 of 87
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