CYW20721 [INFINEON]
The CYW20721 is a Bluetooth® 5.1-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver with Bluetooth® LE, EDR and BR. The device is intended for use in audio, IoT, sensors (medical, home, security, and so forth) and human interface device (HID) applications. Manufactured using an advanced 40 nm CMOS low-power fabrication process, the CYW20721 employs high level of integration to reduce external components, thereby minimizing application footprint and costs.;型号: | CYW20721 |
厂家: | Infineon |
描述: | The CYW20721 is a Bluetooth® 5.1-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver with Bluetooth® LE, EDR and BR. The device is intended for use in audio, IoT, sensors (medical, home, security, and so forth) and human interface device (HID) applications. Manufactured using an advanced 40 nm CMOS low-power fabrication process, the CYW20721 employs high level of integration to reduce external components, thereby minimizing application footprint and costs. |
文件: | 总47页 (文件大小:975K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CYW20721
Enhanced Low Power, Bluetooth LE
Bluetooth 5.1 SOC for Audio
CYW20721, Single-Chip Bluetooth Transceiver for Wearables and Internet of Things (IoT) Devices
The CYW20721 is a Bluetooth 5.1-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver with
Bluetooth LE, EDR and BR. The device is intended for use in audio, IoT, sensors (medical, home, security, and so forth) and human
interface device (HID) applications. Manufactured using an advanced 40nm CMOS low-power fabrication process, the CYW20721
employs high level of integration to reduce external components, thereby minimizing application footprint and costs.
This datasheet provides details of the functional, operational, and electrical characteristics of the CYW20721 device. It is intended for
hardware, design, application, and OEM engineers.
Functional Block Diagram
RF
MODEM
PKA
SHA
LCU
RX/TX
AES
96 MHz
ARM CM4
w/FPU
Patch RAM
64 KB
RAM
448 KB
ROM 2 MB
Flash 1 MB
Bluetooth 5.0
MAC
Security Engine
Patch Control
AHB Bus Matrix
Random
Number
Generator
PWM x6
ADC
Core Buck
HP- LPO
128 KHz
XTALOSC
32 KHz
Key Scan
Watchdog
Peripheral
UART
GPIO
x40
Digital
LDO
LP- LPO
32 KHz
XTALOSC
24 MHz
SPIFFY X2
(MIPI
DBI-C, SPI,
Quad SPI)
1x I2C M/S
1x I2C
master
HCI UART
HID OFF
Timer
RF LDO
Power Management
Unit
Clock Management
Hardware Peripheral Block
Cypress Semiconductor Corporation
Document Number: 002-26642 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 14, 2022
CYW20721
Features
Bluetooth Subsystem
Peripherals and Communication
■ 6x 16-bit PWMs
■ Complies with Bluetooth Core Specification v5.1 with LE 2
Mbps
■ Programmable key-scan matrix interface, up to 8x20 key-
scanning matrix1, 2
■ Supports Basic Rate (BR), Enhanced Data Rate (EDR) 2&3
Mbps, Bluetooth Low Energy
■ Watchdog timer (WDT)
■ Supports Adaptive Frequency Hopping (AFH)
■ TX power 5 dBm
■ 1x peripheral UART, 1x UART for programming and HCI
■ 2x SPI (master or slave mode) Blocks (SPI, Quad SPI, and
MIPI DBI-C)
■ 1x I2C master
■ RX sensitivity -95.5 dBm (Bluetooth LE)
■ Ultra-low-power radio
❐ RX current 5.9 mA (Bluetooth LE)
❐ TX current 5.6 mA @ 0 dBm (Bluetooth LE)
■ 1x 28-channel ADC (10-ENoB for DC measurement and 12-
ENOB for Audio measurement)
■ Hardware security engine
Coexistence Support
■ Support for Global Coexistence Interface for easy coexis-
tence implementation with select Cypress Wi-Fi devices
General Purpose Input Output (GPIO)
■ 16 GPIOs on QFN package
■ 40 GPIOs on WLCSP package
■ Support up to 3.63 V operation
MCU Subsystem
■ 96-MHz Arm® Cortex-M4 microcontroller unit MCU with float-
ing point unit (FPU)
■ Four GPIOs support 16 mA and 8 mA sink at 3.3 V and 1.8 V
respectively
■ Supports serial wire debug (SWD)
■ Runs Bluetooth stack and application
■ Option to execute from on-chip flash or RAM
Operating Voltage and Low-power Support
■ Wide operating voltage range: 1.76V to 3.63V
■ 5 power modes to implement ultra-low power application –
Memory Subsystem
■ 1 MB flash
managed by real time operating system
■ 0.4 μA current in HID-OFF2 mode (wake from GPIO).
■ 512 KB RAM
Packages
■ 2 MB ROM that stores Bluetooth stack and driver and off-
loads flash for user applications
■ 5 mm 5 mm 40-pin quad flat no-lead (QFN)
■ 3.2 mm 3.1 mm 134-ball Wafer Level Chip Scale Package
(WLCSP)
Audio Features and Interfaces
■ 1x I2S with master and slave modes
Software Support
■ 1x PCM
■ Modus Toolbox. Features are subject to support in the Blue-
■ PDM2
tooth SDK.
■ Analog front end for analog microphone1
■ Check the latest version of the Bluetooth SDK Technical brief
for supported features.
Clocks
■ On-chip 32 kHz oscillator (LP-LPO)
Applications
■ On-chip 128 kHz oscillator (HP-LPO)
■ Wearables and Fitness bands
■ Headsets, earbuds, and other audio solutions
■ Home automation
■ 32 kHz crystal oscillator (Optional if low power modes not
required)
■ 24 MHz crystal oscillator
■ Blood pressure monitors and other medical applications
■ Proximity sensors
■ 48-bit real time clock (RTC)
■ Key Fobs
■ Thermostats and thermometers
■ Toys
1. Available only in WLCSP Package.
2. Subjected to driver support in Bluetooth SDK.
Document Number: 002-26642 Rev. *F
Page 2 of 47
CYW20721
Contents
1. Bluetooth Baseband Core ...........................................4
1.1 BQB and Regulatory Testing Support ...................4
2. MCU ...............................................................................5
3. External Reset ...............................................................5
4. Power Management Unit (PMU) ..................................5
5. Integrated Radio Transceiver ......................................6
5.1 Transmitter Path ....................................................6
5.2 Receiver Path ........................................................6
5.3 Local Oscillator (LO) ..............................................6
6. Peripheral and Communication Interfaces ................7
6.1 I2C Compatible Master ..........................................7
6.2 HCI UART Interface ..............................................7
6.3 Peripheral UART Interface ....................................7
6.4 Crystal Oscillators .................................................7
6.5 Low-Frequency Clock Sources .............................9
6.6 GPIO Ports ..........................................................10
6.7 Keyboard Scanner (Available only on
8. Pin Assignments and GPIOs .....................................16
8.1 40-Pin QFN and WLCSP Pin Assignments .........16
8.2 40-Pin QFN and WLCSP GPIOs .........................18
9. Pin/Ball Maps ..............................................................23
9.1 40-Pin QFN Pin Map ...........................................23
9.2 WLCSP Ball Map ...............................................................24
10. Specifications ...........................................................28
10.1 Electrical Characteristics ...................................28
10.2 RF Specifications ..............................................32
10.3 Timing and AC Characteristics ..........................35
11. Mechanical Information ...........................................40
11.1 40-Pin QFN Package ........................................40
11.2 WLCSP Package ...............................................41
11.3 WLCSP Package Keep-out ...............................42
11.4 Tape Reel and Packaging Specifications ..........42
12. Ordering Information ................................................43
13. Acronyms ..................................................................44
14. Document Conventions ...........................................45
14.1 Units of Measure ...............................................45
15. Document History Page ...........................................46
15. Sales, Solutions, and Legal Information ................47
Worldwide Sales and Design Support .......................47
Products ....................................................................47
PSoC® Solutions ......................................................47
Cypress Developer Community .................................47
Technical Support .....................................................47
WLCSP Package) ...............................................10
6.8 ADC .....................................................................10
6.9 PWM ....................................................................11
6.10 Serial Peripheral Interface Block .......................12
6.11 Pulse Density Modulation (PDM) Microphone ...12
6.12 I2S Interface ..................................................................... 12
................................................................. 13
6.13 PCM Interface
6.14 Security Engine .................................................14
6.15 Power Modes ................................................................... 14
7. Firmware ......................................................................15
Document Number: 002-26642 Rev. *F
Page 3 of 47
CYW20721
1. Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The
BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities
including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host
controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward
error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and
data whitening/dewhitening.
Table 1. Bluetooth Features
Bluetooth 1.0
Bluetooth 1.2
Interlaced Scans
Bluetooth 2.0
Basic Rate
SCO
EDR 2 Mbps and 3 Mbps
Adaptive Frequency Hopping
eSCO
–
Paging and Inquiry
Page and Inquiry Scan
Sniff
–
–
–
–
–
Bluetooth 2.1
Bluetooth 3.0
Bluetooth 4.0
Bluetooth Low Energy
–
Secure Simple Pairing
Enhanced Inquiry Response
Sniff Subrating
Unicast Connectionless Data
Enhanced Power Control
eSCO
–
Bluetooth 4.1
Bluetooth 4.2
Bluetooth 5.0
LE 2 Mbps
Low Duty Cycle Advertising
Dual Mode
Data Packet Length Extension
LE Secure Connection
Link Layer Privacy
Slot Availability Mask
High Duty Cycle Advertising
LE Link Layer Topology
1.1 BQB and Regulatory Testing Support
The CYW20721 fully supports Bluetooth Test mode as described in Part 1:1 of the Specification of the Bluetooth System v3.0. This
includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYW20721 also supports enhanced testing features to simplify RF debugging
and qualification and type-approval testing. These features include:
■ Fixed frequency carrier wave (unmodulated) transmission
❐ Simplifies some type-approval measurements (Japan)
❐ Aids in transmitter performance analysis
■ Fixed frequency constant receiver mode
❐ Receiver output directed to I/O pin
❐ Allows for direct BER measurements using standard RF test equipment
❐ Facilitates spurious emissions testing for receive mode
■ Fixed frequency constant transmission
❐ 8-bit fixed pattern or PRBS-9
❐ Enables modulated signal measurements with standard RF test equipment
Document Number: 002-26642 Rev. *F
Page 4 of 47
CYW20721
2. MCU
The CYW20721 includes a Cortex M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip
flash. The CM4 has a maximum speed of 96 MHz. CYW20721 supports execution from on-chip flash (OCF).
The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU).
The CM4 runs all the Bluetooth layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stack
layers freeing up the flash for application usage. A standard SWD Interface provides debugging support.
3. External Reset
An external active-low reset signal, RESET_N, can be used to put the CYW20721 in the reset state. The RESET_N should be released
only after the VDDO supply voltage level has been stabilized for at least 35 ms.
4. Power Management Unit (PMU)
Figure 1 shows the CYW20721 PMU block diagram. The CYW20721 includes an integrated buck regulator, a bypass LDO, a capless
LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once Vbat supply falls
below 2.1 V.
The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.
Figure 1. Default Usage Mode
PMU
VBAT: 1.76V to 3.63V
SR_VDDBAT3V
DIGLDO_
VDDOUT
DIGLDO_VDDIN
SR_VLX
Digital LDO
VBAT
Core Buck
Regulator
Bluetooth Digital
SR_
PVSS
Internal LDO (capless)
CBUCK
Bluetooth Retention
Memory
Maximum 50 mA
RFLDO_
VDDOUT
BYPLDO
50 mA
RF LDO
Bluetooth RF
RFLDO_VDDIN
Denotes board pin
Denotes chip pin
Denotes power switch
Document Number: 002-26642 Rev. *F
Page 5 of 47
CYW20721
5. Integrated Radio Transceiver
The CYW20721 has an integrated radio transceiver that has been designed to provide low power operation in the globally available
2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and exceeds the requirements to provide
the highest communication link quality of service.
5.1 Transmitter Path
The CYW20721 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
Power Amplifier
The CYW20721 has an integrated power amplifier (PA) that can transmit up to +5 dBm.
5.2 Receiver Path
The receiver path uses a low IF scheme to down-convert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in
the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYW20721 to be used
in most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20721 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
5.3 Local Oscillator (LO)
LO provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels for BR/EDR functionality. The
CYW20721 uses an internal loop filter.
Document Number: 002-26642 Rev. *F
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CYW20721
6. Peripheral and Communication Interfaces
2
6.1 I C Compatible Master
The CYW20721 provides a 2-pin I2C compatible Master interface to communicate with I2C compatible peripherals. The I2C compatible
master supports the following clock speeds:
■ 100 kHz
■ 400 kHz
■ 800 kHz (Not a standard I2C-compatible speed.)
■ 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA
the GPIOs go into open drain mode and require an external pull-up for proper operation. I2C block does not support multi master
capability by either master/slave devices.
6.2 HCI UART Interface
The CYW20721 includes a UART interface for factory programming as well as when operating as a Bluetooth HCI device in a system
with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates
from 115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available.
Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The
CYW20721 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.
The UART interface has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface
supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
During HCI mode the DEV_WAKE signal can be programmed to wake up the CYW20721 or allow the CYW20721 to sleep when radio
activities permit. The CYW20721 can also wake up the host as needed or allow the host to sleep via the HOST_WAKE signal. The
combined two signals allow the host and the CYW20721 to optimize system power consumption by allowing independent control of
low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor specific command.
6.3 Peripheral UART Interface
The CYW20721 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the
optional I/O ports, which can be configured individually and separately for each functional pin. The CYW20721 can map the peripheral
UART to any GPIO (P0-P39). The Peripheral UART is functionally the same as HCI UART but with a 256 byte transmit and receive
FIFO.
6.4 Crystal Oscillators
6.4.1 24-MHz Crystal Oscillator
The CYW20721 uses a 24 MHz crystal oscillator (XTAL). The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth
specification. Two external load capacitors are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-
dependent (see Figure 2).
Figure 2. Recommended 24 MHz Oscillator Configuration
CL1
XIN
Crystal
XOUT
CL2
Document Number: 002-26642 Rev. *F
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CYW20721
Table 2. Reference Crystal Electrical Specifications
Parameter Conditions
Nominal frequency
Min.
Typ.
Max.
Unit
MHz
–
–
–
–
24.000
–
Oscillation mode
Fundamental
Includes operating temperature
range and aging
Frequency accuracy
–
–
± 20
ppm
Equivalent series resistance
Load capacitance
Drive level
–
–
–
–
–
–
–
–
–
8
–
–
60
–
Ω
pF
μW
pF
200
2
Shunt capacitance
6.4.2 32 kHz Crystal Oscillator
The CYW20721includes a 32 kHz oscillator to provide accurate timing during low power operations. Figure 3 shows the 32 kHz XTAL
oscillator with external components and Table 3 lists the oscillator’s characteristics. This oscillator can be operated with 32.768 kHz
crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 MΩ and C1 = C2 =
~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Figure 3. Recommended 32 kHz Oscillator Electrical Specification
C2
32.768 kHz
R1
XTAL
C1
Table 3. Reference 32 kHz Oscillator Electrical Specification
Parameter
Output frequency
Symbol
Foscout
–
Conditions
Min.
Typ.
32.768
100
500
–
Max.
–
Unit
kHz
ppm
ms
–
–
–
–
–
–
–
Frequency tolerance
Start-up time
Crystal-dependent
–
–
Tstartup
Pdrv
–
XTAL drive level
For crystal selection
For crystal selection
For crystal selection
0.5
70
2.2
μW
kΩ
XTAL series resistance
XTAL shunt capacitance
Rseries
Cshunt
–
–
pF
C
R
couple = 100 pF;
bias= 10 MΩ
External AC input amplitude
VIN (AC)
400
–
–
mVpp
Document Number: 002-26642 Rev. *F
Page 8 of 47
CYW20721
6.5 Low-Frequency Clock Sources
The 32-kHz low-frequency clock (lhl_lpo_32-kHz on the following figure) can be obtained from multiple sources. There are two internal
low-power oscillators (LPOs) called the LP-LPO and HP-LPO and external crystal (OSC32K). The firmware determines the clock
source to use among the available LPOs depending on the accuracy and power requirements. The preferred source is the external
LPO (OSC32K) because it has good accuracy with the lowest current consumption. Internal LP-LPO has low current consumption
and low accuracy whereas HP-LPO has higher accuracy and higher current consumption. The firmware assumes the external LPO
has less than 250 PPM error with little or no jitter.
Figure 4. Simplified Clock Source
Variable
Frequency
48/96
M
DIV
HCLK
CPU
DIV
Fixed
Frequency
Block
1 M
Timers
XTAL 24M
ADPLL
96 M
SPI2
SPI1
PUART
HCI UART
I2C
48 M
24 M
DIV
PTU
ADC
(12 M)
24 M
DIV
1 M
24 M
ACLK0
24 M
ACLK1
PWM(0‐5)
OSC32K
HP‐LPO
LP‐LPO
LPO
lhl_lpo
32 K
LHL
RTC
LPO
LPO
Document Number: 002-26642 Rev. *F
Page 9 of 47
CYW20721
6.6 GPIO Ports
The CYW20721 has 40 GPIOs labeled P0-P39 on WLCSP package and 16 GPIOs on QFN package.
All GPIOs support the following:
■ programmable pull-up/down of approx 45 k.
■ input disable, allowing pins to be left floating or analog signals connected without risk of leakage.
■ source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.
■ P15 is Bonded to the same pin as XTALI_32K on the QFN package (Pin 32). If External 32.768kHz crystal is not used, then this
pin can be used as GPIO P15.
■ P26/P27/P28/P29 (some of these pins are not available on QFN package) sink/source 16 mA at 3.3 V and 8 mA at 1.8 V.
Most peripheral functions can be assigned to any GPIO. For details, refer to Table 4 and Table 5.
6.7 Keyboard Scanner (Available only on WLCSP Package)
The CYW20721 includes a HW keyscanner that supports a maximum matrix size of 20x8. The scanner has 8 inputs (also referred to
as rows) and 20 outputs (also referred to as columns). Keys are detected by driving the columns down sequentially and sampling the
rows. The HW scanner includes support for ghost key detection and debouncing. The scanner can also operate in sleep and PDS
mode allowing low power operation while continuing to detect/store all key strokes, up or down. In other low power modes, the scanner
can continue to monitor the matrix and initiate exit to active mode upon detecting a change of state.
Note Subject to the driver support in Bluetooth SDK.
6.8 ADC
CYW20721includes is a Σ-Δ ADC designed for audio (13 bits) and DC (10 bits) measurements. The ADC can measure the voltage
on 28 GPIO. When used for analog inputs, the GPIOs must be placed in digital input disable mode to disconnect the digital circuit
from the pin and avoid leakage. The internal band gap reference has ±5% accuracy without calibration. Calibration and digital
correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode.
■ P0, P1, P8-P18, P21-23, P28-P38 can be used as ADC inputs.
Document Number: 002-26642 Rev. *F
Page 10 of 47
CYW20721
6.9 PWM
The CYW20721 has six internal PWMs, labeled PWM0-5
■ Each of the six PWM channels contains the following registers:
❐ 16-bit initial value register (read/write)
❐ 16-bit toggle register (read/write)
❐ 16-bit PWM counter value register (read)
■ PWM configuration register is shared among PWM0–5 (read/write). This 6-bit register is used:
❐ To enable/disable each PWM channel
❐ To select the clock of each PWM channel
❐ To invert the output phase of each PWM channel
The application can access the PWM module through the FW driver.
Figure 5 shows the structure of one PWM channel.
Figure 5. PWM Block Diagram
pwm_cfg_adr register
pwm#_init_val_adr register
pwm#_togg_val_adr register
16
16
pwm#_cntr_adr
16
cntr value is ARM readable
pwm_out
Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)
PWM cntr w/ pwm#_init_val = x (solid line)
16'HFFFF
pwm_togg_val_adr
16'Hx
16'H000
pwm#_init
_value is x
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CYW20721
6.10 Serial Peripheral Interface Block
The CYW20721 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well
as MIPI DBI-C Interface. Either of the interface can be a master/slave. SPI2 can support only one slave. SPI1 has a 1024 byte transmit
and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and receive buffers. To
support more flexibility for user applications, the CYW20721 has optional I/O ports that can be configured individually and separately
for each functional pin. SPI I/O voltage depends on VDDO.
6.10.1 MIPI interface
There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYW20721 plays the role of host, and only
the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins
are used. In the 8-bit mode, an additional pin DCX, indicating whether the current outgoing bit stream is a command or data byte is
required.
6.11 Pulse Density Modulation (PDM) Microphone
The CYW20721 accepts a ΣΔ-based one-bit PDM input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates.
The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input
shares the filter path with the aux ADC. Two types of data rates can be supported:
■ 8 kHz
■ 16 kHz
The external digital microphone takes in a 2.4 MHz clock generated by the CYW20721 and outputs a PDM signal which is registered
by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The
design can accommodate two simultaneous PDM input channels, so stereo voice is possible.
Note Subject to the driver support in Bluetooth SDK.
2
6.12 I S Interface
The CYW20721 supports a single I2S digital audio port in both master and slave modes. The I2S signals are:
■ I2S Clock: I2S SCK
■ I2S Word Select: I2S WS
■ I2S Data Out: I2S DO
■ I2S Data In: I2S DI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output and I2S DI
stays as input. The channel word length is fixed to 16 bits (frame length of 32 bits) and the data is justified so that the MSB of the left-
channel data is aligned with the MSB of the I2S bus, as per I2S Specifications. The MSB of each data word is transmitted one bit clock
cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I2S WS is low,
and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW20721 are synchronized with the falling edge
of I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK.
The I2S port is primarily used to transfer audio samples while using the A2DP profile[1]. The A2DP controller is half duplex and the
direction of the audio samples depend on the A2DP role (sink/source). The I2S clock in the master mode can either be
■ 44.1 kHz x 32 bits per frame = 1411.2 kHz
■ 48 kHz x 32 bits per frame = 1536 kHz
In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz.
Note PCM interface shares HW with the I2S interface which means that both voice and audio cannot be routed at the same time.
Note
2
1. The I S port cannot be used at the application level for purposes other than routing A2DP audio samples.
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CYW20721
6.13 PCM Interface
The CYW20721 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode,
the CYW20721 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another device on
the PCM interface and are inputs to the CYW20721. Some of the parameters of the PCM interface may be configured by the host.
The PCM interface is used for full-duplex bi-directional transfer of 8K or 16K voice samples from and to a SCO or eSCO connection[2]
.
By default, the PCM interface runs in an I2S compatible mode, which allows the CYW20721 to transfer voice samples to I2S devices.
Note PCM interface shares HW with the I2S interface which means that both voice and audio cannot be routed simultaneously.
6.13.1 Slot Mapping
The CYW20721 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface, when operating
in HCI mode. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8
kHz or 16 kHz voice sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface
rate (128 kHz, 256kHz, 512 kHz, 1024 kHz or 2048 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and
16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output
driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver
tristates its output after the falling edge of the PCM clock during the last bit of the slot.
6.13.2 Frame Synchronization
The CYW20721 supports both short and long-frame synchronization in both master and slave modes and can be configured from the
host. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a
single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of
the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode,
the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and
the pulse starts coincident with the first bit of the first slot.
6.13.3 Data Formatting
The CYW20721 may be configured to generate or accept several different data formats. For conventional narrow band speech mode,
the CYW20721 always uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support
various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit,
or a programmed value on the output. The default format is 13-bit 2's complement data, left justified, filled with 0's and clocked MSB
first.
6.13.4 Burst PCM Mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and
save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with
an HCI command from the host.
Note
2. The PCM interface cannot be used as a generic serial interface at the application level. It can only be used for routing SCO or eSCO voice samples.
Document Number: 002-26642 Rev. *F
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CYW20721
6.14 Security Engine
The CYW20721 includes a hardware security accelerator which greatly decreases the time required to perform typical security
operations.This security engine includes:
■ Public key acceleration (PKA) cryptography
■ AES-CTR/CBC-MAC/CCM acceleration
■ SHA2 message hash and HMAC acceleration
■ RSA encryption and decryption of modulus sizes up to 2048 bits
■ Elliptic curve Diffie-Hellman in prime field GF(p)
Note Security engine is used only by Bluetooth stack to reduce CPU overhead. It is not available for application use
6.14.1 Random Number Generator
This hardware block is used for key generation for Bluetooth.
Note Availability for use by the application is subject to the support in Bluetooth SDK.
6.15 Power Modes
The CYW20721 supports the following HW power modes:
■ Active mode - Normal operating mode in which all peripherals are available and the CPU is active.
■ Idle mode- In this mode, the CPU is in “Wait for Interrupt” (WFI) and the HCLK, which is the high frequency clock derived from the
main crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained.
■ Sleep mode - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off
and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU),
and SRAM is retained.
■ Power Down Sleep (PDS) mode -This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and
SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused.
■ Shut Down Sleep (SDS) mode -Everything is turned off except I/O Power Domain, RTC, and LPO. The device can come out of
this mode either due to Bluetooth activity or by an external interrupt. Before going into this mode, the application can store some
bytes of data into “Always On RAM” (AON). When the device comes out of this mode, the data from AON is restored. After waking
from SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON.
In the SDS mode, a single Bluetooth task with no data activity, such as an ACL connection, Bluetooth LE connection, or Bluetooth
LE advertisement can be performed.
■ HID-OFF[3] (Timed-Wake) mode -The device can enter this mode asynchronously, that is, the application can force the device into
this mode at any time. I/O Power Domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wake
the device up after a predetermined fixed time.
■ HID-OFF[3] (External Interrupt-Waked) mode - This mode is similar to Timed-Wake, but in HID-OFF mode even the LPO and RTC
are turned off. Therefore, the only wakeup source is an external interrupt.
Transition between power modes is handled by the on-chip firmware with host/application involvement. Please see Firmware Section
for details.
Note
3. Subject to driver support in Bluetooth SDK.
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CYW20721
7. Firmware
The CYW20721 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip
hardware functions as well as the Bluetooth/LE baseband, Link Manager (LM), HCI, Generic Attribute Profile (GATT), Attribute
Protocol (ATT), Logical Link Control and Adaptation Protocol (L2CAP) and Service Discovery Protocol (SDP) layers. The ROM also
includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between
different power modes.
The CYW20721 is fully supported by the Cypress Modus Toolbox platform. Bluetooth SDK releases provide latest ROM patches,
drivers, and sample applications allowing customized applications using the CYW20721 to be built quickly and efficiently.
Refer to CYW20721 Product Guide for details on the firmware architecture, driver documentation, power modes and how to write
applications/profiles using the CYW20721.
Document Number: 002-26642 Rev. *F
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CYW20721
8. Pin Assignments and GPIOs
This section addresses both QFN and WLCSP pin assignments and GPIOs for the CYW20721 device.
8.1 40-Pin QFN and WLCSP Pin Assignments
Table 4. 40-Pin QFN and WLCSP Pin Assignments
Pin Number
Pin Name
I/O
Power Domain
Description
QFN-40
WLCSP
Microphone
ADC_avddBAT
ADC_AVDDC
Mic_avdd
–
–
–
–
–
–
–
–
–
–
5
I
I
I
I
I
I
I
I
I
I
VDDIO
–
VDDIO
3
No Connect
19
32
4
MIC_AVDD
MIC_AVDD
MIC_AVDD
MIC_AVDD
AVSS
Microphone supply
Micbias
Microphone Bias Supply
Microphone negative input
Microphone positive input
Analog ground
Micn
Micp
18
34
17
33
47
ADC_AVSS
ADC_AVSSC
ADC_REFGND
Mic_avss
AVSS
Analog ground
AVSS
Analog reference ground
Microphone analog ground
AVSS
Baseband Supply
1,8,9,11,14,26,29,4
2,56,66,91
BT_VDDO
BT_VDDC
VDDO
25
–
I
I/O
I
VDDO
VDDC
VDDO
I/O Pad Power supply
2,43,58,74,
99
Baseband core power supply
LHL PAD power supply. Can be tied to
BT_VDDO.
39
-
RF Power Supply
BT_PAVDD
17
21
20
19
116
106
125
110
I
I
I
I
PAVDD
PA supply
BT_PLLVDD1p2
BT_VCOVDD1p2
BT_IFVDD1P2
Onboard LDO’s
DIGLDO_VDDIN
DIGLDO_VDDOUT
RFLDO_VDDIN
RFLDO_VDDOUT
SR_VDDBAT3V
VDDBAT3V
PLLVDD1P2 RFPLL and crystal oscillator supply
VCOVDD1P2 VCO supply
IFVDD1P2
IFPLL Power Supply
16
–
127
126
111
128
129
120
I
O
I
Internal Digital LDO input
Internal Digital LDO output
RF LDO Input
15
14
13
–
–
–
–
–
O
I
RF LDO Output
Core Buck Input
I
Core Buck Input
Core Buck Output
SR_VLX
12
121
O
–
Ground Pins
BT_PAVSS
BT_PLLVSS
BT_VCOVSS
BT_IFVSS
–
–
–
–
123
107
119
115
I
I
I
I
VSS
VSS
VSS
VSS
Ground
Ground
Ground
Ground
30, 57, 75, 87, 117,
118, 124, 133, 134
BT_VSSC
–
I
VSS
Ground
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CYW20721
Table 4. 40-Pin QFN and WLCSP Pin Assignments (Cont.)
Pin Number
Pin Name
I/O
Power Domain
Description
QFN-40
WLCSP
VSSC
–
112
I
I
VSS
VSS
VSS
Ground
Ground
Ground
10,13, 25, 28,72,
96,101
VSSO_0
–
SR_PVSS
xtal_avss
PMU_AVSS
VSS
–
–
130
35
I
I
I
I
XTAL_AVSS Crystal ground
PMU_AVSS PMU ground
–
113,114
–
H
VSS
Exposed center pad, connect to ground.
UART
Clear to send (CTS) for HCI UART
interface. Leave unconnected if not
used.
BT_UART_CTS_N
30
29
15
31
I, PU
VDDO
VDDO
Request to send (RTS) for HCI UART
interface. Leave unconnected if not
used.
BT_UART_RTS_N
BT_UART_RXD
O, PU
UART serial input. Serial data input for
the HCI UART interface.
27
28
45
46
I
VDDO
VDDO
UART serial output. Serial data output
for the HCI UART interface.
BT_UART_TXD
O, PU
Crystal
Crystal oscillator input. See “The XTAL
must have an accuracy of ±20 ppm as
defined by the Bluetooth specification.
Two external load capacitors are
required to work with the crystal oscil-
lator. The selection of the load capac-
itors is XTAL-dependent (see Figure 2)”
for options.
BT_XTALI
22
105
I
PLLVDD1P2
BT_XTALO
XTALI_32K
XTALO_32K
BT_RF
23
32
31
18
–
104
6
O
I
PLLVDD1P2 Crystal oscillator output.
VDDO
VDDO
–
Low-power oscillator input.
Low-power oscillator output.
RF Antenna Port
20
O
–
132
68
BT_CLK_REQ
O
N/A
Used for shared-clock application.
Reserved Arm® JTAG debug mode
control. Connect to GND for all applica-
tions.
JTAG_SEL
11
10
102
103
–
I
–
Active-low system reset with internal
pull-up resistor.
RST_N
VDDO
Reserved Pins
Reserved
21, 36, 49, 61, 77,
84, 85, 108
26
–
N/A
N/A
N/A
N/A
Reserved. Leave unconnected.
Reserved, connect to GND
Reserved, Connect to
GND
16, 92
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CYW20721
8.2 40-Pin QFN and WLCSP GPIOs
Table 5. 40-Pin QFN and WLCSP GPIOs
Pin Number
Pin Name
Power
Domain
I/O
Description
QFN-40
WLCSP
A signal from the host to the CYW20721 indicating that
the host requires attention.
BT_DEV_WAKE
BT_HOST_WAKE
–
86
76
I
VDDO
VDDO
A signal from the CYW20721 device to the host
indicating that the Bluetooth device requires attention.
24
O
BT_GPIO_2
BT_GPIO_3
BT_GPIO_4
BT_GPIO_5
–
–
–
–
44
59
79
78
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
GPIO: Can also be configured as a GCI Pin
GPIO: Can also be configured as a GCI Pin
GPIO: Can also be configured as a GCI Pin
GPIO: Can also be configured as a GCI Pin
■ GPIO: P0
■ Keyboard scan input (row): KSI0
■ A/D converter input 29
■ Supermux I/O functions as defined in Table 6.
P0
P1
3
4
93
54
I/O
I/O
VDDO
VDDO
■ GPIO: P1
■ Keyboard scan input (row): KSI1
■ A/D converter input 28
■ Supermux I/O functions as defined in Table 6
■ GPIO: P2
P2
P3
P4
P5
P6
P7
P8
34
–
60
22
23
37
50
62
69
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
■ Keyboard scan input (row): KSI2
■ Supermux I/O functions as defined in Table 6
■ GPIO: P3
■ Keyboard scan input (row): KSI3
■ Supermux I/O functions as defined in Table 6
■ GPIO: P4
■ Keyboard scan input (row): KSI4
■ Supermux I/O functions as defined in Table 6
35
–
■ GPIO: P5
■ Keyboard scan input (row): KSI5
■ Supermux I/O functions as defined in Table 6
■ GPIO: P6
■ Keyboard scan input (row): KSI6
■ Supermux I/O functions as defined in Table 6
36
37
–
■ GPIO: P7
■ Keyboard scan input (row): KSI7
■ Supermux I/O functions as defined in Table 6
■ GPIO: P8
■ A/D converter input 27
■ Supermux I/O functions as defined in Table 6
■ GPIO: P9
■ A/D converter input 26
■ External T/R switch control: tx_pd
■ Supermux I/O functions as defined in Table 6
P9
–
52
63
I/O
I/O
VDDO
VDDO
■ GPIO: P10
■ Keyboard scan output (column): KSO2
■ A/D converter input 25
P10
40
■ Supermux I/O functions as defined in Table 6
Notes
4. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.
5. During power-on reset, all inputs are disabled.
6. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow
through these pins until the part comes out of reset.
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CYW20721
Table 5. 40-Pin QFN and WLCSP GPIOs (Cont.)
Pin Number
Pin Name
Power
Domain
I/O
Description
QFN-40
WLCSP
■ GPIO: P11
■ A/D converter input 24
■ Supermux I/O functions as defined in Table 6
P11
P12
P13
P14
P15
P16
P17
P18
–
70
I/O
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
■ GPIO: P12
■ A/D converter input 23
■ Supermux I/O functions as defined in Table 6
–
–
40
71
24
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
■ GPIO: P13
■ A/D converter input 22
■ Supermux I/O functions as defined in Table 6
■ GPIO: P14
■ A/D converter input 21
■ Supermux I/O functions as defined in Table 6
–
■ GPIO: P15
■ A/D converter input 20
■ Supermux I/O functions as defined in Table 6
c
32
33
38
–
■ GPIO: P16
■ A/D converter input 19
■ Supermux I/O functions as defined in Table 6
48
38
51
■ GPIO: P17
■ A/D converter input 18
■ Supermux I/O functions as defined in Table 6
■ GPIO: P18
■ A/D converter input 17
■ Supermux I/O functions as defined in Table 6
P19
P20
–
–
39
12
I/O
I/O
VDDO
VDDO
■ Reserved for system use. Leave unconnected.
■ Reserved for system use. Leave unconnected.
■ GPIO: P21
P21
P22
P23
–
–
–
53
27
64
I/O
I/O
I/O
VDDO
VDDO
VDDO
■ A/D converter input 14
■ Supermux I/O functions as defined in Table 6
■ GPIO: P22
■ A/D converter input 13
■ Supermux I/O functions as defined in Table 6
■ GPIO: P23
■ A/D converter input 12
■ Supermux I/O functions as defined in Table 6
■ GPIO: P24
■ Supermux I/O functions as defined in Table 6
P24
P25
–
8
90
97
I/O
I/O
VDDO
VDDO
■ GPIO: P25
■ Supermux I/O functions as defined in Table 6
■ GPIO: P26
P26
P27
7
–
83
94
I/O
I/O
VDDO
VDDO
■ Current: 16 mA sink
■ Supermux I/O functions as defined in Table 6
■ GPIO: P27
■ Current: 16 mA sink
■ Supermux I/O functions as defined in Table 6
■ GPIO: P28
■ A/D converter input 11
■ Current: 16 mA sink
P28
1
41
I/O
VDDO
■ Supermux I/O functions as defined in Table 6
Notes
4. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.
5. During power-on reset, all inputs are disabled.
6. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow
through these pins until the part comes out of reset.
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CYW20721
Table 5. 40-Pin QFN and WLCSP GPIOs (Cont.)
Pin Number
Pin Name
Power
Domain
I/O
Description
QFN-40
WLCSP
■ GPIO: P29
■ A/D converter input 10
■ Current: 16 mA sink
2
P29
80
I/O
VDDO
■ Supermux I/O functions as defined in Table 6
■ GPIO: P30
P30
P31
P32
P33
P34
P35
P36
P37
–
–
–
9
5
–
–
–
95
73
98
100
81
65
55
88
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
■ A/D converter input 9
■ Supermux I/O functions as defined in Table 6
■ GPIO: P31
■ A/D converter input 8
■ Supermux I/O functions as defined in Table 6
■ GPIO: P32
■ A/D converter input 7
■ Supermux I/O functions as defined in Table 6
■ GPIO: P33
■ A/D converter input 6
■ Supermux I/O functions as defined in Table 6
■ GPIO: P34
■ A/D converter input 5
■ Supermux I/O functions as defined in Table 6
■ GPIO: P35
■ A/D converter input 4
■ Supermux I/O functions as defined in Table 6
■ GPIO: P36
■ A/D converter input 3
■ Supermux I/O functions as defined in Table 6
■ GPIO: P37
■ A/D converter input 2
[6]
■ Supermux I/O functions as defined in Table 6
■ GPIO: P38
P38
P39
6
–
89
82
I/O
I/O
VDDO
VDDO
■ A/D converter input 1
■ Supermux I/O functions as defined in Table 6
■ Reserved for system use. Leave unconnected.
Strapping Pins
Device test mode control. Connect to GND for all appli-
cations.
BT_TM1
–
–
67
I
I
–
PMU_DISABLE
109
VDDO
PMU Enable/Disable. Connected to ground.
Notes
4. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.
5. During power-on reset, all inputs are disabled.
6. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow
through these pins until the part comes out of reset.
Document Number: 002-26642 Rev. *F
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CYW20721
Table 6. GPIO Supermux Input Functions
Input Description
SWDCK
Table 7. GPIO Supermux Output Functions
Output
Description
Serial Wire Debugger Clock
Serial Wire Debugger I/O
SPIFFY 1 Clock (Slave)
do_P# (data out of GPIO. For example: 0)
SWDIO
kso0
Key Scan output 0
Key Scan output 1
spiffy1_clk[s]
spiffy1_cs[s]
kso1
SPIFFY 1 Chip Select (Slave)
kso2
Key Scan output 2
Key Scan output 3
Key Scan output 4
Key Scan output 5
Key Scan output 6
Key Scan output 7
Key Scan output 8
Key Scan output 9
Key Scan output 10
Key Scan output 11
Key Scan output 12
Key Scan output 13
Key Scan output 14
Key Scan output 15
Key Scan output 16
Key Scan output 17
Key Scan output 18
Key Scan output 19
PWM Channel 0
spiffy1_mosi[s] SPIFFY 1 MOSI (Slave)
spiffy1_miso[m] SPIFFY 1 MISO (Master)
kso3
kso4
spiffy1_io2
SPIFFY 1 I/O 2 (Quad SPI)
SPIFFY 1 I/O 3 (Quad SPI)
SPIFFY 1 Interrupt (Slave)
SPIFFY 2 Clock (Slave)
kso5
spiffy1_io3
kso6
spiffy1_int[s]
spiffy2_clk[s]
spiffy2_cs[s]
kso7
kso8
SPIFFY 2 Chip Select (Slave)
kso9
spiffy2_mosi[s] SPIFFY 2 MOSI (Slave)
spiffy2_miso[m] SPIFFY 2 MISO (Master)
kso10
kso11
spiffy2_io2
spiffy2_io3
spiffy2_int[s]
puart_rx
SPIFFY 2 I/O 2
SPIFFY 2 I/O 3
SPIFFY 2 Interrupt (Slave)
Peripheral UART RX
Peripheral UART CTS
I2C Clock
kso12
kso13
kso14
kso15
puart_cts_n
SCL
kso16
kso17
SDA
I2C Data
kso18
PCM_IN
PCM_CLK
PCM_SYNC
I2S_DI
PCM Input
kso19
PCM Clock
do_P# ^ pwm0
do_P# ^ pwm1
do_P# ^ pwm2
do_P# ^ pwm3
do_P# ^ pwm4
do_P# ^ pwm5
aclk0
PCM Sync
PWM Channel 1
I2S Data Input
I2S Word Select
I2S Clock
PWM Channel 2
I2S_WS
PWM Channel 3
I2S_CLK
PWM Channel 4
PDM_IN_Ch_1 PDM Input Channel 1
PDM_IN_Ch 2 PDM Input Channel 2
PWM Channel 5
Auxiliary clock Output 0
Auxiliary clock Output 1
HID-OFF Indicator
External PA ramp
aclk1
HID_OFF
pa_ramp
tx_pu
External PA Control Signal
External PA Control Signal
rx_pu
Serial Wire Debugger Input/
Output
SWDIO
puart_tx (uart2_tx)
puart_rts_n (uart2_rts_n)
spiffy1_CLK
Peripheral UART TX
Peripheral UART RTS
SPIFFY 1 Clock
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Page 21 of 47
CYW20721
Table 7. GPIO Supermux Output Functions (Cont.)
Output
spiffy1_CS
Description
SPIFFY 1 Chip Select
SPIFFY 1 MOSI
SPIFFY 1 MISO
SPIFFY I/O 2
spiffy1_MOSI
spiffy1_MISO
spiffy1_IO2
spiffy1_IO3
spiffy1_INT
SPIFFY I/O 3
SPIFFY Interrupt
MIPI-DBI Data/Command
Indicator
spiffy1_DCX
spiffy2_CLK
spiffy2_CS
SPIFFY 2 Clock
SPIFFY 2 Chip Select
SPIFFY 2 MOSI
SPIFFY 2 MISO
SPIFFY 2 I/O 2
spiffy2_MOSI
spiffy2_MISO
spiffy2_IO2
spiffy2_IO3
spiffy2_INT
SPIFFY 2 I/O 3
SPIFFY 2 Interrupt
MIPI-DBI Data/Command
Indicator
spiffy2_DCX
pcm_in_o
pcm_out_o
pcm_bclk_o
pcm_sync_o
i2s_ssd
PCM IN
PCM Out
PCM Bit Clock
PCM Sync Output
I2S Slave Serial Data
I2S Slave Word Select
I2S Slave Clock
I2S Master Serial Data
I2S Master Word Select
I2S Master Clock
i2s_sws
i2s_sck
i2s_msd
i2s_mws
i2s_mck
Document Number: 002-26642 Rev. *F
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CYW20721
9. Pin/Ball Maps
9.1 40-Pin QFN Pin Map
The CYW20721 40-pin QFN package is shown in Figure 6.
Figure 6. 40-Pin QFN Pin Map
40
39
38
37
36
35
34
33
32
31
xtali_32k/
P15
P10
P17
LHL_VDDO
P7
P6
P4
P2
P16
xtalo_32K
UART_
CTS_N
P28
P29
P0
1
2
30
29
28
27
26
25
24
23
22
21
UART_
RTS_N
3
UART_TXD
UART_RXD
P1
4
CYW20721 5x5 QFN-40
P34
P38
P26
5
RSVD
6
BT_VDDO
HOST_
WAKE
7
P25
8
XTALO
P33
9
XTAL1
RST_N
10
PLLVDD1p2
SR_
VDDBAT3V
RFLDO_
VDDOOUT
RFLDO_
VDDIN
DIGLDO_
VDDIN
BT_RF
18
IFVDD1p2 VCOVDD1p2
SR_VLX
12
PAVDD
17
JTAG_SEL
11
13
14
15
16
19
20
Document Number: 002-26642 Rev. *F
Page 23 of 47
CYW20721
9.2 WLCSP Ball Map
The CYW20721 WLCSP package is shown in Figure 7.
Figure 7. WLCSP Ball Map
14
28
42
55
66
73
83
91
98
103
13
27
41
54
65
72
82
90
97
102
12
26
40
53
64
71
81
89
96
101
11
25
39
52
63
70
80
88
95
100
10
24
38
51
9
8
7
6
5
4
3
2
1
23
37
50
62
69
22
36
49
61
21
35
48
60
20
34
19
33
47
18
32
46
59
17
31
45
58
16
30
44
57
68
77
86
15
29
43
56
67
76
85
74
79
78
87
75
84
92
94
93
99
105
104
106
107
109
108
113
120
129
110
114
122
131
112
128
111
127
115
116
118
117
123
119
125
121
130
124
126
132
134
133
Notes
7. Figure 7 shows the bottom view of the WLCSP package (Bumps facing up).
8. See Table 4 and Table 8 and for additional WLCSP information.
9. Table 8 shows the package view from the bottom (bumps facing up).
10. Coordinate origin (0, 0) is at the center of the WLCSP package with the bumps facing up.
Document Number: 002-26642 Rev. *F
Page 24 of 47
CYW20721
Table 8. CYW20721 WLCSP Bump Coordinates
Bump#
1
NET_NAME
X-COORD (μm)
1232.28
1032.28
832.28
632.28
432.28
232.29
32.29
Y-COORD (μm)
BT_VDDO
BT_VDDC
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1356.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
1156.88
956.88
2
3
Reserved - Do not connect
Micn
4
5
ADC_avddBAT
xtali_32K
P15
6
7
8
VDDO_0
VDDO_0
VSSO_0
-167.7
9
-367.7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
-567.7
VDDO_0
P20
-767.7
-967.69
-1167.69
-1367.69
1232.28
1032.28
832.28
632.28
432.28
232.29
32.29
VSSO_0
VDDO_0
BT_UART_CTS_N
Reserved, Connect to GND
ADC_AVSSC
Micp
Mic_avdd
xtalo_32K
Reserved
P3
-167.7
P4
-367.7
P14
-567.7
VSSO_0
-767.7
VDDO_0
P22
-967.69
-1167.69
-1367.69
1232.28
1032.28
832.28
632.28
432.28
232.29
32.29
VSSO_0
BT_VDDO
BT_VSSC
BT_UART_RTS_N
Micbias
956.88
956.88
956.88
ADC_REFGND
ADC_AVSS
xtal_avss
Reserved
P5
956.88
956.88
956.88
-167.7
956.88
-367.7
956.88
P17
-567.7
956.88
P19
-767.7
956.88
P12
-967.69
-1167.69
-1367.69
1232.28
1032.28
832.28
632.28
956.88
P28
956.88
VDDO_0
BT_VDDC
BT_GPIO_2
BT_UART_RXD
BT_UART_TXD
956.88
756.89
756.89
756.89
756.89
Document Number: 002-26642 Rev. *F
Page 25 of 47
CYW20721
Table 8. CYW20721 WLCSP Bump Coordinates (Cont.)
Bump#
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
NET_NAME
X-COORD (μm)
432.28
Y-COORD (μm)
Mic_avss
P16
756.89
756.89
756.89
756.89
756.89
756.89
756.89
756.89
756.89
556.89
556.89
556.89
556.89
556.89
556.89
556.89
556.89
556.89
556.89
556.89
356.89
356.89
356.89
356.89
356.89
356.89
356.89
322.94
156.89
156.89
156.89
156.89
156.89
156.89
156.89
156.89
156.89
-43.1
32.29
Reserved
P6
-167.7
-367.7
P18
-567.7
P9
-767.7
P21
-967.69
-1167.69
-1367.69
1232.28
1032.28
832.28
P1
P36
BT_VDDO
BT_VSSC
BT_VDDC
BT_GPIO_3
P2
632.28
32.29
Reserved
P7
-167.7
-367.7
P10
-767.7
P23
-967.69
-1167.69
-1367.69
1232.28
1032.28
-367.7
P35
VDDO_0
BT_TM1
BT_CLK_REQ
P8
P11
-767.7
P13
-967.69
-1167.69
-1367.69
401.88
VSSO_0
P31
BT_VDDC
BT_VSSC
BT_HOST_WAKE
Reserved
BT_GPIO_5
BT_GPIO_4
P29
1432.27
1232.28
1032.28
832.28
632.28
-767.7
P34
-967.69
-1167.69
-1367.69
1432.27
1232.28
1032.28
832.28
P39
P26
Reserved
Reserved
BT_DEV_WAKE
BT_VSSC
P37
-43.1
-43.1
-43.1
-767.7
-43.1
P38
-967.69
-1167.69
-1367.69
1432.27
-43.1
P24
-43.1
VDDO_0
-43.1
Reserved, Connect to GND
-243.09
Document Number: 002-26642 Rev. *F
Page 26 of 47
CYW20721
Table 8. CYW20721 WLCSP Bump Coordinates (Cont.)
Bump#
93
NET_NAME
X-COORD (μm)
-367.7
Y-COORD (μm)
P0
-243.09
-243.09
-243.09
-243.09
-243.09
-243.09
-435.87
-443.09
-443.09
-443.09
-443.09
-597.97
-597.97
-797.97
-814.63
-819
94
P27
-567.7
95
P30
-767.7
96
VSSO_0
P25
-967.69
-1167.69
-1367.69
56.23
97
98
P32
99
BT_VDDC
P33
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
-767.7
VSSO_0
JTAG_SEL
RST_N
-967.69
-1167.69
-1367.69
1462.79
1262.79
1262.79
1462.79
-1059.5
-1259.5
1062.79
-659.5
BT_XTALO
BT_XTALI
BT_PLLVDD1p2
BT_PLLVSS
Reserved
PMU_DISABLE
BT_IFVDD1p2
-819
-849.66
-1018.99
-1018.99
-1018.99
-1018.99
-1035.5
-1087.29
-1128.6
-1128.6
-1212.28
-1218.99
-1218.99
-1218.99
-1153.5
-1328.59
-1412.28
-1418.99
-1418.99
-1418.99
-1418.99
-1418.99
-1418.99
-1475
RFLDO_VDDIN1P5
VSSC
-859.5
PMU_AVSS
PMU_AVSS
BT_IFVSS
-1059.5
-1459.49
1159.51
756.99
-234
BT_PAVDD
BT_VSSC
BT_VSSC
-433.99
1472.59
-1059.5
-1259.5
-1459.49
994.94
-34
BT_VCOVSS
VDDBAT3V
SR_VLX
Reserved
BT_PAVSS
BT_VSSC
BT_VCOVDD1p2
DIGLDO_VDDOUT
DIGLDO_VDDIN1P5
RFLDO_VDDOUT
SR_VDDBAT3V
SR_PVSS
1472.59
-459.5
-659.5
-859.5
-1059.5
-1259.5
-1459.49
988.31
365.99
165.99
Reserved
BT_RF
BT_VSSC
-1479.96
-1479.96
BT_VSSC
Document Number: 002-26642 Rev. *F
Page 27 of 47
CYW20721
10. Specifications
10.1 Electrical Characteristics
Caution! The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even
if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at
absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 9. Absolute Maximum Ratings
Requirement Parameter
Maximum Junction Temperature
Specifications
Unit
Min.
–
Nom.
Max.
125
–
–
°C
V
VDD IO (BT_VDDO, VDDO_0)
–0.5
3.795
VDD RF (BT_IFVDD1p2, BT_PLLVDD1p2,
BT_VCOVDD1p2, BT_PAVDD)
–0.5
–
1.38
V
VDDBAT3V/SR_VDDBAT3V
DIGLDO_VDDIN1P5
RFLDO_VDDIN1P5
MIC_AVDD
–0.5
–0.5
–0.5
–0.5
–
–
–
–
–
–
3.795
1.65
1.50
3.795
0
V
V
V
V
BT_RF
dBm
Table 10. ESD/Latch up
Requirement Parameter
Specifications
Unit
Min.
–2000
–500
–
Nom.
–
Max.
2000
500
–
ESD Tolerance HBM
ESD Tolerance CDM
Latch up
V
V
–
200
mA
Table 11. Environmental Ratings
Characteristics
Value
Unit
°C
Operating Temperature
Storage Temperature
–30 to +85
–40 to +150
°C
Note
11. Lowest operating temperature for the 32 kHz xtal is -10°C.
Table 12. Recommended Operating Conditions
Parameter
Specifications
Unit
Min.
1.76
1.76
1.76
Typ.
3.0
Max.
3.63
3.63
3.63
VDDIO (BT_VDDO, VDDO_0)
VDDBAT3V/SR_VDDBAT3V
MIC_AVDD
V
V
V
3.0
3.0
Document Number: 002-26642 Rev. *F
Page 28 of 47
CYW20721
10.1.1 Core Buck Regulator
Table 13. Core Buck Regulator
Parameter
Input supply voltage DC, VBAT
CBUCK output current
Conditions
Min.
1.76
–
Typ.
3.0
–
Max.
3.63
65
Unit
V
DC voltage range inclusive of disturbances
Low Power Operation Mode (LPOM) only
mA
Programmable, 30mV/step
default = 1.2 V (bits = 0000)
Output voltage range
1.2
1.26
1.5
V
Output voltage DC accuracy
Includes load and line regulation
–
–4
+4
%
LPOM efficiency (high load)
LPOM efficiency (low load)
–
–
–
85
80
–
–
–
–
%
%
–
Input supply voltage ramp-up time
0 to 3.3 V
40
μs
■ Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature,
and aging.
■ Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any
decoupling capacitors connected at the load side, if any.
10.1.2 Recommended External Component for Core Buck Regulator
Table 14. Recommended External Component for Core Buck Regulator
Parameter
Conditions
Min.
Typ.
Max.
Unit
2.2 μH ±25%, DCR=114 mΩ ±20%, ACR<1Ω
(for frequency<1 MHz)
External output inductor L
–
2.2
–
μH
4.7μF±10%, 6.3V, 0402, X5R, MLCCcapacitor
+board total-ESR < 20 mΩ
External output capacitor, Cout
External input capacitor, Cin
–
–
4.7
10
–
–
μF
μF
For SR_VDDBAT pin
Ceramic, X5R, 0402, ESR<30 mΩ at
4 MHz, +/-20%, 6.3V, 10 μF
10.1.3 Recommended External Components for RFLDO
Table 15. Recommended External Components for RFLDO
Parameter
Conditions
Total ESR (trace/cap): 5 m–240 mΩ
Min.
Typ.
Max.
Unit
External output capacitor, Co
0.5
2.2
4.7
μF
Document Number: 002-26642 Rev. *F
Page 29 of 47
CYW20721
10.1.4 Digital I/O Characteristics
Table 16. Digital I/O Characteristics
Characteristics
Input low voltage (VDDO = 3 V)
Input high voltage (VDDO = 3 V)
Input low voltage (VDDO = 1.8 V)
Input high voltage (VDDO = 1.8 V)
Output low voltage
Symbol
VIL
Min.
Typ.
–
Max.
Unit
V
–
0.8
–
VIH
VIL
2.4
–
V
–
–
0.4
–
V
VIH
VOL
VOH
IIL
1.4
–
V
–
–
0.45
–
V
Output high voltage
VDDO – 0.45 V
–
V
Input low current
–
–
–
–
–
–
–
–
1.0
1.0
0.4
8.0
4.0
8.0
4.0
μA
μA
pF
mA
mA
mA
mA
Input high current
IIH
–
Input capacitance
CIN
IOL
–
Output low current (VDDO = 3 V, VOL = 0.5 V)
Output low current (VDDO = 1.8 V, VOL = 0.5 V)
Output high current (VDDO = 3 V, VOH = 2.55 V)
Output high current (VDDO = 1.8 V, VOH = 1.35 V)
–
IOL
–
IOH
IOH
–
–
10.1.5 ADC Electrical Characteristics
Table 17. Electrical Characteristics
Parameter
Current consumption
Power down current
ADC Core Specification
ADC reference voltage
ADC sampling clock
Absolute error
Symbol
ITOT
–
Conditions/Comments
Min.
Typ.
Max.
Unit
mA
μA
–
–
–
2
1
3
–
At room temperature
VREF
From BG with ±3% accuracy
–
–
–
–
0.85
12
–
–
–
5
V
MHz
%
–
–
Includes gain error, offset and
distortion. Without factory calibration.
Includes gain error, offset and
distortion. After factory calibration.
–
–
2
%
ENOB
–
For audio application
For static measurement
For audio application
For static measurement
For audio application
For audio application
For static measurement
For audio application
For static measurement
For audio application
For static measurement
12
10
–
13
–
–
–
Bit
ADC input full scale
FS
1.6
–
–
1.8
8
3.6
–
Conversion rate
Signal bandwidth
–
–
16
–
kHz
Hz
20
–
8K
–
DC
–
Input impedance
Startup time
RIN
–
10
500
–
–
KΩ
–
–
10
20
–
ms
μs
–
–
MIC PGA Specifications
MIC PGA gain range
–
–
–
–
0
–
–
1
42
–
dB
dB
MIC PGA gain step
Note
12. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.
Document Number: 002-26642 Rev. *F
Page 30 of 47
CYW20721
Table 17. Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions/Comments
At 42 dB PGA gain A-weighted
Includes part-to-part gain variation
At 42 dB PGA gain A-weighted
PGA and ADC, 100 Hz–4 kHz
Min.
–
Typ.
Max.
Unit
μV
PGA input referred noise
MIC PGA gain error
–
–
–
–
–
–
–
–
4
1
–1
dB
PGA input referred noise
Passband gain flatness
MIC Bias Specifications
MIC bias output voltage
MIC bias loading current
MIC bias noise
–
4
μV
–0.5
0.5
dB
–
–
–
At 3 V supply, 25°C, default settings
–
–
–
–
2.4
–
–
3
3
V
mA
μV
Refers to PGA input 20 Hz to
8 kHz, A-weighted
–
MIC bias PSRR
ADC SNR
–
–
at 1 kHz
40
–
–
–
–
dB
dB
A-weighted 0 dB PGA gain,
Temperature= 25°C
78
ADC THD + N
–
–3 dBFS input 0 dB PGA gain,
Temperature= 25°C
–
70
–
dB
GPIO input voltage
GPIO source impedance[12]
Always lower than avddBAT
Resistance
–
–
–
–
–
–
3.6
1
V
–
kΩ
pF
Capacitance
10
Note
12. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.
10.1.6 Current Consumption
In Table 18, current consumption measurements are taken at input of VBAT and VDDIO combined (LDOIN = VDDIO = 3.0V).
Table 18. Current Consumption Bluetooth/LE
Operational Mode
Conditions
Typ.
1.1
2.2
5.9
5.6
61
Unit
mA
mA
mA
mA
μA
HCI
48 MHz with Pause
48 MHz Without Pause
Continuous RX
RX
TX
Continuous TX - 0 dBm
PDS
HID-Off
32 kHz XTAL and 16 KB Retention RAM on
Unconnectable - 1 sec
1.6
14
μA
Advertising
μA
Connectable undirected - 1 sec
Master - 1 sec
17
μA
LE Connection - SDS
16
μA
Slave - 1 sec
17
μA
Page Scan - PDS
Sniff - PDS
Interlaced - R1
122
132
138
6.9
μA
500 ms Sniff, 1 attempt, 0 timeout - Master
500 ms Sniff, 1 attempt, 0 timeout - Slave
μA
μA
Bi-Directional Data Exchange Continuous DM5 or DH5 packets - Master/Slave
mA
Document Number: 002-26642 Rev. *F
Page 31 of 47
CYW20721
10.2 RF Specifications
Note Table 19 and Table 20 apply to single-ended industrial temperatures. Unused inputs are left open.
Table 19. Receiver RF Specifications
Parameter
Frequency range
Mode and Conditions
Min.
Typ.
–
Max.
Unit
MHz
dBm
dBm
dBm
dBm
dBm
dBm
dBm
–
2402
2480
GFSK, 0.1% BER, 1 Mbps
π/4-DQPSK, 0.01% BER, 2 Mbps
8-DPSK, 0.01% BER, 3 Mbps
GFSK, 0.1% BER, 1 Mbps
π/4-DQPSK, 0.01% BER, 2 Mbps
8-DPSK, 0.01% BER, 3 Mbps
All data rates
–
–
–
–
–
–
–
–92.0[13]
–94.0[14]
–88.0[14]
–91.5[14]
–93.5[14]
–87.5[14]
–
–
–
RX sensitivity (QFN)[13]
–
–
RX sensitivity (WLCSP)[13]
–
–
Maximum input
–20
GFSK Modulation
C/I cochannel
GFSK, 0.1% BER[13]
GFSK, 0.1% BER[14]
GFSK, 0.1% BER[15]
GFSK, 0.1% BER[13]
GFSK, 0.1% BER[15]
–
–
–
–
–
–
–
–
–
–
–
–
11.0
0
dB
dB
dB
dB
dB
dB
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I image channel
–30.0
–40.0
–9.0
–20.0
C/I 1 MHz adjacent to image channel GFSK, 0.1% BER[15]
QPSK Modulation
C/I cochannel
p/4-DQPSK, 0.1% BER[15]
p/4-DQPSK, 0.1% BER[16]
p/4-DQPSK, 0.1% BER[15]
p/4-DQPSK, 0.1% BER[17]
p/4-DQPSK, 0.1% BER[15]
–
–
–
–
–
–
–
–
–
–
–
–
13.0
0
dB
dB
dB
dB
dB
dB
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I image channel
–30.0
–40.0
–9.0
–20.0
C/I 1 MHz adjacent to image channel p/4-DQPSK, 0.1% BER[15]
8PSK Modulation
C/I cochannel
8-DPSK, 0.1% BER[15]
8-DPSK, 0.1% BER[15]
8-DPSK, 0.1% BER[15]
8-DPSK, 0.1% BER[17]
8-DPSK, 0.1% BER[15]
–
–
–
–
–
–
–
–
–
–
–
–
21.0
5.0
dB
dB
dB
dB
dB
dB
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I image channel
–25.0
–33.0
0
C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER[15]
13
Out-of-Band Blocking Performance (CW)[16]
30 MHz to 2000 MHz
BDR GFSK 0.1% BER
BDR GFSK 0.1% BER
BDR GFSK 0.1% BER
BDR GFSK 0.1% BER
–
–
–
–
–10.0
–27.0
–27.0
–10.0
–
–
–
–
dBm
dBm
dBm
dBm
2000 MHz to 2399 MHz
2498 MHz to 3000 MHz
3000 MHz to 12.75 GHz
Inter-modulation Performance[13]
Notes
13. Dirty TX is off.
14. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
15. The receiver sensitivity is measured at BER of 0.1% on the device interface.
16. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
17. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
18. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal at
frequency f2, f0 = 2*f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.
Document Number: 002-26642 Rev. *F
Page 32 of 47
CYW20721
Table 19. Receiver RF Specifications (Cont.)
Parameter
Mode and Conditions
Min.
Typ.
Max.
Unit
Bluetooth, interferer signal level
Spurious Emissions
30 MHz to 1 GHz
BDR GFSK 0.1% BER
–
–
–39.0
dBm
–
–
–
–
–
–
–57.0
–55.0
dBm
dBm
1 GHz to 12.75 GHz
Notes
13. Dirty TX is off.
14. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
15. The receiver sensitivity is measured at BER of 0.1% on the device interface.
16. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
17. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
18. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal at
frequency f2, f0 = 2*f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.
Table 20. Transmitter RF Specifications
Parameter
Min.
Typ.
Max.
Unit
Transmitter Section
Frequency range
GFSK TX power
EDR TX power
2402
–
5
2480
–
MHz
dBm
dBm
kHz
–
–
–
0
–
20 dB bandwidth
Adjacent Channel Power
|M – N| = 2
930
1000
–
–
–
–
–20
–40
dBm
dBm
|M – N| 3
Out-of-Band Spurious Emission
30 MHz to 1 GHz
–
–
–
–
–
–
–
–
–36.0
–30.0
–47.0
–47.0
dBm
dBm
dBm
dBm
1 GHz to 12.75 GHz
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
LO Performance
Initial carrier frequency tolerance
Frequency Drift
–75
–
+75
kHz
DH1 packet
–25
–40
–40
–20
–
–
–
+25
+40
+40
20
kHz
kHz
DH3 packet
DH5 packet
kHz
Drift rate
kHz/50 µs
Frequency Deviation
Average deviation in payload (sequence used is 00001111)
Maximum deviation in payload (sequence used is 10101010)
Channel spacing
140
115
–
–
–
1
175
–
kHz
kHz
MHz
–
Modulation Accuracy
p/4-DQPSK frequency stability
p/4-DQPSK RMS DEVM
p/4-QPSK Peak DEVM
p/4-DQPSK 99% DEVM
–10
–
–
–
–
–
10
20
35
30
kHz
%
–
%
–
%
Document Number: 002-26642 Rev. *F
Page 33 of 47
CYW20721
Table 20. Transmitter RF Specifications (Cont.)
Parameter
8-DPSK frequency stability
8-DPSK RMS DEVM
Min.
–10
–
Typ.
Max.
Unit
kHz
%
–
–
–
–
10
13
25
20
8-DPSK Peak DEVM
–
%
8-DPSK 99% DEVM
–
%
In-Band Spurious Emissions
1.0 MHz < |M – N| < 1.5 MHz
1.5 MHz < |M – N| < 2.5 MHz
|M – N| > 2.5 MHz
–
–
–
–
–
–
–26
–20
–40
dBc
dBm
dBm
Table 21. Bluetooth LE RF Specifications
Parameter
Frequency range
RX sensitivity (QFN)[19]
Conditions
Min.
Typ.
Max.
Unit
MHz
dBm
dBm
dBm
kHz
%
N/A
2402
–
–
–95.5[20]
–94.5[20]
5.5
2480
LE GFSK, 0.1% BER, 1 Mbps
–
–
RX sensitivity (WLCSP)[19] LE GFSK, 0.1% BER, 1 Mbps
–
TX power N/A
–
–
Mod Char: Delta F1 average N/A
Mod Char: Delta F2 max[20] N/A
225
99.9
0.8
255
275
–
–
Mod Char: Ratio
N/A
0.95
–
%
Notes
19. Dirty Tx is Off.
20. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
21. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.
Table 22. BLE2M RF Specifications
Parameter
Frequency range
RX sensitivity[22]
Conditions
Min.
2402
–
Typ.
–
Max.
2480
–
Unit
MHz
dBm
dBm
kHz
N/A
255 Packets
N/A
–90.5
5.5
500
–
TX power
–
–
Mod char: Delta F1 average
Mod char: Delta F2 max
Mod char: Ratio
Frequency drift
N/A
450
370
0.8
–50
–20
550
–
N/A
kHz
N/A
–
–
%
N/A
–
50
20
kHz
Drift rate
N/A
–
kHz/50μs
Note
22. Dirty Tx is Off.
Table 23. CYW20721 GPS and GLONASS Band Spurious Emission
Parameter Conditions
1570-1580 MHz
1592-1610 MHz
Min.
Typ.
–160
–159
Max.
Unit
GPS
–
–
–
–
dBm/Hz
dBm/Hz
GLONASS
Document Number: 002-26642 Rev. *F
Page 34 of 47
CYW20721
10.3 Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
10.3.1 UART Timing
Table 24. UART Timing Specifications
Reference
Characteristics
Min.
Typ.
Max.
1.50
0.67
1.33
Unit
1
2
3
Delay time, UART_CTS_N low to UART_TXD valid
Setup time, UART_CTS_N high before midpoint of stop bit
Delay time, midpoint of stop bit to UART_RTS_N HIGH
–
–
–
–
–
–
Bit periods
Bit periods
Bit periods
Figure 8. UART Timing
UART_CTS_N
2
1
UART_TXD
Midpoint of STO P bit
Midpoint of STO P bit
UART_RXD
3
UART_RTS_N
Document Number: 002-26642 Rev. *F
Page 35 of 47
CYW20721
10.3.2 SPI Timing
The SPI interface can be clocked from 1 to 12 MHz and 24 MHz.
Table 25 and Figure 9 show the timing requirements when operating in SPI Mode 0 and 2.
Table 25. SPI Mode 0 and 2
Reference
Characteristics
Time from master assert SPI_CSN to first clock edge
Hold time for MOSI data lines
Min.
45
Max.
Unit
ns
1
2
3
4
5
–
½ SCK
100
–
12
ns
Time from last sample on MOSI/MISO to slave deassert SPI_INT
Time from slave deassert SPI_INT to master deassert SPI_CSN
Idle time between subsequent SPI transactions
0
ns
0
ns
1 SCK
–
ns
Figure 9. SPI Timing, Mode 0 and 2
5
SPI_CSN
SPI_INT
(DirectWrite)
SPI_INT
(DirectRead)
1
SPI_CLK
(Mode 0)
SPI_CLK
(Mode 2)
2
First Bit
Second Bit
Second Bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
First Bit
Not Driven
Not Driven
Table 26 and Figure 10 show the timing requirements when operating in SPI Mode 0 and 2.
Table 26. SPI Mode 1 and 3
Reference
Characteristics
Time from master assert SPI_CSN to first clock edge
Hold time for MOSI data lines
Min.
45
Max.
Unit
ns
1
2
3
4
5
–
½ SCK
100
–
12
ns
Time from last sample on MOSI/MISO to slave deassert SPI_INT
Time from slave deassert SPI_INT to master deassert SPI_CSN
Idle time between subsequent SPI transactions
0
ns
0
ns
1 SCK
–
ns
Document Number: 002-26642 Rev. *F
Page 36 of 47
CYW20721
Figure 10. SPI Timing, Mode 1 and 3
SPI_CSN
5
SPI_INT
(DirectWrite)
3
4
SPI_INT
(DirectRead)
SPI_CLK
(Mode 1)
1
SPI_CLK
(Mode 3)
2
Invalid bit
Invalid bit
First bit
Last bit
Last bit
SPI_MOSI
SPI_MISO
Not Driven
Not Driven
First bit
10.3.3 I2C Compatible Interface Timing
The specifications in Table 27 references Figure 11.
Table 27. I2C Compatible Interface Timing Specifications (up to 1 MHz)
Reference
Characteristics
Min.
Max.
Unit
1
Clock frequency
–
100
400
800
1000
–
kHz
2
3
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
ns
–
4
–
5
Clock high time
–
6
Data input hold time[23]
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time[24]
–
7
100
280
–
–
8
–
9
400
–
10
650
Notes
23. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
24. Time that the CBUS must be free before a new transaction can start.
Document Number: 002-26642 Rev. *F
Page 37 of 47
CYW20721
Figure 11. I2C Interface Timing Diagram
1
5
SCL
2
8
6
4
3
7
SDA
IN
10
9
SDA
OUT
Table 28. Timing for I2S Transmitters and Receivers
Transmitter
Lower Limit Upper Limit
Min. Max. Min. Max.
Ttr
Master Mode: Clock generated by transmitter or receiver
Receiver
Lower Limit
Min. Max.
Tr
Upper Limit
Notes
Min.
Max.
[25]
Clock Period T
–
–
–
–
–
–
[26]
[26]
HIGH tHC
LOWtLC
0.35Ttr
0.35Ttr
–
–
–
–
–
–
0.35Ttr
0.35Ttr
–
–
–
–
–
–
Slave Mode: Clock accepted by transmitter or receiver
[27]
[27]
[28]
HIGH tHC
–
–
–
0.35Ttr
0.35Ttr
–
–
–
–
–
–
–
–
–
0.35Ttr
0.35Ttr
–
–
–
–
–
–
LOW tLC
Rise time tRC
0.15Ttr
Transmitter
Delay tdtr
[29]
[28]
–
0
–
–
–
–
0.8T
–
–
–
–
–
–
–
–
–
Hold time thtr
Receiver
[30]
[30]
Setup time tsr
–
–
–
–
–
–
–
–
0.2Ttr
0.2Ttr
–
–
–
–
–
–
Hold time thr
Notes
25. The system clock period T must be greater than T and T because both the transmitter and receiver have to be able to handle the data transfer rate.
tr
r
26. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t and t are specified with
HC
LC
respect to T.
27. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum
periods are greater than 0.35T , any clock that meets the requirements can be used.
r
28. Because the delay (t ) and the maximum transmitter speed (defined by T ) are related, a fast transmitter driven by a slow clock edge can result in t not exceeding
dtr
tr
dtr
t
which means t becomes zero or negative. Therefore, the transmitter has to guarantee that t zero, so long as the clock rise-time t is not more than t
,
RC
htr
htr
RC
RCmax
where t
is not less than 0.15T
RCmax
tr
29. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient
setup time.
30. The data setup and hold time must not be less than the specified receiver setup and hold time.
Document Number: 002-26642 Rev. *F
Page 38 of 47
CYW20721
Figure 12. I2S Transmitter Timing
T
tRC
*
tLC > 0.35T
tHC > 0.35T
VH = 2.0V
VL = 0.8V
SCK
thtr > 0
totr < 0.8T
SD and WS
T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr
* tRC is only relevant for transmitters in slave mode.
Figure 13. I2S Receiver Timing
T
tLC > 0.35T
tHC > 0.35
VH = 2.0V
VL = 0.8V
SCK
tsr > 0.2T
thr > 0
SD and WS
T = Clock period
Tr = Minimum allowed clock period for transmitter
T > Tr
Document Number: 002-26642 Rev. *F
Page 39 of 47
CYW20721
11. Mechanical Information
11.1 40-Pin QFN Package
Figure 14. CYW20721 5.0 mm x 5.0 mm 40-Pin QFN Package
002-13583 *A
Document Number: 002-26642 Rev. *F
Page 40 of 47
CYW20721
11.2 WLCSP Package
Figure 15. CYW20721 WLCSP Package
6
5
NOTES:
DIMENSIONS
NOM.
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
MAX.
MIN.
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
A
0.33
-
-
-
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A1
D
0.075
-
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS.
4.
5.
3.22 BSC
E
3.31 BSC
2.84 BSC
2.84 BSC
134
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
D1
E1
N
BUMP #1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALIZED MARK, INDENTATION OR OTHER MEANS.
6.
0.100
0.115
0.130
b
7. JEDEC SPECIFICATION NO. REF. : N/A.
002-16658 *A
Document Number: 002-26642 Rev. *F
Page 41 of 47
CYW20721
11.3 WLCSP Package Keep-out
Figure 16 shows the top view of the WLCSP package (Bumps facing down).
Figure 16. CYW20721YB2 WLCSP Keep-out Model
3310.0000
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32 33 34 35 36 37 38 39 40 41 42
43 44 45 46 47
56 57 58 59
48 49 50 51 52 53 54 55
60 61 62
69
63 64 65 66
70 71 72 73
80 81 82 83
88 89 90 91
67 68
75 76 77 78 79
84 85 86 87
92
74
3220.0000
93 94 95 96 97 98
100101102103
99
104105
106
107
108109
110
115
Bump Origin
111112113
114
120121122
126127128129130131
116
117118
123
119
125
124
132
133134
Routing Keep-Out
11.4 Tape Reel and Packaging Specifications
Table 29. CYW20721 Tape Reel Specifications
Parameter
Quantity per reel
Reel diameter
Value
5000
13 inches
4 inches
12 mm
Hub diameter
Tape width
Tape pitch
8 mm
The top-left corner of the CYW20721 package is situated near the sprocket holes, as shown in Figure 17.
Figure 17. Pin 1 Orientation
Pin 1: Top left corner of package toward sprocket holes
Document Number: 002-26642 Rev. *F
Page 42 of 47
CYW20721
12. Ordering Information
Table 30. Ordering Information
Part Number
CYW20721B2KWB9G
CYW20721B2KUMLG
Package
Ambient Operating Temperature
3.2 3.1 134-Ball WLCSP
5 5 40-pin QFN
–30°C to 85°C
–30°C to 85°C
13. Acronyms
Table 31. Acronyms Used in this Document (Cont.)
Term Description
PLL phase locked loop
Table 31. Acronyms Used in this Document
Term
AFH
Description
adaptive frequency hopping
Attribute Protocol
PMU
POR
PRBS
PWM
QFN
QoS
power management unit
power-on reset
ATT
BBC
BDR
BR
Bluetooth Baseband Core
basic data rate
Pseudo Random Binary Sequence
pulse width modulation
quad flat no-lead
basic data rate
BQS
CRC
ED
Bluetooth Qualification Body
cyclic redundancy check
erroneous data
quality of service
RAM
random access memory
A resistor-capacitor oscillator is a circuit
composed of an amplifier, which provides the
output signal, and a resistor-capacitor network,
which controls the frequency of the signal.
EIR
extended inquiry response
encryption pause resume
forward error correction
floating point unit
RC oscillator
EPR
FEC
FPU
GATT
GAP
GFSK
GPIO
HCI
RF
radio frequency
ROM
RX/TX
SCO
SDP
read-only memory
Generic Attribute Profile
generic access profile
Gaussian Frequency Shift Keying
general-purpose I/O
host control interface
intermediate frequency
Joint Test Action Group
Logical Link Control and Adaptation Protocol
link control unit
receive/transmit
synchronous connection-oriented
Service Discovery Protocol
Shut Down Sleep
SDS
SPI
serial peripheral interface
serial peripheral interface fully functional
secure simple pairing
IF
SPIFFY
SSP
JTAG
L2CAP
LCU
LDO
LE
SSR
sniff subrating
SWD
TSSI
UART
WLCSP
serial wire debug
low drop-out
transmit signal strength indicator
universal asynchronous receiver/transmitter
wafer level chip scale package
low energy
LM
Link Manager
LO
local oscillator
LPO
LSTO
PA
low power oscillator
link supervision time out
power amplifier
PBF
PDM
PDS
packet boundary flag
pulse density modulation
Power down sleep
Document Number: 002-26642 Rev. *F
Page 43 of 47
CYW20721
14. Document Conventions
14.1 Units of Measure
Table 32. Units of Measure
Symbol
°C
Unit of Measure
degrees Celsius
decibel
dB
dBi
dBm
GHz
Hz
decibels relative to isotropic
decibel-milliwatts
gigahertz
hertz
KB
kHz
k
1024 bytes
kilohertz
kilo ohm
kV
kilovolt
mA
Mbps
MHz
M
mm
Msps
mV
µA
milliamperes
megabits per second
megahertz
mega-ohm
millimeters
megasamples per second
millivolt
microampere
microfarad
micrometers
microsecond
microvolt
µF
µm
µs
µV
µW
mA
m
ms
mV
nA
microwatt
milliampere
milliohm
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
V
samples per second
volt
Document Number: 002-26642 Rev. *F
Page 44 of 47
CYW20721
15. Document History Page
Document Title: CYW20721, Enhanced Low Power, Bluetooth LE Bluetooth 5.1 SOC for Audio
Document Number: 002-26642
Submission
Revision
ECN
Description of Change
Date
Removed “Preliminary” status.
Updated Table 4.
*F
7655810
02/14/2022
Document Number: 002-26642 Rev. *F
Page 46 of 47
CYW20721
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
47m
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any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates, and its directors, officers, employees, agents, distributors,
and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising
from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to
the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance
written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of
Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-26642 Rev. *F
Revised February 14, 2022
Page 47 of 47
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