D5001R803R3PB/H [INFINEON]
DC-DC Regulated Power Supply Module;
| 型号： | D5001R803R3PB/H |
| 厂家： | 
Infineon |
| 描述： | DC-DC Regulated Power Supply Module |
| 文件： | 总10页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-97809
D5001R803R3P
26 to 55V Input, Regulated Dual Outputs
(+1.8V and +3.3V)
HIGH RELIABILITY,
RADIATION TOLERANT,
LOW POWER,
DC-DC CONVERTER
Description
The D-Series of DC-DC converters are low power
radiation hardened, high reliability devices designed
for radiation environments such as those encountered
by geostationary earth orbit satellites, deep space
probes and communication systems. Features include
small size, high efficiency, low weight and a high
tolerance to total ionizing dose, single event effects,
and environmental stresses such as temperature
extremes, mechanical shock, and vibration. All
components are fully derated to meet the requirements
of EEE-INST-002. Extensive documentation including
worst case analysis, radiation susceptibility, thermal
analysis, stress analysis, and reliability analysis are
Features
n Total Dose > 50K Rad(Si)
n SEE > 40MeV.cm2/mg
n Low Weight < 55 grams
n 26V to 55V DC Input Range
n Up to 10W Output Power
n Independently Regulated Outputs:
+1.8V and +3.3V and Other Outputs Available
n -55°C to +80°C Operating Temperature Range
n 100MΩ @ 100VDC Isolation
available.
.
The D-Series converters have two outputs, each is
independently regulated. The outputs can be both n Input Under-Voltage Protection
positive or one positive and one negative. The D-Series n Meets Conducted Emission Requirements
converters incorporate a fixed frequency flyback power
stage topology and internal EMI filter. The converters
include an enhanced input EMI filter that meets most
major satellite power buses. The converters can be
of Most Major Power Buses:
100Hz - 100KHz: 80dBµArms
100KHz - 10MHz: Log-linear Decrease
10MHz - 50MHz: 40dBµArms
remotely turned on and off via an Inhibit pin. Additional n Short Circuit and Overload Protection
Inhibit pins are also provided to control the outputs n Meets the Derating Requirments of
individually. This feature facilitates turn-on outputs
EEE-INST-002
sequencing if desired. Each converter is encased in a n Synchronization Input / Output
cold rolled steel hermetic package. The package n On/Off Control via Converters’s Inhibit Pin
measures 1.80"L x 1.40"W x 0.42"H and weighs less
than 55 grams.The package utilizes rugged ceramic
feed-through copper core pins and is hermetically sealed
using parallel seam welding. Two package options are
available. Please refer to page 8 for I/O configurations.
and Individual Output’s Inhibit Pin
n High CS Damping
Applications
n Launch Vehicles
Environmental screening includes temperature cycling,
constant acceleration, fine and gross leak, and burn-in
as specified by MIL-PRF-38534 for class H hybrids.
n Communication Systems
n Geostationary or Low Earth Orbit Satellites
Non-flight versions of the D-Series converters are
available for system development purposes. Variations
in electrical specifications and screening to meet custom
requirements can be accommodated.
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1
05/24/13
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Circuit Description
The D-Series DC-DC converters utilize two-stage
regulation with a flyback topology with a switching
frequency of 250KHz for primary regulation and linear
post regulation in the secondary for each of the
outputs.
An inhibit pin is provided to control converter operation.
This inhibit pin is intended for operation with an open
collector transistor drive or a relay closure to the
input return. The pin may be left open for normal
operation and has a nominal open circuit voltage of
4.0V. Also provided are the individual output on/off
control pins (Pin 10, Output 1 Inhibit and Pin 9, Output
Output power is limited under any load fault
condition to approximately 110% of rated output.
An overload condition causes the converter output
to behave like a constant current source with the
output voltage dropping below nominal. The
converter will resume normal operation when the
load current is reduced below the current limit point.
This protects the converter from both overload and
short circuit conditions. There are no latching
elements to eliminate the possibility of falsely
triggering the protection circuits during single event
radiation exposure.
2 Inhibit).
Synchronization input pin is included allowing
multiple converters to operate at a common switching
frequency. Converters can be synchronized to a
common frequency with an external clock. This may
be used to eliminate beat frequency noise or to avoid
generating noise at certain frequencies for noise
sensitive systems.
Design Methodology
An under-voltage protection circuit prohibits the
converter from operating when the line voltage is
too low for safe operation. The converter will not
start until the line voltage rises to approximately 20V.
The D-Series isdeveloped using aproven conservative
design methodology, which includes selecting
radiation tolerant and established reliability
components and fully derating to the requirements
of EEE-INST-002. Heavy derating of the radiation-
hardened power MOSFET virtually eliminates the
possibility of SEGR and SEB.
2
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Specifications
Absolute Maximum Ratings
Input voltage range
Recommended Operating Conditions
-0.5Vdc to +80Vdc Input voltage range (Note 13)
Internally limited Output power
+300°C for 10sec Operating temperature
26Vdc to 55Vdc
0 to Max. Rated
-55°C to +115°C
-55°C to +80°C
Output power
Lead temperature
Operating case temperature (Note 12) -55°C to +125°C Operating temperature,
Storage temperature -55°C to +135°C derated (Note 13)
Electrical Performance Characteristics
Conditions
-55°C ≤ T ≤ +85°C
Limits
Nom
42
Group A
Subgroup
C
Parameter
Unit
Max
V
= 42V DC ± 5%, C = 0
IN
L
Min
26
unless otherwise specified
Input Voltage
Output voltage (V
55
V
Note 1
)
OUT
(Out 1 / Out 2)
1.8V
1
1
1.782
3.267
1.800
3.300
1.818
3.333
V
V
I
I
= 100% rated load
= 100% rated load
OUT
OUT
3.3V
2.3
2,3
1.746
3.200
1.800
3.300
1.854
3.399
1.8V
3.3V
Output power (P
)
OUT
(Out 1/ Out 2)
1.8V
1,2,3
2.7
5.0
W
V
V
= 26, 42, 55V, Notes 2, 11
Either Output
IN
3.3V
Output power (I
)
OUT
(Out 1/ Out 2)
1.8V
1,2,3
1,2,3
1,2,3
0
0
1.5
1.5
A
= 26, 42, 55V, Notes 2, 11
Either Output
IN
3.3V
-0.2
0.2
%
%
Line regulation (VR
Each output
)
V
IN
= 26, 42, 55V
LINE
I
I
= 0%, 50%, 100% rated
= 0%, 50%, 100% rated
OUT
OUT
-0.5
1.5
Load regulation (VR
Each output
)
LOAD
V
IN
= 26, 42, 55V
Cross regulation (VR
Input current
)
CROSS
1,2,3
1,2,3
5.0
mV
mA
V
= 26, 42, 55V, Note 1
IN
I
35
10
= 0, Pin 6 open
OUT
Pin 6 connected to Pin 2
1,2,3
1,2,3
225
250
275
KHz
Switching frequency (F )
S
Synchronization Input
Frequency range
Pulse high level
External clock on sync In (Pin 4)
Note 1
450
2.5
-0.5
40
550
5.0
0.5
KHz
V
Pulse low level
V
V/µs
%
Pulse transition time
Pulse duty cycle
20
80
For Notes to Electrical Performance Characteristic Table, refer to page 5
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3
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Electrical Performance Characteristics (continued)
Conditions
-55°C ≤ T ≤ +85°C
C
= 42V DC ± 5%, C = 0
Limits
Nom
Group A
Subgroup
Parameter
Unit
V
IN
L
Min
Max
unless otherwise specified
Output ripple (V
Each output
)
V
= 26, 42, 55V
RIP
IN
I
= 100% rated load
Note 3
OUT
1,2,3
50
50
mV p-p
1.8V
3.3V
Output ripple @ switch
frequency
1,2,3
1,2,3
1,2,3
V
= 26, 42, 55V
0.5
47
0.75
mV rms
%
IN
I
= 100% rated load, Note 1
OUT
I
45
Efficiency (E
)
FF
= 100% rated load
OUT
Enable Input (Inhibit)
Open circuit voltage
Drive current (sink)
Voltage range
Note 1
0
4
V
µA
V
600
50
-0.5
Current Limit Point
Each output
1.8V
V
OUT = 90% of Nominal
Note 10
%
W
1,2,3
1,2,3
105
105
145
145
3.3V
Power dissipation load fault
Short Circuit, Overload, Note 5
24
(P )
D
Output response to
step load changes (V
)
TLD
mV pk
15
15
1.8V
3.3V
4,5,6
Half Load to/ from Full Load, Note 6
-15
-15
Recovery time,
step load changes (T
)
TLD
µs
µs
1.8V
3.3V
4,5,6
4,5,6
Half Load to/from Full Load, Notes 6, 7
26V to/from 55V
500
500
Recovery time,
100
step line changes ( T
Turn-on Response
)
I
= 100% rated load, Notes 1, 7, 8
OUT
TLN
Overshoot (V
)
OS
4,5,6
1
10% Load, Full Load
Note 9
25
25
mV
ms
1.8V
3.3V
Turn-on Delay (T
10
)
0.2
DLY
Capacitive Load (C )
L
I
= 100% rated load
1.8V
3.3V
220
220
µF
OUT
No effect on DC performance, Notes 1, 4
Each output
For Notes to Electrical Performance Characteristic Table, refer to page 5
4
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Electrical Performance Characteristics (continued)
Conditions
Limits
Nom
Group A
Subgroup
-55°C ≤ T ≤ +85°C
C
Parameter
Unit
dB
V
= 42V DC ± 5%, C = 0
IN
L
Min
80
Max
unless otherwise specified
EMC conducted
susceptibility
I
= 100% rated load
Primary power sine wave injection of
2Vp-p, 100Hz to 50MHz, Note 1
OUT
1
90
(Line rejection)
Electromagnetic Interference
(EMI), conducted emission
(CE)
I
OUT = 100% rated load, Note 1
1
1
Limits per Figure 1
Isolation
Input to Output or Any Pin to Case
except pin 3, test @ 50VDC
100
MΩ
Device Weight
MTBF
55
g
5
hours
MIL-HDBK-217F2, SF, 35°C
1 x 10
Notes: Specification and Electrical Performance Characteristics
1. Parameter is tested as part of design characterization or after design changes. Thereafter, parameter shall be
guaranteed to the limits specified.
2. Parameter verified during line and load regulation tests.
3. Guaranteed for a D.C. to 20MHz bandwidth. Tested using a 20KHz to 10MHz bandwidth.
4. Capacitive load may be any value from 0 to the maximum limit without compromising dc performance.
A capacitive load in excess of the maximum limit may interfere with the proper operation of the converter’s overload
protection, causing erratic behavior during turn-on.
5. Overload power dissipation is defined as the device power dissipation with the load set such that both outputs are in a
short circuit mode.
6. Load step transition time ≤ 10 µsec.
7. Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady
state value.
8. Line step transition time ≤100 µsec.
9. Turn-on delay time from either a step application of input power or a logic low to a logic high transition on the inhibit pin
(pin 6) to the point where VOUT = 90% of nominal.
10. Current limit point expressed as a percentage of full rated load current.
11. For models with two positive outputs the envelope specification for the design is that each output voltage is limited to the
range 1V to 5V.
12. Although operation at temperatures between +85°C and +125°C is guaranteed, no parameter limits are specified.
13. Meets the derating requirements of EEE-INST-002 – except for ceramic capacitors with voltage stress below 10V will
minimum be rated at 50V and a minimum load of 20mA on each output.
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5
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Device Screening
Test / Inspection
Element Evaluation
Nondestructive Bond Pull
Internal Visual
Method
/EM Suffix Flight (No Suffix)
MIL-STD-38534 Class K equivalent with SEM
MIL-STD-883, Method 2023
N/A
N/A
X
X
X
MIL-STD-883, Method 2017
Note 1
N/A
Temperature Cycling
Constant Acceleration
PIND
MIL-STD-883, Method 1010
Condition C
3000 G’s
A
MIL-STD-883, Method 2001, Y1 Axis
MIL-STD-883, Method 2020
N/A
N/A
Burn-in (2 x 220 hours)
MIL-STD-883, Method 1015
48 Hours
@ 115°C
X
440 Hours
@ 115°C
X
Final Electrical (Group A)
In accordance with device specification
MIL-STD-883, Method 1014
Seal
Condition A
Fine Leak
Gross Leak
Radiographic
A1
C
MIL-STD-883, Method 2012
MIL-STD-883, Method 2009
N/A
N/A
External Visual
Note 1
Yes
Notes:
1. Best commercial practice
Radiation Performance Characteristics
Test
Conditions
Min
Unit
MIL-STD-883, Method 1019.5
Operating bias applied during exposure,
50
KRads (Si)
*
Total Ionizing Dose (Gamma)
Full Rated Load, VIN = 50V
Heavy Ions (LET)
2
Operating bias applied during exposure,
40
*
Single Event Effects
·
MeV cm /mg
SEU, SEL, SEGR, SEB
Full Rated Load, VIN = 26, 42, 55V
* Test performed at TAMU
International Rectifier currently does not have a DSCC certified Radiation Hardness Assurance Program.
6
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Fig. 1 - EMI Conducted Emission Performance Limit
Fig. 2 - A Typical input EMI Conducted Emission Performance
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7
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Mechanical Outline - Option A (Straight Pins)
All dimensions are in inch.
.XX: ±0.01
.XXX: ±0.005
Mechanical Outline - Option B (Down Pins)
Ø 0.140
0.050
0.400
0.200 Typ.
Non-cum
1.000
Ref.
1.30 1.550 1.800
Pin Ø
0.040
0.220
1.400
1.650
1.90
0.41
1.70
0.15
0.420 Max.
All dimensions are in inch.
.XX: ±0.01
.XXX: ±0.005
8
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D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Block Diagram
12
11
10
1
2
3
9
8
7
4
5
6
Pin Designation
Pin #
P
(Both Outputs Positive)
Input
1
2
Input Return
Case
3
Sync In
4
Sync Out
5
Inhibit
6
Output 2
7
Output 2 Return
Output 2 Inhibit
Output 1 Inhibit
Output 1 Return
Output 1
8
9
10
11
12
Note: Pins 8 and 11 are internally connected
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9
D5001R803R3P
(26 TO 55V Input, Regulated Dual Outputs)
(+1.8V and +3.3V)
Part Numbering
D 50 01R8 03R3 P A A /EM
Model
D = Two Outputs,
5W Max each,
Radiation-
Quality Level
EM = Engineering Model
H = Class H per MIL-PRF-38534
Tolerant Design
Lead Finish
A = Solder Dipped
C = Gold Plated
Blank = for EM, Lead Finish as available
Input Voltage
50 = 50V
Output 1
01R8 = 1.8V
I/O Pin Option
A = Straight Pins
B = Down Pins
Output 2
03R3 = 3.3V
Output Configuration
P = Both Positive
WORLD HEADQUARTERS: 101 N, Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105
IR SAN JOSE: 2520 Junction Avenue, San Jose, California 95134, USA Tel: (408) 434-5000
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 05/2013
10
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