ECJ-4YB1E226M [INFINEON]

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR; 8A高度集成的宽输入电压同步降压稳压器
ECJ-4YB1E226M
型号: ECJ-4YB1E226M
厂家: Infineon    Infineon
描述:

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
8A高度集成的宽输入电压同步降压稳压器

稳压器 输入元件
文件: 总21页 (文件大小:1072K)
中文:  中文翻译
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PD-97472  
IR3871MPBF  
TM  
SupIRBuck  
8A HIGHLY INTEGRATED  
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR  
Features  
Description  
The IR3871 SupIRBuckTM is an easy-to-use,  
fully integrated and highly efficient DC/DC  
voltage regulator. The onboard constant on time  
hysteretic controller and MOSFETs make  
IR3871 a space-efficient solution that delivers up  
to 8A of precisely controlled output voltage in  
60°C ambient temperature applications without  
airflow.  
. Input Voltage Range: 3V to 26V  
. Output Voltage Range: 0.5V to 12V  
. Continuous 8A Load Capability  
. Constant On-Time control  
. Excellent Efficiency at very low output current levels  
. Compensation Loop not required  
. Programmable switching frequency, soft start, and  
over current protection  
. Power Good Output  
. Precision Voltage Reference (0.5V, +/-1%)  
. Pre-bias Start Up  
. Under/Over Voltage Fault Protection  
. Ultra small, low profile 5 x 6mm QFN Package  
Programmable switching frequency, soft start,  
and over current protection allows for a very  
flexible solution suitable for many different  
applications and an ideal choice for battery  
powered applications.  
Applications  
Additional features include pre-bias startup, very  
precise 0.5V reference, over/under voltage shut  
down, power good output, and enable input with  
voltage monitoring capability.  
. Notebook and desktop computers  
. Game consoles  
. Consumer electronics STB, LCD, TV, printers  
. General purpose POL DC-DC converters  
1
IR3871MPBF  
ABSOLUTE MAXIMUM RATINGS  
(Voltages referenced to GND unless otherwise specified)  
VIN. FF …………………………………………..……. -0.3V to 30V  
VCC, PGood, EN ………………….…....….…..….… -0.3V to 8.0V  
Boot ……………………………………..……..…...…. -0.3V to 40V  
PHASE ……………………………………………....... -0.3V to 30V(DC), -5V(100ns)  
Boot to PHASE …..………………………………..….. -0.3V to 8V  
ISET …………………………………………..….……. -0.3V to 30V  
PGND to GND ……………...……………..………….. -0.3V to +0.3V  
All other pins ……………...………………….……….. -0.3V to 3.9V  
Storage Temperature Range ................................... -65°C To 150°C  
Junction Temperature Range ................................... -40°C To 150°C  
ESD Classification …………………………….……… JEDEC Class 1C  
Moisture sensitivity level ……….……...…………..… JEDEC Level 2 @ 260°C (Note 2)  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. These are stress ratings only and functional operation of the device at these or any other  
conditions beyond those indicated in the operational sections of the specifications are not implied.  
PACKAGE INFORMATION  
5mm x 6mm POWER QFN  
θJA = 35oC / W  
θJ-PCB = 2oC / W  
ORDERING INFORMATION  
PKG DESIG  
PACKAGE  
PIN COUNT  
PARTS PER  
REEL  
DESCRIPTION  
M
M
IR3871MTRPbF  
IR3871MTR1PbF  
17  
17  
4000  
750  
2
IR3871MPBF  
Simplified Block Diagram  
3
IR3871MPBF  
Pin Description  
NAME  
NUMBER I/O  
LEVEL  
DESCRIPTION  
NC  
1
2
-----  
No connection.  
ISET  
PGOOD  
GND  
FB  
Connecting resistor to PHASE pin sets over current trip point.  
Power good open drain output pull up with a resistor to 3.3V.  
Bias return and signal reference.  
3
5V  
4,17  
5
Reference  
3.3V  
Inverting input to PWM comparator, OVP / PGood sense.  
SS  
6
3.3V  
Soft start/shutdown. This pin provides user programmable soft-  
start function. Connect an external capacitor from this pin to  
GND to set the startup time of the output voltage. The converter  
can be shutdown by pulling this pin below 0.3V.  
NC  
7
8
-----  
No connection.  
3VCBP  
3.3V  
LDO output. A minimum of 1.0 µF ceramic capacitor is required  
from 3VCBP to GND.  
NC  
9
-----  
5V  
No connection.  
VCC  
10  
Gate drive supply. A minimum of 1.0µF ceramic capacitor must  
be connected from this pin to the power return (PGND).  
PGND  
PHASE  
VIN  
11  
12  
13  
14  
Reference  
VIN  
Power return.  
Phase node (or switching node) of MOSFET half bridge.  
Input voltage for the system.  
VIN  
BOOT  
VIN +VCC  
Bootstrapped gate drive supply connect a capacitor to  
PHASE.  
FF  
15  
16  
VIN  
5V  
Input voltage feed forward sets on-time with a resistor to VIN.  
EN  
Enable pin to turn on and off the device. Use two external  
resistors to set the turn on threshold (see Electrical  
Specifications) for input voltage monitoring.  
4
IR3871MPBF  
Recommended Operating Conditions  
Symbol  
VIN  
Definition  
Input Voltage  
Min  
3
Max  
26*  
Unit  
VCC  
VOUT  
IOUT  
Fs  
Supply Voltage  
4.5  
7.5  
V
Output Voltage  
0.5  
0
12  
8
Output Current  
A
Switching Frequency  
Junction Temperature  
N/A  
0
1000  
125  
kHz  
oC  
TJ  
* PHASE pin must not exceed 30V.  
Electrical Specifications  
Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC.  
PARAMETER  
BIAS SUPPLIES  
NOTE  
TEST CONDITION  
MIN TYP MAX UNIT  
VCC Turn-on Threshold  
VCC Turn-off Threshold  
VCC Threshold Hysteresis  
VCC Operating Current  
3.9  
3.6  
4.2  
3.9  
150  
7.1  
4.5  
4.2  
V
V
mV  
mA  
RFF = 200K,  
EN = HIGH, Fs = 300kHz  
EN = LOW  
VCC Shutdown Current  
FF Shutdown Current  
VIN Shutdown Current  
INTERNAL LDO OUTPUT  
LDO Output Voltage Range  
Output Current  
35  
2
50  
µA  
µA  
µA  
EN = LOW  
EN = LOW  
1
C3VCBP = 1µF  
3.1  
3.3  
3.5  
8
V
mA  
CONTROL LOOP  
Reference Accuracy, VREF  
On-Time Accuracy  
VREF  
0.495 0.5  
0.505  
320  
V
ns  
RFF = 180K, TJ = 65oC  
280  
300  
400  
10  
Min Off Time  
1
1
ns  
Soft-Start Current  
EN = HIGH  
8
12  
0
µA  
mV  
Zero Current Threshold  
FAULT PROTECTION  
ISET Pin Output Current  
Under Voltage Threshold  
Under Voltage Hysteresis  
Over Voltage Threshold  
Over Voltage Hysteresis  
Measure at VPHASE  
-5  
-2.4  
18  
20  
0.4  
10  
22  
µA  
V
Falling VFB & Monitor PGOOD  
Rising VFB  
0.37  
0.43  
1
1
mV  
V
Rising VFB & Monitor PGOOD  
Falling VFB  
0.58 0.62  
0.66  
10  
1
mV  
V
PGOOD Delay Threshold  
(VSS)  
5
IR3871MPBF  
Electrical Specifications (continued)  
Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC.  
PARAMETER  
GATE DRIVE  
Dead Time  
NOTE  
TEST CONDITION  
MIN TYP MAX UNIT  
1
Monitor body diode conduction  
on PHASE pin  
5
30  
ns  
BOOTSTRAP PFET  
Forward Voltage  
I(BOOT) = 10mA  
100  
200  
300  
mV  
UPPER MOSFET  
Static Drain-to-Source On-  
Resistance  
VCC = 5V, ID = 7A, TJ = 25oC  
14.5 20.8  
25.5  
mΩ  
LOWER MOSFET  
Static Drain-to-Source On-  
Resistance  
VCC = 5V, ID = 9A, TJ = 25oC  
8
10  
12.5  
mΩ  
LOGIC INPUT AND OUTPUT  
EN High Logic Level  
2
-
-
-
V
V
EN Low Logic Level  
-
0.6  
EN Input Current  
EN = 3.3V  
11  
25  
µA  
Ω
PGOOD Pull Down  
Resistance  
50  
Note 1: Guaranteed by design, not tested in production  
Note 2: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application  
note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3 for Consumer  
Market.  
6
IR3871MPBF  
TYPICAL OPERATING DATA  
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, Vout = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,  
unless otherwise specified  
95%  
85%  
75%  
65%  
55%  
45%  
35%  
100%  
90%  
80%  
70%  
60%  
50%  
40%  
EFF @ 8VIN  
EFF @ 19VIN  
EFF @ 3.3VOUT, L = 3.3µH  
EFF @ 1.5VOUT, L = 2.2µH  
EFF @ 1.05VOUT, L = 1.5µH  
EFF @ 12VIN  
0.01  
0.1  
1
10  
0.01  
0.1  
1
10  
Output Current (A)  
Output Current (A)  
Figure 1. Efficiency vs. Output Current for  
VOUT = 1.05V  
Figure 2. Efficiency vs. Output Current for  
VIN = 12V  
350  
300  
250  
200  
150  
100  
50  
1200  
1000  
800  
600  
400  
200  
0
5.0 Vout  
4.0  
3.0  
2.0  
1.0  
4.5  
3.5  
2.5  
1.5  
0.5  
0
0
1
2
3
4
5
6
7
8
200  
400  
600  
Frequency (kHz)  
800  
1000  
Output Current (A)  
Figure 3. Switching Frequency vs. Output  
Current  
Figure 4. Frequency vs. RFF  
1.052  
1.051  
1.050  
1.049  
1.048  
1.052  
VOUT @ 12VIN  
1.051  
1.050  
1.049  
1.048  
VOUT @ 19VIN  
VOUT @ 8VIN  
0
1
2
3
4
5
6
7
8
6
8
10  
12  
14  
16  
18  
20  
Output Current (A)  
Input Voltage (V)  
Figure 5. Output Voltage Regulation vs.  
Output Current  
Figure 6. Output Voltage Regulation vs.  
Input Voltage at IOUT = 8A  
7
IR3871MPBF  
TYPICAL APPLICATION CIRCUIT  
Demoboard Schematic: VOUT = 1.05V, Fs = 300kHz  
+3.3V  
VCC  
+Vins  
T P1  
R1  
VINS  
open  
VIN  
T P2  
VIN  
R2  
10K  
T P3  
FCCM  
+
C1  
1uF  
C2  
22uF  
C3  
68uF  
EN  
T P4  
EN  
FCCM  
+Vin1s  
C4  
T P20  
+Vin1s  
R3  
200K  
T P5  
PGND  
SW1  
EN / FCCM  
R4  
10.5K  
-Vins  
0.22uF  
T P6  
PGNDS  
T P23  
+Vsws  
VSW  
ISET  
L1  
1.5uH  
VSW  
VOUT  
U1  
IR3871  
T P7  
VOUT  
+3.3V  
R5  
C5  
open  
2
5
T P8  
VOUTS  
C6  
open  
C7  
open  
C8  
open  
C9  
330uF  
C10  
47uF  
C11  
open  
C12  
0.1uF  
1
2
3
4
5
6
7
NC  
R6  
open  
C13  
open  
10K  
ISET  
PGOOD  
GND1  
FB  
T P11  
PGOOD  
PGOOD  
T P10  
PGND  
12  
T P9  
+Vout1s  
PHASE  
IR3871  
T P22  
+Vsws  
T P24  
+Vsws  
FB  
2
5
SS  
T P13  
SS  
T P12  
VSWS  
SS  
C20  
0.1uF  
C15  
open  
C16  
open  
C17  
open  
C18  
open  
C19  
open  
C26  
open  
C27  
open  
NC1  
T P21  
-Vsws  
+3.3V  
-Vout1s  
T P14  
+3.3V  
T P15  
-Vout1s  
+Vdd2s  
-Vdd2s  
C21  
1uF  
T P25  
-Vin1s  
T P26  
AGND  
+Vdd1s  
-Vdd1s  
C22  
open  
C25  
1uF  
C24  
open  
R7  
2.80K  
C14  
open  
VCC  
T P16  
VCC  
T P18  
VOLT AGE SENSE  
C23  
open  
T P17  
PGND  
R11  
open  
T P19  
FB  
R12  
open  
R8  
2.55K  
R13  
open  
R14  
open  
R9  
0
R10  
open  
Figure 7. Typical Application Circuit for VOUT = 1.05V, Fs = 300kHz  
Demoboard Bill of Materials  
Quantity Reference  
Value  
Description  
Manufacturer  
Part-Number  
1
3
1
1
1
1
2
1
2
1
1
1
1
1
1
1
C4  
C1, C21, C25 1uF  
0.22uF CAP,CER,0.22uF,50V,10%,X7R,0603  
Murata Electronics GRM188R71H224KA64D  
Murata Electronics GRM188R71E105KA12D  
CAP,CER,1.0uF,25V,X7R,0603  
CAP,22uF,25V,CERAMIC,X5R,1210  
CAP,68uF,25V,ELECT,FK,SMD  
C2  
C3  
22uF  
68uF  
Panasonic  
Panasonic  
Sanyo  
ECJ-4YB1E226M  
EEV-FK1E680P  
2R5TPE330M9  
C9  
330uF POSCAP, 330uF, 2.5V, SMD  
C10  
C12, C20  
L1  
47uF  
0.1uF  
CAP,CER,47uF,6.3V,X5R,0805  
CAP,CER,0.1uF,50V,10%,X7R,0603  
TDK  
TDK  
C2012X5R0J476M  
C1608X7R1H104K  
PCMB065T-1R5MS  
CRCW060310K0FKEA  
CRCW06030000Z0EAHP  
CRCW0603200KFKEA  
CRCW060310K5FKEA  
CRCW06032K80FKEA  
CRCW06032K55FKEA  
1.5uH INDUCTOR, 1.5uH, 11A, 6.7mOhm,SMD  
CYNTEC  
Vishay/Dale  
Vishay/Dale  
Vishay/Dale  
Vishay/Dale  
Vishay/Dale  
Vishay/Dale  
R2, R5  
R9  
10K  
0
RES,10.0K,OHM,1/10W,1%,0603,SMD  
RES,0.0,OHM,1/10W,1%,0603,SMD  
RES,200K,OHM,1/10W,1%,0603,SMD  
R3  
200K  
R4  
R7  
10.5K RES,10.5K,OHM,1/10W,1%,0603,SMD  
2.8K RES,2.8K,OHM,1/10W,1%,0603,SMD  
R8  
SW1  
U1  
2.55K RES,2.55K,OHM,1/10W,1%,0603,SMD  
SPST SWITCH, DIP, SPST, SMT  
IR3871 5mm x 6mm QFN  
C&K Components SD02H0SK  
IR IR3871MPBF  
8
IR3871MPBF  
TYPICAL OPERATING DATA  
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, Vout = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,  
unless otherwise specified  
EN  
EN  
PGOOD  
PGOOD  
SS  
SS  
VOUT  
VOUT  
5V/div  
5V/div 1V/div 500mV/div  
5ms/div  
5V/div 5V/div 1V/div 500mV/div  
200µs/div  
Figure 9: Shutdown  
Figure 8: Startup  
VOUT  
VOUT  
PHASE  
PHASE  
iL  
iL  
20mV/div  
20mV/div  
5V/div 5A/div  
5V/div 2A/div  
10µs/div  
2µs/div  
Figure 11: CCM (IOUT = 6A)  
Figure 10: DCM (IOUT = 0.1A)  
PGOOD  
PGOOD  
SS  
FB  
VOUT  
iL  
VOUT  
IOUT  
5V/div 1V/div 1V/div 10A/div  
1ms/div  
5V/div 1V/div 500mV/div 2A/div  
50µs/div  
Figure 12: Over Current Protection  
(tested by shorting VOUT to PGND)  
Figure 13: Over Voltage Protection  
(tested by shorting FB to VOUT  
)
9
IR3871MPBF  
TYPICAL OPERATING DATA  
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, Vout = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,  
unless otherwise specified  
VOUT  
VOUT  
PHASE  
iL  
PHASE  
iL  
50mV/div  
50mV/div  
10V/div 2A/div  
20µs/div  
10V/div 2A/div  
20µs/div  
Figure 15: Load Transient 4-8A  
Figure 14: Load Transient 0-4A  
Figure 16: Thermal Image at VIN = 12V, IOUT  
=
Figure 17: Thermal Image at VIN = 19V, IOUT =  
8A (IR3871: 66oC, Inductor: 58oC, PCB: 40oC)  
8A (IR3871: 71oC, Inductor: 59oC, PCB: 44oC)  
10  
IR3871MPBF  
CIRCUIT DESCRIPTION  
PGOOD  
PWM COMPARATOR  
The PGOOD pin is open drain and it needs to be  
externally pulled high. High state indicates that  
output is in regulation. The PGOOD logic monitors  
EN_DELAY, SS_DELAY, and under/over voltage  
fault signals. PGOOD is released only when  
EN_DELAY and SS_DELAY = HIGH and output  
voltage is within the OV and UV thresholds.  
The PWM comparator initiates a SET signal  
(PWM pulse) when the FB pin falls below the  
reference (Vref) or the soft start (SS) voltage.  
ON-TIME GENERATOR  
The PWM on-time duration is programmed with  
an external resistor (RFF) from the input supply  
(VIN) to the FF pin. The simplified calculation for  
RFF is shown in equation 1. The FF pin is held to  
an internal reference after EN goes HIGH. A copy  
of the current in RFF charges a timing capacitor,  
which sets the on-time duration, as shown in  
equation 2.  
PRE-BIAS STARTUP  
IR3871 is able to start up into pre-charged output,  
which prevents oscillation and disturbances of the  
output voltage.  
With constant on-time control, the output voltage  
is compared with the soft start voltage (SS) or  
Vref, depending on which one is lower, and will  
not start switching unless the output voltage drops  
below the reference. This scheme prevents  
discharge of a pre-biased output voltage.  
V
OUT  
R
FF  
(1)  
(2)  
1V 20pF FSW  
FF 1V 20pF  
R
TON  
V
IN  
SHUTDOWN  
CONTROL LOGIC  
The IR3871 will shutdown if VCC is below its  
UVLO limit. The IR3871 can be shutdown by  
pulling the EN pin below its lower threshold.  
Alternatively, the output can be shutdown by  
pulling the soft start pin below 0.3V.  
The control logic monitors input power sources,  
sequences the converter through the soft-start  
and protective modes, and initiates an internal  
RUN signal when all conditions are met.  
VCC and 3VCBP pins are continuously monitored,  
and the IR3871 will be disabled if the voltage of  
either pin drops below the falling thresholds.  
EN_DELAY will become HIGH when VCC and  
3VCBP are in the normal operating range and the  
EN pin = HIGH.  
SOFT START  
With EN = HIGH, an internal 10µA current source  
charges the external capacitor (CSS) on the SS pin  
to set the output voltage slew rate during the soft  
start interval. The soft start time (tSS) can be  
calculated from equation 3.  
CSS 0.5V  
10A  
tSS   
(3)  
The feedback voltage tracks the SS pin until SS  
reaches the 0.5V reference voltage (Vref), then  
feedback is regulated to Vref. CSS will continue to  
be charged, and when SS pin reaches VSS (see  
Electrical Specification), SS_DELAY goes HIGH.  
With EN_DELAY = LOW, the capacitor voltage  
and SS pin is held to the FB pin voltage. A normal  
startup sequence is shown in Figure 18.  
Figure 18. Normal Startup  
11  
IR3871MPBF  
CIRCUIT DESCRIPTION  
UNDER/OVER VOLTAGE MONITOR  
OVER CURRENT MONITOR  
The IR3871 monitors the voltage at the FB node  
through a 350ns filter. If the FB voltage is below  
the under voltage threshold, UV# is set to LOW  
holding PGOOD to be LOW. If the FB voltage is  
above the over voltage threshold, OV# is set to  
LOW, the shutdown signal (SD) is set to HIGH,  
MOSFET gates are turned off, and PGOOD  
signal is pulled low. Toggling VCC or EN will  
allow the next start up. Figure 19 shows  
PGOOD status change when UV/OV is  
detected. The over voltage and under voltage  
thresholds can be found in the Electrical  
Specification section.  
The over-current circuitry monitors the output  
current during each switching cycle. The voltage  
across the lower MOSFET, VPHASE, is  
monitored for over current and zero crossing. The  
OCP circuit evaluates VPHASE for an over  
current condition typically 270ns after the lower  
MOSFET is gated on. This delay functions to filter  
out switching noise. The minimum lower gate  
interval allows time to sample VPHASE.  
The over current trip point is programmed with a  
resistor from the ISET pin to PHASE pin, as  
shown in equation 4, where Tj is the junction  
temperature of Q2 at operation conditions, and 0.4  
is the temperature coefficient (~4000 ppm/C) of  
Q2 RDSON. When over current is detected, the  
output gates are tri-state and SS voltage is pulled  
to 0V. This initiates a new soft start cycle. If there  
is a total of four OC events, the IR3871 will  
disable switching, as shown in Figure 20. Toggling  
VCC or EN will allow the next start up.  
Tj 25  
R
DSON OC  
I
RSET  
(1  
0.4) (4)  
20 A  
100  
Figure 19(a). Under/Over Voltage Monitor  
Figure 20. Over Current Protection  
* typical filter delay  
Figure 19(b). Over Voltage Protection  
12  
IR3871MPBF  
CIRCUIT DESCRIPTION  
GATE DRIVE LOGIC  
STABILITY CONSIDERATIONS  
The gate drive logic features adaptive dead  
time, diode emulation, and a minimum lower  
gate interval.  
Constant-on-time control is a fast , ripple based  
control scheme. Unstable operation can occur  
if certain conditions are not met. The system  
instability is usually caused by:  
An adaptive dead time prevents the  
simultaneous conduction of the upper and lower  
MOSFETs. The lower gate voltage (LGATE)  
must be below approximately 1V after PWM  
goes HIGH before the upper MOSFET can be  
gated on. Also, the upper gate voltage  
(UGATE), the difference voltage between  
UGATE and PHASE, must be below  
approximately 1V after PWM goes LOW before  
the lower MOSFET can be gated on.  
Switching noise coupled to FB input. This  
causes the PWM comparator to trigger  
prematurely after the 400ns minimum Q2 on-  
time. It will result in double or multiple pulses  
every switching cycle instead of the expected  
single pulse. Double pulsing can causes  
higher output voltage ripple, but in most  
application it will not affect operation. This can  
usually be prevented by careful layout of the  
ground plane and the FB sensing trace.  
The control MOSFET is gated on after the  
adaptive delay for PWM = HIGH and the  
synchronous MOSFET is gated on after the  
adaptive delay for PWM = LOW. The lower  
MOSFET is driven ‘off’ when the signal  
ZCROSS indicates that the inductor current has  
reversed as detected by the PHASE voltage  
crossing the zero current threshold. The  
synchronous MOSFET stays ‘off’ until the next  
PWM falling edge. When the lower peak of  
inductor current is above zero, a forced  
continuous current condition is selected. The  
control MOSFET is gated on after the adaptive  
delay for PWM = HIGH, and the synchronous  
MOSFET is gated on after the adaptive delay for  
PWM = LOW.  
Steady state ripple on FB pin being too small.  
The PWM comparator in IR3871 requires  
minimum 7mVp-p ripple voltage to operate  
stably. Not enough ripple will result in similar  
double pulsing issue described above. Solving  
this may require using output capacitors with  
higher ESR.  
ESR loop instability. The stability criteria of  
constant on-time is: ESR*Cout>Ton/2. If ESR  
is too small that this criteria is violated then  
sub-harmonic oscillation will occur. This is  
similar to the instability problem of peak-  
current-mode control with D>0.5. Increasing  
ESR is the most effective way to stabilize the  
system, but the price paid is the larger output  
voltage ripple.  
The synchronous MOSFET gate is driven on for  
a minimum duration. This minimum duration  
allows time to recharge the bootstrap capacitor  
and allows the current monitor to sample the  
PHASE voltage.  
For applications with all ceramic output  
capacitors, the ESR is usually too small to  
meet the stability criteria. In these  
applications, external slope compensation is  
necessary to make the loop stable. The ramp  
injection circuit, composed of R6, C13, and  
C14, shown in Figure 7 is required. The  
inductor current ripple sensed by R6 and C13  
is AC coupled to the FB pin through C14. C14  
is usually chosen between 1 to 10nF, and C13  
between 10 to 100nF. R6 should then be  
chosen such that L/DCR = C13*R6.  
13  
IR3871MPBF  
COMPONENT SELECTION  
Selection of components for the converter is an  
iterative process which involves meeting the  
INPUT CAPACITOR SELECTION  
The main function of the input capacitor bank is  
to provide the input ripple current and fast slew  
rate current during the load current step up. The  
input capacitor bank must have adequate ripple  
current carrying capability to handle the total  
RMS current. Figure 21 shows a typical input  
current. Equation 6 shows the RMS input  
current. The RMS input current contains the DC  
load current and the inductor ripple current. As  
shown in equation 5, the inductor ripple current  
is unrelated to the load current. The maximum  
RMS input current occurs at the maximum  
output current. The maximum power dissipation  
in the input capacitor equals the square of the  
maximum RMS input current times the input  
capacitor’s total ESR.  
specifications  
and  
trade-offs  
between  
performance and cost. The following sections will  
guide one through the process.  
INDUCTOR SELECTION  
Inductor selection involves meeting the steady  
state output ripple requirement, minimizing the  
switching loss of upper MOSFETs, meeting  
transient response specifications and minimizing  
the output capacitance. The output voltage  
includes a DC voltage and a small AC ripple  
component due to the low pass filter which has  
incomplete  
attenuation  
of  
the  
switching  
harmonics. Neglecting the inductance in series  
with the output capacitor, the magnitude of the AC  
voltage ripple is determined by the total inductor  
ripple current flowing through the total equivalent  
series resistance (ESR) of the output capacitor  
bank.  
IOUT  
Input Current  
ΔI  
TON  
V
IN  
VOUT  
(5)  
ΔI   
TS  
2L  
Figure 21. Typical Input Current Waveform.  
One can use equation 5 to find the required  
inductance. ΔI is defined as shown in Figure 21.  
The main advantage of small inductance is  
increased inductor current slew rate during a load  
Ts  
1
IIN_RMS  
f 2  
t
dt  
transient, which leads to  
a smaller output  
Ts  
0
capacitance requirement as discussed in the  
Output Capacitor Selection section. The draw  
back of using smaller inductances is increased  
switching power loss in upper MOSFET, which  
reduces the system efficiency and increases the  
thermal dissipation.  
2  
1
ΔI  
IOUT TonFs 1   
(6)  
3 IOUT  
The voltage rating of the input capacitor needs  
to be greater than the maximum input voltage  
because of high frequency ringing at the phase  
node. The typical percentage is 25%.  
14  
IR3871MPBF  
COMPONENT SELECTION  
OUTPUT CAPACITOR SELECTION  
The second purpose of the output capacitor is to  
minimize the overshoot of the output voltage  
when the load decreases as shown in Figure  
23. By using the law of energy before and after  
the load removal, equation 8 shows the output  
capacitance requirement for a load step.  
Selection of the output capacitor requires meeting  
voltage overshoot requirements during load  
removal, and meeting steady state output ripple  
voltage requirements. The output capacitor is the  
most expensive converter component and  
increases the overall system cost. The output  
capacitor decoupling in the converter typically  
includes the low frequency capacitor, such as  
Specialty Polymer Aluminum, and mid frequency  
ceramic capacitors.  
2
LISTEP  
COUT  
(8)  
2
V
OS2 VOUT  
VOS  
The first purpose of output capacitors is to provide  
current when the load demand exceeds the  
inductor current, as shown in Figure 22. Equation  
7 shows the charge requirement for a certain load.  
The advantage provided by the IR3871 at a load  
step is to reduce the delay compared to a fixed  
frequency control method (in microseconds or (1-  
D)*Ts). If the load increases right after the PWM  
signal goes low, the longest delay will be equal to  
the minimum lower gate on as shown in the  
Electrical Specification table. The IR3871 also  
reduces the inductor current slew time, the time it  
takes for the inductor current to reach equality  
with the output current, by increasing the  
switching frequency up to 2.5MHz. The result  
reduces the recovery time.  
VOUT  
VL  
VDROP  
VESR  
ISTEP  
IOUT  
Figure 23. Typical Output Voltage Response  
Waveform.  
BOOT CAPACITOR SELECTION  
The boot capacitor starts the cycle fully charged  
to a voltage of VB(0). Cg equals 0.65nF in  
IR3871. Choose a sufficiently small ΔV such  
that VB(0)-ΔV exceeds the maximum gate  
threshold voltage to turn on the high side  
MOSFET.  
Load  
Current  
ISTEP  
Output  
Charge  
Inductor  
Slew  
V (0)  
B
CBOOT C   
1 (9)  
g
ΔV  
Rate  
Choose a boot capacitor value larger than the  
calculated CBOOT in equation 9. Equation 9 is  
based on charge balance at CCM operation.  
Usually the boot capacitor will be discharged to  
a much lower voltage when the circuit is  
operating in DCM mode at light load, due to  
much longer Q2 off time and the bias current  
drawn by the IC. Boot capacitance needs to be  
increased if insufficient turn-on of Q1 is  
observed at light load, typically larger than  
0.1µF is needed. The voltage rating of this part  
needs to be larger than VB(0) plus the desired  
derating voltage. Its ESR and ESL needs to be  
low in order to allow it to deliver the large  
current and di/dt’s which drive MOSFETs most  
efficiently. In support of these requirements a  
ceramic capacitor should be chosen.  
t
Δt  
Figure 22. Charge Requirement during Load Step  
Q CV 0.5Istept (7a)  
2
1
1
2
LIstep  
COUT  
(7b)  
V
DROP  
V
IN  
V
OUT  
The output voltage drop, VDROP, initially depends  
on the characteristic of the output capacitor.  
VDROP is the sum of the equivalent series  
inductance (ESL) of the output capacitor times the  
rate of change of the output current and the ESR  
times the change of the output current. VESR is  
usually much greater than VESL. The IR3871  
requires a total ESR such that the ripple voltage at  
the FB pin is greater than 7mV.  
15  
IR3871MPBF  
DESIGN EXAMPLE  
Design Criteria:  
Choose an inductor with the lowest DCR and  
AC power loss as possible to increase the  
overall system efficiency. For instance, choose  
an FDU0650-R82M manufactured by TOKO.  
The inductance of this part is 820nH and has  
4.2DCR. Ripple current needs to be  
recalculated using the chosen inductor.  
Input Voltage, VIN, = 6V to 21V  
Output Voltage, VOUT = 1.25V  
Switching Frequency, FS = 400KHz  
Inductor Ripple Current, 2ΔI = 3A  
Maximum Output Current, IOUT = 6A  
Over Current Trip, IOC = 9A  
Overshoot Allowance, VOS = VOUT + 50mV  
Undershoot Allowance, VDROP = 50mV  
1.25V   
221V 0.82H 400kHz  
21V -1.25V  
ΔI   
1.75A  
Find RFF  
:
Choose an input capacitor:  
1.25V  
1V 20pF 400kHz  
RFF  
156 k  
2
1.25V  
1 1.75A  
I
IN_RMS 6A  
1   
1.5A  
Pick a standard value 158 kΩ, 1% resistor.  
Find RSET  
21V  
3
6A  
:
A
Panasonic  
10µF  
(ECJ3YB1E106M)  
accommodates 6 Arms of ripple current at  
300KHz. Due to the chemistry of multilayer  
ceramic capacitors, the capacitance varies over  
temperature and operating voltage, both AC and  
DC. One 10µF capacitor is recommended. In a  
practical solution, one 1µF capacitor is required  
along with 10µF. The purpose of the 1µF  
capacitor is to suppress the switching noise and  
deliver high frequency current.  
1.410m9A  
RSET  
6.3k  
20A  
The RDSON of the lower MOSFET could be  
expected to increase by a factor of 1.4 over  
temperature.  
Therefore, pick a 6.49kΩ, 1%  
standard resistor.  
Find a resistive voltage divider for VOUT = 1.25V:  
Choose an output capacitor:  
R
2
VFB  
VOUT 0.5V  
1
R2  
R  
To meet the undershoot specification, select a  
set of output capacitors which has an equivalent  
ESR of 10(50mV/5A). To meet the  
overshoot specification, equation 8 will be used  
to calculate the minimum output capacitance.  
As a result, 160µF will be needed for 5A load  
remover. Combine those two requirements, one  
can choose a set of output capacitors from  
manufactures such as SP-Cap (Specialty  
Polymer Capacitor) from Panasonic or  
R2 = 1.33kΩ, R1 = 1.96 kΩ, both 1% standard  
resistors.  
Choose the soft start capacitor:  
Once the soft start time has chosen, such as  
1000us to reach to the reference voltage, a 22nF  
for CSS is used to meet 1000µs.  
Choose an inductor to meet the design  
specification:  
POSCAP  
(EEFSL0D151R)  
from  
Sanyo.  
from  
A
150µF  
is  
Panasonic  
V
OUT  
V
IN   
V
OUT  
recommended. This capacitor has 9ESR  
which leaves margin for the voltage drop of the  
ESL during load step up. The typical ESL for  
this capacitor is around 2nH.  
L   
1.25VIN21V -1.25V  
V
2ΔI F  
s
21V 3A400kHz  
1.0H  
16  
IR3871MPBF  
LAYOUT RECOMMENDATION  
Bypass Capacitor:  
V
IN  
One 1µF high quality ceramic capacitor should be  
placed as near VCC pin as possible. The other  
end of capacitor can be connected to a via or  
connected directly to GND plane. Use a GND  
plane instead of a thin trace to the GND pin  
because a thin trace have too much impedance.  
ON  
Q1  
VOUT  
IR3871  
Q2  
Boot Circuit:  
OFF  
CIN  
CBOOT should be placed near the BOOT and  
PHASE pins to reduce the impedance when the  
upper MOSFET turns on.  
COUT  
Power Stage:  
Figure 24 shows the current paths and their  
directions for the on and off periods. The on time  
path has low average DC current and high AC  
current. Therefore, it is recommended to place the  
input ceramic capacitor, upper, and lower  
MOSFET in a tight loop as shown in Figure 24.  
Figure 24. Current Path of Power Stage  
The purpose of the tight loop from the input  
ceramic capacitor is to suppress the high  
frequency (10MHz range) switching noise and  
reduce Electromagnetic Interference (EMI). If this  
path has high inductance, the circuit will cause  
voltage spikes and ringing, and increase the  
switching loss. The off time path has low AC and  
high average DC current. Therefore, it should be  
laid out with a tight loop and wide trace at both  
ends of the inductor. Lowering the loop resistance  
reduces the power loss. The typical resistance  
value of 1-ounce copper thickness is 0.5per  
square inch.  
17  
IR3871MPBF  
PCB Metal and Components Placement  
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to  
lead spacing should be 0.2mm to minimize shorting.  
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The  
outboard extension ensures a large toe fillet that can be easily inspected.  
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width.  
However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or  
no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper.  
18  
IR3871MPBF  
Solder Resist  
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist  
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.  
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist  
onto the copper of 0.05mm to accommodate solder resist misalignment.  
Ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the  
high aspect ratio of the solder resist strip separating the lead lands from the pad land.  
19  
IR3871MPBF  
Stencil Design  
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads.  
Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much  
solder is deposited on the center pad the part will float and the lead lands will open.  
The maximum length and width of the land pad stencil aperture should be equal to the solder resist  
opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land  
to the lead lands when the part is pushed into the solder paste.  
20  
IR3871MPBF  
MILIMITERS  
MIN MAX  
INCHES  
MILIMITERS  
INCHES  
MIN  
DIM  
A
A1  
b
b1  
c
D
E
e
e1  
e2  
MIN  
0.0315  
0
MAX  
0.0394  
0.002  
DIM  
L
M
N
O
P
Q
R
MIN  
0.35  
MAX  
0.45  
MAX  
0.0177  
0.1001  
0.0314  
0.0858  
0.1316  
0.05374  
0.1081  
0.063  
0.8  
0
0.375  
0.25  
1
0.0138  
0.0962  
0.0277  
0.0819  
0.1276  
0.0498  
0.1042  
0.0591  
0.05  
0.475  
0.35  
2.441  
0.703  
2.079  
3.242  
1.265  
2.644  
1.5  
2.541  
0.803  
2.179  
3.342  
1.365  
2.744  
1.6  
0.1477  
0.0098  
0.1871  
0.1379  
0.203 REF.  
0.008 REF.  
5.000 BASIC  
6.000 BASIC  
1.033 BASIC  
0.650 BASIC  
0.852 BASIC  
1.970 BASIC  
2.364 BASIC  
0.0407 BASIC  
0.0256 BASIC  
0.0259 BASIC  
S
t1, t2, t3  
t4  
0.401 BASIC  
1.153 BASIC  
0.727 BASIC  
0.016 BACIS  
0.045 BASIC  
0.0286 BASIC  
t5  
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105  
TAC Fax: (310) 252-7903  
This product has been designed and qualified for the Industrial Market (Note 2)  
Visit us at www.irf.com for sales contact information  
Data and specifications subject to change without notice. 03/12  
21  

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