ERJ-3EKF2001V [INFINEON]
USER GUIDE FOR IR3898 EVALUATION BOARD; 用户指南IR3898评估板
| 型号： | ERJ-3EKF2001V |
| 厂家： | 
Infineon |
| 描述： | USER GUIDE FOR IR3898 EVALUATION BOARD |
| 文件： | 总17页 (文件大小：2992K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRDC3898-P1V2
TM
SupIRBuck
USER GUIDE FOR IR3898 EVALUATION BOARD
1.2Vout
DESCRIPTION
Output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
Mosfet for optimum cost and performance and
the current limit is thermally compensated.
The IR3898 is
converter, providing
performance and flexible solution in a small
4mm X 5 mm Power QFN package.
a
synchronous buck
compact, high
a
Key features offered by the IR3898 include
internal Digital Soft Start/Soft Stop, precision
This user guide contains the schematic and bill
of materials for the IR3898 evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3898 is available in the
IR3898 data sheet.
0.5Vreference voltage, Power Good,
thermal protection, programmable switching
frequency, Enable input, input under-voltage
lockout for proper start-up, enhanced line/
load regulation with feed forward, external
frequency synchronization with smooth
clocking, internal LDO and pre-bias start-
up.
BOARD FEATURES
• Vin = +12V (+ 13.2V Max)
•Vout = +1.2V @ 0- 6A
• Fs=600kHz
• L= 1.0uH
• Cin= 3x10uF (ceramic 1206) + 1X330uF (electrolytic)
• Cout=4x22uF (ceramic 0805)
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IRDC3898-P1V2
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 6A load should be
connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I.
IR3898 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc
is required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin
and Vcc/LDO_Out pins should be shorted together for external Vcc operation.
The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero
ohm resistor for R21). The value of R14 and R28 can be selected to provide the desired tracking ratio
between output voltage and the tracking input.
Table I. Connections
Connection
VIN+
Signal Name
Vin (+12V)
VIN-
Ground of Vin
Vout(+1.2V)
Vout+
Vout-
Vcc+
Vcc-
Ground for Vout
Vcc/ LDO_Out Pin
Ground for Vcc input
Enable
Enable
PGood
AGnd
Power Good Signal
Analog ground
LAYOUT
The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCB
thickness is 0.062”. The IR3898 and other major power components are mounted on the top side of the
board.
Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located
close to IR3898. The feedback resistors are connected to the output at the point of regulation and are
located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the
length of the on-board power ground current path.
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IRDC3898-P1V2
Connection Diagram
Vin
Gnd
Gnd
Vout
Enable
VDDQ
Top View
Vref
Sync
S-Ctrl
AGnd
Vsns
Vcc-
Vcc+
PGood
Bottom View
Fig. 1: Connection Diagram of IR3899/98/97 Evaluation Boards
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IRDC3898-P1V2
Fig. 2: Board Layout-Top Layer
Single point connection
between AGnd and PGnd
Fig. 3: Board Layout-Bottom Layer
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IRDC3898-P1V2
Fig. 4: Board Layout-Mid Layer 1
Fig. 5: Board Layout-Mid Layer 2
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IRDC3898-P1V2
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IRDC3898-P1V2
Bill of Materials
Item Qty
Part Reference
Value
330uF
10uF
0.1uF
2200pF
180pF
22uF
2.2uF
10nF
1.0uF
1.0uH
2K
Description
Manufacturer
Part Number
EEV-FK1E331P
SMD Electrolytic F size 25V
20%
Panasonic
1
2
1
3
4
1
1
4
1
1
1
1
1
2
2
1
1
1
5
2
1
1
C1
1206, 25V, X5R, 20%
C3 C4 C5
TDK
C3216X5R1E106M
GRM188R71E104KA01B
3
C7 C12 C14 C24
0603, 25V, X7R, 10%
Murata
4
C8
0603,50V,X7R
Murata
Murata
GRM188R71H222KA01B
GRM1885C1H181JA01D
0603, 50V, NP0, 5%
5
C11
0805, 6.3V, X5R, 20%
0603, 16V, X5R, 20%
0603, 25V, X7R, 10%
0603, 25V, X5R, 10%
6
C15 C16 C17 C18
TDK
C2012X5R0J226M
C1608X5R1C225M
GRM188R71E103KA01J
GRM188R61E105KA12D
SPM6550T-1R0
7
C23
TDK
8
C26
Murata
9
C32
Murata
10
11
12
13
14
15
16
17
18
19
20
L1
SMD 7.1x6.5x5mm,4.7mΩ
TDK
Thick Film, 0603,1/10W,1%
R1
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
IR
ERJ-3EKF2001V
ERJ-3EKF3321V
ERJ-3EKF2371V
ERJ-3EKF1000V
ERJ-3EKF20R0V
ERJ-3EKF3922V
ERJ-3GEY0R00V
ERJ-3EKF4992V
ERJ-3EKF7501V
IR3898MPBF
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W
R2 R11
3.32K
2.37K
100
R3 R12
R4
R6
20
R9
39.2K
0
R10 R13 R14 R15 R50
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
R17 R18
R19
49.9K
7.5K
U1
IR3898
PQFN 4x5mm
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IRDC3898-P1V2
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no airflow
Fig. 8: Start up at 6A Load,
Fig. 7: Start up at 6A Load
Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:PGood
Ch1:Vin, Ch2:Vo, Ch3:PGood Ch4:Enable
Fig. 10: Output Voltage Ripple, 6A load
Ch2: Vout
Fig. 9: Start up with 1V Pre Bias , 0A Load,
Ch2:Vo
Fig. 12: Short circuit (Hiccup) Recovery
Ch2:Vout , Ch4:Iout
Fig. 11: Inductor node at 6A load
Ch3:LX
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IRDC3898-P1V2
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
Fig. 13: Transient Response, 3A to 6A step
Ch2:Vout Ch4-Iout
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IRDC3898-P1V2
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
Fig. 14: Bode Plot at 6A load shows a bandwidth of 110.8KHz and phase margin of 50.5 degrees
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IRDC3898-P1V2
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
Fig (15) Soft start and soft stop using S_Ctrl pin
Fig (16) Feed Forward for Vin change from 7 to 16V and back to 7V
Ch2-Vout Ch4-Vin
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IRDC3898-P1V2
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, no air flow
90
89
88
87
86
85
84
83
82
81
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
Iout(A)
Fig.17: Efficiency versus load current
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
1.2
1.8
2.4
3
3.6
4.2
4.8
5.4
6
Iout(A)
Fig.18: Power loss versus load current
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IRDC3898-P1V2
THERMAL IMAGES
Vin=12.0V, Vo=1.2V, Io=0-6A, Room Temperature, No Air flow
Fig. 19: Thermal Image of the board at 6A load
Test point 1 is IR3898
Test point 2 is inductor
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IRDC3898-P1V2
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout
as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X
and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments
should be run to confirm the limits of self-centering on specific processes. For further information, please
refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting
Application Note.” (AN1132)
Figure 20: PCB Metal Pad Spacing (all dimensions in mm)
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IRDC3898-P1V2
SOLDER RESIST
IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.)
This allows the underlying Copper traces to be as large as possible, which helps in terms of current
carrying capability and device cooling capability. When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on each edge) than the Solder Mask window,
in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.)
However, for the smaller Signal type leads around the edge of the device, IR recommends that
these are Non Solder Mask Defined or Copper Defined. When using NSMD pads,
the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on
each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to
layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at
least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip.
Figure 21: Solder resist
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IRDC3898-P1V2
STENCIL DESIGN
Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than
0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the
ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm
(0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall
performance is achieved using the stencil design shown in following figure. This design is for
a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses.
Figure 22: Stencil Pad Spacing (all dimensions in mm)
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IRDC3898-P1V2
PACKAGE INFORMATION
Figure 23: Package Dimensions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice.12/11
12/8/2011
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