FZL4146G [INFINEON]
Quad Driver Incl. Short-Circuit Signaling; 四核驱动含短路信号
| 型号： | FZL4146G |
| 厂家： | 
Infineon |
| 描述： | Quad Driver Incl. Short-Circuit Signaling |
| 文件： | 总14页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FZL 4146
Quad Driver Incl. Short-Circuit Signaling
Bipolar IC
Features
● Short-circuit signaling
● Four driver circuits for driving power transistors
● Turn-ON threshold setting from 1.5 to 7 V
P-DSO-20-7
Package
Type
Ordering Code
FZL 4146 G
Q67000-H8743
P-DSO-20-7 (SMD)
General Description
The IC comprises four driver circuits capable of driving power transistors (PNP or
PMOS). The output transistors are protected against short-circuit to ground and supply
voltage. The turn-ON threshold can be set from 1.5 V to 7 V. Overload at one or several
outputs will be indicated at pin SQ (signaling output). The corresponding power
transistors are then protected by changeover to clock-governed operation.
Circuit Description
Each driver circuit has one active high driver input Dl and a common enable input ENA
(active high) is provided for all stages. The Q output is designed to drive the output
transistors. The load current is sampled and, if necessary, limited via pin W. If the load
current exceeds the preset value, the output stage switches off. Switching-ON again is
provided by the built-in clock generator T. Its operation requires an external capacitor Ce
at pin CE. If Ce is bridged by a break-key, switching-ON can only be carried out by
operating this key. The duty cycle of the clock generator is 1:47 (e.g. 45 µs/2.1 ms with
Ce = 10 nF). The clock generator is privileged versus the current sensor shut down.
When the supply is connected, the internal RS-FF goes into the state corresponding to
the released output.
Semiconductor Group
1
03.96
FZL 4146
The turn-ON threshold at input Dl and ENA can be set via pin TS from 1.5 to 7 V.
VTS = 0 V … 1.5 V
VTS = 1.5 V … 7 V
VTS = VS
Turn-ON threshold = 1.5 V
Turn-ON threshold = VTS
Turn-ON threshold = 7 V
Inputs Dl, ENA and W are proof against line break, i.e. an open input at Dl or ENA
corresponds to input L, open input W corresponds to overcurrent. If input TS is open, the
highest turn-ON threshold is provided.
The internal current supply B and the undervoltage monitor UV ensure that in case of a
supply voltage that is below the VS turn-OFF threshold, outputs Q and SQ are disabled
and the inputs go high-impedance. Basic functioning is possible within the range from VS
turn-OFF threshold to 4.5 V.
In case of overcurrent or short-circuit to ground at any output stage the signaling output
(SQ) will go low. In clock-governed operation (i.e. when there is automatic switching-ON
by the clock and not by a key), SQ goes high and low at the clock rate as long as a short-
circuit or overload is present. SQ is an open-collector output.
Any input and output is ESD proof within the limit values.
Semiconductor Group
2
FZL 4146
Pin Configuration
(top view)
P-DSO-20-7
Semiconductor Group
3
FZL 4146
Pin Definitions and Functions
Pin
1
Symbol
CE
Function
Pin for Ce
2
ENA
DI1
DI2
N.C.
GND
DI3
DI4
TS
Enable input for drivers 1 to 4
Input driver 1
3
4
Input driver 2
5
Not connected
Ground
6
7
Input driver 3
8
Input driver 4
9
Threshold changeover for all inputs
10
11
12
13
14
15
16
17
18
19
20
SQ
Short-circuit signaling output for drivers 1 to 4
Output current sensor driver 4
Output driver 4
W4
Q4
W3
Output current sensor driver 3
Output driver 3
Q3
VS
Supply voltage
GND
W2
Ground
Output current sensor driver 2
Output driver 2
Q2
W1
Output current sensor driver 1
Output driver 1
Q1
Semiconductor Group
4
FZL 4146
Block Diagram
Semiconductor Group
5
FZL 4146
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
Supply voltage
Supply voltage
VS
VS
– 0.3
– 0.3
40
45
V
V
100 ms,
5 s interval
Supply voltage
VS
IGND
VDI, ENA,TS – 5
VDI, ENA,TS – 5
– 0.3
48
0.5
40
45
V
A
V
V
120 µs
1) 4)
Reverse supply current in GND
Input voltage at DI, ENA, TS
Input voltage at DI, ENA, TS
100 ms,
5 s interval
min. – 0.3 V
Output voltage Q
VQ
VS – 8
– 10
VS
V
18)
Current in Q
Voltage at W
IQ
VW
3
mA
VS – 6.5 VS + 5 V
min. – 0.3 V,
max. 45
Voltage at W
Voltage at CE
VW
VC
VS – 12 VS + 5 V
min. – 0.3 V,
max. 45 V2)
min. – 0.3 V,
max. 45 V3)
Output high
– 0.3
– 0.5
VS
V
Voltage at SQ
VSQ
45
3
V
4)
Input current DI, ENA, TS
VDI, ENA, TS – 3
VDI, ENA, TS – 5
VDI, ENA, TS – 10
mA
Input current DI, ENA, TS
Input current DI, ENA, TS
5
mA
mA
100 ms,
5 s interval
10 µs, 500 µs
interval
10
Notes: 1) An adequate resistor in the GND line can provide protection in case of wrong polarization
of VS. It should be noted, however, that in this case all pins may become conductive
across GND.
2) Loading may lead to degradation and thus to a shift of the switching threshold at W.
(Characteristics: switching threshold at W).
Short loading may lead to a deviation of approx. 20 mV.
3) In case of short-circuit of VS, the capacitance stored in Ce during previous operation will
not damage the IC.
4) Note the power loss.
Semiconductor Group
6
FZL 4146
Absolute Maximum Ratings (cont’d)
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
Current in SQ
Current in W
ISQ
IW
– 3
– 5
8
5
mA
mA
Output low
1 ms, 50 ms
interval 5)
Current in W
IW
– 10
10
mA
10 µs, 500 µs
interval 5)
Junction temperature
Storage temperature
Therm. resistance,
system-ambient
Therm. resistance,
system-packag.
Tj
Tstg
Rth SA
– 40
– 50
150
150
95
°C
°C
K/W
6)
Rth SP
VESD
25
2
K/W
kV
ESD strength acc. to MIL -
hrs. 883 Meth. 3015
(100 pF/1.5 kΩ,
– 2
5 discharges/polarity)
7)
8)
Burst strength of the inputs/
outputs Q and W connected to
the power transistors (in acc.
with IEC publ. 801-4)
VBurst
300
V
Junction temperature in normal Tj15
operation during 15 years with
100 % ED
125
°C
Notes: 5) Loading may lead to degradation and thus to a shift of the switching threshold at W.
Unfrequent loading leads to a deviation of approx. 20 mV.
6) Related to GND; the GND pins are connected with the chip carrier via the leadframe.
7) If it can be prooved with samples.
8) During normal operation, the failure rate is ≤ 100 fit acc. to SN 29500 at a junction
temperature of 75 °C.
Semiconductor Group
7
FZL 4146
Operating Range
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
Supply voltage11)
Supply voltage12)
Supply voltage13)
Supply voltage rise
VS
VS
VS
dVS/dt
4.5
40
V
V
V
V/µs
V
V
TS = 0 … 1.5 V
TS = 1.5 … 7 V
VTS + 3 40
10
– 1
40
1
VTS = VS
20)
Junction temperature
Tj
– 25
1
150
100
°C
10)
Time-determining capacitor of
the clock generator
Ce
nF
14) 15) 16) 17) 19)
Input voltage
VDI, ENA, TS
ISQ
– 2
– 1
40
6
V
Current at output SQ
mA
9)
Notes:
W pins that remain open, must be connected to VS.
The Ce value depends on the desired pulse width tp during short circuit.
It applies: Ce = 0.25 mS x tp.
At an input threshold = 1.5 V
At an input threshold = 1.5 V to 7 V
At an input threshold = 7 V
10)
11)
12)
13)
14)
This function is also ensured for 40 V ≤ VS ≤ 45 V and – 40 °C ≤ Tj ≤ – 25 °C as long as
0 V ≤ VDI, ENA, TS ≤ 40 V.
15)
16)
17)
18)
19)
20)
The outputs Q are disabled even if – 3 V ≤ VDI, ENA ≤ – 2 V or – 1 mA ≤ IDI, ENA ≤ 50 µA and
VS – 5 V ≤ VW ≤ VS + 5 V, max. 45 V.
The outputs Q are enabled even if 40 V ≤ VDI, ENA ≤ 45 V and VS – 0.2 V ≤ VW ≤ VS + 5 V,
max. 45 V.
Current limiting and disabling of outputs Q are ensured even if 40 V ≤ VDI, ENA ≤ 45 V and
VS – 5 V ≤ VW ≤ VS – 0.4 V.
Dynamic charge reversal of a 2-nF capacitor as in figure 1 is permissible (corresponds
to short circuit to conducting output in P-channel MOSFET)
Proper working of the IC is also ensured if, before VS is turned-On, an input voltage
V
DI, ENA is present in the permissible range (footnote 15).
At 10 V/µs short-term malfunction is possible, but never a latch-up.
Semiconductor Group
8
FZL 4146
Characteristics
Supply voltage 4.5 V ≤ VS ≤ 40 V, junction temperature – 25 °C ≤ Tj ≤ 125 °C
Parameter
Symbol
Limit Values
min. typ. max.
Unit Test Condition
Current consumption Is, OFF
Current consumption Is, ON
5
mA VENA = 0 V,
4)
Vw = VS
13.5 mA VENA = VDI = Vw = VQ = VS;
VTS = 0 V3)
H-input voltage
at DI, ENA
H-input voltage
at DI, ENA
L-input voltage
at DI, ENA
L-input voltage
at DI, ENA
VI H
VI H
VI L
VI L
2
V
V
V
V
VTS = 0 V
VTS = VS
VTS = 0 V
VTS = VS
6.8
0.7
4.8
Input hysteresis
VHI
VHI
30
30
100 300 mV 0 V ≤ VTS ≤ VS ≤ 30 V
100 300 mV 2 V ≤ VTS ≤ VS
Input current DI, ENA1), 7) IDI, ENA
Input current DI, ENA IDI0, ENA0
50
200 µA 1.5 V ≤ VDI, ENA ≤ 30 V
100 µA 0 V ≤ VDI, ENA ≤ 30 V
VS = 0 V
L-output voltage at SQ VSQ L
0.5
V
ISQ = 5 mA,
VW = VS – 2 V
ISQ H
Leakage current
output SQ
10
µA VW = VS
Output current Q
Current from TS
Current in W
IQ0
0.6
2
1.6
10
mA VS – 2 V ≤ VQ ≤ VS
µA VTS = 0.7 V
– ITS
IW
5
100 µA VS – 2 V ≤ VW ≤ VS
Switching threshold VW
VS –
0.25
VS – VS – V
0.3 0.35
at W 2)
Notes see page 11.
Semiconductor Group
9
FZL 4146
Characteristics (cont’d)
Supply voltage 4.5 V ≤ VS ≤ 40 V, junction temperature – 25 °C ≤ Tj ≤ 125 °C
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ. max.
Current in W
IW
100 µA VS – 2 V ≤ VW ≤ VS
µA
Charge current
from CE
– ICe
5
Discharge current
from CE
ICe
235
µA
Upper switching
threshold at CE
Lower switching
threshold at CE
VCU
VCL
2.4
1.4
V
V
V
6)
VQ at overcurrent
VQR
VS –
VW = VS – 2 V,
IQ = – 20 µA
0.4 V
6)
VQ at output disable VQL
VS –
V
VENA = 0 V,
0.4 V
IQ = – 20 µA,
0 V ≤ VS ≤ 40 V
Signal run time LH
Signal run time HL
Pulse width
tPLH
tPHL
tP
50
50
65
µs
µs
µs
33
45
Ce = 10 nF
Ce = 10 nF
VC = 0 V
Duty cycle
tP/t0
tPWM
1:55
1:47 1:40
10
5)
Delay time of the
short-circuit signaling
µs
µs
Duration of the
tVZ
1
negative spikes at
input W, which do not
result in switching off
Notes see page 11.
Semiconductor Group
10
FZL 4146
Characteristics (cont’d)
Supply voltage 4.5 V ≤ VS ≤ 40 V, junction temperature – 25 °C ≤ Tj ≤ 125 °C
Parameter
Symbol
Limit Values
Unit Test Condition
min.
typ. max.
Difference between VDIH –
– 0.2
0.2
V
2 V ≤ VTS ≤ 4.8 V
VTS and input
switching
VTS
threshold ENA, DI
during transition
from L to H
Idling voltage at
output Q
VQH
VS –
13
VS – VS – V
11.5 10
VS ≥ 18 V
VS turn-Off threshold VTSV
2.5
8
4.5
19
V
VQ > VQL;
IQ = – 20 µA
Resistance
RQ
RZ
13
20
kΩ
VENA = 0 V;
IQ = – 100 µA
RQ = (VS – VQ)/0.1 mA
across Q and VS
Z-diode
50
Ω
VENA = 0 V;
internal resistance
IQ1 = – 3 mA
IQ2 = – 8 mA,
RQ = ∆VQ/5 mA
Footnotes for the Characteristics
1)
The given limit values apply to inputs Dl, ENA, if they are not measured, from 0 to 40 V.
The layout provides an adaption of Vwtyp. from VS – 0.3 V to VS – 0.4 V or VS – 0.48 V by simply
changing of the ALU mask.
2)
3)
All inputs Dl1 to Dl4 and W1 to W4 as well as Q1 to Q4
ISON means the sum of all currents flowing from the voltage source VS into the IC, i.e.
I
SON = IS + Σ IDI + Σ IENA + Σ IW + Σ IQ.
4)
5)
All other pins are open.
The delay time of loop W → I regulator → RS-FF → AND → current source → Q is
unaccessable for measurement without external wiring due to fast reaction of the current
regulator. For this reason, in case of overload, the above mentioned switch-OFF delay time is
replaced by the delay time for input W → output SQ.
Measurement: jump function at W from VW = VS to VW = VS – 1 V
6)
7)
IQ = leakage current ICBO of the external PNP-driver transistor
For VDI, TS < 1.5 V, IDl, ENA remains below its minimum value; it is however ensured that in case of
open inputs the corresponding outputs will be safely disabled.
Semiconductor Group
11
FZL 4146
Figure 1
Figure 2
Application Circuit
Semiconductor Group
12
FZL 4146
Figure 3
Operating Mode: Automatic Turn-ON after Overload
Semiconductor Group
13
FZL 4146
Package Outlines
P-DSO-20-7
(Plastic Dual Small Outline Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
SMD = Surface Mounted Device
Semiconductor Group
14
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